| 1 | /* $NetBSD: i8259reg.h,v 1.4 2008/04/28 20:23:50 martin Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Jason R. Thorpe. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #ifndef _DEV_IC_I8259REG_H_ |
| 33 | #define _DEV_IC_I8259REG_H_ |
| 34 | |
| 35 | /* |
| 36 | * Register definitions for the Intel i8259 Programmable Interrupt |
| 37 | * Controller. |
| 38 | * |
| 39 | * XXX More bits should be filled in, here, as this was taken from |
| 40 | * XXX the Intel PIIX4 manual. Someone with a real 8259 data sheet |
| 41 | * XXX should fill them in. |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | * Note a write to ICW1 starts an initialization cycle, and must be |
| 46 | * followied by writes to ICW2, ICW3, and ICW4. |
| 47 | */ |
| 48 | #define PIC_ICW1 0x00 /* Initialization Command Word 1 (w) */ |
| 49 | #define ICW1_IC4 (1U << 0) /* ICW4 Write Required */ |
| 50 | #define ICW1_SNGL (1U << 1) /* 1 == single, 0 == cascade */ |
| 51 | #define ICW1_ADI (1U << 2) /* CALL address interval */ |
| 52 | #define ICW1_LTIM (1U << 3) /* 1 == intrs are level trigger */ |
| 53 | #define ICW1_SELECT (1U << 4) /* select ICW1 */ |
| 54 | #define ICW1_IVA(x) ((x) << 5) /* interrupt vector address (MCS-80) */ |
| 55 | |
| 56 | #define PIC_ICW2 0x01 /* Initialization Command Word 2 (w) */ |
| 57 | #define ICW2_VECTOR(x) ((x) & 0xf8) /* vector base address */ |
| 58 | #define ICW2_IRL(x) ((x) << 0) /* interrupt request level */ |
| 59 | |
| 60 | #define PIC_ICW3 0x01 /* Initialization Command Word 3 (w) */ |
| 61 | #define ICW3_CASCADE(x) (1U << (x)) /* cascaded mode enable */ |
| 62 | #define ICW3_SIC(x) ((x) << 0) /* slave identifcation code */ |
| 63 | |
| 64 | #define PIC_ICW4 0x01 /* Initialization Command Word 4 (w) */ |
| 65 | #define ICW4_8086 (1U << 0) /* 8086 mode */ |
| 66 | #define ICW4_AEOI (1U << 1) /* automatic end-of-interrupt */ |
| 67 | #define ICW4_BUFM (1U << 2) /* buffered mode master */ |
| 68 | #define ICW4_BUF (1U << 3) /* buffered mode */ |
| 69 | #define ICW4_SFNM (1U << 4) /* special fully nested mode */ |
| 70 | |
| 71 | /* |
| 72 | * After an initialization sequence, you get to access the OCWs. |
| 73 | */ |
| 74 | #define PIC_OCW1 0x01 /* Operational Control Word 1 (r/w) */ |
| 75 | #define OCW1_IRM(x) (1U << (x)) /* interrupt request mask */ |
| 76 | |
| 77 | #define PIC_OCW2 0x00 /* Operational Control Word 2 (w) */ |
| 78 | #define OCW2_SELECT (0) /* select OCW2 */ |
| 79 | #define OCW2_EOI (1U << 5) /* EOI */ |
| 80 | #define OCW2_SL (1U << 6) /* specific */ |
| 81 | #define OCW2_R (1U << 7) /* rotate */ |
| 82 | #define OCW2_ILS(x) ((x) << 0) /* interrupt level select */ |
| 83 | |
| 84 | #define PIC_OCW3 0x00 /* Operational Control Word 3 (r/w) */ |
| 85 | #define OCW3_SSMM (1U << 6) /* set special mask mode */ |
| 86 | #define OCW3_SMM (1U << 5) /* 1 = enable smm, 0 = disable */ |
| 87 | #define OCW3_SELECT (1U << 3) /* select OCW3 */ |
| 88 | #define OCW3_POLL (1U << 2) /* poll mode command */ |
| 89 | #define OCW3_RR (1U << 1) /* register read */ |
| 90 | #define OCW3_RIS (1U << 0) /* 1 = read IS, 0 = read IR */ |
| 91 | |
| 92 | #define OCW3_POLL_IRQ(x) ((x) & 0x7f) |
| 93 | #define OCW3_POLL_PENDING (1U << 7) |
| 94 | |
| 95 | #endif /* _DEV_IC_I8259REG_H_ */ |
| 96 | |