| 1 | /* $NetBSD: ohcireg.h,v 1.27 2016/04/23 10:15:32 skrll Exp $ */ |
| 2 | /* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 1998 The NetBSD Foundation, Inc. |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * This code is derived from software contributed to The NetBSD Foundation |
| 9 | * by Lennart Augustsson (lennart@augustsson.net) at |
| 10 | * Carlstedt Research & Technology. |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or without |
| 13 | * modification, are permitted provided that the following conditions |
| 14 | * are met: |
| 15 | * 1. Redistributions of source code must retain the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer. |
| 17 | * 2. Redistributions in binary form must reproduce the above copyright |
| 18 | * notice, this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 23 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 24 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 31 | * POSSIBILITY OF SUCH DAMAGE. |
| 32 | */ |
| 33 | |
| 34 | #ifndef _DEV_USB_OHCIREG_H_ |
| 35 | #define _DEV_USB_OHCIREG_H_ |
| 36 | |
| 37 | /*** PCI config registers ***/ |
| 38 | |
| 39 | #define PCI_CBMEM 0x10 /* configuration base memory */ |
| 40 | |
| 41 | #define PCI_INTERFACE_OHCI 0x10 |
| 42 | |
| 43 | /*** OHCI registers */ |
| 44 | |
| 45 | #define OHCI_REVISION 0x00 /* OHCI revision # */ |
| 46 | #define OHCI_REV_LO(rev) ((rev)&0xf) |
| 47 | #define OHCI_REV_HI(rev) (((rev)>>4)&0xf) |
| 48 | #define OHCI_REV_LEGACY(rev) ((rev) & 0x100) |
| 49 | |
| 50 | #define OHCI_CONTROL 0x04 |
| 51 | #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ |
| 52 | #define OHCI_RATIO_1_1 0x00000000 |
| 53 | #define OHCI_RATIO_1_2 0x00000001 |
| 54 | #define OHCI_RATIO_1_3 0x00000002 |
| 55 | #define OHCI_RATIO_1_4 0x00000003 |
| 56 | #define OHCI_PLE 0x00000004 /* Periodic List Enable */ |
| 57 | #define OHCI_IE 0x00000008 /* Isochronous Enable */ |
| 58 | #define OHCI_CLE 0x00000010 /* Control List Enable */ |
| 59 | #define OHCI_BLE 0x00000020 /* Bulk List Enable */ |
| 60 | #define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalState */ |
| 61 | #define OHCI_HCFS_RESET 0x00000000 |
| 62 | #define OHCI_HCFS_RESUME 0x00000040 |
| 63 | #define OHCI_HCFS_OPERATIONAL 0x00000080 |
| 64 | #define OHCI_HCFS_SUSPEND 0x000000c0 |
| 65 | #define OHCI_IR 0x00000100 /* Interrupt Routing */ |
| 66 | #define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ |
| 67 | #define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ |
| 68 | #define OHCI_COMMAND_STATUS 0x08 |
| 69 | #define OHCI_HCR 0x00000001 /* Host Controller Reset */ |
| 70 | #define OHCI_CLF 0x00000002 /* Control List Filled */ |
| 71 | #define OHCI_BLF 0x00000004 /* Bulk List Filled */ |
| 72 | #define OHCI_OCR 0x00000008 /* Ownership Change Request */ |
| 73 | #define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ |
| 74 | #define OHCI_INTERRUPT_STATUS 0x0c |
| 75 | #define OHCI_SO 0x00000001 /* Scheduling Overrun */ |
| 76 | #define OHCI_WDH 0x00000002 /* Writeback Done Head */ |
| 77 | #define OHCI_SF 0x00000004 /* Start of Frame */ |
| 78 | #define OHCI_RD 0x00000008 /* Resume Detected */ |
| 79 | #define OHCI_UE 0x00000010 /* Unrecoverable Error */ |
| 80 | #define OHCI_FNO 0x00000020 /* Frame Number Overflow */ |
| 81 | #define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ |
| 82 | #define OHCI_OC 0x40000000 /* Ownership Change */ |
| 83 | #define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ |
| 84 | #define OHCI_INTERRUPT_ENABLE 0x10 |
| 85 | #define OHCI_INTERRUPT_DISABLE 0x14 |
| 86 | #define OHCI_HCCA 0x18 |
| 87 | #define OHCI_PERIOD_CURRENT_ED 0x1c |
| 88 | #define OHCI_CONTROL_HEAD_ED 0x20 |
| 89 | #define OHCI_CONTROL_CURRENT_ED 0x24 |
| 90 | #define OHCI_BULK_HEAD_ED 0x28 |
| 91 | #define OHCI_BULK_CURRENT_ED 0x2c |
| 92 | #define OHCI_DONE_HEAD 0x30 |
| 93 | #define OHCI_FM_INTERVAL 0x34 |
| 94 | #define OHCI_GET_IVAL(s) ((s) & 0x3fff) |
| 95 | #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) |
| 96 | #define OHCI_FIT 0x80000000 |
| 97 | #define OHCI_FM_REMAINING 0x38 |
| 98 | #define OHCI_FM_NUMBER 0x3c |
| 99 | #define OHCI_PERIODIC_START 0x40 |
| 100 | #define OHCI_LS_THRESHOLD 0x44 |
| 101 | #define OHCI_RH_DESCRIPTOR_A 0x48 |
| 102 | #define OHCI_GET_NDP(s) ((s) & 0xff) |
| 103 | #define OHCI_PSM 0x0100 /* Power Switching Mode */ |
| 104 | #define OHCI_NPS 0x0200 /* No Power Switching */ |
| 105 | #define OHCI_DT 0x0400 /* Device Type */ |
| 106 | #define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ |
| 107 | #define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ |
| 108 | #define OHCI_GET_POTPGT(s) ((s) >> 24) |
| 109 | #define OHCI_POTPGT_MASK 0xff000000 |
| 110 | #define OHCI_RH_DESCRIPTOR_B 0x4c |
| 111 | #define OHCI_RH_STATUS 0x50 |
| 112 | #define OHCI_LPS 0x00000001 /* Local Power Status */ |
| 113 | #define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ |
| 114 | #define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ |
| 115 | #define OHCI_LPSC 0x00010000 /* Local Power Status Change */ |
| 116 | #define OHCI_CCIC 0x00020000 /* OverCurrent Indicator Change */ |
| 117 | #define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ |
| 118 | #define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */ |
| 119 | |
| 120 | #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) |
| 121 | #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \ |
| 122 | OHCI_FNO | OHCI_RHSC | OHCI_OC) |
| 123 | #define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) |
| 124 | |
| 125 | #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) |
| 126 | #define OHCI_PERIODIC(i) ((i)*9/10) |
| 127 | |
| 128 | typedef uint32_t ohci_physaddr_t; |
| 129 | |
| 130 | #define OHCI_NO_INTRS 32 |
| 131 | struct ohci_hcca { |
| 132 | volatile ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS]; |
| 133 | volatile uint32_t hcca_frame_number; |
| 134 | volatile ohci_physaddr_t hcca_done_head; |
| 135 | #define OHCI_DONE_INTRS 1 |
| 136 | }; |
| 137 | #define OHCI_HCCA_SIZE 256 |
| 138 | #define OHCI_HCCA_ALIGN 256 |
| 139 | |
| 140 | #define OHCI_PAGE_SIZE 0x1000 |
| 141 | #define OHCI_PAGE(x) ((x) &~ 0xfff) |
| 142 | #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) |
| 143 | |
| 144 | typedef struct { |
| 145 | volatile uint32_t ed_flags; |
| 146 | #define OHCI_ED_GET_FA(s) ((s) & 0x7f) |
| 147 | #define OHCI_ED_ADDRMASK 0x0000007f |
| 148 | #define OHCI_ED_SET_FA(s) (s) |
| 149 | #define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf) |
| 150 | #define OHCI_ED_SET_EN(s) ((s) << 7) |
| 151 | #define OHCI_ED_DIR_MASK 0x00001800 |
| 152 | #define OHCI_ED_DIR_TD 0x00000000 |
| 153 | #define OHCI_ED_DIR_OUT 0x00000800 |
| 154 | #define OHCI_ED_DIR_IN 0x00001000 |
| 155 | #define OHCI_ED_SPEED 0x00002000 |
| 156 | #define OHCI_ED_SKIP 0x00004000 |
| 157 | #define OHCI_ED_FORMAT_GEN 0x00000000 |
| 158 | #define OHCI_ED_FORMAT_ISO 0x00008000 |
| 159 | #define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff) |
| 160 | #define OHCI_ED_SET_MAXP(s) ((s) << 16) |
| 161 | #define OHCI_ED_MAXPMASK (0x7ff << 16) |
| 162 | volatile ohci_physaddr_t ed_tailp; |
| 163 | volatile ohci_physaddr_t ed_headp; |
| 164 | #define OHCI_HALTED 0x00000001 |
| 165 | #define OHCI_TOGGLECARRY 0x00000002 |
| 166 | #define OHCI_HEADMASK 0xfffffffc |
| 167 | volatile ohci_physaddr_t ed_nexted; |
| 168 | } ohci_ed_t; |
| 169 | /* #define OHCI_ED_SIZE 16 */ |
| 170 | #define OHCI_ED_ALIGN 16 |
| 171 | |
| 172 | typedef struct { |
| 173 | volatile uint32_t td_flags; |
| 174 | #define OHCI_TD_R 0x00040000 /* Buffer Rounding */ |
| 175 | #define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */ |
| 176 | #define OHCI_TD_SETUP 0x00000000 |
| 177 | #define OHCI_TD_OUT 0x00080000 |
| 178 | #define OHCI_TD_IN 0x00100000 |
| 179 | #define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ |
| 180 | #define OHCI_TD_SET_DI(x) ((x) << 21) |
| 181 | #define OHCI_TD_NOINTR 0x00e00000 |
| 182 | #define OHCI_TD_INTR_MASK 0x00e00000 |
| 183 | #define OHCI_TD_TOGGLE_CARRY 0x00000000 |
| 184 | #define OHCI_TD_TOGGLE_0 0x02000000 |
| 185 | #define OHCI_TD_TOGGLE_1 0x03000000 |
| 186 | #define OHCI_TD_TOGGLE_MASK 0x03000000 |
| 187 | #define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */ |
| 188 | #define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */ |
| 189 | #define OHCI_TD_NOCC 0xf0000000 |
| 190 | volatile ohci_physaddr_t td_cbp; /* Current Buffer Pointer */ |
| 191 | volatile ohci_physaddr_t td_nexttd; /* Next TD */ |
| 192 | volatile ohci_physaddr_t td_be; /* Buffer End */ |
| 193 | } ohci_td_t; |
| 194 | /* #define OHCI_TD_SIZE 16 */ |
| 195 | #define OHCI_TD_ALIGN 16 |
| 196 | |
| 197 | #define OHCI_ITD_NOFFSET 8 |
| 198 | typedef struct { |
| 199 | volatile uint32_t itd_flags; |
| 200 | #define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff) |
| 201 | #define OHCI_ITD_SET_SF(x) ((x) & 0xffff) |
| 202 | #define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */ |
| 203 | #define OHCI_ITD_SET_DI(x) ((x) << 21) |
| 204 | #define OHCI_ITD_NOINTR 0x00e00000 |
| 205 | #define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */ |
| 206 | #define OHCI_ITD_SET_FC(x) (((x)-1) << 24) |
| 207 | #define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */ |
| 208 | #define OHCI_ITD_NOCC 0xf0000000 |
| 209 | volatile ohci_physaddr_t itd_bp0; /* Buffer Page 0 */ |
| 210 | volatile ohci_physaddr_t itd_nextitd; /* Next ITD */ |
| 211 | volatile ohci_physaddr_t itd_be; /* Buffer End */ |
| 212 | volatile uint16_t itd_offset[OHCI_ITD_NOFFSET];/* Buffer offsets */ |
| 213 | #define itd_pswn itd_offset /* Packet Status Word*/ |
| 214 | #define OHCI_ITD_PAGE_SELECT 0x00001000 |
| 215 | #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) |
| 216 | #define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */ |
| 217 | #define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */ |
| 218 | } ohci_itd_t; |
| 219 | /* #define OHCI_ITD_SIZE 32 */ |
| 220 | #define OHCI_ITD_ALIGN 32 |
| 221 | |
| 222 | |
| 223 | #define OHCI_CC_NO_ERROR 0 |
| 224 | #define OHCI_CC_CRC 1 |
| 225 | #define OHCI_CC_BIT_STUFFING 2 |
| 226 | #define OHCI_CC_DATA_TOGGLE_MISMATCH 3 |
| 227 | #define OHCI_CC_STALL 4 |
| 228 | #define OHCI_CC_DEVICE_NOT_RESPONDING 5 |
| 229 | #define OHCI_CC_PID_CHECK_FAILURE 6 |
| 230 | #define OHCI_CC_UNEXPECTED_PID 7 |
| 231 | #define OHCI_CC_DATA_OVERRUN 8 |
| 232 | #define OHCI_CC_DATA_UNDERRUN 9 |
| 233 | #define OHCI_CC_BUFFER_OVERRUN 12 |
| 234 | #define OHCI_CC_BUFFER_UNDERRUN 13 |
| 235 | #define OHCI_CC_NOT_ACCESSED 14 |
| 236 | #define OHCI_CC_NOT_ACCESSED_MASK 14 |
| 237 | |
| 238 | /* Some delay needed when changing certain registers. */ |
| 239 | #define OHCI_ENABLE_POWER_DELAY 5 |
| 240 | #define OHCI_READ_DESC_DELAY 5 |
| 241 | |
| 242 | #endif /* _DEV_USB_OHCIREG_H_ */ |
| 243 | |