| 1 | /* $NetBSD: if_urlreg.h,v 1.11 2016/04/23 10:15:31 skrll Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 2001, 2002 |
| 4 | * Shingo WATANABE <nabe@nabechan.org>. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. Neither the name of the author nor the names of any co-contributors |
| 15 | * may be used to endorse or promote products derived from this software |
| 16 | * without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | * |
| 30 | */ |
| 31 | |
| 32 | #include <sys/rndsource.h> |
| 33 | |
| 34 | #define URL_IFACE_INDEX 0 |
| 35 | #define URL_CONFIG_NO 1 |
| 36 | |
| 37 | #define URL_TX_LIST_CNT 1 |
| 38 | #define URL_RX_LIST_CNT 1 |
| 39 | |
| 40 | #define URL_TX_TIMEOUT 1000 |
| 41 | #define URL_TIMEOUT 10000 |
| 42 | |
| 43 | #define ETHER_ALIGN 2 |
| 44 | |
| 45 | |
| 46 | /* Packet length */ |
| 47 | #define URL_MAX_MTU 1536 |
| 48 | #define URL_MIN_FRAME_LEN 60 |
| 49 | #define URL_BUFSZ URL_MAX_MTU |
| 50 | |
| 51 | /* Request */ |
| 52 | #define URL_REQ_MEM 0x05 |
| 53 | |
| 54 | #define URL_CMD_READMEM 1 |
| 55 | #define URL_CMD_WRITEMEM 2 |
| 56 | |
| 57 | /* Registers */ |
| 58 | #define URL_IDR0 0x0120 /* Ethernet Address, load from 93C46 */ |
| 59 | #define URL_IDR1 0x0121 /* Ethernet Address, load from 93C46 */ |
| 60 | #define URL_IDR2 0x0122 /* Ethernet Address, load from 93C46 */ |
| 61 | #define URL_IDR3 0x0123 /* Ethernet Address, load from 93C46 */ |
| 62 | #define URL_IDR4 0x0124 /* Ethernet Address, load from 93C46 */ |
| 63 | #define URL_IDR5 0x0125 /* Ethernet Address, load from 93C46 */ |
| 64 | |
| 65 | #define URL_MAR0 0x0126 /* Multicast register */ |
| 66 | #define URL_MAR1 0x0127 /* Multicast register */ |
| 67 | #define URL_MAR2 0x0128 /* Multicast register */ |
| 68 | #define URL_MAR3 0x0129 /* Multicast register */ |
| 69 | #define URL_MAR4 0x012a /* Multicast register */ |
| 70 | #define URL_MAR5 0x012b /* Multicast register */ |
| 71 | #define URL_MAR6 0x012c /* Multicast register */ |
| 72 | #define URL_MAR7 0x012d /* Multicast register */ |
| 73 | #define URL_MAR URL_MAR0 |
| 74 | |
| 75 | #define URL_CR 0x012e /* Command Register */ |
| 76 | #define URL_CR_WEPROM (1<<5) /* EEPROM Write Enable */ |
| 77 | #define URL_CR_SOFT_RST (1<<4) /* Software Reset */ |
| 78 | #define URL_CR_RE (1<<3) /* Ethernet Receive Enable */ |
| 79 | #define URL_CR_TE (1<<2) /* Ethernet Transmit Enable */ |
| 80 | #define URL_CR_EP3CLREN (1<<1) /* Enable clearing the performance counter */ |
| 81 | #define URL_CR_AUTOLOAD (1<<0) /* Auto-load the contents of 93C46 */ |
| 82 | |
| 83 | #define URL_TCR 0x012f /* Transmit Control Register */ |
| 84 | #define URL_TCR_TXRR1 (1<<7) /* TX Retry Count */ |
| 85 | #define URL_TCR_TXRR0 (1<<6) /* TX Retry Count */ |
| 86 | #define URL_TCR_IFG1 (1<<4) /* Interframe Gap Time */ |
| 87 | #define URL_TCR_IFG0 (1<<4) /* Interframe Gap Time */ |
| 88 | #define URL_TCR_NOCRC (1<<0) /* no CRC Append */ |
| 89 | |
| 90 | #define URL_RCR 0x0130 /* Receive Configuration Register */ |
| 91 | #define URL_RCR_TAIL (1<<7) |
| 92 | #define URL_RCR_AER (1<<6) |
| 93 | #define URL_RCR_AR (1<<5) |
| 94 | #define URL_RCR_AM (1<<4) |
| 95 | #define URL_RCR_AB (1<<3) |
| 96 | #define URL_RCR_AD (1<<2) |
| 97 | #define URL_RCR_AAM (1<<1) |
| 98 | #define URL_RCR_AAP (1<<0) |
| 99 | |
| 100 | #define URL_MSR 0x137 /* Media Status Register */ |
| 101 | #define URL_MSR_TXFCE (1<<7) |
| 102 | #define URL_MSR_RXFCE (1<<6) |
| 103 | #define URL_MSR_DUPLEX (1<<4) |
| 104 | #define URL_MSR_SPEED_100 (1<<3) |
| 105 | #define URL_MSR_LINK (1<<2) |
| 106 | #define URL_MSR_TXPF (1<<1) |
| 107 | #define URL_MSR_RXPF (1<<0) |
| 108 | |
| 109 | #define URL_PHYADD 0x138 /* MII PHY Address select */ |
| 110 | #define URL_PHYADD_MASK 0x1f /* MII PHY Address select */ |
| 111 | |
| 112 | #define URL_PHYDAT 0x139 /* MII PHY data */ |
| 113 | |
| 114 | #define URL_PHYCNT 0x13b /* MII PHY control */ |
| 115 | #define URL_PHYCNT_PHYOWN (1<<6) /* Own bit */ |
| 116 | #define URL_PHYCNT_RWCR (1<<5) /* MII management data R/W control */ |
| 117 | #define URL_PHY_PHYOFF_MASK 0x1f /* PHY register offset */ |
| 118 | |
| 119 | #define URL_BMCR 0x140 /* Basic mode control register */ |
| 120 | #define URL_BMSR 0x142 /* Basic mode status register */ |
| 121 | #define URL_ANAR 0x144 /* Auto-negotiation advertisement register */ |
| 122 | #define URL_ANLP 0x146 /* Auto-negotiation link partner ability register */ |
| 123 | |
| 124 | |
| 125 | typedef uWord url_rxhdr_t; /* Recive Header */ |
| 126 | #define URL_RXHDR_BYTEC_MASK (0x0fff) /* RX bytes count */ |
| 127 | #define URL_RXHDR_VALID_MASK (0x1000) /* Valid packet */ |
| 128 | #define URL_RXHDR_RUNTPKT_MASK (0x2000) /* Runt packet */ |
| 129 | #define URL_RXHDR_PHYPKT_MASK (0x4000) /* Physical match packet */ |
| 130 | #define URL_RXHDR_MCASTPKT_MASK (0x8000) /* Multicast packet */ |
| 131 | |
| 132 | #define GET_IFP(sc) (&(sc)->sc_ec.ec_if) |
| 133 | #define GET_MII(sc) (&(sc)->sc_mii) |
| 134 | |
| 135 | struct url_chain { |
| 136 | struct url_softc *url_sc; |
| 137 | struct usbd_xfer *url_xfer; |
| 138 | char *url_buf; |
| 139 | struct mbuf *url_mbuf; |
| 140 | int url_idx; |
| 141 | }; |
| 142 | |
| 143 | struct url_cdata { |
| 144 | struct url_chain url_tx_chain[URL_TX_LIST_CNT]; |
| 145 | struct url_chain url_rx_chain[URL_TX_LIST_CNT]; |
| 146 | #if 0 |
| 147 | /* XXX: Interrupt Endpoint is not yet supported! */ |
| 148 | struct url_intrpkg url_ibuf; |
| 149 | #endif |
| 150 | int url_tx_prod; |
| 151 | int url_tx_cons; |
| 152 | int url_tx_cnt; |
| 153 | int url_rx_prod; |
| 154 | }; |
| 155 | |
| 156 | struct url_softc { |
| 157 | device_t sc_dev; /* base device */ |
| 158 | struct usbd_device * sc_udev; |
| 159 | |
| 160 | /* USB */ |
| 161 | struct usbd_interface * sc_ctl_iface; |
| 162 | /* int sc_ctl_iface_no; */ |
| 163 | int sc_bulkin_no; /* bulk in endpoint */ |
| 164 | int sc_bulkout_no; /* bulk out endpoint */ |
| 165 | int sc_intrin_no; /* intr in endpoint */ |
| 166 | struct usbd_pipe * sc_pipe_rx; |
| 167 | struct usbd_pipe * sc_pipe_tx; |
| 168 | struct usbd_pipe * sc_pipe_intr; |
| 169 | struct callout sc_stat_ch; |
| 170 | u_int sc_rx_errs; |
| 171 | /* u_int sc_intr_errs; */ |
| 172 | struct timeval sc_rx_notice; |
| 173 | |
| 174 | /* Ethernet */ |
| 175 | struct ethercom sc_ec; /* ethernet common */ |
| 176 | struct mii_data sc_mii; |
| 177 | krwlock_t sc_mii_rwlock; |
| 178 | int sc_link; |
| 179 | #define sc_media url_mii.mii_media |
| 180 | krndsource_t rnd_source; |
| 181 | struct url_cdata sc_cdata; |
| 182 | |
| 183 | int sc_attached; |
| 184 | int sc_dying; |
| 185 | int sc_refcnt; |
| 186 | |
| 187 | struct usb_task sc_tick_task; |
| 188 | struct usb_task sc_stop_task; |
| 189 | |
| 190 | uint16_t sc_flags; |
| 191 | }; |
| 192 | |