| 1 | /* $NetBSD: smc91cxxreg.h,v 1.5 2003/04/29 08:47:30 scw Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. All advertising materials mentioning features or use of this software |
| 16 | * must display the following acknowledgement: |
| 17 | * This product includes software developed by Gardner Buchanan. |
| 18 | * 4. The name of Gardner Buchanan may not be used to endorse or promote |
| 19 | * products derived from this software without specific prior written |
| 20 | * permission. |
| 21 | * |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 24 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 25 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | * |
| 33 | * from FreeBSD Id: if_snreg.h,v 1.4 1996/03/18 15:47:30 gardner Exp |
| 34 | */ |
| 35 | |
| 36 | /* |
| 37 | * This file contains register information and access macros for |
| 38 | * the SMC91xxx chipset. |
| 39 | * |
| 40 | * Information contained in this file was obtained from the SMC91C92 |
| 41 | * and SMC91C94 manuals from SMC. You will need one of these in order |
| 42 | * to make any meaningful changes to this driver. Information about |
| 43 | * obtaining one can be found at http://www.smc.com in the components |
| 44 | * division. |
| 45 | * |
| 46 | * This FreeBSD driver is derived in part from the smc9194 Linux driver |
| 47 | * by Erik Stahlman. |
| 48 | */ |
| 49 | |
| 50 | |
| 51 | /* |
| 52 | * Wait time for memory to be free. This probably shouldn't be |
| 53 | * tuned that much, as waiting for this means nothing else happens |
| 54 | * in the system |
| 55 | */ |
| 56 | #define MEMORY_WAIT_TIME 1000 |
| 57 | |
| 58 | |
| 59 | /* The SMC91xxx uses 16 I/O ports */ |
| 60 | #define SMC_IOSIZE 16 |
| 61 | |
| 62 | |
| 63 | /* |
| 64 | * A description of the SMC registers is probably in order here, |
| 65 | * although for details, the SMC datasheet is invaluable. |
| 66 | * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet |
| 67 | * Controller With RAM", Rev. 12/0/94. Constant definitions I give |
| 68 | * here are loosely based on the mnemonic names given to them in the |
| 69 | * data sheet, but there are many exceptions. |
| 70 | * |
| 71 | * Basically, the chip has 4 banks of registers (0 to 3), which |
| 72 | * are accessed by writing a number into the BANK_SELECT register |
| 73 | * (I also use a SMC_SELECT_BANK macro for this). Registers are |
| 74 | * either Byte or Word sized. My constant definitions end in _B |
| 75 | * or _W as appropriate. |
| 76 | * |
| 77 | * The banks are arranged so that for most purposes, bank 2 is all |
| 78 | * that is needed for normal run time tasks. |
| 79 | */ |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * Bank Select Register. This also doubles as |
| 84 | * a chip identification register. This register |
| 85 | * is mapped at the same position in all banks. |
| 86 | */ |
| 87 | #define BANK_SELECT_REG_W 0x0e |
| 88 | #define BSR_DETECT_MASK 0xff00 |
| 89 | #define BSR_DETECT_VALUE 0x3300 |
| 90 | |
| 91 | |
| 92 | /* |
| 93 | * BANK 0 |
| 94 | */ |
| 95 | |
| 96 | /* |
| 97 | * Transmit Control Register controls some aspects of the transmit |
| 98 | * behavior of the Ethernet Protocol Handler. |
| 99 | */ |
| 100 | #define TXMIT_CONTROL_REG_W 0x00 |
| 101 | |
| 102 | #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
| 103 | #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */ |
| 104 | #define TCR_FORCOL 0x0004 /* Force Collision on next TX */ |
| 105 | #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */ |
| 106 | #define TCR_NOCRC 0x0100 /* Do not append CRC */ |
| 107 | #define TCR_MON_CSN 0x0400 /* monitors the carrier status */ |
| 108 | #define TCR_FDUPLX 0x0800 /* receive packets sent out */ |
| 109 | #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ |
| 110 | #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */ |
| 111 | #define TCR_SWFDUP 0x8000 /* FEAST: Switched full-duplex (only w/ MII) */ |
| 112 | |
| 113 | |
| 114 | /* |
| 115 | * Status of the last transmitted frame and instantaneous status of |
| 116 | * the Ethernet Protocol Handler jumbled together. In auto-release |
| 117 | * mode this information is simply discarded after each TX. This info |
| 118 | * is copied to the status word of in-memory packets after transmit |
| 119 | * where relevent statuses can be checked. |
| 120 | */ |
| 121 | #define EPH_STATUS_REG_W 0x02 |
| 122 | |
| 123 | #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */ |
| 124 | #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */ |
| 125 | #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */ |
| 126 | #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */ |
| 127 | #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */ |
| 128 | #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */ |
| 129 | #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */ |
| 130 | #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */ |
| 131 | #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */ |
| 132 | #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */ |
| 133 | #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER |
| 134 | * times */ |
| 135 | #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */ |
| 136 | #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */ |
| 137 | #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */ |
| 138 | #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ |
| 139 | |
| 140 | |
| 141 | /* |
| 142 | * Receiver Control Register controls some aspects of the receive |
| 143 | * behavior of the Ethernet Protocol Handler. |
| 144 | */ |
| 145 | #define RECV_CONTROL_REG_W 0x04 |
| 146 | |
| 147 | #define RCR_RX_ABORT 0x0001 /* Received huge packet */ |
| 148 | #define RCR_PROMISC 0x0002 /* enable promiscuous mode */ |
| 149 | #define RCR_ALMUL 0x0004 /* receive all multicast packets */ |
| 150 | #define RCR_ENABLE 0x0100 /* IFF this is set, we can receive packets */ |
| 151 | #define RCR_STRIP_CRC 0x0200 /* strips CRC */ |
| 152 | #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */ |
| 153 | #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */ |
| 154 | #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */ |
| 155 | |
| 156 | |
| 157 | /* |
| 158 | * TX Statistics counters |
| 159 | */ |
| 160 | #define COUNTER_REG_W 0x06 |
| 161 | |
| 162 | #define ECR_COLN_MASK 0x000f /* Vanilla collisions */ |
| 163 | #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */ |
| 164 | #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */ |
| 165 | #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */ |
| 166 | |
| 167 | |
| 168 | /* |
| 169 | * Memory Information |
| 170 | */ |
| 171 | #define MEM_INFO_REG_W 0x08 |
| 172 | |
| 173 | #define MIR_FREE_MASK 0xff00 /* Free memory pages available */ |
| 174 | #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */ |
| 175 | #define MIR_MULT_91C111 1 |
| 176 | #define MIR_SCALE_91C9x 256 |
| 177 | #define MIR_SCALE_91C111 2048 |
| 178 | |
| 179 | |
| 180 | /* |
| 181 | * Memory Configuration |
| 182 | */ |
| 183 | #define MEM_CFG_REG_W 0x0a |
| 184 | |
| 185 | #define MCR_MEM_MULT(x) (((x)>>9)&7) /* Memory size multiplier */ |
| 186 | #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */ |
| 187 | |
| 188 | /* |
| 189 | * Receive/PHY Control Register (SM91C111 only) |
| 190 | */ |
| 191 | #define RX_PHY_CONTROL_REG_W 0x0a /* 91C111 only */ |
| 192 | |
| 193 | #define RPC_LSB_SHIFT 2 /* Shift for LED-B select bits */ |
| 194 | #define RPC_LSA_SHIFT 5 /* Shift for LED-A select bits */ |
| 195 | #define RPC_LS_MASK 0x7 /* LED Select mask */ |
| 196 | #define RPC_LS_LINK_DETECT 0x0 /* 10/100 link detected */ |
| 197 | #define RPC_LS_LINK_10MBPS 0x2 /* 10 MBPS link detected */ |
| 198 | #define RPC_LS_FULL_DUPLEX 0x3 /* Full duplex operation */ |
| 199 | #define RPC_LS_TXRX 0x4 /* Tx/Rx packet */ |
| 200 | #define RPC_LS_LINK_100MBPS 0x5 /* 100 MBPS link detected */ |
| 201 | #define RPC_LS_RX 0x6 /* Rx packet */ |
| 202 | #define RPC_LS_TX 0x7 /* Tx packet */ |
| 203 | #define RPC_ANEG 0x0800 /* Autonegotiate enable */ |
| 204 | #define RPC_DPLX 0x1000 /* Duplex select (set = Full) */ |
| 205 | #define RPC_SPEED 0x2000 /* Speed (set = 100mbps) */ |
| 206 | |
| 207 | |
| 208 | /* |
| 209 | * Bank 0, Register 0x0c is unused in the SMC91C92 |
| 210 | */ |
| 211 | |
| 212 | |
| 213 | /* |
| 214 | * BANK 1 |
| 215 | */ |
| 216 | |
| 217 | /* |
| 218 | * Adapter configuration |
| 219 | */ |
| 220 | #define CONFIG_REG_W 0x00 |
| 221 | |
| 222 | #define CR_INT_SEL0 0x0002 /* Interrupt selector */ |
| 223 | #define CR_INT_SEL1 0x0004 /* Interrupt selector */ |
| 224 | #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */ |
| 225 | #define CR_16BIT 0x0080 /* Bus width */ |
| 226 | #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */ |
| 227 | #define CR_SET_SQLCH 0x0200 /* Squelch level */ |
| 228 | #define CR_FULL_STEP 0x0400 /* AUI signalling mode */ |
| 229 | #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */ |
| 230 | #define CR_MII_SELECT 0x8000 /* FEAST: MII port selected */ |
| 231 | |
| 232 | |
| 233 | /* |
| 234 | * The contents of this port are used by the adapter |
| 235 | * to decode its I/O address. We use it as a varification |
| 236 | * that the adapter is detected properly when probing. |
| 237 | */ |
| 238 | #define BASE_ADDR_REG_W 0x02 /* The selected I/O Base addr. */ |
| 239 | |
| 240 | |
| 241 | /* |
| 242 | * These registers hold the Ethernet MAC address. |
| 243 | */ |
| 244 | #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */ |
| 245 | #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */ |
| 246 | #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */ |
| 247 | |
| 248 | |
| 249 | /* |
| 250 | * General purpose register used for talking to the EEPROM. |
| 251 | */ |
| 252 | #define GENERAL_REG_W 0x0a |
| 253 | |
| 254 | |
| 255 | /* |
| 256 | * Control register used for talking to the EEPROM and |
| 257 | * setting some EPH functions. |
| 258 | */ |
| 259 | #define CONTROL_REG_W 0x0c |
| 260 | |
| 261 | #define CTR_STORE 0x0001 /* Store something to EEPROM */ |
| 262 | #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */ |
| 263 | #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */ |
| 264 | #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */ |
| 265 | #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */ |
| 266 | #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */ |
| 267 | #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */ |
| 268 | #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */ |
| 269 | #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */ |
| 270 | |
| 271 | |
| 272 | /* |
| 273 | * BANK 2 |
| 274 | */ |
| 275 | |
| 276 | |
| 277 | /* |
| 278 | * Memory Management Unit Control Register |
| 279 | * Controls allocation of memory to receive and |
| 280 | * transmit functions. |
| 281 | */ |
| 282 | #define MMU_CMD_REG_W 0x00 |
| 283 | |
| 284 | #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */ |
| 285 | |
| 286 | /* |
| 287 | * MMU Commands: |
| 288 | */ |
| 289 | #define MMUCR_NOP 0x0000 /* Do nothing */ |
| 290 | #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */ |
| 291 | #define MMUCR_RESET 0x0040 /* Reset MMU State */ |
| 292 | #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */ |
| 293 | #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */ |
| 294 | #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */ |
| 295 | #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */ |
| 296 | #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */ |
| 297 | |
| 298 | /* |
| 299 | * Packet Number at TX Area |
| 300 | */ |
| 301 | #define PACKET_NUM_REG_B 0x02 |
| 302 | |
| 303 | /* |
| 304 | * Packet number resulting from MMUCR_ALLOC |
| 305 | */ |
| 306 | #define ALLOC_RESULT_REG_B 0x03 |
| 307 | #define ARR_FAILED 0x80 |
| 308 | |
| 309 | /* |
| 310 | * Transmit and receive queue heads |
| 311 | */ |
| 312 | #define FIFO_PORTS_REG_W 0x04 |
| 313 | #define FIFO_REMPTY 0x8000 |
| 314 | #define FIFO_TEMPTY 0x0080 |
| 315 | #define FIFO_RX_MASK 0x7f00 |
| 316 | #define FIFO_TX_MASK 0x007f |
| 317 | |
| 318 | |
| 319 | /* |
| 320 | * The address within the packet for reading/writing. The |
| 321 | * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number |
| 322 | * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK. |
| 323 | * When PTR_RCV==0, the packet number to be written is found |
| 324 | * in the PACKET_NUM_REG_B. |
| 325 | */ |
| 326 | #define POINTER_REG_W 0x06 |
| 327 | |
| 328 | #define PTR_READ 0x2000 /* Intended access mode */ |
| 329 | #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */ |
| 330 | #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */ |
| 331 | |
| 332 | /* |
| 333 | * Data I/O register to be used in conjunction with |
| 334 | * The pointer register to read and write data from the |
| 335 | * card. The same register can be used for byte and word |
| 336 | * ops. |
| 337 | */ |
| 338 | #define DATA_REG_W 0x08 |
| 339 | #define DATA_REG_B 0x08 |
| 340 | #define DATA_1_REG_B 0x08 |
| 341 | #define DATA_2_REG_B 0x0a |
| 342 | |
| 343 | |
| 344 | /* |
| 345 | * Sense interrupt status (READ) |
| 346 | */ |
| 347 | #define INTR_STAT_REG_B 0x0c |
| 348 | |
| 349 | |
| 350 | /* |
| 351 | * Acknowledge interrupt sources (WRITE) |
| 352 | */ |
| 353 | #define INTR_ACK_REG_B 0x0c |
| 354 | |
| 355 | |
| 356 | /* |
| 357 | * Interrupt mask. Bit set indicates interrupt allowed. |
| 358 | */ |
| 359 | #define INTR_MASK_REG_B 0x0d |
| 360 | |
| 361 | /* |
| 362 | * Interrupts |
| 363 | */ |
| 364 | #define IM_RCV_INT 0x01 /* A packet has been received */ |
| 365 | #define IM_TX_INT 0x02 /* Packet TX complete */ |
| 366 | #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */ |
| 367 | #define IM_ALLOC_INT 0x08 /* Memory allocation completed */ |
| 368 | #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */ |
| 369 | #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */ |
| 370 | #define IM_ERCV_INT 0x40 /* not on SMC9192 */ |
| 371 | #define IM_MD_INT 0x80 /* SMC91C111 Internal PHY status change */ |
| 372 | |
| 373 | |
| 374 | /* |
| 375 | * BANK 3 |
| 376 | */ |
| 377 | |
| 378 | |
| 379 | /* |
| 380 | * Multicast subscriptions. |
| 381 | * The multicast handling in the SMC90Cxx is quite complicated. A table |
| 382 | * of multicast address subscriptions is provided and a clever way of |
| 383 | * speeding the search of that table by hashing is implemented in the |
| 384 | * hardware. I have ignored this and simply subscribed to all multicasts |
| 385 | * and let the kernel deal with the results. |
| 386 | */ |
| 387 | #define MULTICAST1_REG_W 0x00 |
| 388 | #define MULTICAST2_REG_W 0x02 |
| 389 | #define MULTICAST3_REG_W 0x04 |
| 390 | #define MULTICAST4_REG_W 0x06 |
| 391 | |
| 392 | /* |
| 393 | * These registers do not exist on SMC9192, or at least |
| 394 | * are not documented in the SMC91C92 data sheet. |
| 395 | * |
| 396 | * The REVISION_REG_W register does however seem to work. |
| 397 | * |
| 398 | * On the FEAST, the low nibble controls the MII interface. |
| 399 | */ |
| 400 | #define MGMT_REG_W 0x08 |
| 401 | |
| 402 | #define MR_MDOE 0x08 |
| 403 | #define MR_MCLK 0x04 |
| 404 | #define MR_MDI 0x02 |
| 405 | #define MR_MDO 0x01 |
| 406 | |
| 407 | #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */ |
| 408 | #define RR_REV(x) ((x) & 0x0f) |
| 409 | #define RR_ID(x) (((x) >> 4) & 0x0f) |
| 410 | |
| 411 | #define ERCV_REG_W 0x0c |
| 412 | |
| 413 | /* |
| 414 | * These are constants expected to be found in the |
| 415 | * chip id register. |
| 416 | */ |
| 417 | #define CHIP_9190 3 |
| 418 | #define CHIP_9194 4 |
| 419 | #define CHIP_9195 5 |
| 420 | #define CHIP_91100 7 |
| 421 | #define CHIP_91100FD 8 |
| 422 | #define CHIP_91C111 9 |
| 423 | |
| 424 | |
| 425 | /* |
| 426 | * When packets are stuffed into the card or sucked out of the card |
| 427 | * they are set up more or less as follows: |
| 428 | * |
| 429 | * Addr msbyte lsbyte |
| 430 | * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status |
| 431 | * 02 RRRRR - RESERVED (unused) |
| 432 | * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored) |
| 433 | * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS |
| 434 | * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address) |
| 435 | * 08 DDDDDDDD DDDDDDDD |
| 436 | * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS |
| 437 | * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address) |
| 438 | * 0E SSSSSSSS SSSSSSSS |
| 439 | * 10 PPPPPPPP PPPPPPPP |
| 440 | * .. PPPPPPPP PPPPPPPP |
| 441 | * C-2 CCCCCCCC - CONTROL BYTE |
| 442 | * C-2 PPPPPPPP - Last data byte (If odd length) |
| 443 | * |
| 444 | * The STATUS_WORD is derived from the EPH_STATUS_REG_W register |
| 445 | * during transmit and is composed of another set of bits described |
| 446 | * below during receive. |
| 447 | */ |
| 448 | |
| 449 | |
| 450 | /* |
| 451 | * Receive status bits. These values are found in the status word |
| 452 | * field of a received packet. For receive packets I use the RS_ODDFRAME |
| 453 | * to detect whether a frame has an extra byte on it. The CTLB_ODD |
| 454 | * bit of the control byte tells the same thing. |
| 455 | */ |
| 456 | #define RS_MULTICAST 0x0001 /* Packet is multicast */ |
| 457 | #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ |
| 458 | #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ |
| 459 | #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ |
| 460 | #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ |
| 461 | #define RS_BADCRC 0x2000 /* Frame had CRC error */ |
| 462 | #define RS_ALGNERR 0x8000 /* Frame had alignment error */ |
| 463 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
| 464 | |
| 465 | #define RLEN_MASK 0x07ff /* Significant length bits in RX length */ |
| 466 | |
| 467 | /* |
| 468 | * The control byte has the following significant bits. |
| 469 | * For transmit, the CTLB_ODD bit specifies whether an extra byte |
| 470 | * is present in the frame. Bit 0 of the byte count field is |
| 471 | * ignored. I just pad every frame to even length and forget about |
| 472 | * it. |
| 473 | */ |
| 474 | #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */ |
| 475 | #define CTLB_ODD 0x20 /* The packet length is ODD */ |
| 476 | |