| 1 | /* $NetBSD: pciide_sis_reg.h,v 1.16 2009/10/19 18:41:16 bouyer Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 1998 Manuel Bouyer. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * Registers definitions for SiS SiS5597/98 PCI IDE controller. |
| 30 | * Available from http://www.sis.com.tw/html/databook.html |
| 31 | */ |
| 32 | |
| 33 | /* IDE timing control registers (32 bits), for all but 96x */ |
| 34 | #define SIS_TIM(channel) (0x40 + (channel * 4)) |
| 35 | /* for 730, 630 and older (66, 100OLD) */ |
| 36 | #define SIS_TIM66_REC_OFF(drive) (16 * (drive)) |
| 37 | #define SIS_TIM66_ACT_OFF(drive) (8 + 16 * (drive)) |
| 38 | #define SIS_TIM66_UDMA_TIME_OFF(drive) (12 + 16 * (drive)) |
| 39 | /* for older than 96x (100NEW, 133OLD) */ |
| 40 | #define SIS_TIM100_REC_OFF(drive) (16 * (drive)) |
| 41 | #define SIS_TIM100_ACT_OFF(drive) (4 + 16 * (drive)) |
| 42 | #define SIS_TIM100_UDMA_TIME_OFF(drive) (8 + 16 * (drive)) |
| 43 | |
| 44 | /* |
| 45 | * From FreeBSD: on 96x, the timing registers may start from 0x40 or 0x70 |
| 46 | * depending on the value from register 0x57. 32bits of timing info for |
| 47 | * each drive. |
| 48 | */ |
| 49 | #define SIS_TIM133(reg57, channel, drive) \ |
| 50 | ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2)) |
| 51 | |
| 52 | /* IDE general control register 0 (8 bits) */ |
| 53 | #define SIS_CTRL0 0x4a |
| 54 | #define SIS_CTRL0_PCIBURST 0x80 |
| 55 | #define SIS_CTRL0_FAST_PW 0x20 |
| 56 | #define SIS_CTRL0_BO 0x08 |
| 57 | #define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */ |
| 58 | #define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */ |
| 59 | |
| 60 | /* IDE general control register 1 (8 bits) */ |
| 61 | #define SIS_CTRL1 0x4b |
| 62 | #define SIS_CTRL1_POSTW_EN(chan, drv) (0x10 << ((drv) + 2 * (chan))) |
| 63 | #define SIS_CTRL1_PREFETCH_EN(chan, drv) (0x01 << ((drv) + 2 * (chan))) |
| 64 | |
| 65 | /* IDE misc control register (8 bit) */ |
| 66 | #define SIS_MISC 0x52 |
| 67 | #define SIS_MISC_TIM_SEL 0x08 |
| 68 | #define SIS_MISC_GTC 0x04 |
| 69 | #define SIS_MISC_FIFO_SIZE 0x01 |
| 70 | |
| 71 | /* following are from FreeBSD (sorry, no description) */ |
| 72 | #define SIS_REG_49 0x49 |
| 73 | #define SIS_REG_50 0x50 |
| 74 | #define SIS_REG_51 0x51 |
| 75 | #define SIS_REG_52 0x52 |
| 76 | #define SIS_REG_53 0x53 |
| 77 | #define SIS_REG_57 0x57 |
| 78 | |
| 79 | #define SIS_REG_CBL 0x48 |
| 80 | #define SIS_REG_CBL_33(channel) (0x10 << (channel)) |
| 81 | #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2) |
| 82 | #define SIS96x_REG_CBL_33 0x80 |
| 83 | |
| 84 | /* SIS96x: when bit 7 in reg 0x40 is 0, the device masquerade as a SIS503 */ |
| 85 | #define SIS96x_DETECT 0x40 |
| 86 | #define SIS96x_DETECT_MASQ 0x40 |
| 87 | |
| 88 | #define SIS_PRODUCT_5518 0x5518 |
| 89 | |
| 90 | /* timings values, mostly from FreeBSD */ |
| 91 | /* PIO timings, for all up to 133NEW */ |
| 92 | static const u_int8_t sis_pio_act[] __unused = |
| 93 | {12, 6, 4, 3, 3}; |
| 94 | static const u_int8_t sis_pio_rec[] __unused = |
| 95 | {11, 7, 4, 3, 1}; |
| 96 | /* DMA timings for 66 and 100OLD */ |
| 97 | static const u_int8_t sis_udma66_tim[] __unused = |
| 98 | {15, 13, 11, 10, 9, 8}; |
| 99 | /* DMA timings for 100NEW */ |
| 100 | static const u_int8_t sis_udma100new_tim[] __unused = |
| 101 | {0x8b, 0x87, 0x85, 0x84, 0x82, 0x81}; |
| 102 | /* DMA timings for 133OLD */ |
| 103 | static const u_int8_t sis_udma133old_tim[] __unused = |
| 104 | {0x8f, 0x8a, 0x87, 0x85, 0x83, 0x82, 0x81}; |
| 105 | /* PIO, DMA and UDMA timings for 133NEW */ |
| 106 | static const u_int32_t sis_pio133new_tim[] __unused = |
| 107 | {0x28269008, 0x0c266008, 0x4263008, 0x0c0a3008, 0x05093008}; |
| 108 | static const u_int32_t sis_dma133new_tim[] __unused = |
| 109 | {0x22196008, 0x0c0a3008, 0x05093008}; |
| 110 | static const u_int32_t sis_udma133new_tim[] __unused = |
| 111 | {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214}; |
| 112 | |