| 1 | /* |
| 2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
| 3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | * |
| 17 | * $Id: ar5416desc.h,v 1.2 2013/06/25 15:08:43 joerg Exp $ |
| 18 | */ |
| 19 | #ifndef _ATH_AR5416_DESC_H_ |
| 20 | #define _ATH_AR5416_DESC_H_ |
| 21 | |
| 22 | /* |
| 23 | * Hardware-specific descriptor structures. |
| 24 | */ |
| 25 | #include "ah_desc.h" |
| 26 | |
| 27 | /* XXX Need to replace this with a dynamic |
| 28 | * method of determining Owl2 if possible |
| 29 | */ |
| 30 | #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 ) |
| 31 | #define AR5416_DS_TXSTATUS(_ah, _ads) \ |
| 32 | ((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) |
| 33 | #define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \ |
| 34 | ((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) |
| 35 | |
| 36 | #define AR5416_NUM_TX_STATUS 10 /* Number of TX status words */ |
| 37 | /* Clear the whole descriptor */ |
| 38 | #define AR5416_DESC_TX_CTL_SZ sizeof(struct ar5416_tx_desc) |
| 39 | |
| 40 | struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */ |
| 41 | uint32_t ctl2; |
| 42 | uint32_t ctl3; |
| 43 | uint32_t ctl4; |
| 44 | uint32_t ctl5; |
| 45 | uint32_t ctl6; |
| 46 | uint32_t ctl7; |
| 47 | uint32_t ctl8; |
| 48 | uint32_t ctl9; |
| 49 | uint32_t ctl10; |
| 50 | uint32_t ctl11; |
| 51 | uint32_t status[AR5416_NUM_TX_STATUS]; |
| 52 | }; |
| 53 | |
| 54 | struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */ |
| 55 | uint32_t status0; |
| 56 | uint32_t status1; |
| 57 | uint32_t status2; |
| 58 | uint32_t status3; |
| 59 | uint32_t status4; |
| 60 | uint32_t status5; |
| 61 | uint32_t status6; |
| 62 | uint32_t status7; |
| 63 | uint32_t status8; |
| 64 | }; |
| 65 | |
| 66 | |
| 67 | struct ar5416_desc { |
| 68 | uint32_t ds_link; /* link pointer */ |
| 69 | uint32_t ds_data; /* data buffer pointer */ |
| 70 | uint32_t ds_ctl0; /* DMA control 0 */ |
| 71 | uint32_t ds_ctl1; /* DMA control 1 */ |
| 72 | union { |
| 73 | struct ar5416_tx_desc tx; |
| 74 | struct ar5416_rx_desc rx; |
| 75 | } u; |
| 76 | } __packed; |
| 77 | #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) |
| 78 | #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) |
| 79 | |
| 80 | #define ds_ctl2 u.tx.ctl2 |
| 81 | #define ds_ctl3 u.tx.ctl3 |
| 82 | #define ds_ctl4 u.tx.ctl4 |
| 83 | #define ds_ctl5 u.tx.ctl5 |
| 84 | #define ds_ctl6 u.tx.ctl6 |
| 85 | #define ds_ctl7 u.tx.ctl7 |
| 86 | #define ds_ctl8 u.tx.ctl8 |
| 87 | #define ds_ctl9 u.tx.ctl9 |
| 88 | #define ds_ctl10 u.tx.ctl10 |
| 89 | #define ds_ctl11 u.tx.ctl11 |
| 90 | |
| 91 | #define ds_rxstatus0 u.rx.status0 |
| 92 | #define ds_rxstatus1 u.rx.status1 |
| 93 | #define ds_rxstatus2 u.rx.status2 |
| 94 | #define ds_rxstatus3 u.rx.status3 |
| 95 | #define ds_rxstatus4 u.rx.status4 |
| 96 | #define ds_rxstatus5 u.rx.status5 |
| 97 | #define ds_rxstatus6 u.rx.status6 |
| 98 | #define ds_rxstatus7 u.rx.status7 |
| 99 | #define ds_rxstatus8 u.rx.status8 |
| 100 | |
| 101 | /*********** |
| 102 | * TX Desc * |
| 103 | ***********/ |
| 104 | |
| 105 | /* ds_ctl0 */ |
| 106 | #define AR_FrameLen 0x00000fff |
| 107 | #define AR_VirtMoreFrag 0x00001000 |
| 108 | #define AR_TxCtlRsvd00 0x0000e000 |
| 109 | #define AR_XmitPower 0x003f0000 |
| 110 | #define AR_XmitPower_S 16 |
| 111 | #define AR_RTSEnable 0x00400000 |
| 112 | #define AR_VEOL 0x00800000 |
| 113 | #define AR_ClrDestMask 0x01000000 |
| 114 | #define AR_TxCtlRsvd01 0x1e000000 |
| 115 | #define AR_TxIntrReq 0x20000000 |
| 116 | #define AR_DestIdxValid 0x40000000 |
| 117 | #define AR_CTSEnable 0x80000000 |
| 118 | |
| 119 | /* ds_ctl1 */ |
| 120 | #define AR_BufLen 0x00000fff |
| 121 | #define AR_TxMore 0x00001000 |
| 122 | #define AR_DestIdx 0x000fe000 |
| 123 | #define AR_DestIdx_S 13 |
| 124 | #define AR_FrameType 0x00f00000 |
| 125 | #define AR_FrameType_S 20 |
| 126 | #define AR_NoAck 0x01000000 |
| 127 | #define AR_InsertTS 0x02000000 |
| 128 | #define AR_CorruptFCS 0x04000000 |
| 129 | #define AR_ExtOnly 0x08000000 |
| 130 | #define AR_ExtAndCtl 0x10000000 |
| 131 | #define AR_MoreAggr 0x20000000 |
| 132 | #define AR_IsAggr 0x40000000 |
| 133 | #define AR_MoreRifs 0x80000000 |
| 134 | |
| 135 | /* ds_ctl2 */ |
| 136 | #define AR_BurstDur 0x00007fff |
| 137 | #define AR_BurstDur_S 0 |
| 138 | #define AR_DurUpdateEn 0x00008000 |
| 139 | #define AR_XmitDataTries0 0x000f0000 |
| 140 | #define AR_XmitDataTries0_S 16 |
| 141 | #define AR_XmitDataTries1 0x00f00000 |
| 142 | #define AR_XmitDataTries1_S 20 |
| 143 | #define AR_XmitDataTries2 0x0f000000 |
| 144 | #define AR_XmitDataTries2_S 24 |
| 145 | #define AR_XmitDataTries3 0xf0000000 |
| 146 | #define AR_XmitDataTries3_S 28 |
| 147 | |
| 148 | /* ds_ctl3 */ |
| 149 | #define AR_XmitRate0 0x000000ff |
| 150 | #define AR_XmitRate0_S 0 |
| 151 | #define AR_XmitRate1 0x0000ff00 |
| 152 | #define AR_XmitRate1_S 8 |
| 153 | #define AR_XmitRate2 0x00ff0000 |
| 154 | #define AR_XmitRate2_S 16 |
| 155 | #define AR_XmitRate3 0xff000000 |
| 156 | #define AR_XmitRate3_S 24 |
| 157 | |
| 158 | /* ds_ctl4 */ |
| 159 | #define AR_PacketDur0 0x00007fff |
| 160 | #define AR_PacketDur0_S 0 |
| 161 | #define AR_RTSCTSQual0 0x00008000 |
| 162 | #define AR_PacketDur1 0x7fff0000 |
| 163 | #define AR_PacketDur1_S 16 |
| 164 | #define AR_RTSCTSQual1 0x80000000 |
| 165 | |
| 166 | /* ds_ctl5 */ |
| 167 | #define AR_PacketDur2 0x00007fff |
| 168 | #define AR_PacketDur2_S 0 |
| 169 | #define AR_RTSCTSQual2 0x00008000 |
| 170 | #define AR_PacketDur3 0x7fff0000 |
| 171 | #define AR_PacketDur3_S 16 |
| 172 | #define AR_RTSCTSQual3 0x80000000 |
| 173 | |
| 174 | /* ds_ctl6 */ |
| 175 | #define AR_AggrLen 0x0000ffff |
| 176 | #define AR_AggrLen_S 0 |
| 177 | #define AR_TxCtlRsvd60 0x00030000 |
| 178 | #define AR_PadDelim 0x03fc0000 |
| 179 | #define AR_PadDelim_S 18 |
| 180 | #define AR_EncrType 0x0c000000 |
| 181 | #define AR_EncrType_S 26 |
| 182 | #define AR_TxCtlRsvd61 0xf0000000 |
| 183 | |
| 184 | /* ds_ctl7 */ |
| 185 | #define AR_2040_0 0x00000001 |
| 186 | #define AR_GI0 0x00000002 |
| 187 | #define AR_ChainSel0 0x0000001c |
| 188 | #define AR_ChainSel0_S 2 |
| 189 | #define AR_2040_1 0x00000020 |
| 190 | #define AR_GI1 0x00000040 |
| 191 | #define AR_ChainSel1 0x00000380 |
| 192 | #define AR_ChainSel1_S 7 |
| 193 | #define AR_2040_2 0x00000400 |
| 194 | #define AR_GI2 0x00000800 |
| 195 | #define AR_ChainSel2 0x00007000 |
| 196 | #define AR_ChainSel2_S 12 |
| 197 | #define AR_2040_3 0x00008000 |
| 198 | #define AR_GI3 0x00010000 |
| 199 | #define AR_ChainSel3 0x000e0000 |
| 200 | #define AR_ChainSel3_S 17 |
| 201 | #define AR_RTSCTSRate 0x0ff00000 |
| 202 | #define AR_RTSCTSRate_S 20 |
| 203 | #define AR_STBC0 0x10000000 |
| 204 | #define AR_STBC1 0x20000000 |
| 205 | #define AR_STBC2 0x40000000 |
| 206 | #define AR_STBC3 0x80000000 |
| 207 | |
| 208 | /************* |
| 209 | * TX Status * |
| 210 | *************/ |
| 211 | |
| 212 | /* ds_status0 */ |
| 213 | #define 0x000000ff |
| 214 | #define 0 |
| 215 | #define 0x0000ff00 |
| 216 | #define 8 |
| 217 | #define 0x00ff0000 |
| 218 | #define 16 |
| 219 | #define AR_TxStatusRsvd00 0x3f000000 |
| 220 | #define AR_TxBaStatus 0x40000000 |
| 221 | #define AR_TxStatusRsvd01 0x80000000 |
| 222 | |
| 223 | /* ds_status1 */ |
| 224 | #define AR_FrmXmitOK 0x00000001 |
| 225 | #define AR_ExcessiveRetries 0x00000002 |
| 226 | #define AR_FIFOUnderrun 0x00000004 |
| 227 | #define AR_Filtered 0x00000008 |
| 228 | #define AR_RTSFailCnt 0x000000f0 |
| 229 | #define AR_RTSFailCnt_S 4 |
| 230 | #define AR_DataFailCnt 0x00000f00 |
| 231 | #define AR_DataFailCnt_S 8 |
| 232 | #define AR_VirtRetryCnt 0x0000f000 |
| 233 | #define AR_VirtRetryCnt_S 12 |
| 234 | #define AR_TxDelimUnderrun 0x00010000 |
| 235 | #define AR_TxDelimUnderrun_S 13 |
| 236 | #define AR_TxDataUnderrun 0x00020000 |
| 237 | #define AR_TxDataUnderrun_S 14 |
| 238 | #define AR_DescCfgErr 0x00040000 |
| 239 | #define AR_DescCfgErr_S 15 |
| 240 | #define AR_TxTimerExpired 0x00080000 |
| 241 | #define AR_TxStatusRsvd10 0xfff00000 |
| 242 | |
| 243 | /* ds_status2 */ |
| 244 | #define AR_SendTimestamp(_ptr) (_ptr)[2] |
| 245 | |
| 246 | /* ds_status3 */ |
| 247 | #define AR_BaBitmapLow(_ptr) (_ptr)[3] |
| 248 | |
| 249 | /* ds_status4 */ |
| 250 | #define AR_BaBitmapHigh(_ptr) (_ptr)[4] |
| 251 | |
| 252 | /* ds_status5 */ |
| 253 | #define 0x000000ff |
| 254 | #define 0 |
| 255 | #define 0x0000ff00 |
| 256 | #define 8 |
| 257 | #define 0x00ff0000 |
| 258 | #define 16 |
| 259 | #define 0xff000000 |
| 260 | #define 24 |
| 261 | |
| 262 | /* ds_status6 */ |
| 263 | #define AR_TxEVM0(_ptr) (_ptr)[6] |
| 264 | |
| 265 | /* ds_status7 */ |
| 266 | #define AR_TxEVM1(_ptr) (_ptr)[7] |
| 267 | |
| 268 | /* ds_status8 */ |
| 269 | #define AR_TxEVM2(_ptr) (_ptr)[8] |
| 270 | |
| 271 | /* ds_status9 */ |
| 272 | #define AR_TxDone 0x00000001 |
| 273 | #define AR_SeqNum 0x00001ffe |
| 274 | #define AR_SeqNum_S 1 |
| 275 | #define AR_TxStatusRsvd80 0x0001e000 |
| 276 | #define AR_TxOpExceeded 0x00020000 |
| 277 | #define AR_TxStatusRsvd81 0x001c0000 |
| 278 | #define AR_FinalTxIdx 0x00600000 |
| 279 | #define AR_FinalTxIdx_S 21 |
| 280 | #define AR_TxStatusRsvd82 0x01800000 |
| 281 | #define AR_PowerMgmt 0x02000000 |
| 282 | #define AR_TxStatusRsvd83 0xfc000000 |
| 283 | |
| 284 | /*********** |
| 285 | * RX Desc * |
| 286 | ***********/ |
| 287 | |
| 288 | /* ds_ctl0 */ |
| 289 | #define AR_RxCTLRsvd00 0xffffffff |
| 290 | |
| 291 | /* ds_ctl1 */ |
| 292 | #define AR_BufLen 0x00000fff |
| 293 | #define AR_RxCtlRsvd00 0x00001000 |
| 294 | #define AR_RxIntrReq 0x00002000 |
| 295 | #define AR_RxCtlRsvd01 0xffffc000 |
| 296 | |
| 297 | /************* |
| 298 | * Rx Status * |
| 299 | *************/ |
| 300 | |
| 301 | /* ds_status0 */ |
| 302 | #define 0x000000ff |
| 303 | #define 0 |
| 304 | #define 0x0000ff00 |
| 305 | #define 8 |
| 306 | #define 0x00ff0000 |
| 307 | #define 16 |
| 308 | /* Rev specific */ |
| 309 | /* Owl 1.x only */ |
| 310 | #define AR_RxStatusRsvd00 0xff000000 |
| 311 | /* Owl 2.x only */ |
| 312 | #define AR_RxRate 0xff000000 |
| 313 | #define AR_RxRate_S 24 |
| 314 | |
| 315 | /* ds_status1 */ |
| 316 | #define AR_DataLen 0x00000fff |
| 317 | #define AR_RxMore 0x00001000 |
| 318 | #define AR_NumDelim 0x003fc000 |
| 319 | #define AR_NumDelim_S 14 |
| 320 | #define AR_RxStatusRsvd10 0xff800000 |
| 321 | |
| 322 | /* ds_status2 */ |
| 323 | #define AR_RcvTimestamp ds_rxstatus2 |
| 324 | |
| 325 | /* ds_status3 */ |
| 326 | #define AR_GI 0x00000001 |
| 327 | #define AR_2040 0x00000002 |
| 328 | /* Rev specific */ |
| 329 | /* Owl 1.x only */ |
| 330 | #define AR_RxRateV1 0x000003fc |
| 331 | #define AR_RxRateV1_S 2 |
| 332 | #define AR_Parallel40 0x00000400 |
| 333 | #define AR_RxStatusRsvd30 0xfffff800 |
| 334 | /* Owl 2.x only */ |
| 335 | #define AR_DupFrame 0x00000004 |
| 336 | #define AR_RxAntenna 0xffffff00 |
| 337 | #define AR_RxAntenna_S 8 |
| 338 | |
| 339 | /* ds_status4 */ |
| 340 | #define 0x000000ff |
| 341 | #define 0 |
| 342 | #define 0x0000ff00 |
| 343 | #define 8 |
| 344 | #define 0x00ff0000 |
| 345 | #define 16 |
| 346 | #define 0xff000000 |
| 347 | #define 24 |
| 348 | |
| 349 | /* ds_status5 */ |
| 350 | #define AR_RxEVM0 ds_rxstatus5 |
| 351 | |
| 352 | /* ds_status6 */ |
| 353 | #define AR_RxEVM1 ds_rxstatus6 |
| 354 | |
| 355 | /* ds_status7 */ |
| 356 | #define AR_RxEVM2 ds_rxstatus7 |
| 357 | |
| 358 | /* ds_status8 */ |
| 359 | #define AR_RxDone 0x00000001 |
| 360 | #define AR_RxFrameOK 0x00000002 |
| 361 | #define AR_CRCErr 0x00000004 |
| 362 | #define AR_DecryptCRCErr 0x00000008 |
| 363 | #define AR_PHYErr 0x00000010 |
| 364 | #define AR_MichaelErr 0x00000020 |
| 365 | #define AR_PreDelimCRCErr 0x00000040 |
| 366 | #define AR_RxStatusRsvd70 0x00000080 |
| 367 | #define AR_RxKeyIdxValid 0x00000100 |
| 368 | #define AR_KeyIdx 0x0000fe00 |
| 369 | #define AR_KeyIdx_S 9 |
| 370 | #define AR_PHYErrCode 0x0000ff00 |
| 371 | #define AR_PHYErrCode_S 8 |
| 372 | #define AR_RxMoreAggr 0x00010000 |
| 373 | #define AR_RxAggr 0x00020000 |
| 374 | #define AR_PostDelimCRCErr 0x00040000 |
| 375 | #define AR_RxStatusRsvd71 0x2ff80000 |
| 376 | #define AR_HiRxChain 0x10000000 |
| 377 | #define AR_DecryptBusyErr 0x40000000 |
| 378 | #define AR_KeyMiss 0x80000000 |
| 379 | |
| 380 | #define TXCTL_OFFSET(ah) 2 |
| 381 | #define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8) |
| 382 | #define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10) |
| 383 | #define TXSTATUS_NUMWORDS(ah) 10 |
| 384 | |
| 385 | #define RXCTL_OFFSET(ah) 3 |
| 386 | #define RXCTL_NUMWORDS(ah) 1 |
| 387 | #define RXSTATUS_OFFSET(ah) 4 |
| 388 | #define RXSTATUS_NUMWORDS(ah) 9 |
| 389 | #define RXSTATUS_RATE(ah, ads) \ |
| 390 | (AR_SREV_OWL_20_OR_LATER(ah) ? \ |
| 391 | MS((ads)->ds_rxstatus0, AR_RxRate) : \ |
| 392 | ((ads)->ds_rxstatus3 >> 2) & 0xFF) |
| 393 | #define RXSTATUS_DUPLICATE(ah, ads) \ |
| 394 | (AR_SREV_OWL_20_OR_LATER(ah) ? \ |
| 395 | MS((ads)->ds_rxstatus3, AR_Parallel40) : \ |
| 396 | ((ads)->ds_rxstatus3 >> 10) & 0x1) |
| 397 | #endif /* _ATH_AR5416_DESC_H_ */ |
| 398 | |