| 1 | /* |
| 2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
| 3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | * |
| 17 | * $Id: ar5212.h,v 1.4 2011/03/07 11:25:43 cegger Exp $ |
| 18 | */ |
| 19 | #ifndef _ATH_AR5212_H_ |
| 20 | #define _ATH_AR5212_H_ |
| 21 | |
| 22 | #include "ah_eeprom.h" |
| 23 | |
| 24 | #define AR5212_MAGIC 0x19541014 |
| 25 | |
| 26 | /* DCU Transmit Filter macros */ |
| 27 | #define CALC_MMR(dcu, idx) \ |
| 28 | ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) |
| 29 | #define TXBLK_FROM_MMR(mmr) \ |
| 30 | (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) |
| 31 | #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) |
| 32 | #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) |
| 33 | |
| 34 | /* MAC register values */ |
| 35 | |
| 36 | #define INIT_INTERRUPT_MASK \ |
| 37 | ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ |
| 38 | AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ |
| 39 | AR_IMR_HIUERR ) |
| 40 | #define INIT_BEACON_CONTROL \ |
| 41 | ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ |
| 42 | (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) |
| 43 | |
| 44 | #define INIT_CONFIG_STATUS 0x00000000 |
| 45 | #define 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ |
| 46 | #define INIT_IQCAL_LOG_COUNT_MAX 0xF |
| 47 | #define INIT_BCON_CNTRL_REG 0x00000000 |
| 48 | |
| 49 | #define INIT_USEC 40 |
| 50 | #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ |
| 51 | #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ |
| 52 | |
| 53 | #define RX_NON_FULL_RATE_LATENCY 63 |
| 54 | #define TX_HALF_RATE_LATENCY 108 |
| 55 | #define TX_QUARTER_RATE_LATENCY 216 |
| 56 | |
| 57 | #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ |
| 58 | #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ |
| 59 | #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ |
| 60 | #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ |
| 61 | #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ |
| 62 | #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ |
| 63 | |
| 64 | #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ |
| 65 | |
| 66 | /* Tx frame start to tx data start delay */ |
| 67 | #define TX_FRAME_D_START_HALF_RATE 0xc |
| 68 | #define TX_FRAME_D_START_QUARTER_RATE 0xd |
| 69 | |
| 70 | /* |
| 71 | * Various fifo fill before Tx start, in 64-byte units |
| 72 | * i.e. put the frame in the air while still DMAing |
| 73 | */ |
| 74 | #define MIN_TX_FIFO_THRESHOLD 0x1 |
| 75 | #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) |
| 76 | #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD |
| 77 | |
| 78 | #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ |
| 79 | |
| 80 | /* |
| 81 | * Gain support. |
| 82 | */ |
| 83 | #define NUM_CORNER_FIX_BITS 4 |
| 84 | #define NUM_CORNER_FIX_BITS_5112 7 |
| 85 | #define DYN_ADJ_UP_MARGIN 15 |
| 86 | #define DYN_ADJ_LO_MARGIN 20 |
| 87 | #define PHY_PROBE_CCK_CORRECTION 5 |
| 88 | #define CCK_OFDM_GAIN_DELTA 15 |
| 89 | |
| 90 | enum GAIN_PARAMS { |
| 91 | GP_TXCLIP, |
| 92 | GP_PD90, |
| 93 | GP_PD84, |
| 94 | GP_GSEL, |
| 95 | }; |
| 96 | |
| 97 | enum GAIN_PARAMS_5112 { |
| 98 | GP_MIXGAIN_OVR, |
| 99 | GP_PWD_138, |
| 100 | GP_PWD_137, |
| 101 | GP_PWD_136, |
| 102 | GP_PWD_132, |
| 103 | GP_PWD_131, |
| 104 | GP_PWD_130, |
| 105 | }; |
| 106 | |
| 107 | typedef struct _gainOptStep { |
| 108 | int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; |
| 109 | int32_t stepGain; |
| 110 | int8_t stepName[16]; |
| 111 | } GAIN_OPTIMIZATION_STEP; |
| 112 | |
| 113 | typedef struct { |
| 114 | uint32_t numStepsInLadder; |
| 115 | uint32_t defaultStepNum; |
| 116 | GAIN_OPTIMIZATION_STEP optStep[10]; |
| 117 | } GAIN_OPTIMIZATION_LADDER; |
| 118 | |
| 119 | typedef struct { |
| 120 | uint32_t currStepNum; |
| 121 | uint32_t currGain; |
| 122 | uint32_t targetGain; |
| 123 | uint32_t loTrig; |
| 124 | uint32_t hiTrig; |
| 125 | uint32_t gainFCorrection; |
| 126 | uint32_t active; |
| 127 | const GAIN_OPTIMIZATION_STEP *currStep; |
| 128 | } GAIN_VALUES; |
| 129 | |
| 130 | /* RF HAL structures */ |
| 131 | typedef struct RfHalFuncs { |
| 132 | void *priv; /* private state */ |
| 133 | |
| 134 | void (*rfDetach)(struct ath_hal *ah); |
| 135 | void (*writeRegs)(struct ath_hal *, |
| 136 | u_int modeIndex, u_int freqIndex, int regWrites); |
| 137 | uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); |
| 138 | HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); |
| 139 | HAL_BOOL (*setRfRegs)(struct ath_hal *, |
| 140 | HAL_CHANNEL_INTERNAL *, uint16_t modesIndex, |
| 141 | uint16_t *rfXpdGain); |
| 142 | HAL_BOOL (*setPowerTable)(struct ath_hal *ah, |
| 143 | int16_t *minPower, int16_t *maxPower, |
| 144 | HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain); |
| 145 | HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *, |
| 146 | int16_t *maxPow, int16_t *minPow); |
| 147 | int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); |
| 148 | } RF_HAL_FUNCS; |
| 149 | |
| 150 | struct ar5212AniParams { |
| 151 | int maxNoiseImmunityLevel; /* [0..4] */ |
| 152 | int totalSizeDesired[5]; |
| 153 | int coarseHigh[5]; |
| 154 | int coarseLow[5]; |
| 155 | int firpwr[5]; |
| 156 | |
| 157 | int maxSpurImmunityLevel; /* [0..7] */ |
| 158 | int cycPwrThr1[8]; |
| 159 | |
| 160 | int maxFirstepLevel; /* [0..2] */ |
| 161 | int firstep[3]; |
| 162 | |
| 163 | uint32_t ofdmTrigHigh; |
| 164 | uint32_t ofdmTrigLow; |
| 165 | uint32_t cckTrigHigh; |
| 166 | uint32_t cckTrigLow; |
| 167 | int32_t ; |
| 168 | uint32_t ; |
| 169 | |
| 170 | int period; /* update listen period */ |
| 171 | |
| 172 | /* NB: intentionally ordered so data exported to user space is first */ |
| 173 | uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ |
| 174 | uint32_t cckPhyErrBase; /* Base value for cck err counters */ |
| 175 | }; |
| 176 | |
| 177 | /* |
| 178 | * Per-channel ANI state private to the driver. |
| 179 | */ |
| 180 | struct ar5212AniState { |
| 181 | uint8_t noiseImmunityLevel; |
| 182 | uint8_t spurImmunityLevel; |
| 183 | uint8_t firstepLevel; |
| 184 | uint8_t ofdmWeakSigDetectOff; |
| 185 | uint8_t cckWeakSigThreshold; |
| 186 | uint32_t listenTime; |
| 187 | |
| 188 | /* NB: intentionally ordered so data exported to user space is first */ |
| 189 | HAL_CHANNEL c; |
| 190 | HAL_BOOL isSetup; /* has state to do a restore */ |
| 191 | uint32_t txFrameCount; /* Last txFrameCount */ |
| 192 | uint32_t rxFrameCount; /* Last rx Frame count */ |
| 193 | uint32_t cycleCount; /* Last cycleCount |
| 194 | (to detect wrap-around) */ |
| 195 | uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ |
| 196 | uint32_t cckPhyErrCount; /* CCK err count since last reset */ |
| 197 | |
| 198 | const struct ar5212AniParams *params; |
| 199 | }; |
| 200 | |
| 201 | #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ |
| 202 | #define 0x00000002 /* rssi-based processing ena'd*/ |
| 203 | |
| 204 | struct ar5212Stats { |
| 205 | uint32_t ast_ani_niup; /* ANI increased noise immunity */ |
| 206 | uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ |
| 207 | uint32_t ast_ani_spurup; /* ANI increased spur immunity */ |
| 208 | uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ |
| 209 | uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ |
| 210 | uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ |
| 211 | uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ |
| 212 | uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ |
| 213 | uint32_t ast_ani_stepup; /* ANI increased first step level */ |
| 214 | uint32_t ast_ani_stepdown;/* ANI decreased first step level */ |
| 215 | uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ |
| 216 | uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ |
| 217 | uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ |
| 218 | uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ |
| 219 | uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ |
| 220 | HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ |
| 221 | HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ |
| 222 | }; |
| 223 | |
| 224 | /* |
| 225 | * NF Cal history buffer |
| 226 | */ |
| 227 | #define AR5212_CCA_MAX_GOOD_VALUE -95 |
| 228 | #define AR5212_CCA_MAX_HIGH_VALUE -62 |
| 229 | #define AR5212_CCA_MIN_BAD_VALUE -125 |
| 230 | |
| 231 | #define AR512_NF_CAL_HIST_MAX 5 |
| 232 | |
| 233 | struct ar5212NfCalHist { |
| 234 | int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; |
| 235 | int16_t privNF; |
| 236 | uint8_t currIndex; |
| 237 | uint8_t first_run; |
| 238 | uint8_t invalidNFcount; |
| 239 | }; |
| 240 | |
| 241 | struct ath_hal_5212 { |
| 242 | struct ath_hal_private ah_priv; /* base class */ |
| 243 | |
| 244 | /* |
| 245 | * Per-chip common Initialization data. |
| 246 | * NB: RF backends have their own ini data. |
| 247 | */ |
| 248 | HAL_INI_ARRAY ah_ini_modes; |
| 249 | HAL_INI_ARRAY ah_ini_common; |
| 250 | |
| 251 | GAIN_VALUES ah_gainValues; |
| 252 | |
| 253 | uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; |
| 254 | uint8_t ah_bssid[IEEE80211_ADDR_LEN]; |
| 255 | uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; |
| 256 | |
| 257 | /* |
| 258 | * Runtime state. |
| 259 | */ |
| 260 | uint32_t ah_maskReg; /* copy of AR_IMR */ |
| 261 | struct ar5212Stats ah_stats; /* various statistics */ |
| 262 | RF_HAL_FUNCS *ah_rfHal; |
| 263 | uint32_t ah_txDescMask; /* mask for TXDESC */ |
| 264 | uint32_t ah_txOkInterruptMask; |
| 265 | uint32_t ah_txErrInterruptMask; |
| 266 | uint32_t ah_txDescInterruptMask; |
| 267 | uint32_t ah_txEolInterruptMask; |
| 268 | uint32_t ah_txUrnInterruptMask; |
| 269 | HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; |
| 270 | uint32_t ah_intrTxqs; /* tx q interrupt state */ |
| 271 | /* decomp mask array */ |
| 272 | uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; |
| 273 | HAL_POWER_MODE ah_powerMode; |
| 274 | HAL_ANT_SETTING ah_antControl; /* antenna setting */ |
| 275 | HAL_BOOL ah_diversity; /* fast diversity setting */ |
| 276 | enum { |
| 277 | IQ_CAL_INACTIVE, |
| 278 | IQ_CAL_RUNNING, |
| 279 | IQ_CAL_DONE |
| 280 | } ah_bIQCalibration; /* IQ calibrate state */ |
| 281 | HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ |
| 282 | uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ |
| 283 | uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ |
| 284 | uint32_t ah_miscMode; /* MISC_MODE settings */ |
| 285 | uint32_t ; /* RSSI_THR settings */ |
| 286 | HAL_BOOL ah_cwCalRequire; /* for ap51 */ |
| 287 | HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ |
| 288 | HAL_BOOL ah_phyPowerOn; /* PHY power state */ |
| 289 | HAL_BOOL ah_isHb63; /* cached HB63 check */ |
| 290 | uint32_t ah_macTPC; /* tpc register */ |
| 291 | uint32_t ah_beaconInterval; /* XXX */ |
| 292 | enum { |
| 293 | AUTO_32KHZ, /* use it if 32kHz crystal present */ |
| 294 | USE_32KHZ, /* do it regardless */ |
| 295 | DONT_USE_32KHZ, /* don't use it regardless */ |
| 296 | } ah_enable32kHzClock; /* whether to sleep at 32kHz */ |
| 297 | uint32_t ah_ofdmTxPower; |
| 298 | int16_t ah_txPowerIndexOffset; |
| 299 | /* |
| 300 | * Noise floor cal histogram support. |
| 301 | */ |
| 302 | struct ar5212NfCalHist ah_nfCalHist; |
| 303 | |
| 304 | u_int ah_slottime; /* user-specified slot time */ |
| 305 | u_int ah_acktimeout; /* user-specified ack timeout */ |
| 306 | u_int ah_ctstimeout; /* user-specified cts timeout */ |
| 307 | u_int ah_sifstime; /* user-specified sifs time */ |
| 308 | /* |
| 309 | * RF Silent handling; setup according to the EEPROM. |
| 310 | */ |
| 311 | uint32_t ah_gpioSelect; /* GPIO pin to use */ |
| 312 | uint32_t ah_polarity; /* polarity to disable RF */ |
| 313 | uint32_t ah_gpioBit; /* after init, prev value */ |
| 314 | /* |
| 315 | * ANI support. |
| 316 | */ |
| 317 | uint32_t ah_procPhyErr; /* Process Phy errs */ |
| 318 | HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ |
| 319 | struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ |
| 320 | struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ |
| 321 | struct ar5212AniState *ah_curani; /* cached last reference */ |
| 322 | struct ar5212AniState ah_ani[64]; /* per-channel state */ |
| 323 | |
| 324 | /* |
| 325 | * Transmit power state. Note these are maintained |
| 326 | * here so they can be retrieved by diagnostic tools. |
| 327 | */ |
| 328 | uint16_t *ah_pcdacTable; |
| 329 | u_int ah_pcdacTableSize; |
| 330 | uint16_t ah_ratesArray[16]; |
| 331 | |
| 332 | uint8_t ah_txTrigLev; /* current Tx trigger level */ |
| 333 | uint8_t ah_maxTxTrigLev; /* max tx trigger level */ |
| 334 | }; |
| 335 | #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) |
| 336 | |
| 337 | /* |
| 338 | * IS_XXXX macros test the MAC version |
| 339 | * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) |
| 340 | * |
| 341 | * Some single chip radios have equivalent radio/RF (e.g. 5112) |
| 342 | * for those use IS_RADXXX_ANY macros. |
| 343 | */ |
| 344 | #define IS_2317(ah) \ |
| 345 | ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ |
| 346 | (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) |
| 347 | #define IS_2316(ah) \ |
| 348 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) |
| 349 | #define IS_2413(ah) \ |
| 350 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) |
| 351 | #define IS_5424(ah) \ |
| 352 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ |
| 353 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ |
| 354 | AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) |
| 355 | #define IS_5413(ah) \ |
| 356 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) |
| 357 | #define IS_2425(ah) \ |
| 358 | (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) |
| 359 | #define IS_2417(ah) \ |
| 360 | ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) |
| 361 | #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) |
| 362 | |
| 363 | #define AH_RADIO_MAJOR(ah) \ |
| 364 | (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) |
| 365 | #define AH_RADIO_MINOR(ah) \ |
| 366 | (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) |
| 367 | #define IS_RAD5111(ah) \ |
| 368 | (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ |
| 369 | AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) |
| 370 | #define IS_RAD5112(ah) \ |
| 371 | (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ |
| 372 | AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) |
| 373 | /* NB: does not include 5413 as Atheros' IS_5112 macro does */ |
| 374 | #define IS_RAD5112_ANY(ah) \ |
| 375 | (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ |
| 376 | AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) |
| 377 | #define IS_RAD5112_REV1(ah) \ |
| 378 | (IS_RAD5112(ah) && \ |
| 379 | AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) |
| 380 | #define IS_RADX112_REV2(ah) \ |
| 381 | (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ |
| 382 | AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ |
| 383 | AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ |
| 384 | AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) |
| 385 | |
| 386 | #define ar5212RfDetach(ah) do { \ |
| 387 | if (AH5212(ah)->ah_rfHal != AH_NULL) \ |
| 388 | AH5212(ah)->ah_rfHal->rfDetach(ah); \ |
| 389 | } while (0) |
| 390 | #define ar5212GetRfBank(ah, b) \ |
| 391 | AH5212(ah)->ah_rfHal->getRfBank(ah, b) |
| 392 | |
| 393 | /* |
| 394 | * Hack macros for Nala/San: 11b is handled |
| 395 | * using 11g; flip the channel flags to accomplish this. |
| 396 | */ |
| 397 | #define SAVE_CCK(_ah, _chan, _flag) do { \ |
| 398 | if ((IS_2425(_ah) || IS_2417(_ah)) && \ |
| 399 | (((_chan)->channelFlags) & CHANNEL_CCK)) { \ |
| 400 | (_chan)->channelFlags &= ~CHANNEL_CCK; \ |
| 401 | (_chan)->channelFlags |= CHANNEL_OFDM; \ |
| 402 | (_flag) = AH_TRUE; \ |
| 403 | } else \ |
| 404 | (_flag) = AH_FALSE; \ |
| 405 | } while (0) |
| 406 | #define RESTORE_CCK(_ah, _chan, _flag) do { \ |
| 407 | if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\ |
| 408 | (_chan)->channelFlags &= ~CHANNEL_OFDM; \ |
| 409 | (_chan)->channelFlags |= CHANNEL_CCK; \ |
| 410 | } \ |
| 411 | } while (0) |
| 412 | |
| 413 | struct ath_hal; |
| 414 | |
| 415 | extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); |
| 416 | extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, |
| 417 | HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); |
| 418 | extern void ar5212Detach(struct ath_hal *ah); |
| 419 | extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); |
| 420 | extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, |
| 421 | uint16_t flags, uint16_t *low, uint16_t *high); |
| 422 | extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); |
| 423 | |
| 424 | extern void ar5212SetBeaconTimers(struct ath_hal *ah, |
| 425 | const HAL_BEACON_TIMERS *); |
| 426 | extern void ar5212BeaconInit(struct ath_hal *ah, |
| 427 | uint32_t next_beacon, uint32_t beacon_period); |
| 428 | extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); |
| 429 | extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, |
| 430 | const HAL_BEACON_STATE *); |
| 431 | |
| 432 | extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); |
| 433 | extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); |
| 434 | extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); |
| 435 | extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); |
| 436 | |
| 437 | extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); |
| 438 | extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); |
| 439 | extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); |
| 440 | extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, |
| 441 | uint16_t entry, const uint8_t *mac); |
| 442 | extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, |
| 443 | const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); |
| 444 | |
| 445 | extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); |
| 446 | extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); |
| 447 | extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); |
| 448 | extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); |
| 449 | extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); |
| 450 | extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); |
| 451 | extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, |
| 452 | uint16_t regDomain, HAL_STATUS *stats); |
| 453 | extern u_int ar5212GetWirelessModes(struct ath_hal *ah); |
| 454 | extern void ar5212EnableRfKill(struct ath_hal *); |
| 455 | extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, |
| 456 | HAL_GPIO_MUX_TYPE); |
| 457 | extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); |
| 458 | extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); |
| 459 | extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); |
| 460 | extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); |
| 461 | extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); |
| 462 | extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, |
| 463 | uint16_t assocId); |
| 464 | extern uint32_t ar5212GetTsf32(struct ath_hal *ah); |
| 465 | extern uint64_t ar5212GetTsf64(struct ath_hal *ah); |
| 466 | extern void ar5212ResetTsf(struct ath_hal *ah); |
| 467 | extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); |
| 468 | extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); |
| 469 | extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); |
| 470 | extern void ar5212EnableMibCounters(struct ath_hal *); |
| 471 | extern void ar5212DisableMibCounters(struct ath_hal *); |
| 472 | extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); |
| 473 | extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); |
| 474 | extern uint32_t (struct ath_hal *ah); |
| 475 | extern u_int ar5212GetDefAntenna(struct ath_hal *ah); |
| 476 | extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); |
| 477 | extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); |
| 478 | extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); |
| 479 | extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); |
| 480 | extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); |
| 481 | extern u_int ar5212GetSifsTime(struct ath_hal *); |
| 482 | extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); |
| 483 | extern u_int ar5212GetSlotTime(struct ath_hal *); |
| 484 | extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); |
| 485 | extern u_int ar5212GetAckTimeout(struct ath_hal *); |
| 486 | extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); |
| 487 | extern u_int ar5212GetAckCTSRate(struct ath_hal *); |
| 488 | extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); |
| 489 | extern u_int ar5212GetCTSTimeout(struct ath_hal *); |
| 490 | extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); |
| 491 | void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); |
| 492 | extern void ar5212SetPCUConfig(struct ath_hal *); |
| 493 | extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); |
| 494 | extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); |
| 495 | extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); |
| 496 | extern int16_t ar5212GetNfAdjust(struct ath_hal *, |
| 497 | const HAL_CHANNEL_INTERNAL *); |
| 498 | extern void ar5212SetCompRegs(struct ath_hal *ah); |
| 499 | extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, |
| 500 | uint32_t, uint32_t *); |
| 501 | extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, |
| 502 | uint32_t, uint32_t, HAL_STATUS *); |
| 503 | extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, |
| 504 | const void *args, uint32_t argsize, |
| 505 | void **result, uint32_t *resultsize); |
| 506 | |
| 507 | extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, |
| 508 | int setChip); |
| 509 | extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); |
| 510 | extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); |
| 511 | |
| 512 | extern uint32_t ar5212GetRxDP(struct ath_hal *ath); |
| 513 | extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp); |
| 514 | extern void ar5212EnableReceive(struct ath_hal *ah); |
| 515 | extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); |
| 516 | extern void ar5212StartPcuReceive(struct ath_hal *ah); |
| 517 | extern void ar5212StopPcuReceive(struct ath_hal *ah); |
| 518 | extern void ar5212SetMulticastFilter(struct ath_hal *ah, |
| 519 | uint32_t filter0, uint32_t filter1); |
| 520 | extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); |
| 521 | extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); |
| 522 | extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); |
| 523 | extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); |
| 524 | extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, |
| 525 | struct ath_desc *, uint32_t size, u_int flags); |
| 526 | extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, |
| 527 | uint32_t, struct ath_desc *, uint64_t, |
| 528 | struct ath_rx_status *); |
| 529 | |
| 530 | extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, |
| 531 | HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status); |
| 532 | extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *); |
| 533 | extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); |
| 534 | extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); |
| 535 | extern HAL_BOOL ar5212Disable(struct ath_hal *ah); |
| 536 | extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *); |
| 537 | extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, |
| 538 | HAL_BOOL *isIQdone); |
| 539 | extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, |
| 540 | u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); |
| 541 | extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan); |
| 542 | extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); |
| 543 | extern void ar5212InitNfCalHistBuffer(struct ath_hal *); |
| 544 | extern int16_t ar5212GetNfHistMid(const int16_t calData[]); |
| 545 | extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *); |
| 546 | extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, |
| 547 | HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan); |
| 548 | extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); |
| 549 | extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, |
| 550 | HAL_CHANNEL *chans, uint32_t nchans); |
| 551 | extern void ar5212InitializeGainValues(struct ath_hal *); |
| 552 | extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); |
| 553 | extern void ar5212RequestRfgain(struct ath_hal *); |
| 554 | |
| 555 | extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, |
| 556 | HAL_BOOL IncTrigLevel); |
| 557 | extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, |
| 558 | const HAL_TXQ_INFO *qInfo); |
| 559 | extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, |
| 560 | HAL_TXQ_INFO *qInfo); |
| 561 | extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, |
| 562 | const HAL_TXQ_INFO *qInfo); |
| 563 | extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); |
| 564 | extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); |
| 565 | extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); |
| 566 | extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); |
| 567 | extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); |
| 568 | extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); |
| 569 | extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); |
| 570 | extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, |
| 571 | u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, |
| 572 | u_int txRate0, u_int txTries0, |
| 573 | u_int keyIx, u_int antMode, u_int flags, |
| 574 | u_int rtsctsRate, u_int rtsctsDuration, |
| 575 | u_int compicvLen, u_int compivLen, u_int comp); |
| 576 | extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, |
| 577 | u_int txRate1, u_int txRetries1, |
| 578 | u_int txRate2, u_int txRetries2, |
| 579 | u_int txRate3, u_int txRetries3); |
| 580 | extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, |
| 581 | u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, |
| 582 | const struct ath_desc *ds0); |
| 583 | extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, |
| 584 | struct ath_desc *, struct ath_tx_status *); |
| 585 | extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); |
| 586 | extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); |
| 587 | |
| 588 | extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); |
| 589 | |
| 590 | extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, |
| 591 | const struct ar5212AniParams *, HAL_BOOL ena); |
| 592 | extern void ar5212AniDetach(struct ath_hal *); |
| 593 | extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); |
| 594 | extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); |
| 595 | extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); |
| 596 | extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, |
| 597 | const struct ar5212AniParams *, const struct ar5212AniParams *); |
| 598 | struct ath_rx_status; |
| 599 | extern void ar5212AniPhyErrReport(struct ath_hal *ah, |
| 600 | const struct ath_rx_status *rs); |
| 601 | extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); |
| 602 | extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *, |
| 603 | HAL_CHANNEL *); |
| 604 | extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *, |
| 605 | HAL_OPMODE, int); |
| 606 | |
| 607 | extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); |
| 608 | extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); |
| 609 | #endif /* _ATH_AR5212_H_ */ |
| 610 | |