| 1 | /* $NetBSD: if_txpreg.h,v 1.6 2012/10/27 17:18:34 chs Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 18 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 19 | * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, |
| 20 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 22 | * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 24 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 25 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 26 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #define TXP_PCI_LOMEM 0x14 /* pci conf, memory map BAR */ |
| 30 | #define TXP_PCI_LOIO 0x10 /* pci conf, IO map BAR */ |
| 31 | |
| 32 | /* |
| 33 | * Typhoon registers. |
| 34 | */ |
| 35 | #define TXP_SRR 0x00 /* soft reset register */ |
| 36 | #define TXP_ISR 0x04 /* interrupt status register */ |
| 37 | #define TXP_IER 0x08 /* interrupt enable register */ |
| 38 | #define TXP_IMR 0x0c /* interrupt mask register */ |
| 39 | #define TXP_SIR 0x10 /* self interrupt register */ |
| 40 | #define TXP_H2A_7 0x14 /* host->arm comm 7 */ |
| 41 | #define TXP_H2A_6 0x18 /* host->arm comm 6 */ |
| 42 | #define TXP_H2A_5 0x1c /* host->arm comm 5 */ |
| 43 | #define TXP_H2A_4 0x20 /* host->arm comm 4 */ |
| 44 | #define TXP_H2A_3 0x24 /* host->arm comm 3 */ |
| 45 | #define TXP_H2A_2 0x28 /* host->arm comm 2 */ |
| 46 | #define TXP_H2A_1 0x2c /* host->arm comm 1 */ |
| 47 | #define TXP_H2A_0 0x30 /* host->arm comm 0 */ |
| 48 | #define TXP_A2H_3 0x34 /* arm->host comm 3 */ |
| 49 | #define TXP_A2H_2 0x38 /* arm->host comm 2 */ |
| 50 | #define TXP_A2H_1 0x3c /* arm->host comm 1 */ |
| 51 | #define TXP_A2H_0 0x40 /* arm->host comm 0 */ |
| 52 | |
| 53 | /* |
| 54 | * interrupt bits (IMR, ISR, IER) |
| 55 | */ |
| 56 | #define TXP_INT_RESERVED 0xffff0000 |
| 57 | #define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ |
| 58 | #define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ |
| 59 | #define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ |
| 60 | #define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ |
| 61 | #define TXP_INT_SELF 0x00000800 /* self interrupt */ |
| 62 | #define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ |
| 63 | #define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ |
| 64 | #define TXP_INT_DMA3 0x00000100 /* dma3 done */ |
| 65 | #define TXP_INT_DMA2 0x00000080 /* dma2 done */ |
| 66 | #define TXP_INT_DMA1 0x00000040 /* dma1 done */ |
| 67 | #define TXP_INT_DMA0 0x00000020 /* dma0 done */ |
| 68 | #define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ |
| 69 | #define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ |
| 70 | #define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ |
| 71 | #define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ |
| 72 | #define TXP_INT_LATCH 0x00000001 /* interrupt latch */ |
| 73 | |
| 74 | /* |
| 75 | * soft reset register (SRR) |
| 76 | */ |
| 77 | #define TXP_SRR_ALL 0x0000007f /* full reset */ |
| 78 | |
| 79 | /* |
| 80 | * Typhoon boot commands. |
| 81 | */ |
| 82 | #define TXP_BOOTCMD_NULL 0x00 |
| 83 | #define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb |
| 84 | #define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc |
| 85 | #define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd |
| 86 | #define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff |
| 87 | |
| 88 | /* |
| 89 | * Typhoon runtime commands. |
| 90 | */ |
| 91 | #define TXP_CMD_GLOBAL_RESET 0x00 |
| 92 | #define TXP_CMD_TX_ENABLE 0x01 |
| 93 | #define TXP_CMD_TX_DISABLE 0x02 |
| 94 | #define TXP_CMD_RX_ENABLE 0x03 |
| 95 | #define TXP_CMD_RX_DISABLE 0x04 |
| 96 | #define TXP_CMD_RX_FILTER_WRITE 0x05 |
| 97 | #define TXP_CMD_RX_FILTER_READ 0x06 |
| 98 | #define TXP_CMD_READ_STATISTICS 0x07 |
| 99 | #define TXP_CMD_CYCLE_STATISTICS 0x08 |
| 100 | #define TXP_CMD_CLEAR_STATISTICS 0x09 |
| 101 | #define TXP_CMD_MEMORY_READ 0x0a |
| 102 | #define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b |
| 103 | #define TXP_CMD_VARIABLE_SECTION_READ 0x0c |
| 104 | #define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d |
| 105 | #define TXP_CMD_STATIC_SECTION_READ 0x0e |
| 106 | #define TXP_CMD_STATIC_SECTION_WRITE 0x0f |
| 107 | #define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 |
| 108 | #define TXP_CMD_NVRAM_PAGE_READ 0x11 |
| 109 | #define TXP_CMD_NVRAM_PAGE_WRITE 0x12 |
| 110 | #define TXP_CMD_XCVR_SELECT 0x13 |
| 111 | #define TXP_CMD_TEST_MUX 0x14 |
| 112 | #define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 |
| 113 | #define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 |
| 114 | #define TXP_CMD_MAC_CONTROL_READ 0x17 |
| 115 | #define TXP_CMD_MAC_CONTROL_WRITE 0x18 |
| 116 | #define TXP_CMD_MAX_PKT_SIZE_READ 0x19 |
| 117 | #define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a |
| 118 | #define TXP_CMD_MEDIA_STATUS_READ 0x1b |
| 119 | #define TXP_CMD_MEDIA_STATUS_WRITE 0x1c |
| 120 | #define TXP_CMD_NETWORK_DIAGS_READ 0x1d |
| 121 | #define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e |
| 122 | #define TXP_CMD_PHY_MGMT_READ 0x1f |
| 123 | #define TXP_CMD_PHY_MGMT_WRITE 0x20 |
| 124 | #define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 |
| 125 | #define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 |
| 126 | #define TXP_CMD_GOTO_SLEEP 0x23 |
| 127 | #define TXP_CMD_FIREWALL_CONTROL 0x24 |
| 128 | #define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 |
| 129 | #define TXP_CMD_STATION_ADDRESS_WRITE 0x26 |
| 130 | #define TXP_CMD_STATION_ADDRESS_READ 0x27 |
| 131 | #define TXP_CMD_STATION_MASK_WRITE 0x28 |
| 132 | #define TXP_CMD_STATION_MASK_READ 0x29 |
| 133 | #define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a |
| 134 | #define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b |
| 135 | #define TXP_CMD_VLAN_MASK_READ 0x2c |
| 136 | #define TXP_CMD_VLAN_MASK_WRITE 0x2d |
| 137 | #define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e |
| 138 | #define TXP_CMD_BCAST_THROTTLE_READ 0x2f |
| 139 | #define TXP_CMD_DHCP_PREVENT_WRITE 0x30 |
| 140 | #define TXP_CMD_DHCP_PREVENT_READ 0x31 |
| 141 | #define TXP_CMD_RECV_BUFFER_CONTROL 0x32 |
| 142 | #define TXP_CMD_SOFTWARE_RESET 0x33 |
| 143 | #define TXP_CMD_CREATE_SA 0x34 |
| 144 | #define TXP_CMD_DELETE_SA 0x35 |
| 145 | #define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 |
| 146 | #define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 |
| 147 | #define TXP_CMD_RANDOM_NUMBER_READ 0x38 |
| 148 | #define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 |
| 149 | #define TXP_CMD_MATRIX_DETAIL_READ 0x3a |
| 150 | #define TXP_CMD_FILTER_ARRAY_READ 0x3b |
| 151 | #define TXP_CMD_FILTER_DETAIL_READ 0x3c |
| 152 | #define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d |
| 153 | #define TXP_CMD_FILTER_TCL_WRITE 0x3e |
| 154 | #define TXP_CMD_FILTER_TBL_READ 0x3f |
| 155 | #define TXP_CMD_VERSIONS_READ 0x43 |
| 156 | #define TXP_CMD_FILTER_DEFINE 0x45 |
| 157 | #define TXP_CMD_ADD_WAKEUP_PKT 0x46 |
| 158 | #define TXP_CMD_ADD_SLEEP_PKT 0x47 |
| 159 | #define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 |
| 160 | #define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 |
| 161 | #define TXP_CMD_GET_IP_ADDRESS 0x4a |
| 162 | #define TXP_CMD_READ_PCI_REG 0x4c |
| 163 | #define TXP_CMD_WRITE_PCI_REG 0x4d |
| 164 | #define TXP_CMD_OFFLOAD_READ 0x4e |
| 165 | #define TXP_CMD_OFFLOAD_WRITE 0x4f |
| 166 | #define TXP_CMD_HELLO_RESPONSE 0x57 |
| 167 | #define TXP_CMD_ENABLE_RX_FILTER 0x58 |
| 168 | #define TXP_CMD_RX_FILTER_CAPABILITY 0x59 |
| 169 | #define TXP_CMD_HALT 0x5d |
| 170 | #define TXP_CMD_READ_IPSEC_INFO 0x54 |
| 171 | #define TXP_CMD_GET_IPSEC_ENABLE 0x67 |
| 172 | #define TXP_CMD_INVALID 0xffff |
| 173 | |
| 174 | #define TXP_FRAGMENT 0x0000 |
| 175 | #define TXP_TXFRAME 0x0001 |
| 176 | #define TXP_COMMAND 0x0002 |
| 177 | #define TXP_OPTION 0x0003 |
| 178 | #define TXP_RECEIVE 0x0004 |
| 179 | #define TXP_RESPONSE 0x0005 |
| 180 | |
| 181 | #define TXP_TYPE_IPSEC 0x0000 |
| 182 | #define TXP_TYPE_TCPSEGMENT 0x0001 |
| 183 | |
| 184 | #define TXP_PFLAG_NOCRC 0x0000 |
| 185 | #define TXP_PFLAG_IPCKSUM 0x0001 |
| 186 | #define TXP_PFLAG_TCPCKSUM 0x0002 |
| 187 | #define TXP_PFLAG_TCPSEGMENT 0x0004 |
| 188 | #define TXP_PFLAG_INSERTVLAN 0x0008 |
| 189 | #define TXP_PFLAG_IPSEC 0x0010 |
| 190 | #define TXP_PFLAG_PRIORITY 0x0020 |
| 191 | #define TXP_PFLAG_UDPCKSUM 0x0040 |
| 192 | #define TXP_PFLAG_PADFRAME 0x0080 |
| 193 | |
| 194 | #define TXP_MISC_FIRSTDESC 0x0000 |
| 195 | #define TXP_MISC_LASTDESC 0x0001 |
| 196 | |
| 197 | #define TXP_ERR_INTERNAL 0x0000 |
| 198 | #define TXP_ERR_FIFOUNDERRUN 0x0001 |
| 199 | #define TXP_ERR_BADSSD 0x0002 |
| 200 | #define TXP_ERR_RUNT 0x0003 |
| 201 | #define TXP_ERR_CRC 0x0004 |
| 202 | #define TXP_ERR_OVERSIZE 0x0005 |
| 203 | #define TXP_ERR_ALIGNMENT 0x0006 |
| 204 | #define TXP_ERR_DRIBBLEBIT 0x0007 |
| 205 | |
| 206 | #define TXP_PROTO_UNKNOWN 0x0000 |
| 207 | #define TXP_PROTO_IP 0x0001 |
| 208 | #define TXP_PROTO_IPX 0x0002 |
| 209 | #define TXP_PROTO_RESERVED 0x0003 |
| 210 | |
| 211 | #define TXP_STAT_PROTO 0x0001 |
| 212 | #define TXP_STAT_VLAN 0x0002 |
| 213 | #define TXP_STAT_IPFRAGMENT 0x0004 |
| 214 | #define TXP_STAT_IPSEC 0x0008 |
| 215 | #define TXP_STAT_IPCKSUMBAD 0x0010 |
| 216 | #define TXP_STAT_TCPCKSUMBAD 0x0020 |
| 217 | #define TXP_STAT_UDPCKSUMBAD 0x0040 |
| 218 | #define TXP_STAT_IPCKSUMGOOD 0x0080 |
| 219 | #define TXP_STAT_TCPCKSUMGOOD 0x0100 |
| 220 | #define TXP_STAT_UDPCKSUMGOOD 0x0200 |
| 221 | |
| 222 | struct txp_tx_desc { |
| 223 | volatile u_int8_t tx_flags; /* type/descriptor flags */ |
| 224 | volatile u_int8_t tx_numdesc; /* number of descriptors */ |
| 225 | volatile u_int16_t tx_totlen; /* total packet length */ |
| 226 | volatile u_int32_t tx_addrlo; /* virt addr low word */ |
| 227 | volatile u_int32_t tx_addrhi; /* virt addr high word */ |
| 228 | volatile u_int32_t tx_pflags; /* processing flags */ |
| 229 | }; |
| 230 | #define TX_FLAGS_TYPE_M 0x07 /* type mask */ |
| 231 | #define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ |
| 232 | #define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ |
| 233 | #define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ |
| 234 | #define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ |
| 235 | #define TX_FLAGS_TYPE_RX 0x04 /* type: command */ |
| 236 | #define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ |
| 237 | #define TX_FLAGS_RESP 0x40 /* response requested */ |
| 238 | #define TX_FLAGS_VALID 0x80 /* valid descriptor */ |
| 239 | |
| 240 | #define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ |
| 241 | #define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ |
| 242 | #define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ |
| 243 | #define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ |
| 244 | #define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ |
| 245 | #define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ |
| 246 | #define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ |
| 247 | #define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ |
| 248 | #define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ |
| 249 | #define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ |
| 250 | #define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ |
| 251 | #define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ |
| 252 | |
| 253 | struct txp_rx_desc { |
| 254 | volatile u_int8_t rx_flags; /* type/descriptor flags */ |
| 255 | volatile u_int8_t rx_numdesc; /* number of descriptors */ |
| 256 | volatile u_int16_t rx_len; /* frame length */ |
| 257 | volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */ |
| 258 | volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */ |
| 259 | volatile u_int32_t rx_stat; /* status */ |
| 260 | volatile u_int16_t rx_filter; /* filter status */ |
| 261 | volatile u_int16_t rx_hash; /* hash status */ |
| 262 | volatile u_int32_t rx_vlan; /* vlan tag/priority */ |
| 263 | }; |
| 264 | |
| 265 | /* txp_rx_desc.rx_flags */ |
| 266 | #define RX_FLAGS_TYPE_M 0x07 /* type mask */ |
| 267 | #define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ |
| 268 | #define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ |
| 269 | #define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ |
| 270 | #define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ |
| 271 | #define RX_FLAGS_TYPE_RX 0x04 /* type: command */ |
| 272 | #define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ |
| 273 | #define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ |
| 274 | #define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ |
| 275 | #define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ |
| 276 | #define RX_FLAGS_ERROR 0x40 /* error in packet */ |
| 277 | |
| 278 | /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ |
| 279 | #define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ |
| 280 | #define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ |
| 281 | #define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ |
| 282 | #define RX_ERROR_RUNT 0x00000003 /* runt packet */ |
| 283 | #define RX_ERROR_CRC 0x00000004 /* bad crc */ |
| 284 | #define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ |
| 285 | #define RX_ERROR_ALIGN 0x00000006 /* alignment error */ |
| 286 | #define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ |
| 287 | |
| 288 | /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ |
| 289 | #define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ |
| 290 | #define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ |
| 291 | #define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ |
| 292 | #define RX_STAT_PROTO_IP 0x00000002 /* IP */ |
| 293 | #define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ |
| 294 | #define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ |
| 295 | #define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ |
| 296 | #define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ |
| 297 | #define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ |
| 298 | #define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ |
| 299 | #define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ |
| 300 | #define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ |
| 301 | #define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ |
| 302 | #define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ |
| 303 | |
| 304 | |
| 305 | struct txp_rxbuf_desc { |
| 306 | volatile u_int32_t rb_paddrlo; |
| 307 | volatile u_int32_t rb_paddrhi; |
| 308 | volatile u_int32_t rb_vaddrlo; |
| 309 | volatile u_int32_t rb_vaddrhi; |
| 310 | }; |
| 311 | |
| 312 | /* Extension descriptor */ |
| 313 | struct txp_ext_desc { |
| 314 | volatile u_int32_t ext_1; |
| 315 | volatile u_int32_t ext_2; |
| 316 | volatile u_int32_t ext_3; |
| 317 | volatile u_int32_t ext_4; |
| 318 | }; |
| 319 | |
| 320 | struct txp_cmd_desc { |
| 321 | volatile u_int8_t cmd_flags; |
| 322 | volatile u_int8_t cmd_numdesc; |
| 323 | volatile u_int16_t cmd_id; |
| 324 | volatile u_int16_t cmd_seq; |
| 325 | volatile u_int16_t cmd_par1; |
| 326 | volatile u_int32_t cmd_par2; |
| 327 | volatile u_int32_t cmd_par3; |
| 328 | }; |
| 329 | #define CMD_FLAGS_TYPE_M 0x07 /* type mask */ |
| 330 | #define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ |
| 331 | #define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ |
| 332 | #define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ |
| 333 | #define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ |
| 334 | #define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ |
| 335 | #define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ |
| 336 | #define CMD_FLAGS_RESP 0x40 /* response requested */ |
| 337 | #define CMD_FLAGS_VALID 0x80 /* valid descriptor */ |
| 338 | |
| 339 | struct txp_rsp_desc { |
| 340 | volatile u_int8_t rsp_flags; |
| 341 | volatile u_int8_t rsp_numdesc; |
| 342 | volatile u_int16_t rsp_id; |
| 343 | volatile u_int16_t rsp_seq; |
| 344 | volatile u_int16_t rsp_par1; |
| 345 | volatile u_int32_t rsp_par2; |
| 346 | volatile u_int32_t rsp_par3; |
| 347 | }; |
| 348 | #define RSP_FLAGS_TYPE_M 0x07 /* type mask */ |
| 349 | #define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ |
| 350 | #define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ |
| 351 | #define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ |
| 352 | #define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ |
| 353 | #define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ |
| 354 | #define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ |
| 355 | #define RSP_FLAGS_ERROR 0x40 /* response error */ |
| 356 | |
| 357 | struct txp_frag_desc { |
| 358 | volatile u_int8_t frag_flags; /* type/descriptor flags */ |
| 359 | volatile u_int8_t frag_rsvd1; |
| 360 | volatile u_int16_t frag_len; /* bytes in this fragment */ |
| 361 | volatile u_int32_t frag_addrlo; /* phys addr low word */ |
| 362 | volatile u_int32_t frag_addrhi; /* phys addr high word */ |
| 363 | volatile u_int32_t frag_rsvd2; |
| 364 | }; |
| 365 | #define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ |
| 366 | #define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ |
| 367 | #define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ |
| 368 | #define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ |
| 369 | #define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ |
| 370 | #define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ |
| 371 | #define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ |
| 372 | #define FRAG_FLAGS_VALID 0x80 /* valid descriptor */ |
| 373 | |
| 374 | struct txp_opt_desc { |
| 375 | u_int8_t opt_desctype:3, |
| 376 | opt_rsvd:1, |
| 377 | opt_type:4; |
| 378 | |
| 379 | u_int8_t opt_num; |
| 380 | u_int16_t opt_dep1; |
| 381 | u_int32_t opt_dep2; |
| 382 | u_int32_t opt_dep3; |
| 383 | u_int32_t opt_dep4; |
| 384 | }; |
| 385 | |
| 386 | struct txp_ipsec_desc { |
| 387 | u_int8_t ipsec_desctpe:3, |
| 388 | ipsec_rsvd:1, |
| 389 | ipsec_type:4; |
| 390 | |
| 391 | u_int8_t ipsec_num; |
| 392 | u_int16_t ipsec_flags; |
| 393 | u_int16_t ipsec_ah1; |
| 394 | u_int16_t ipsec_esp1; |
| 395 | u_int16_t ipsec_ah2; |
| 396 | u_int16_t ipsec_esp2; |
| 397 | u_int32_t ipsec_rsvd1; |
| 398 | }; |
| 399 | |
| 400 | struct txp_tcpseg_desc { |
| 401 | u_int8_t tcpseg_desctype:3, |
| 402 | tcpseg_rsvd:1, |
| 403 | tcpseg_type:4; |
| 404 | |
| 405 | u_int8_t tcpseg_num; |
| 406 | |
| 407 | u_int16_t tcpseg_mss:12, |
| 408 | tcpseg_misc:4; |
| 409 | |
| 410 | u_int32_t tcpseg_respaddr; |
| 411 | u_int32_t tcpseg_txbytes; |
| 412 | u_int32_t tcpseg_lss; |
| 413 | }; |
| 414 | |
| 415 | /* |
| 416 | * Transceiver types |
| 417 | */ |
| 418 | #define TXP_XCVR_10_HDX 0 |
| 419 | #define TXP_XCVR_10_FDX 1 |
| 420 | #define TXP_XCVR_100_HDX 2 |
| 421 | #define TXP_XCVR_100_FDX 3 |
| 422 | #define TXP_XCVR_AUTO 4 |
| 423 | |
| 424 | #define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ |
| 425 | #define TXP_MEDIA_CD 0x0010 /* collision detection */ |
| 426 | #define TXP_MEDIA_CS 0x0020 /* carrier sense */ |
| 427 | #define TXP_MEDIA_POL 0x0400 /* polarity reversed */ |
| 428 | #define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ |
| 429 | |
| 430 | /* |
| 431 | * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} |
| 432 | */ |
| 433 | #define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ |
| 434 | #define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ |
| 435 | #define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ |
| 436 | #define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ |
| 437 | #define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ |
| 438 | |
| 439 | /* multicast polynomial */ |
| 440 | #define TXP_POLYNOMIAL 0x04c11db7 |
| 441 | |
| 442 | /* |
| 443 | * boot record (pointers to rings) |
| 444 | */ |
| 445 | struct txp_boot_record { |
| 446 | volatile u_int32_t br_hostvar_lo; /* host ring pointer */ |
| 447 | volatile u_int32_t br_hostvar_hi; |
| 448 | volatile u_int32_t br_txlopri_lo; /* tx low pri ring */ |
| 449 | volatile u_int32_t br_txlopri_hi; |
| 450 | volatile u_int32_t br_txlopri_siz; |
| 451 | volatile u_int32_t br_txhipri_lo; /* tx high pri ring */ |
| 452 | volatile u_int32_t br_txhipri_hi; |
| 453 | volatile u_int32_t br_txhipri_siz; |
| 454 | volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */ |
| 455 | volatile u_int32_t br_rxlopri_hi; |
| 456 | volatile u_int32_t br_rxlopri_siz; |
| 457 | volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */ |
| 458 | volatile u_int32_t br_rxbuf_hi; |
| 459 | volatile u_int32_t br_rxbuf_siz; |
| 460 | volatile u_int32_t br_cmd_lo; /* command ring */ |
| 461 | volatile u_int32_t br_cmd_hi; |
| 462 | volatile u_int32_t br_cmd_siz; |
| 463 | volatile u_int32_t br_resp_lo; /* response ring */ |
| 464 | volatile u_int32_t br_resp_hi; |
| 465 | volatile u_int32_t br_resp_siz; |
| 466 | volatile u_int32_t br_zero_lo; /* zero word */ |
| 467 | volatile u_int32_t br_zero_hi; |
| 468 | volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */ |
| 469 | volatile u_int32_t br_rxhipri_hi; |
| 470 | volatile u_int32_t br_rxhipri_siz; |
| 471 | }; |
| 472 | |
| 473 | /* |
| 474 | * hostvar structure (shared with typhoon) |
| 475 | */ |
| 476 | struct txp_hostvar { |
| 477 | volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */ |
| 478 | volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */ |
| 479 | volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */ |
| 480 | volatile u_int32_t hv_resp_read_idx; /* host->arm */ |
| 481 | volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */ |
| 482 | volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */ |
| 483 | volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */ |
| 484 | volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */ |
| 485 | volatile u_int32_t hv_cmd_read_idx; /* arm->host */ |
| 486 | volatile u_int32_t hv_resp_write_idx; /* arm->host */ |
| 487 | volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */ |
| 488 | }; |
| 489 | |
| 490 | /* |
| 491 | * TYPHOON status register state (in TXP_A2H_0) |
| 492 | */ |
| 493 | #define STAT_ROM_CODE 0x00000001 |
| 494 | #define STAT_ROM_EEPROM_LOAD 0x00000002 |
| 495 | #define STAT_WAITING_FOR_BOOT 0x00000007 |
| 496 | #define STAT_RUNNING 0x00000009 |
| 497 | #define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d |
| 498 | #define STAT_WAITING_FOR_SEGMENT 0x00000010 |
| 499 | #define STAT_SLEEPING 0x00000011 |
| 500 | #define STAT_HALTED 0x00000014 |
| 501 | |
| 502 | #define TX_ENTRIES 256 |
| 503 | #define RX_ENTRIES 128 |
| 504 | #define RXBUF_ENTRIES 256 |
| 505 | #define CMD_ENTRIES 32 |
| 506 | #define RSP_ENTRIES 32 |
| 507 | |
| 508 | #define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ |
| 509 | #define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ |
| 510 | #define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ |
| 511 | #define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ |
| 512 | #define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ |
| 513 | #define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ |
| 514 | #define OFFLOAD_VLAN 0x00000080 /* vlan enable */ |
| 515 | #define OFFLOAD_FILTER 0x00000100 /* filter enable */ |
| 516 | #define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ |
| 517 | #define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ |
| 518 | |
| 519 | /* |
| 520 | * Macros for converting array indices to offsets within the descriptor |
| 521 | * arrays. The chip operates on offsets, but it's much easier for us |
| 522 | * to operate on indices. Assumes descriptor entries are 16 bytes. |
| 523 | */ |
| 524 | #define TXP_IDX2OFFSET(idx) ((idx) << 4) |
| 525 | #define TXP_OFFSET2IDX(off) ((off) >> 4) |
| 526 | |
| 527 | struct txp_dma_alloc { |
| 528 | u_int64_t dma_paddr; |
| 529 | void * dma_vaddr; |
| 530 | bus_dmamap_t dma_map; |
| 531 | bus_dma_segment_t dma_seg; |
| 532 | int dma_nseg; |
| 533 | }; |
| 534 | |
| 535 | struct txp_cmd_ring { |
| 536 | struct txp_cmd_desc *base; |
| 537 | u_int32_t lastwrite; |
| 538 | u_int32_t size; |
| 539 | }; |
| 540 | |
| 541 | struct txp_rsp_ring { |
| 542 | struct txp_rsp_desc *base; |
| 543 | u_int32_t lastwrite; |
| 544 | u_int32_t size; |
| 545 | }; |
| 546 | |
| 547 | struct txp_tx_ring { |
| 548 | struct txp_tx_desc *r_desc; /* base address of descs */ |
| 549 | u_int32_t r_reg; /* register to activate */ |
| 550 | u_int32_t r_prod; /* producer */ |
| 551 | u_int32_t r_cons; /* consumer */ |
| 552 | u_int32_t r_cnt; /* # descs in use */ |
| 553 | volatile u_int32_t *r_off; /* hostvar index pointer */ |
| 554 | }; |
| 555 | |
| 556 | struct txp_swdesc { |
| 557 | struct mbuf * sd_mbuf; |
| 558 | bus_dmamap_t sd_map; |
| 559 | }; |
| 560 | |
| 561 | struct txp_rx_ring { |
| 562 | struct txp_rx_desc *r_desc; /* base address of descs */ |
| 563 | volatile u_int32_t *r_roff; /* hv read offset ptr */ |
| 564 | volatile u_int32_t *r_woff; /* hv write offset ptr */ |
| 565 | }; |
| 566 | |
| 567 | struct txp_softc { |
| 568 | device_t sc_dev; /* base device */ |
| 569 | struct ethercom sc_arpcom; /* ethernet common */ |
| 570 | struct txp_hostvar *sc_hostvar; |
| 571 | struct txp_boot_record *sc_boot; |
| 572 | bus_space_handle_t sc_bh; /* bus handle (regs) */ |
| 573 | bus_space_tag_t sc_bt; /* bus tag (regs) */ |
| 574 | bus_dma_tag_t sc_dmat; /* dma tag */ |
| 575 | struct txp_cmd_ring sc_cmdring; |
| 576 | struct txp_rsp_ring sc_rspring; |
| 577 | struct txp_swdesc sc_txd[TX_ENTRIES]; |
| 578 | void * sc_ih; |
| 579 | struct callout sc_tick; |
| 580 | struct ifmedia sc_ifmedia; |
| 581 | struct txp_tx_ring sc_txhir, sc_txlor; |
| 582 | struct txp_rxbuf_desc *sc_rxbufs; |
| 583 | struct txp_rx_ring sc_rxhir, sc_rxlor; |
| 584 | u_int16_t sc_xcvr; |
| 585 | u_int16_t sc_seq; |
| 586 | struct txp_dma_alloc sc_boot_dma, sc_host_dma, sc_zero_dma; |
| 587 | struct txp_dma_alloc sc_rxhiring_dma, sc_rxloring_dma; |
| 588 | struct txp_dma_alloc sc_txhiring_dma, sc_txloring_dma; |
| 589 | struct txp_dma_alloc sc_cmdring_dma, sc_rspring_dma; |
| 590 | struct txp_dma_alloc sc_rxbufring_dma; |
| 591 | int sc_cold; |
| 592 | u_int32_t sc_rx_capability, sc_tx_capability; |
| 593 | int sc_flags; |
| 594 | #define TXP_USESUBSYSTEM 0x1 /* use PCI subsys reg for detail info */ |
| 595 | #define TXP_SERVERVERSION 0x2 |
| 596 | #define TXP_FIBER 0x4 |
| 597 | }; |
| 598 | |
| 599 | #define TXP_DEVNAME(sc) ((sc)->sc_cold ? "" : device_xname((sc)->sc_dev)) |
| 600 | |
| 601 | struct { |
| 602 | u_int8_t [8]; /* TYPHOON\0 */ |
| 603 | u_int32_t ; |
| 604 | u_int32_t ; |
| 605 | u_int32_t ; |
| 606 | }; |
| 607 | |
| 608 | struct { |
| 609 | u_int32_t ; |
| 610 | u_int16_t ; |
| 611 | u_int16_t ; |
| 612 | u_int32_t ; |
| 613 | }; |
| 614 | |
| 615 | #define TXP_MAX_SEGLEN 0xffff |
| 616 | #define TXP_MAX_PKTLEN 0x0800 |
| 617 | |
| 618 | #define WRITE_REG(sc,reg,val) \ |
| 619 | bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val) |
| 620 | #define READ_REG(sc,reg) \ |
| 621 | bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg) |
| 622 | |
| 623 | |