| 1 | /* $NetBSD: siopreg.h,v 1.22 2009/10/19 18:41:13 bouyer Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2000 Manuel Bouyer. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * Devices definitions for Symbios/NCR M53c8xx PCI-SCSI I/O Processors |
| 30 | * Docs available from http://www.symbios.com/ |
| 31 | */ |
| 32 | |
| 33 | #define SIOP_SCNTL0 0x00 /* SCSI control 0, R/W */ |
| 34 | #define SCNTL0_ARB_MASK 0xc0 |
| 35 | #define SCNTL0_SARB 0x00 |
| 36 | #define SCNTL0_FARB 0xc0 |
| 37 | #define SCNTL0_START 0x20 |
| 38 | #define SCNTL0_WATM 0x10 |
| 39 | #define SCNTL0_EPC 0x08 |
| 40 | #define SCNTL0_AAP 0x02 |
| 41 | #define SCNTL0_TRG 0x01 |
| 42 | |
| 43 | #define SIOP_SCNTL1 0x01 /* SCSI control 1, R/W */ |
| 44 | #define SCNTL1_EXC 0x80 |
| 45 | #define SCNTL1_ADB 0x40 |
| 46 | #define SCNTL1_DHP 0x20 |
| 47 | #define SCNTL1_CON 0x10 |
| 48 | #define SCNTL1_RST 0x08 |
| 49 | #define SCNTL1_AESP 0x04 |
| 50 | #define SCNTL1_IARB 0x02 |
| 51 | #define SCNTL1_SST 0x01 |
| 52 | |
| 53 | #define SIOP_SCNTL2 0x02 /* SCSI control 2, R/W */ |
| 54 | #define SCNTL2_SDU 0x80 |
| 55 | #define SCNTL2_CHM 0x40 /* 875 only */ |
| 56 | #define SCNTL2_SLPMD 0x20 /* 875 only */ |
| 57 | #define SCNTL2_SLPHBEN 0x10 /* 875 only */ |
| 58 | #define SCNTL2_WSS 0x08 /* 875 only */ |
| 59 | #define SCNTL2_VUE0 0x04 /* 875 only */ |
| 60 | #define SCNTL2_VUE1 0x02 /* 875 only */ |
| 61 | #define SCNTL2_WSR 0x01 /* 875 only */ |
| 62 | |
| 63 | #define SIOP_SCNTL3 0x03 /* SCSI control 3, R/W */ |
| 64 | #define SCNTL3_ULTRA 0x80 /* 875 only */ |
| 65 | #define SCNTL3_SCF_SHIFT 4 |
| 66 | #define SCNTL3_SCF_MASK 0x70 |
| 67 | #define SCNTL3_EWS 0x08 /* 875 only */ |
| 68 | #define SCNTL3_CCF_SHIFT 0 |
| 69 | #define SCNTL3_CCF_MASK 0x07 |
| 70 | |
| 71 | /* periods for various SCF values, assume transfer period of 4 */ |
| 72 | struct scf_period { |
| 73 | int clock; /* clock period (ns * 10) */ |
| 74 | int period; /* scsi period, as set in the SDTR message */ |
| 75 | int scf; /* scf value to use */ |
| 76 | }; |
| 77 | |
| 78 | static const struct scf_period scf_period[] __unused = { |
| 79 | {250, 25, 1}, /* 10.0 MHz */ |
| 80 | {250, 37, 2}, /* 6.67 MHz */ |
| 81 | {250, 50, 3}, /* 5.00 MHz */ |
| 82 | {250, 75, 4}, /* 3.33 MHz */ |
| 83 | {125, 12, 1}, /* 20.0 MHz */ |
| 84 | {125, 18, 2}, /* 13.3 MHz */ |
| 85 | {125, 25, 3}, /* 10.0 MHz */ |
| 86 | {125, 37, 4}, /* 6.67 MHz */ |
| 87 | {125, 50, 5}, /* 5.0 MHz */ |
| 88 | { 62, 10, 1}, /* 40.0 MHz */ |
| 89 | { 62, 12, 3}, /* 20.0 MHz */ |
| 90 | { 62, 18, 4}, /* 13.3 MHz */ |
| 91 | { 62, 25, 5}, /* 10.0 MHz */ |
| 92 | }; |
| 93 | |
| 94 | static const struct scf_period dt_scf_period[] __unused = { |
| 95 | { 62, 9, 1}, /* 80.0 MHz */ |
| 96 | { 62, 10, 3}, /* 40.0 MHz */ |
| 97 | { 62, 12, 5}, /* 20.0 MHz */ |
| 98 | { 62, 18, 6}, /* 13.3 MHz */ |
| 99 | { 62, 25, 7}, /* 10.0 MHz */ |
| 100 | }; |
| 101 | |
| 102 | #define SIOP_SCID 0x04 /* SCSI chip ID R/W */ |
| 103 | #define SCID_RRE 0x40 |
| 104 | #define SCID_SRE 0x20 |
| 105 | #define SCID_ENCID_SHIFT 0 |
| 106 | #define SCID_ENCID_MASK 0x07 |
| 107 | |
| 108 | #define SIOP_SXFER 0x05 /* SCSI transfer, R/W */ |
| 109 | #define SXFER_TP_SHIFT 5 |
| 110 | #define SXFER_TP_MASK 0xe0 |
| 111 | #define SXFER_MO_SHIFT 0 |
| 112 | #define SXFER_MO_MASK 0x3f |
| 113 | |
| 114 | #define SIOP_SDID 0x06 /* SCSI destination ID, R/W */ |
| 115 | #define SDID_ENCID_SHIFT 0 |
| 116 | #define SDID_ENCID_MASK 0x07 |
| 117 | |
| 118 | #define SIOP_GPREG 0x07 /* General purpose, R/W */ |
| 119 | #define GPREG_GPIO4 0x10 /* 875 only */ |
| 120 | #define GPREG_GPIO3 0x08 /* 875 only */ |
| 121 | #define GPREG_GPIO2 0x04 /* 875 only */ |
| 122 | #define GPREG_GPIO1 0x02 |
| 123 | #define GPREG_GPIO0 0x01 |
| 124 | |
| 125 | #define SIOP_SFBR 0x08 /* SCSI first byte received, R/W */ |
| 126 | |
| 127 | #define SIOP_SOCL 0x09 /* SCSI output control latch, RW */ |
| 128 | |
| 129 | #define SIOP_SSID 0x0A /* SCSI selector ID, RO */ |
| 130 | #define SSID_VAL 0x80 |
| 131 | #define SSID_ENCID_SHIFT 0 |
| 132 | #define SSID_ENCID_MASK 0x0f |
| 133 | |
| 134 | #define SIOP_SBCL 0x0B /* SCSI control line, RO */ |
| 135 | |
| 136 | #define SIOP_DSTAT 0x0C /* DMA status, RO */ |
| 137 | #define DSTAT_DFE 0x80 |
| 138 | #define DSTAT_MDPE 0x40 |
| 139 | #define DSTAT_BF 0x20 |
| 140 | #define DSTAT_ABRT 0x10 |
| 141 | #define DSTAT_SSI 0x08 |
| 142 | #define DSTAT_SIR 0x04 |
| 143 | #define DSTAT_IID 0x01 |
| 144 | |
| 145 | #define SIOP_SSTAT0 0x0D /* STSI status 0, RO */ |
| 146 | #define SSTAT0_ILF 0x80 |
| 147 | #define SSTAT0_ORF 0x40 |
| 148 | #define SSTAT0_OLF 0x20 |
| 149 | #define SSTAT0_AIP 0x10 |
| 150 | #define SSTAT0_LOA 0x08 |
| 151 | #define SSTAT0_WOA 0x04 |
| 152 | #define SSTAT0_RST 0x02 |
| 153 | #define SSTAT0_SDP 0x01 |
| 154 | |
| 155 | #define SIOP_SSTAT1 0x0E /* STSI status 1, RO */ |
| 156 | #define SSTAT1_FFO_SHIFT 4 |
| 157 | #define SSTAT1_FFO_MASK 0x80 |
| 158 | #define SSTAT1_SDPL 0x08 |
| 159 | #define SSTAT1_MSG 0x04 |
| 160 | #define SSTAT1_CD 0x02 |
| 161 | #define SSTAT1_IO 0x01 |
| 162 | #define SSTAT1_PHASE_MASK (SSTAT1_IO | SSTAT1_CD | SSTAT1_MSG) |
| 163 | #define SSTAT1_PHASE_DATAOUT 0 |
| 164 | #define SSTAT1_PHASE_DATAIN SSTAT1_IO |
| 165 | #define SSTAT1_PHASE_CMD SSTAT1_CD |
| 166 | #define SSTAT1_PHASE_STATUS (SSTAT1_CD | SSTAT1_IO) |
| 167 | #define SSTAT1_PHASE_MSGOUT (SSTAT1_MSG | SSTAT1_CD) |
| 168 | #define SSTAT1_PHASE_MSGIN (SSTAT1_MSG | SSTAT1_CD | SSTAT1_IO) |
| 169 | |
| 170 | #define SIOP_SSTAT2 0x0F /* STSI status 2, RO */ |
| 171 | #define SSTAT2_ILF1 0x80 /* 875 only */ |
| 172 | #define SSTAT2_ORF1 0x40 /* 875 only */ |
| 173 | #define SSTAT2_OLF1 0x20 /* 875 only */ |
| 174 | #define SSTAT2_FF4 0x10 /* 875 only */ |
| 175 | #define SSTAT2_SPL1 0x08 /* 875 only */ |
| 176 | #define SSTAT2_DF 0x04 /* 875 only */ |
| 177 | #define SSTAT2_LDSC 0x02 |
| 178 | #define SSTAT2_SDP1 0x01 /* 875 only */ |
| 179 | |
| 180 | #define SIOP_DSA 0x10 /* data struct addr, R/W */ |
| 181 | |
| 182 | #define SIOP_ISTAT 0x14 /* IRQ status, R/W */ |
| 183 | #define ISTAT_ABRT 0x80 |
| 184 | #define ISTAT_SRST 0x40 |
| 185 | #define ISTAT_SIGP 0x20 |
| 186 | #define ISTAT_SEM 0x10 |
| 187 | #define ISTAT_CON 0x08 |
| 188 | #define ISTAT_INTF 0x04 |
| 189 | #define ISTAT_SIP 0x02 |
| 190 | #define ISTAT_DIP 0x01 |
| 191 | |
| 192 | #define SIOP_CTEST0 0x18 /* Chip test 0, R/W */ |
| 193 | #define CTEST0_EHP 0x04 /* 720/770 */ |
| 194 | |
| 195 | #define SIOP_CTEST1 0x19 /* Chip test 1, R/W */ |
| 196 | |
| 197 | #define SIOP_CTEST2 0x1A /* Chip test 2, R/W */ |
| 198 | #define CTEST2_SRTCH 0x04 /* 875 only */ |
| 199 | |
| 200 | #define SIOP_CTEST3 0x1B /* Chip test 3, R/W */ |
| 201 | #define CTEST3_FLF 0x08 |
| 202 | #define CTEST3_CLF 0x04 |
| 203 | #define CTEST3_FM 0x02 |
| 204 | #define CTEST3_WRIE 0x01 |
| 205 | |
| 206 | #define SIOP_TEMP 0x1C /* Temp register (used by CALL/RET), R/W */ |
| 207 | |
| 208 | #define SIOP_DFIFO 0x20 /* DMA FIFO */ |
| 209 | |
| 210 | #define SIOP_CTEST4 0x21 /* Chip test 4, R/W */ |
| 211 | #define CTEST4_MUX 0x80 /* 720/770 */ |
| 212 | #define CTEST4_BDIS 0x80 |
| 213 | #define CTEST_ZMOD 0x40 |
| 214 | #define CTEST_ZSD 0x20 |
| 215 | #define CTEST_SRTM 0x10 |
| 216 | #define CTEST_MPEE 0x08 |
| 217 | |
| 218 | #define SIOP_CTEST5 0x22 /* Chip test 5, R/W */ |
| 219 | #define CTEST5_ADCK 0x80 |
| 220 | #define CTEST5_BBCK 0x40 |
| 221 | #define CTEST5_DFS 0x20 |
| 222 | #define CTEST5_MASR 0x10 |
| 223 | #define CTEST5_DDIR 0x08 |
| 224 | #define CTEST5_BOMASK 0x03 |
| 225 | |
| 226 | #define SIOP_CTEST6 0x23 /* Chip test 6, R/W */ |
| 227 | |
| 228 | #define SIOP_DBC 0x24 /* DMA byte counter, R/W */ |
| 229 | |
| 230 | #define SIOP_DCMD 0x27 /* DMA command, R/W */ |
| 231 | |
| 232 | #define SIOP_DNAD 0x28 /* DMA next addr, R/W */ |
| 233 | |
| 234 | #define SIOP_DSP 0x2C /* DMA scripts pointer, R/W */ |
| 235 | |
| 236 | #define SIOP_DSPS 0x30 /* DMA scripts pointer save, R/W */ |
| 237 | |
| 238 | #define SIOP_SCRATCHA 0x34 /* scratch register A. R/W */ |
| 239 | |
| 240 | #define SIOP_DMODE 0x38 /* DMA mode, R/W */ |
| 241 | #define DMODE_BL_SHIFT 6 |
| 242 | #define DMODE_BL_MASK 0xC0 |
| 243 | #define DMODE_SIOM 0x20 |
| 244 | #define DMODE_DIOM 0x10 |
| 245 | #define DMODE_ERL 0x08 |
| 246 | #define DMODE_ERMP 0x04 |
| 247 | #define DMODE_BOF 0x02 |
| 248 | #define DMODE_MAN 0x01 |
| 249 | |
| 250 | #define SIOP_DIEN 0x39 /* DMA interrupt enable, R/W */ |
| 251 | #define DIEN_MDPE 0x40 |
| 252 | #define DIEN_BF 0x20 |
| 253 | #define DIEN_AVRT 0x10 |
| 254 | #define DIEN_SSI 0x08 |
| 255 | #define DIEN_SIR 0x04 |
| 256 | #define DIEN_IID 0x01 |
| 257 | |
| 258 | #define SIOP_SBR 0x3A /* scratch byte register, R/W */ |
| 259 | |
| 260 | #define SIOP_DCNTL 0x3B /* DMA control, R/W */ |
| 261 | #define DCNTL_CLSE 0x80 |
| 262 | #define DCNTL_PFF 0x40 |
| 263 | #define DCNTL_EA 0x20 /* 720/770 */ |
| 264 | #define DCNTL_PFEN 0x20 /* 8xx */ |
| 265 | #define DCNTL_SSM 0x10 |
| 266 | #define DCNTL_IRQM 0x08 |
| 267 | #define DCNTL_STD 0x04 |
| 268 | #define DCNTL_IRQD 0x02 |
| 269 | #define DCNTL_COM 0x01 |
| 270 | |
| 271 | #define SIOP_ADDER 0x3C /* adder output sum, RO */ |
| 272 | |
| 273 | #define SIOP_SIEN0 0x40 /* SCSI interrupt enable 0, R/W */ |
| 274 | #define SIEN0_MA 0x80 |
| 275 | #define SIEN0_CMP 0x40 |
| 276 | #define SIEN0_SEL 0x20 |
| 277 | #define SIEN0_RSL 0x10 |
| 278 | #define SIEN0_SGE 0x08 |
| 279 | #define SIEN0_UDC 0x04 |
| 280 | #define SIEN0_SRT 0x02 |
| 281 | #define SIEN0_PAR 0x01 |
| 282 | |
| 283 | #define SIOP_SIEN1 0x41 /* SCSI interrupt enable 1, R/W */ |
| 284 | #define SIEN1_SBMC 0x10 /* 895 only */ |
| 285 | #define SIEN1_STO 0x04 |
| 286 | #define SIEN1_GEN 0x02 |
| 287 | #define SIEN1_HTH 0x01 |
| 288 | |
| 289 | #define SIOP_SIST0 0x42 /* SCSI interrupt status 0, RO */ |
| 290 | #define SIST0_MA 0x80 |
| 291 | #define SIST0_CMP 0x40 |
| 292 | #define SIST0_SEL 0x20 |
| 293 | #define SIST0_RSL 0x10 |
| 294 | #define SIST0_SGE 0x08 |
| 295 | #define SIST0_UDC 0x04 |
| 296 | #define SIST0_RST 0x02 |
| 297 | #define SIST0_PAR 0x01 |
| 298 | |
| 299 | #define SIOP_SIST1 0x43 /* SCSI interrupt status 1, RO */ |
| 300 | #define SIST1_SBMC 0x10 /* 895 only */ |
| 301 | #define SIST1_STO 0x04 |
| 302 | #define SIST1_GEN 0x02 |
| 303 | #define SIST1_HTH 0x01 |
| 304 | |
| 305 | #define SIOP_SLPAR 0x44 /* scsi longitudinal parity, R/W */ |
| 306 | |
| 307 | #define SIOP_SWIDE 0x45 /* scsi wide residue, RW, 875 only */ |
| 308 | |
| 309 | #define SIOP_MACNTL 0x46 /* memory access control, R/W */ |
| 310 | |
| 311 | #define SIOP_GPCNTL 0x47 /* General Purpose Pin control, R/W */ |
| 312 | #define GPCNTL_ME 0x80 /* 875 only */ |
| 313 | #define GPCNTL_FE 0x40 /* 875 only */ |
| 314 | #define GPCNTL_IN4 0x10 /* 875 only */ |
| 315 | #define GPCNTL_IN3 0x08 /* 875 only */ |
| 316 | #define GPCNTL_IN2 0x04 /* 875 only */ |
| 317 | #define GPCNTL_IN1 0x02 |
| 318 | #define GPCNTL_IN0 0x01 |
| 319 | |
| 320 | #define SIOP_STIME0 0x48 /* SCSI timer 0, R/W */ |
| 321 | #define STIME0_HTH_SHIFT 4 |
| 322 | #define STIME0_HTH_MASK 0xf0 |
| 323 | #define STIME0_SEL_SHIFT 0 |
| 324 | #define STIME0_SEL_MASK 0x0f |
| 325 | |
| 326 | #define SIOP_STIME1 0x49 /* SCSI timer 1, R/W */ |
| 327 | #define STIME1_HTHBA 0x40 /* 875 only */ |
| 328 | #define STIME1_GENSF 0x20 /* 875 only */ |
| 329 | #define STIME1_HTHSF 0x10 /* 875 only */ |
| 330 | #define STIME1_GEN_SHIFT 0 |
| 331 | #define STIME1_GEN_MASK 0x0f |
| 332 | |
| 333 | #define SIOP_RESPID0 0x4A /* response ID, R/W */ |
| 334 | |
| 335 | #define SIOP_RESPID1 0x4B /* response ID, R/W, 875-only */ |
| 336 | |
| 337 | #define SIOP_STEST0 0x4C /* SCSI test 0, RO */ |
| 338 | |
| 339 | #define SIOP_STEST1 0x4D /* SCSI test 1, RO, RW on 875 */ |
| 340 | #define STEST1_DOGE 0x20 /* 1010 only */ |
| 341 | #define STEST1_DIGE 0x10 /* 1010 only */ |
| 342 | #define STEST1_DBLEN 0x08 /* 875-only */ |
| 343 | #define STEST1_DBLSEL 0x04 /* 875-only */ |
| 344 | #define STEST1_SCLK 0x80 |
| 345 | |
| 346 | #define SIOP_STEST2 0x4E /* SCSI test 2, RO, R/W on 875 */ |
| 347 | #define STEST2_DIF 0x20 /* 875 only */ |
| 348 | #define STEST2_EXT 0x02 |
| 349 | |
| 350 | #define SIOP_STEST3 0x4F /* SCSI test 3, RO, RW on 875 */ |
| 351 | #define STEST3_TE 0x80 |
| 352 | #define STEST3_HSC 0x20 |
| 353 | |
| 354 | #define SIOP_STEST4 0x52 /* SCSI test 4, 895 only */ |
| 355 | #define STEST4_MODE_MASK 0xc0 |
| 356 | #define STEST4_MODE_DIF 0x40 |
| 357 | #define STEST4_MODE_SE 0x80 |
| 358 | #define STEST4_MODE_LVD 0xc0 |
| 359 | #define STEST4_LOCK 0x20 |
| 360 | #define STEST4_ |
| 361 | |
| 362 | #define SIOP_SIDL 0x50 /* SCSI input data latch, RO */ |
| 363 | |
| 364 | #define SIOP_SODL 0x54 /* SCSI output data latch, R/W */ |
| 365 | |
| 366 | #define SIOP_SBDL 0x58 /* SCSI bus data lines, RO */ |
| 367 | |
| 368 | #define SIOP_SCRATCHB 0x5C /* Scratch register B, R/W */ |
| 369 | |
| 370 | #define SIOP_SCRATCHC 0x60 /* Scratch register C, R/W, 875 only */ |
| 371 | |
| 372 | #define SIOP_SCRATCHD 0x64 /* Scratch register D, R/W, 875-only */ |
| 373 | |
| 374 | #define SIOP_SCRATCHE 0x68 /* Scratch register E, R/W, 875-only */ |
| 375 | |
| 376 | #define SIOP_SCRATCHF 0x6c /* Scratch register F, R/W, 875-only */ |
| 377 | |
| 378 | #define SIOP_SCRATCHG 0x70 /* Scratch register G, R/W, 875-only */ |
| 379 | |
| 380 | #define SIOP_SCRATCHH 0x74 /* Scratch register H, R/W, 875-only */ |
| 381 | |
| 382 | #define SIOP_SCRATCHI 0x78 /* Scratch register I, R/W, 875-only */ |
| 383 | |
| 384 | #define SIOP_SCRATCHJ 0x7c /* Scratch register J, R/W, 875-only */ |
| 385 | |
| 386 | #define SIOP_SCNTL4 0xBC /* SCSI control 4, R/W, 1010-only */ |
| 387 | #define SCNTL4_XCLKS_ST 0x01 |
| 388 | #define SCNTL4_XCLKS_DT 0x02 |
| 389 | #define SCNTL4_XCLKH_ST 0x04 |
| 390 | #define SCNTL4_XCLKH_DT 0x08 |
| 391 | #define SCNTL4_AIPEN 0x40 |
| 392 | #define SCNTL4_U3EN 0x80 |
| 393 | |
| 394 | #define SIOP_DFBC 0xf0 /* DMA fifo byte count, RO */ |
| 395 | |
| 396 | #define SIOP_AIPCNTL0 0xbe /* AIP Control 0, 1010-only */ |
| 397 | #define AIPCNTL0_ERRLIVE 0x04 /* AIP error status, live */ |
| 398 | #define AIPCNTL0_ERR 0x02 /* AIP error status, latched */ |
| 399 | #define AIPCNTL0_PARITYERRs 0x01 /* Parity error */ |
| 400 | |
| 401 | #define SIOP_AIPCNTL1 0xbf /* AIP Control 1, 1010-only */ |
| 402 | #define AIPCNTL1_DIS 0x08 /* disable AIP generation, 1010-66 only */ |
| 403 | #define AIPCNTL1_RSETERR 0x04 /* reset AIP error 1010-66 only */ |
| 404 | #define AIPCNTL1_FB 0x02 /* force bad AIP value 1010-66 only */ |
| 405 | #define AIPCNTL1_RSET 0x01 /* reset AIP sequence value 1010-66 only */ |
| 406 | |
| 407 | /* |
| 408 | * Non-volatile configuration settings stored in the EEPROM. There |
| 409 | * are at least two known formats: Symbios Logic format and Tekram format. |
| 410 | */ |
| 411 | |
| 412 | #define SIOP_NVRAM_SYM_SIZE 368 |
| 413 | #define SIOP_NVRAM_SYM_ADDRESS 0x100 |
| 414 | |
| 415 | struct nvram_symbios { |
| 416 | /* Header (6 bytes) */ |
| 417 | uint16_t type; /* 0x0000 */ |
| 418 | uint16_t byte_count; /* excluding header/trailer */ |
| 419 | uint16_t checksum; |
| 420 | |
| 421 | /* Adapter configuration (20 bytes) */ |
| 422 | uint8_t v_major; |
| 423 | uint8_t v_minor; |
| 424 | uint32_t boot_crc; |
| 425 | uint16_t flags; |
| 426 | #define NVRAM_SYM_F_SCAM_ENABLE 0x0001 |
| 427 | #define NVRAM_SYM_F_PARITY_ENABLE 0x0002 |
| 428 | #define NVRAM_SYM_F_VERBOSE_MESSAGES 0x0004 |
| 429 | #define NVRAM_SYM_F_CHS_MAPPING 0x0008 |
| 430 | uint16_t flags1; |
| 431 | #define NVRAM_SYM_F1_SCAN_HI_LO 0x0001 |
| 432 | uint16_t term_state; |
| 433 | #define NVRAM_SYM_TERM_CANT_PROGRAM 0 |
| 434 | #define NVRAM_SYM_TERM_ENABLED 1 |
| 435 | #define NVRAM_SYM_TERM_DISABLED 2 |
| 436 | uint16_t rmvbl_flags; |
| 437 | #define NVRAM_SYM_RMVBL_NO_SUPPORT 0 |
| 438 | #define NVRAM_SYM_RMVBL_BOOT_DEVICE 1 |
| 439 | #define NVRAM_SYM_RMVBL_MEDIA_INSTALLED 2 |
| 440 | uint8_t host_id; |
| 441 | uint8_t num_hba; |
| 442 | uint8_t num_devices; |
| 443 | uint8_t max_scam_devices; |
| 444 | uint8_t num_valid_scam_devices; |
| 445 | uint8_t rsvd; |
| 446 | |
| 447 | /* Boot order (14 bytes x 4) */ |
| 448 | struct nvram_symbios_host { |
| 449 | uint16_t type; /* 4 - 8xx */ |
| 450 | uint16_t device_id; /* PCI device ID */ |
| 451 | uint16_t vendor_id; /* PCI vendor ID */ |
| 452 | uint8_t bus_nr; /* PCI bus number */ |
| 453 | uint8_t device_fn; /* PCI device/func # << 3 */ |
| 454 | uint16_t word8; |
| 455 | uint16_t flags; |
| 456 | #define NVRAM_SYM_HOST_F_SCAN_AT_BOOT 0x0001 |
| 457 | uint16_t io_port; /* PCI I/O address */ |
| 458 | } __packed host[4]; |
| 459 | |
| 460 | /* Targets (8 bytes x 16) */ |
| 461 | struct nvram_symbios_target { |
| 462 | uint8_t flags; |
| 463 | #define NVRAM_SYM_TARG_F_DISCONNECT_EN 0x0001 |
| 464 | #define NVRAM_SYM_TARG_F_SCAN_AT_BOOT 0x0002 |
| 465 | #define NVRAM_SYM_TARG_F_SCAN_LUNS 0x0004 |
| 466 | #define NVRAM_SYM_TARG_F_TQ_EN 0x0008 |
| 467 | uint8_t rsvd; |
| 468 | uint8_t bus_width; |
| 469 | uint8_t sync_offset; /* 8, 16, etc. */ |
| 470 | uint16_t sync_period; /* 4 * factor */ |
| 471 | uint16_t timeout; |
| 472 | } __packed target[16]; |
| 473 | |
| 474 | /* SCAM table (8 bytes x 4) */ |
| 475 | struct nvram_symbios_scam { |
| 476 | uint16_t id; |
| 477 | uint16_t method; |
| 478 | #define NVRAM_SYM_SCAM_DEFAULT_METHOD 0 |
| 479 | #define NVRAM_SYM_SCAM_DONT_ASSIGN 1 |
| 480 | #define NVRAM_SYM_SCAM_SET_SPECIFIC_ID 2 |
| 481 | #define NVRAM_SYM_SCAM_USE_ORDER_GIVEN 3 |
| 482 | uint16_t status; |
| 483 | #define NVRAM_SYM_SCAM_UNKNOWN 0 |
| 484 | #define NVRAM_SYM_SCAM_DEVICE_NOT_FOUND 1 |
| 485 | #define NVRAM_SYM_SCAM_ID_NOT_SET 2 |
| 486 | #define NVRAM_SYM_SCAM_ID_VALID 3 |
| 487 | uint8_t target_id; |
| 488 | uint8_t rsvd; |
| 489 | } __packed scam[4]; |
| 490 | |
| 491 | uint8_t spare_devices[15 * 8]; |
| 492 | uint8_t trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ |
| 493 | } __packed; |
| 494 | |
| 495 | #define SIOP_NVRAM_TEK_SIZE 64 |
| 496 | #define SIOP_NVRAM_TEK_93c46_ADDRESS 0 |
| 497 | #define SIOP_NVRAM_TEK_24c16_ADDRESS 0x40 |
| 498 | |
| 499 | static const uint8_t tekram_sync_table[16] __unused = { |
| 500 | 25, 31, 37, 43, |
| 501 | 50, 62, 75, 125, |
| 502 | 12, 15, 18, 21, |
| 503 | 6, 7, 9, 10, |
| 504 | }; |
| 505 | |
| 506 | struct nvram_tekram { |
| 507 | struct nvram_tekram_target { |
| 508 | uint8_t flags; |
| 509 | #define NVRAM_TEK_TARG_F_PARITY_CHECK 0x01 |
| 510 | #define NVRAM_TEK_TARG_F_SYNC_NEGO 0x02 |
| 511 | #define NVRAM_TEK_TARG_F_DISCONNECT_EN 0x04 |
| 512 | #define NVRAM_TEK_TARG_F_START_CMD 0x08 |
| 513 | #define NVRAM_TEK_TARG_F_TQ_EN 0x10 |
| 514 | #define NVRAM_TEK_TARG_F_WIDE_NEGO 0x20 |
| 515 | uint8_t sync_index; |
| 516 | uint16_t word2; |
| 517 | } __packed target[16]; |
| 518 | uint8_t host_id; |
| 519 | uint8_t flags; |
| 520 | #define NVRAM_TEK_F_MORE_THAN_2_DRIVES 0x01 |
| 521 | #define NVRAM_TEK_F_DRIVES_SUP_1G 0x02 |
| 522 | #define NVRAM_TEK_F_RESET_ON_POWER_ON 0x04 |
| 523 | #define NVRAM_TEK_F_ACTIVE_NEGATION 0x08 |
| 524 | #define NVRAM_TEK_F_IMMEDIATE_SEEK 0x10 |
| 525 | #define NVRAM_TEK_F_SCAN_LUNS 0x20 |
| 526 | #define NVRAM_TEK_F_REMOVABLE_FLAGS 0xc0 /* 0 dis, 1 boot, 2 all */ |
| 527 | uint8_t boot_delay_index; |
| 528 | uint8_t max_tags_index; |
| 529 | uint16_t flags1; |
| 530 | #define NVRAM_TEK_F_F2_F6_ENABLED 0x0001 |
| 531 | uint16_t spare[29]; |
| 532 | } __packed; |
| 533 | |