| 1 | /* $NetBSD: mb89352reg.h,v 1.6 2005/12/11 12:21:27 christos Exp $ */ |
| 2 | /* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. |
| 6 | * All rights reserved. |
| 7 | * Copyright (c) 1990, 1993 |
| 8 | * The Regents of the University of California. All rights reserved. |
| 9 | * |
| 10 | * This code is derived from software contributed to The NetBSD Foundation |
| 11 | * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. |
| 12 | * |
| 13 | * This code is derived from software contributed to Berkeley by |
| 14 | * Van Jacobson of Lawrence Berkeley Laboratory. |
| 15 | * |
| 16 | * Redistribution and use in source and binary forms, with or without |
| 17 | * modification, are permitted provided that the following conditions |
| 18 | * are met: |
| 19 | * 1. Redistributions of source code must retain the above copyright |
| 20 | * notice, this list of conditions and the following disclaimer. |
| 21 | * 2. Redistributions in binary form must reproduce the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer in the |
| 23 | * documentation and/or other materials provided with the distribution. |
| 24 | * 3. Neither the name of the University nor the names of its contributors |
| 25 | * may be used to endorse or promote products derived from this software |
| 26 | * without specific prior written permission. |
| 27 | * |
| 28 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 29 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 31 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 37 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 38 | * SUCH DAMAGE. |
| 39 | * |
| 40 | * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 |
| 41 | */ |
| 42 | |
| 43 | /* |
| 44 | * [NetBSD for NEC PC-98 series] |
| 45 | * Copyright (c) 1996, 1997, 1998 |
| 46 | * NetBSD/pc98 porting staff. All rights reserved. |
| 47 | * Copyright (c) 1996, 1997, 1998 |
| 48 | * Kouichi Matsuda. All rights reserved. |
| 49 | */ |
| 50 | |
| 51 | /* |
| 52 | * FUJITSU MB89352A SCSI Protocol Controller Hardware Description. |
| 53 | */ |
| 54 | |
| 55 | /* Definitions, most of them has turned out to be unneccesary, but here they |
| 56 | * are anyway. |
| 57 | */ |
| 58 | |
| 59 | #define BDID 0x00 /* Bus Device ID (R/W) */ |
| 60 | #define SCTL 0x01 /* SPC Control register (R/W) */ |
| 61 | #define SCMD 0x02 /* Command Register (R/W) */ |
| 62 | #define TMOD 0x03 /* Transmit Mode Register (synch models) */ |
| 63 | #define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */ |
| 64 | #define PSNS 0x05 /* Phase Sence (R); SPC Diagnostic Control (W) */ |
| 65 | #define SSTS 0x06 /* SPC status (R/O) */ |
| 66 | #define SERR 0x07 /* SPC error status (R/O) */ |
| 67 | #define PCTL 0x08 /* Phase Control (R/W) */ |
| 68 | #define MBC 0x09 /* Modified Byte Counter (R/O) */ |
| 69 | #define DREG 0x0a /* Data Register (R/W) */ |
| 70 | #define TEMP 0x0b /* Temporary Register (R/W) */ |
| 71 | #define TCH 0x0c /* Transfer Counter High (R/W) */ |
| 72 | #define TCM 0x0d /* Transfer Counter Middle (R/W) */ |
| 73 | #define TCL 0x0e /* Transfer Counter Low (R/W) */ |
| 74 | #define EXBF 0x0f /* External Buffer (synch models) */ |
| 75 | |
| 76 | /* What all the bits do */ |
| 77 | |
| 78 | /* SCSI_BDID */ |
| 79 | /* SCSI selection/reselection ID (both target *and* initiator) */ |
| 80 | #define SELID7 0x80 |
| 81 | #define SELID6 0x40 |
| 82 | #define SELID5 0x20 |
| 83 | #define SELID4 0x10 |
| 84 | #define SELID3 0x08 |
| 85 | #define SELID2 0x04 |
| 86 | #define SELID1 0x02 |
| 87 | #define SELID0 0x01 |
| 88 | |
| 89 | /* SCSI_SCTL */ |
| 90 | #define SCTL_DISABLE 0x80 |
| 91 | #define SCTL_CTRLRST 0x40 |
| 92 | #define SCTL_DIAG 0x20 |
| 93 | #define SCTL_ABRT_ENAB 0x10 |
| 94 | #define SCTL_PARITY_ENAB 0x08 |
| 95 | #define SCTL_SEL_ENAB 0x04 |
| 96 | #define SCTL_RESEL_ENAB 0x02 |
| 97 | #define SCTL_INTR_ENAB 0x01 |
| 98 | |
| 99 | /* SCSI_SCMD */ |
| 100 | #define SCMD_RST 0x10 |
| 101 | #define SCMD_ICPT_XFR 0x08 |
| 102 | #define SCMD_PROG_XFR 0x04 |
| 103 | #define SCMD_PAD 0x01 /* if initiator */ |
| 104 | #define SCMD_PERR_STOP 0x01 /* if target */ |
| 105 | /* command codes */ |
| 106 | #define SCMD_BUS_REL 0x00 |
| 107 | #define SCMD_SELECT 0x20 |
| 108 | #define SCMD_RST_ATN 0x40 |
| 109 | #define SCMD_SET_ATN 0x60 |
| 110 | #define SCMD_XFR 0x80 |
| 111 | #define SCMD_XFR_PAUSE 0xa0 |
| 112 | #define SCMD_RST_ACK 0xc0 |
| 113 | #define SCMD_SET_ACK 0xe0 |
| 114 | |
| 115 | /* SCSI_TMOD */ |
| 116 | #define TMOD_SYNC 0x80 |
| 117 | |
| 118 | /* SCSI_INTS */ |
| 119 | #define INTS_SEL 0x80 |
| 120 | #define INTS_RESEL 0x40 |
| 121 | #define INTS_DISCON 0x20 |
| 122 | #define INTS_CMD_DONE 0x10 |
| 123 | #define INTS_SRV_REQ 0x08 |
| 124 | #define INTS_TIMEOUT 0x04 |
| 125 | #define INTS_HARD_ERR 0x02 |
| 126 | #define INTS_RST 0x01 |
| 127 | |
| 128 | /* SCSI_PSNS */ |
| 129 | #define PSNS_REQ 0x80 |
| 130 | #define PSNS_ACK 0x40 |
| 131 | #define PSNS_ATN 0x20 |
| 132 | #define PSNS_SEL 0x10 |
| 133 | #define PSNS_BSY 0x08 |
| 134 | |
| 135 | /* PSNS */ |
| 136 | #define REQI 0x80 |
| 137 | #define ACKI 0x40 |
| 138 | #define ATNI 0x20 |
| 139 | #define SELI 0x10 |
| 140 | #define BSYI 0x08 |
| 141 | #define MSGI 0x04 |
| 142 | #define CDI 0x02 |
| 143 | #define IOI 0x01 |
| 144 | |
| 145 | /* Important! The 3 most significant bits of this register, in initiator mode, |
| 146 | * represents the "expected" SCSI bus phase and can be used to trigger phase |
| 147 | * mismatch and phase change interrupts. But more important: If there is a |
| 148 | * phase mismatch the chip will not transfer any data! This is actually a nice |
| 149 | * feature as it gives us a bit more control over what is happening when we are |
| 150 | * bursting data (in) through the FIFOs and the phase suddenly changes from |
| 151 | * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the |
| 152 | * proper phase to be set in this register instead of dumping the bits into the |
| 153 | * FIFOs. |
| 154 | */ |
| 155 | #if 0 |
| 156 | #define REQO 0x80 |
| 157 | #define ACKO 0x40 |
| 158 | #define ATNO 0x20 |
| 159 | #define SELO 0x10 |
| 160 | #define BSYO 0x08 |
| 161 | #endif |
| 162 | /* PCTL */ |
| 163 | #define MSGO 0x04 |
| 164 | #define CDO 0x02 |
| 165 | #define IOO 0x01 |
| 166 | |
| 167 | /* Information transfer phases */ |
| 168 | #define PH_DATAOUT (0) |
| 169 | #define PH_DATAIN (IOI) |
| 170 | #define PH_CMD (CDI) |
| 171 | #define PH_STAT (CDI | IOI) |
| 172 | #define PH_MSGOUT (MSGI | CDI) |
| 173 | #define PH_MSGIN (MSGI | CDI | IOI) |
| 174 | |
| 175 | #define PH_MASK (MSGI | CDI | IOI) |
| 176 | |
| 177 | #define PH_INVALID 0xff |
| 178 | |
| 179 | /* SCSI_SSTS */ |
| 180 | #define SSTS_INITIATOR 0x80 |
| 181 | #define SSTS_TARGET 0x40 |
| 182 | #define SSTS_BUSY 0x20 |
| 183 | #define SSTS_XFR 0x10 |
| 184 | #define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR) |
| 185 | #define SSTS_RST 0x08 |
| 186 | #define SSTS_TCZERO 0x04 |
| 187 | #define SSTS_DREG_FULL 0x02 |
| 188 | #define SSTS_DREG_EMPTY 0x01 |
| 189 | |
| 190 | /* SCSI_SERR */ |
| 191 | #define SERR_SCSI_PAR 0x80 |
| 192 | #define SERR_SPC_PAR 0x40 |
| 193 | #define SERR_TC_PAR 0x08 |
| 194 | #define SERR_PHASE_ERR 0x04 |
| 195 | #define SERR_SHORT_XFR 0x02 |
| 196 | #define SERR_OFFSET 0x01 |
| 197 | |
| 198 | /* SCSI_PCTL */ |
| 199 | #define PCTL_BFINT_ENAB 0x80 |
| 200 | |