| 1 | /* $NetBSD: anreg.h,v 1.15 2007/12/25 18:33:38 perry Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 1997, 1998, 1999 |
| 4 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by Bill Paul. |
| 17 | * 4. Neither the name of the author nor the names of any co-contributors |
| 18 | * may be used to endorse or promote products derived from this software |
| 19 | * without specific prior written permission. |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 31 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | * |
| 33 | * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.3 2000/11/13 23:04:12 wpaul Exp $ |
| 34 | */ |
| 35 | |
| 36 | #ifndef _DEV_IC_ANREG_H |
| 37 | #define _DEV_IC_ANREG_H |
| 38 | |
| 39 | /* |
| 40 | * Hermes register definitions and what little I know about them. |
| 41 | */ |
| 42 | |
| 43 | /* Hermes command/status registers. */ |
| 44 | #define AN_COMMAND 0x00 |
| 45 | #define AN_PARAM0 0x02 |
| 46 | #define AN_PARAM1 0x04 |
| 47 | #define AN_PARAM2 0x06 |
| 48 | #define AN_STATUS 0x08 |
| 49 | #define AN_RESP0 0x0A |
| 50 | #define AN_RESP1 0x0C |
| 51 | #define AN_RESP2 0x0E |
| 52 | #define AN_LINKSTAT 0x10 |
| 53 | |
| 54 | /* Command register */ |
| 55 | #define AN_CMD_BUSY 0x8000 /* busy bit */ |
| 56 | #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */ |
| 57 | #define AN_CMD_CODE_MASK 0x003F |
| 58 | #define AN_CMD_QUAL_MASK 0x7F00 |
| 59 | |
| 60 | /* Command codes */ |
| 61 | #define AN_CMD_NOOP 0x0000 /* no-op */ |
| 62 | #define AN_CMD_ENABLE 0x0001 /* enable */ |
| 63 | #define AN_CMD_DISABLE 0x0002 /* disable */ |
| 64 | #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */ |
| 65 | #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */ |
| 66 | #define AN_CMD_HOST_SLEEP 0x0005 |
| 67 | #define AN_CMD_MAGIC_PKT 0x0006 |
| 68 | #define AN_CMD_READCFG 0x0008 |
| 69 | #define AN_CMD_SET_MODE 0x0009 |
| 70 | #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ |
| 71 | #define AN_CMD_TX 0x000B /* transmit */ |
| 72 | #define AN_CMD_DEALLOC_MEM 0x000C |
| 73 | #define AN_CMD_NOOP2 0x0010 |
| 74 | #define AN_CMD_ACCESS 0x0021 |
| 75 | #define AN_CMD_ALLOC_BUF 0x0028 |
| 76 | #define AN_CMD_PSP_NODES 0x0030 |
| 77 | #define AN_CMD_SET_PHYREG 0x003E |
| 78 | #define AN_CMD_TX_TEST 0x003F |
| 79 | #define AN_CMD_SLEEP 0x0085 |
| 80 | #define AN_CMD_SAVECFG 0x0108 |
| 81 | |
| 82 | /* |
| 83 | * Reclaim qualifier bit, applicable to the |
| 84 | * TX command. |
| 85 | */ |
| 86 | #define AN_RECLAIM 0x0100 /* reclaim NIC memory */ |
| 87 | |
| 88 | /* |
| 89 | * ACCESS command qualifier bits. |
| 90 | */ |
| 91 | #define AN_ACCESS_READ 0x0000 |
| 92 | #define AN_ACCESS_WRITE 0x0100 |
| 93 | |
| 94 | /* |
| 95 | * PROGRAM command qualifier bits. |
| 96 | */ |
| 97 | #define AN_PROGRAM_DISABLE 0x0000 |
| 98 | #define AN_PROGRAM_ENABLE_RAM 0x0100 |
| 99 | #define AN_PROGRAM_ENABLE_NVRAM 0x0200 |
| 100 | #define AN_PROGRAM_NVRAM 0x0300 |
| 101 | |
| 102 | /* Status register values */ |
| 103 | #define AN_STAT_CMD_CODE 0x003F |
| 104 | #define AN_STAT_CMD_RESULT 0x7F00 |
| 105 | |
| 106 | /* Linkstat register */ |
| 107 | #define AN_LINKSTAT_ASSOCIATED 0x0400 |
| 108 | #define AN_LINKSTAT_AUTHFAIL 0x0300 |
| 109 | #define AN_LINKSTAT_ASSOC_FAIL 0x8400 |
| 110 | #define AN_LINKSTAT_DISASSOC 0x8200 |
| 111 | #define AN_LINKSTAT_DEAUTH 0x8100 |
| 112 | #define AN_LINKSTAT_SYNCLOST_TSF 0x8004 |
| 113 | #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003 |
| 114 | #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002 |
| 115 | #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001 |
| 116 | #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000 |
| 117 | |
| 118 | /* memory handle management registers */ |
| 119 | #define AN_RX_FID 0x20 |
| 120 | #define AN_ALLOC_FID 0x22 |
| 121 | #define AN_TX_CMP_FID 0x24 |
| 122 | |
| 123 | /* |
| 124 | * Buffer Access Path (BAP) registers. |
| 125 | * These are I/O channels. I believe you can use each one for |
| 126 | * any desired purpose independently of the other. In general |
| 127 | * though, we use BAP1 for reading and writing LTV records and |
| 128 | * reading received data frames, and BAP0 for writing transmit |
| 129 | * frames. This is a convention though, not a rule. |
| 130 | */ |
| 131 | #define AN_SEL0 0x18 |
| 132 | #define AN_SEL1 0x1A |
| 133 | #define AN_OFF0 0x1C |
| 134 | #define AN_OFF1 0x1E |
| 135 | #define AN_DATA0 0x36 |
| 136 | #define AN_DATA1 0x38 |
| 137 | #define AN_BAP0 AN_DATA0 |
| 138 | #define AN_BAP1 AN_DATA1 |
| 139 | |
| 140 | #define AN_OFF_BUSY 0x8000 |
| 141 | #define AN_OFF_ERR 0x4000 |
| 142 | #define AN_OFF_DONE 0x2000 |
| 143 | #define AN_OFF_DATAOFF 0x0FFF |
| 144 | |
| 145 | /* Event registers */ |
| 146 | #define AN_EVENT_STAT 0x30 /* Event status */ |
| 147 | #define AN_INT_EN 0x32 /* Interrupt enable/disable */ |
| 148 | #define AN_EVENT_ACK 0x34 /* Ack event */ |
| 149 | |
| 150 | /* Events */ |
| 151 | #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */ |
| 152 | #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */ |
| 153 | #define AN_EV_MIC 0x1000 /* Message Integrity Check*/ |
| 154 | #define AN_EV_TX_CPY 0x0400 |
| 155 | #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/ |
| 156 | #define AN_EV_LINKSTAT 0x0080 /* link status available */ |
| 157 | #define AN_EV_CMD 0x0010 /* command completed */ |
| 158 | #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ |
| 159 | #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */ |
| 160 | #define AN_EV_TX 0x0002 /* async xmit completed successfully */ |
| 161 | #define AN_EV_RX 0x0001 /* async rx completed */ |
| 162 | |
| 163 | /* Host software registers */ |
| 164 | #define AN_SW0 0x28 |
| 165 | #define AN_SW1 0x2A |
| 166 | #define AN_SW2 0x2C |
| 167 | #define AN_SW3 0x2E |
| 168 | |
| 169 | #define AN_CNTL 0x14 |
| 170 | |
| 171 | #define AN_CNTL_AUX_ENA 0xC000 |
| 172 | #define AN_CNTL_AUX_ENA_STAT 0xC000 |
| 173 | #define AN_CNTL_AUX_DIS_STAT 0x0000 |
| 174 | #define AN_CNTL_AUX_ENA_CNTL 0x8000 |
| 175 | #define AN_CNTL_AUX_DIS_CNTL 0x4000 |
| 176 | |
| 177 | #define AN_AUX_PAGE 0x3A |
| 178 | #define AN_AUX_OFFSET 0x3C |
| 179 | #define AN_AUX_DATA 0x3E |
| 180 | |
| 181 | /* |
| 182 | * General configuration information. |
| 183 | */ |
| 184 | #define AN_RID_GENCONFIG 0xFF10 |
| 185 | struct an_rid_genconfig { |
| 186 | /* General configuration. */ |
| 187 | u_int16_t an_opmode; /* 0x02 */ |
| 188 | u_int16_t an_rxmode; /* 0x04 */ |
| 189 | u_int16_t an_fragthresh; /* 0x06 */ |
| 190 | u_int16_t an_rtsthresh; /* 0x08 */ |
| 191 | u_int8_t an_macaddr[6]; /* 0x0A */ |
| 192 | u_int8_t an_rates[8]; /* 0x10 */ |
| 193 | u_int16_t an_shortretry_limit; /* 0x18 */ |
| 194 | u_int16_t an_longretry_limit; /* 0x1A */ |
| 195 | u_int16_t an_tx_msdu_lifetime; /* 0x1C */ |
| 196 | u_int16_t an_rx_msdu_lifetime; /* 0x1E */ |
| 197 | u_int16_t an_stationary; /* 0x20 */ |
| 198 | u_int16_t an_ordering; /* 0x22 */ |
| 199 | u_int16_t an_devtype; /* 0x24 */ |
| 200 | u_int16_t an_rsvd0[5]; /* 0x26 */ |
| 201 | /* Scanning associating. */ |
| 202 | u_int16_t an_scanmode; /* 0x30 */ |
| 203 | u_int16_t an_probedelay; /* 0x32 */ |
| 204 | u_int16_t an_probe_energy_timeout;/* 0x34 */ |
| 205 | u_int16_t an_probe_response_timeout;/*0x36 */ |
| 206 | u_int16_t an_beacon_listen_timeout;/*0x38 */ |
| 207 | u_int16_t an_ibss_join_net_timeout;/*0x3A */ |
| 208 | u_int16_t an_auth_timeout; /* 0x3C */ |
| 209 | u_int16_t an_authtype; /* 0x3E */ |
| 210 | u_int16_t an_assoc_timeout; /* 0x40 */ |
| 211 | u_int16_t an_specified_ap_timeout;/* 0x42 */ |
| 212 | u_int16_t an_offline_scan_interval;/*0x44 */ |
| 213 | u_int16_t an_offline_scan_duration;/*0x46 */ |
| 214 | u_int16_t an_link_loss_delay; /* 0x48 */ |
| 215 | u_int16_t an_max_beacon_lost_time;/* 0x4A */ |
| 216 | u_int16_t an_refresh_interval; /* 0x4C */ |
| 217 | u_int16_t an_rsvd1; /* 0x4E */ |
| 218 | /* Power save operation */ |
| 219 | u_int16_t an_psave_mode; /* 0x50 */ |
| 220 | u_int16_t an_sleep_for_dtims; /* 0x52 */ |
| 221 | u_int16_t an_listen_interval; /* 0x54 */ |
| 222 | u_int16_t an_fast_listen_interval;/* 0x56 */ |
| 223 | u_int16_t an_listen_decay; /* 0x58 */ |
| 224 | u_int16_t an_fast_listen_decay; /* 0x5A */ |
| 225 | u_int16_t an_rsvd2[2]; /* 0x5C */ |
| 226 | /* Ad-hoc (or AP) operation. */ |
| 227 | u_int16_t an_beacon_period; /* 0x60 */ |
| 228 | u_int16_t an_atim_duration; /* 0x62 */ |
| 229 | u_int16_t an_rsvd3; /* 0x64 */ |
| 230 | u_int16_t an_ds_channel; /* 0x66 */ |
| 231 | u_int16_t an_rsvd4; /* 0x68 */ |
| 232 | u_int16_t an_dtim_period; /* 0x6A */ |
| 233 | u_int16_t an_rsvd5[2]; /* 0x6C */ |
| 234 | /* Radio operation. */ |
| 235 | u_int16_t an_radiotype; /* 0x70 */ |
| 236 | u_int16_t an_diversity; /* 0x72 */ |
| 237 | u_int16_t an_tx_power; /* 0x74 */ |
| 238 | u_int16_t ; /* 0x76 */ |
| 239 | u_int16_t an_modulation_type; /* 0x78 */ |
| 240 | u_int16_t an_short_preamble; /* 0x7A */ |
| 241 | u_int16_t an_home_product; /* 0x7C */ |
| 242 | u_int16_t an_rsvd6; /* 0x7E */ |
| 243 | /* Aironet extensions. */ |
| 244 | u_int8_t an_nodename[16]; /* 0x80 */ |
| 245 | u_int16_t an_arl_thresh; /* 0x90 */ |
| 246 | u_int16_t an_arl_decay; /* 0x92 */ |
| 247 | u_int16_t an_arl_delay; /* 0x94 */ |
| 248 | u_int8_t an_rsvd7; /* 0x96 */ |
| 249 | u_int8_t an_rsvd8; /* 0x97 */ |
| 250 | u_int8_t an_magic_packet_action; /* 0x98 */ |
| 251 | u_int8_t an_magic_packet_ctl; /* 0x99 */ |
| 252 | u_int16_t an_rsvd9; |
| 253 | u_int16_t an_spare[24]; |
| 254 | } __packed; |
| 255 | |
| 256 | #define AN_OPMODE_IBSS_ADHOC 0x0000 |
| 257 | #define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001 |
| 258 | #define AN_OPMODE_AP 0x0002 |
| 259 | #define AN_OPMODE_AP_REPEATER 0x0003 |
| 260 | #define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100 |
| 261 | #define AN_OPMODE_AIRONET_EXTENSIONS 0x0200 |
| 262 | #define AN_OPMODE_AP_EXTENSIONS 0x0400 |
| 263 | #define AN_OPMODE_ANTENNA_ALIGN 0x0800 |
| 264 | #define AN_OPMODE_ETHER_LLC 0x1000 |
| 265 | #define AN_OPMODE_LEAF_NODE 0x2000 |
| 266 | #define AN_OPMODE_CF_POLLABLE 0x4000 |
| 267 | #define AN_OPMODE_MIC 0x8000 |
| 268 | |
| 269 | #define AN_RXMODE_BC_MC_ADDR 0x0000 |
| 270 | #define AN_RXMODE_BC_ADDR 0x0001 |
| 271 | #define AN_RXMODE_ADDR 0x0002 |
| 272 | #define AN_RXMODE_80211_MONITOR_CURBSS 0x0003 |
| 273 | #define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004 |
| 274 | #define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005 |
| 275 | #define 0x0100 |
| 276 | #define 0x0200 |
| 277 | |
| 278 | #define AN_RATE_1MBPS 0x0002 |
| 279 | #define AN_RATE_2MBPS 0x0004 |
| 280 | #define AN_RATE_5_5MBPS 0x000B |
| 281 | #define AN_RATE_11MBPS 0x0016 |
| 282 | |
| 283 | #define AN_DEVTYPE_PC4500 0x0065 |
| 284 | #define AN_DEVTYPE_PC4800 0x006D |
| 285 | |
| 286 | #define AN_SCANMODE_ACTIVE 0x0000 |
| 287 | #define AN_SCANMODE_PASSIVE 0x0001 |
| 288 | #define AN_SCANMODE_AIRONET_ACTIVE 0x0002 |
| 289 | |
| 290 | #define AN_AUTHTYPE_NONE 0x0000 |
| 291 | #define AN_AUTHTYPE_OPEN 0x0001 |
| 292 | #define AN_AUTHTYPE_SHAREDKEY 0x0002 |
| 293 | #define AN_AUTHTYPE_MASK 0x00ff |
| 294 | #define AN_AUTHTYPE_PRIVACY_IN_USE 0x0100 |
| 295 | #define AN_AUTHTYPE_ALLOW_UNENCRYPTED 0x0200 |
| 296 | #define AN_AUTHTYPE_LEAP 0x1000 |
| 297 | |
| 298 | #define AN_PSAVE_CAM 0x0000 |
| 299 | #define AN_PSAVE_PSP 0x0001 |
| 300 | #define AN_PSAVE_PSP_CAM 0x0002 |
| 301 | |
| 302 | #define AN_RADIOTYPE_80211_FH 0x0001 |
| 303 | #define AN_RADIOTYPE_80211_DS 0x0002 |
| 304 | #define AN_RADIOTYPE_LM2000_DS 0x0004 |
| 305 | |
| 306 | #define AN_DIVERSITY_FACTORY_DEFAULT 0x0000 |
| 307 | #define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001 |
| 308 | #define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002 |
| 309 | #define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003 |
| 310 | |
| 311 | #define AN_TXPOWER_FACTORY_DEFAULT 0x0000 |
| 312 | #define AN_TXPOWER_50MW 50 |
| 313 | #define AN_TXPOWER_100MW 100 |
| 314 | #define AN_TXPOWER_250MW 250 |
| 315 | |
| 316 | /* |
| 317 | * Valid SSID list. You can specify up to three SSIDs denoting |
| 318 | * the service sets that you want to join. The first SSID always |
| 319 | * defaults to "tsunami" which is a handy way to detect the |
| 320 | * card. |
| 321 | */ |
| 322 | #define AN_RID_SSIDLIST 0xFF11 |
| 323 | struct an_rid_ssidlist { |
| 324 | struct an_rid_ssid_entry { |
| 325 | u_int16_t an_ssid_len; |
| 326 | char an_ssid[32]; |
| 327 | } __packed an_entry[3]; /* 25 for fwver.5 */ |
| 328 | } __packed; |
| 329 | |
| 330 | /* |
| 331 | * Valid AP list. |
| 332 | */ |
| 333 | #define AN_RID_APLIST 0xFF12 |
| 334 | struct an_rid_aplist { |
| 335 | u_int8_t an_ap1[8]; |
| 336 | u_int8_t an_ap2[8]; |
| 337 | u_int8_t an_ap3[8]; |
| 338 | u_int8_t an_ap4[8]; |
| 339 | } __packed; |
| 340 | |
| 341 | /* |
| 342 | * Driver name. |
| 343 | */ |
| 344 | #define AN_RID_DRVNAME 0xFF13 |
| 345 | struct an_rid_drvname { |
| 346 | u_int8_t an_drvname[16]; |
| 347 | } __packed; |
| 348 | |
| 349 | /* |
| 350 | * Frame encapsulation. |
| 351 | */ |
| 352 | #define AN_RID_ENCAP 0xFF14 |
| 353 | #define AN_ENCAP_NENTS 8 |
| 354 | struct an_rid_encap { |
| 355 | struct an_rid_encap_entry { |
| 356 | u_int16_t an_ethertype; |
| 357 | u_int16_t an_action; |
| 358 | } __packed an_entry[AN_ENCAP_NENTS]; |
| 359 | } __packed; |
| 360 | |
| 361 | #define AN_ENCAP_ACTION_RX 0x0001 |
| 362 | #define AN_ENCAP_ACTION_TX 0x0002 |
| 363 | |
| 364 | #define AN_RXENCAP_NONE 0x0000 |
| 365 | #define AN_RXENCAP_RFC1024 0x0001 |
| 366 | |
| 367 | #define AN_TXENCAP_RFC1024 0x0000 |
| 368 | #define AN_TXENCAP_80211 0x0002 |
| 369 | |
| 370 | /* |
| 371 | * Actual config, same structure as general config (read only). |
| 372 | */ |
| 373 | #define AN_RID_ACTUALCFG 0xFF20 |
| 374 | |
| 375 | /* |
| 376 | * Card capabilities (read only). |
| 377 | */ |
| 378 | #define AN_RID_CAPABILITIES 0xFF00 |
| 379 | struct an_rid_caps { |
| 380 | u_int8_t an_oui[3]; /* 0x02 */ |
| 381 | u_int8_t an_rsvd0; /* 0x05 */ |
| 382 | u_int16_t an_prodnum; /* 0x06 */ |
| 383 | u_int8_t an_manufname[32]; /* 0x08 */ |
| 384 | u_int8_t an_prodname[16]; /* 0x28 */ |
| 385 | u_int8_t an_prodvers[8]; /* 0x38 */ |
| 386 | u_int8_t an_oemaddr[6]; /* 0x40 */ |
| 387 | u_int8_t an_aironetaddr[6]; /* 0x46 */ |
| 388 | u_int16_t an_radiotype; /* 0x4C */ |
| 389 | u_int16_t an_regdomain; /* 0x4E */ |
| 390 | u_int8_t an_callid[6]; /* 0x50 */ |
| 391 | u_int8_t an_rates[8]; /* 0x56 */ |
| 392 | u_int8_t an_rx_diversity; /* 0x5E */ |
| 393 | u_int8_t an_tx_diversity; /* 0x5F */ |
| 394 | u_int16_t an_tx_powerlevels[8]; /* 0x60 */ |
| 395 | u_int16_t an_hwrev; /* 0x70 */ |
| 396 | u_int16_t an_hwcaps; /* 0x72 */ |
| 397 | u_int16_t an_temprange; /* 0x74 */ |
| 398 | u_int16_t an_fwrev; /* 0x76 */ |
| 399 | u_int16_t an_fwsubrev; /* 0x78 */ |
| 400 | u_int16_t an_ifacerev; /* 0x7A */ |
| 401 | u_int16_t an_softcaps; /* 0x7C */ |
| 402 | u_int16_t an_bootblockrev; /* 0x7E */ |
| 403 | u_int16_t an_req_hw_support; /* 0x80 */ |
| 404 | /* extended capabilities */ |
| 405 | u_int16_t an_ext_softcaps; /* 0x82 */ |
| 406 | u_int16_t an_spare[94]; |
| 407 | } __packed; |
| 408 | |
| 409 | #define AN_REGDOMAIN_USA 0 |
| 410 | #define AN_REGDOMAIN_EUROPE 1 |
| 411 | #define AN_REGDOMAIN_JAPAN 2 |
| 412 | #define AN_REGDOMAIN_SPAIN 3 |
| 413 | #define AN_REGDOMAIN_FRANCE 4 |
| 414 | #define AN_REGDOMAIN_BELGIUM 5 |
| 415 | #define AN_REGDOMAIN_ISRAEL 6 |
| 416 | #define AN_REGDOMAIN_CANADA 7 |
| 417 | #define AN_REGDOMAIN_AUSTRALIA 8 |
| 418 | #define AN_REGDOMAIN_JAPANWIDE 9 |
| 419 | |
| 420 | #define AN_SOFTCAPS_WEP 0x0002 |
| 421 | #define 0x0008 |
| 422 | #define AN_SOFTCAPS_WEP128 0x0100 |
| 423 | |
| 424 | #define AN_EXT_SOFTCAPS_MIC 0x0001 |
| 425 | |
| 426 | /* |
| 427 | * Access point (read only) |
| 428 | */ |
| 429 | #define AN_RID_APINFO 0xFF01 |
| 430 | struct an_rid_apinfo { |
| 431 | u_int16_t an_tim_addr; |
| 432 | u_int16_t an_airo_addr; |
| 433 | } __packed; |
| 434 | |
| 435 | /* |
| 436 | * Radio info (read only). |
| 437 | */ |
| 438 | #define AN_RID_RADIOINFO 0xFF02 |
| 439 | |
| 440 | /* |
| 441 | * Status (read only). Note: the manual claims this RID is 108 bytes |
| 442 | * long (0x6A is the last datum, which is 2 bytes long) however when |
| 443 | * this RID is read from the NIC, it returns a length of 110 or 112. |
| 444 | * To be on the safe side, this structure is padded with 4 extra 16-bit |
| 445 | * words. (There is a misprint in the manual which says the macaddr |
| 446 | * field is 8 bytes long.) |
| 447 | * |
| 448 | * Also, the channel_set and current_channel fields appear to be |
| 449 | * reversed. Either that, or the hop_period field is unused. |
| 450 | */ |
| 451 | #define AN_RID_STATUS 0xFF50 |
| 452 | struct an_rid_status { |
| 453 | u_int8_t an_macaddr[6]; /* 0x02 */ |
| 454 | u_int16_t an_opmode; /* 0x08 */ |
| 455 | u_int16_t an_errcode; /* 0x0A */ |
| 456 | u_int16_t an_cur_signal_strength; /* 0x0C */ |
| 457 | u_int16_t an_ssidlen; /* 0x0E */ |
| 458 | u_int8_t an_ssid[32]; /* 0x10 */ |
| 459 | u_int8_t an_ap_name[16]; /* 0x30 */ |
| 460 | u_int8_t an_cur_bssid[6]; /* 0x40 */ |
| 461 | u_int8_t an_prev_bssid1[6]; /* 0x46 */ |
| 462 | u_int8_t an_prev_bssid2[6]; /* 0x4C */ |
| 463 | u_int8_t an_prev_bssid3[6]; /* 0x52 */ |
| 464 | u_int16_t an_beacon_period; /* 0x58 */ |
| 465 | u_int16_t an_dtim_period; /* 0x5A */ |
| 466 | u_int16_t an_atim_duration; /* 0x5C */ |
| 467 | u_int16_t an_hop_period; /* 0x5E */ |
| 468 | u_int16_t an_cur_channel; /* 0x62 */ |
| 469 | u_int16_t an_channel_set; /* 0x60 */ |
| 470 | u_int16_t an_hops_to_backbone; /* 0x64 */ |
| 471 | u_int16_t an_ap_total_load; /* 0x66 */ |
| 472 | u_int16_t an_our_generated_load; /* 0x68 */ |
| 473 | u_int16_t an_accumulated_arl; /* 0x6A */ |
| 474 | u_int16_t an_cur_signal_quality; /* 0x6C */ |
| 475 | u_int16_t an_current_tx_rate; /* 0x6E */ |
| 476 | u_int16_t an_ap_device; /* 0x70 */ |
| 477 | u_int16_t ; /* 0x72 */ |
| 478 | u_int16_t an_short_pre_in_use; /* 0x74 */ |
| 479 | u_int8_t an_ap_ip_addr[4]; /* 0x76 */ |
| 480 | u_int16_t an_max_noise_prev_sec; /* 0x7A */ |
| 481 | u_int16_t an_avg_noise_prev_min; /* 0x7C */ |
| 482 | u_int16_t an_max_noise_prev_min; /* 0x7E */ |
| 483 | u_int16_t an_spare[11]; |
| 484 | } __packed; |
| 485 | |
| 486 | #define AN_STATUS_OPMODE_CONFIGURED 0x0001 |
| 487 | #define AN_STATUS_OPMODE_MAC_ENABLED 0x0002 |
| 488 | #define AN_STATUS_OPMODE_RX_ENABLED 0x0004 |
| 489 | #define AN_STATUS_OPMODE_IN_SYNC 0x0010 |
| 490 | #define AN_STATUS_OPMODE_ASSOCIATED 0x0020 |
| 491 | #define AN_STATUS_OPMODE_ERROR 0x8000 |
| 492 | |
| 493 | /* |
| 494 | * Statistics |
| 495 | */ |
| 496 | #define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */ |
| 497 | #define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */ |
| 498 | #define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */ |
| 499 | #define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */ |
| 500 | #define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */ |
| 501 | #define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */ |
| 502 | |
| 503 | /* |
| 504 | * Grrr. The manual says the statistics record is 384 bytes in length, |
| 505 | * but the card says the record is 404 bytes. There's some padding left |
| 506 | * at the end of this structure to account for any discrepancies. |
| 507 | */ |
| 508 | struct an_rid_stats { |
| 509 | u_int16_t an_spacer; /* 0x02 */ |
| 510 | u_int32_t an_rx_overruns; /* 0x04 */ |
| 511 | u_int32_t an_rx_plcp_csum_errs; /* 0x08 */ |
| 512 | u_int32_t an_rx_plcp_format_errs; /* 0x0C */ |
| 513 | u_int32_t an_rx_plcp_len_errs; /* 0x10 */ |
| 514 | u_int32_t an_rx_mac_crc_errs; /* 0x14 */ |
| 515 | u_int32_t an_rx_mac_crc_ok; /* 0x18 */ |
| 516 | u_int32_t an_rx_wep_errs; /* 0x1C */ |
| 517 | u_int32_t an_rx_wep_ok; /* 0x20 */ |
| 518 | u_int32_t an_retry_long; /* 0x24 */ |
| 519 | u_int32_t an_retry_short; /* 0x28 */ |
| 520 | u_int32_t an_retry_max; /* 0x2C */ |
| 521 | u_int32_t an_no_ack; /* 0x30 */ |
| 522 | u_int32_t an_no_cts; /* 0x34 */ |
| 523 | u_int32_t an_rx_ack_ok; /* 0x38 */ |
| 524 | u_int32_t an_rx_cts_ok; /* 0x3C */ |
| 525 | u_int32_t an_tx_ack_ok; /* 0x40 */ |
| 526 | u_int32_t an_tx_rts_ok; /* 0x44 */ |
| 527 | u_int32_t an_tx_cts_ok; /* 0x48 */ |
| 528 | u_int32_t an_tx_lmac_mcasts; /* 0x4C */ |
| 529 | u_int32_t an_tx_lmac_bcasts; /* 0x50 */ |
| 530 | u_int32_t an_tx_lmac_ucast_frags; /* 0x54 */ |
| 531 | u_int32_t an_tx_lmac_ucasts; /* 0x58 */ |
| 532 | u_int32_t an_tx_beacons; /* 0x5C */ |
| 533 | u_int32_t an_rx_beacons; /* 0x60 */ |
| 534 | u_int32_t an_tx_single_cols; /* 0x64 */ |
| 535 | u_int32_t an_tx_multi_cols; /* 0x68 */ |
| 536 | u_int32_t an_tx_defers_no; /* 0x6C */ |
| 537 | u_int32_t an_tx_defers_prot; /* 0x70 */ |
| 538 | u_int32_t an_tx_defers_energy; /* 0x74 */ |
| 539 | u_int32_t an_rx_dups; /* 0x78 */ |
| 540 | u_int32_t an_rx_partial; /* 0x7C */ |
| 541 | u_int32_t an_tx_too_old; /* 0x80 */ |
| 542 | u_int32_t an_rx_too_old; /* 0x84 */ |
| 543 | u_int32_t an_lostsync_max_retries;/* 0x88 */ |
| 544 | u_int32_t an_lostsync_missed_beacons;/* 0x8C */ |
| 545 | u_int32_t an_lostsync_arl_exceeded;/*0x90 */ |
| 546 | u_int32_t an_lostsync_deauthed; /* 0x94 */ |
| 547 | u_int32_t an_lostsync_disassociated;/*0x98 */ |
| 548 | u_int32_t an_lostsync_tsf_timing; /* 0x9C */ |
| 549 | u_int32_t an_tx_host_mcasts; /* 0xA0 */ |
| 550 | u_int32_t an_tx_host_bcasts; /* 0xA4 */ |
| 551 | u_int32_t an_tx_host_ucasts; /* 0xA8 */ |
| 552 | u_int32_t an_tx_host_failed; /* 0xAC */ |
| 553 | u_int32_t an_rx_host_mcasts; /* 0xB0 */ |
| 554 | u_int32_t an_rx_host_bcasts; /* 0xB4 */ |
| 555 | u_int32_t an_rx_host_ucasts; /* 0xB8 */ |
| 556 | u_int32_t an_rx_host_discarded; /* 0xBC */ |
| 557 | u_int32_t an_tx_hmac_mcasts; /* 0xC0 */ |
| 558 | u_int32_t an_tx_hmac_bcasts; /* 0xC4 */ |
| 559 | u_int32_t an_tx_hmac_ucasts; /* 0xC8 */ |
| 560 | u_int32_t an_tx_hmac_failed; /* 0xCC */ |
| 561 | u_int32_t an_rx_hmac_mcasts; /* 0xD0 */ |
| 562 | u_int32_t an_rx_hmac_bcasts; /* 0xD4 */ |
| 563 | u_int32_t an_rx_hmac_ucasts; /* 0xD8 */ |
| 564 | u_int32_t an_rx_hmac_discarded; /* 0xDC */ |
| 565 | u_int32_t an_tx_hmac_accepted; /* 0xE0 */ |
| 566 | u_int32_t an_ssid_mismatches; /* 0xE4 */ |
| 567 | u_int32_t an_ap_mismatches; /* 0xE8 */ |
| 568 | u_int32_t an_rates_mismatches; /* 0xEC */ |
| 569 | u_int32_t an_auth_rejects; /* 0xF0 */ |
| 570 | u_int32_t an_auth_timeouts; /* 0xF4 */ |
| 571 | u_int32_t an_assoc_rejects; /* 0xF8 */ |
| 572 | u_int32_t an_assoc_timeouts; /* 0xFC */ |
| 573 | u_int32_t an_reason_outside_table;/* 0x100 */ |
| 574 | u_int32_t an_reason1; /* 0x104 */ |
| 575 | u_int32_t an_reason2; /* 0x108 */ |
| 576 | u_int32_t an_reason3; /* 0x10C */ |
| 577 | u_int32_t an_reason4; /* 0x110 */ |
| 578 | u_int32_t an_reason5; /* 0x114 */ |
| 579 | u_int32_t an_reason6; /* 0x118 */ |
| 580 | u_int32_t an_reason7; /* 0x11C */ |
| 581 | u_int32_t an_reason8; /* 0x120 */ |
| 582 | u_int32_t an_reason9; /* 0x124 */ |
| 583 | u_int32_t an_reason10; /* 0x128 */ |
| 584 | u_int32_t an_reason11; /* 0x12C */ |
| 585 | u_int32_t an_reason12; /* 0x130 */ |
| 586 | u_int32_t an_reason13; /* 0x134 */ |
| 587 | u_int32_t an_reason14; /* 0x138 */ |
| 588 | u_int32_t an_reason15; /* 0x13C */ |
| 589 | u_int32_t an_reason16; /* 0x140 */ |
| 590 | u_int32_t an_reason17; /* 0x144 */ |
| 591 | u_int32_t an_reason18; /* 0x148 */ |
| 592 | u_int32_t an_reason19; /* 0x14C */ |
| 593 | u_int32_t an_rx_mgmt_pkts; /* 0x150 */ |
| 594 | u_int32_t an_tx_mgmt_pkts; /* 0x154 */ |
| 595 | u_int32_t an_rx_refresh_pkts; /* 0x158 */ |
| 596 | u_int32_t an_tx_refresh_pkts; /* 0x15C */ |
| 597 | u_int32_t an_rx_poll_pkts; /* 0x160 */ |
| 598 | u_int32_t an_tx_poll_pkts; /* 0x164 */ |
| 599 | u_int32_t an_host_retries; /* 0x168 */ |
| 600 | u_int32_t an_lostsync_hostreq; /* 0x16C */ |
| 601 | u_int32_t an_host_tx_bytes; /* 0x170 */ |
| 602 | u_int32_t an_host_rx_bytes; /* 0x174 */ |
| 603 | u_int32_t an_uptime_usecs; /* 0x178 */ |
| 604 | u_int32_t an_uptime_secs; /* 0x17C */ |
| 605 | u_int32_t an_lostsync_better_ap; /* 0x180 */ |
| 606 | u_int32_t an_rsvd[10]; |
| 607 | } __packed; |
| 608 | |
| 609 | /* |
| 610 | * Volatile WEP Key |
| 611 | */ |
| 612 | #define AN_RID_WEP_VOLATILE 0xFF15 /* Volatile WEP Key */ |
| 613 | struct an_rid_wepkey { |
| 614 | u_int16_t an_key_index; /* 0x02 */ |
| 615 | u_int8_t an_mac_addr[6]; /* 0x04 */ |
| 616 | u_int16_t an_key_len; /* 0x0A */ |
| 617 | u_int8_t an_key[16]; /* 0x0C */ |
| 618 | } __packed; |
| 619 | |
| 620 | /* |
| 621 | * Persistent WEP Key |
| 622 | */ |
| 623 | #define AN_RID_WEP_PERSISTENT 0xFF16 /* Persistent WEP Key */ |
| 624 | |
| 625 | /* |
| 626 | * LEAP Key |
| 627 | */ |
| 628 | #define AN_RID_LEAP_USER 0xFF23 /* User Name for LEAP */ |
| 629 | #define AN_RID_LEAP_PASS 0xFF24 /* Password for LEAP */ |
| 630 | struct an_rid_leapkey { |
| 631 | u_int16_t an_key_len; /* 0x02 */ |
| 632 | u_int8_t an_key[32]; /* 0x04 */ |
| 633 | } __packed; |
| 634 | |
| 635 | /* |
| 636 | * MIC |
| 637 | */ |
| 638 | #define AN_RID_MIC 0xFF57 /* Message Integrity Check */ |
| 639 | struct an_rid_mic { |
| 640 | u_int16_t an_mic_state; /* 0x02 */ |
| 641 | u_int16_t an_mic_mcast_valid; /* 0x04 */ |
| 642 | u_int8_t an_mic_mcast[16]; /* 0x06 */ |
| 643 | u_int16_t an_mic_ucast_valid; /* 0x16 */ |
| 644 | u_int8_t an_mic_ucast[16]; /* 0x18 */ |
| 645 | } __packed; |
| 646 | |
| 647 | /* |
| 648 | * Receive frame structure. |
| 649 | */ |
| 650 | struct an_rxframe { |
| 651 | u_int32_t an_rx_time; /* 0x00 */ |
| 652 | u_int16_t an_rx_status; /* 0x04 */ |
| 653 | u_int16_t an_rx_payload_len; /* 0x06 */ |
| 654 | u_int8_t an_rsvd0; /* 0x08 */ |
| 655 | u_int8_t an_rx_signal_strength; /* 0x09 */ |
| 656 | u_int8_t an_rx_rate; /* 0x0A */ |
| 657 | u_int8_t an_rx_chan; /* 0x0B */ |
| 658 | u_int8_t an_rx_assoc_cnt; /* 0x0C */ |
| 659 | u_int8_t an_rsvd1[3]; /* 0x0D */ |
| 660 | u_int8_t an_plcp_hdr[4]; /* 0x10 */ |
| 661 | struct ieee80211_frame_addr4 an_whdr; |
| 662 | u_int16_t an_gaplen; /* 0x32 */ |
| 663 | } __packed; |
| 664 | #define AN_RXGAP_MAX 8 |
| 665 | |
| 666 | /* |
| 667 | * Transmit frame structure. |
| 668 | */ |
| 669 | struct an_txframe { |
| 670 | u_int32_t an_tx_sw; /* 0x00 */ |
| 671 | u_int16_t an_tx_status; /* 0x04 */ |
| 672 | u_int16_t an_tx_payload_len; /* 0x06 */ |
| 673 | u_int16_t an_tx_ctl; /* 0x08 */ |
| 674 | u_int16_t an_tx_assoc_id; /* 0x0A */ |
| 675 | u_int16_t an_tx_retry; /* 0x0C */ |
| 676 | u_int8_t an_tx_assoc_cnt; /* 0x0E */ |
| 677 | u_int8_t an_tx_rate; /* 0x0F */ |
| 678 | u_int8_t an_tx_max_long_retries; /* 0x10 */ |
| 679 | u_int8_t an_tx_max_short_retries; /*0x11 */ |
| 680 | u_int8_t an_rsvd0[2]; /* 0x12 */ |
| 681 | struct ieee80211_frame_addr4 an_whdr; |
| 682 | u_int16_t an_gaplen; /* 0x32 */ |
| 683 | } __packed; |
| 684 | |
| 685 | #define AN_TXGAP_802_3 0 |
| 686 | #define AN_TXGAP_802_11 6 |
| 687 | |
| 688 | struct an_802_3_hdr { |
| 689 | u_int16_t an_802_3_status; |
| 690 | u_int16_t an_802_3_payload_len; |
| 691 | u_int8_t an_dst_addr[6]; |
| 692 | u_int8_t an_src_addr[6]; |
| 693 | } __packed; |
| 694 | |
| 695 | #define AN_TXSTAT_EXCESS_RETRY 0x0002 |
| 696 | #define AN_TXSTAT_LIFE_EXCEEDED 0x0004 |
| 697 | #define AN_TXSTAT_AID_FAIL 0x0008 |
| 698 | #define AN_TXSTAT_MAC_DISABLED 0x0010 |
| 699 | #define AN_TXSTAT_ASSOC_LOST 0x0020 |
| 700 | |
| 701 | #define AN_TXCTL_RSVD 0x0001 |
| 702 | #define AN_TXCTL_TXOK_INTR 0x0002 |
| 703 | #define AN_TXCTL_TXERR_INTR 0x0004 |
| 704 | #define 0x0008 |
| 705 | #define AN_TXCTL_PAYLOAD_TYPE 0x0010 |
| 706 | #define AN_TXCTL_NORELEASE 0x0020 |
| 707 | #define AN_TXCTL_NORETRIES 0x0040 |
| 708 | #define AN_TXCTL_CLEAR_AID 0x0080 |
| 709 | #define AN_TXCTL_STRICT_ORDER 0x0100 |
| 710 | #define AN_TXCTL_USE_RTS 0x0200 |
| 711 | |
| 712 | #define 0x0000 |
| 713 | #define 0x0008 |
| 714 | |
| 715 | #define AN_PAYLOADTYPE_ETHER 0x0000 |
| 716 | #define AN_PAYLOADTYPE_LLC 0x0010 |
| 717 | |
| 718 | #define AN_TXCTL_80211 \ |
| 719 | (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \ |
| 720 | AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE) |
| 721 | |
| 722 | #define AN_TXCTL_8023 \ |
| 723 | (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \ |
| 724 | AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE) |
| 725 | |
| 726 | #define AN_STAT_BADCRC 0x0001 |
| 727 | #define AN_STAT_UNDECRYPTABLE 0x0002 |
| 728 | #define AN_STAT_ERRSTAT 0x0003 |
| 729 | #define AN_STAT_MAC_PORT 0x0700 |
| 730 | #define AN_STAT_1042 0x2000 /* RFC1042 encoded */ |
| 731 | #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ |
| 732 | #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ |
| 733 | #define AN_RXSTAT_MSG_TYPE 0xE000 |
| 734 | |
| 735 | #define AN_ENC_TX_802_3 0x00 |
| 736 | #define AN_ENC_TX_802_11 0x11 |
| 737 | #define AN_ENC_TX_E_II 0x0E |
| 738 | |
| 739 | #define AN_ENC_TX_1042 0x00 |
| 740 | #define AN_ENC_TX_TUNNEL 0xF8 |
| 741 | |
| 742 | #define AN_TXCNTL_MACPORT 0x00FF |
| 743 | #define AN_TXCNTL_STRUCTTYPE 0xFF00 |
| 744 | |
| 745 | #endif /* _DEV_IC_ANREG_H */ |
| 746 | |