| 1 | /* |
| 2 | * Copyright 2007-11 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
| 29 | #include "radeon.h" |
| 30 | #include "radeon_asic.h" |
| 31 | #include "atom.h" |
| 32 | #include <linux/backlight.h> |
| 33 | |
| 34 | extern int atom_debug; |
| 35 | |
| 36 | static u8 |
| 37 | radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) |
| 38 | { |
| 39 | u8 backlight_level; |
| 40 | u32 bios_2_scratch; |
| 41 | |
| 42 | if (rdev->family >= CHIP_R600) |
| 43 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
| 44 | else |
| 45 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
| 46 | |
| 47 | backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> |
| 48 | ATOM_S2_CURRENT_BL_LEVEL_SHIFT); |
| 49 | |
| 50 | return backlight_level; |
| 51 | } |
| 52 | |
| 53 | static void |
| 54 | radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, |
| 55 | u8 backlight_level) |
| 56 | { |
| 57 | u32 bios_2_scratch; |
| 58 | |
| 59 | if (rdev->family >= CHIP_R600) |
| 60 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
| 61 | else |
| 62 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
| 63 | |
| 64 | bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; |
| 65 | bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & |
| 66 | ATOM_S2_CURRENT_BL_LEVEL_MASK); |
| 67 | |
| 68 | if (rdev->family >= CHIP_R600) |
| 69 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| 70 | else |
| 71 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| 72 | } |
| 73 | |
| 74 | u8 |
| 75 | atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) |
| 76 | { |
| 77 | struct drm_device *dev = radeon_encoder->base.dev; |
| 78 | struct radeon_device *rdev = dev->dev_private; |
| 79 | |
| 80 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
| 81 | return 0; |
| 82 | |
| 83 | return radeon_atom_get_backlight_level_from_reg(rdev); |
| 84 | } |
| 85 | |
| 86 | void |
| 87 | atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
| 88 | { |
| 89 | struct drm_encoder *encoder = &radeon_encoder->base; |
| 90 | struct drm_device *dev = radeon_encoder->base.dev; |
| 91 | struct radeon_device *rdev = dev->dev_private; |
| 92 | struct radeon_encoder_atom_dig *dig; |
| 93 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
| 94 | int index; |
| 95 | |
| 96 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
| 97 | return; |
| 98 | |
| 99 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
| 100 | radeon_encoder->enc_priv) { |
| 101 | dig = radeon_encoder->enc_priv; |
| 102 | dig->backlight_level = level; |
| 103 | radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); |
| 104 | |
| 105 | switch (radeon_encoder->encoder_id) { |
| 106 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 107 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 108 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
| 109 | if (dig->backlight_level == 0) { |
| 110 | args.ucAction = ATOM_LCD_BLOFF; |
| 111 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 112 | } else { |
| 113 | args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; |
| 114 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 115 | args.ucAction = ATOM_LCD_BLON; |
| 116 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 117 | } |
| 118 | break; |
| 119 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 120 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 121 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 122 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 123 | if (dig->backlight_level == 0) |
| 124 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
| 125 | else { |
| 126 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); |
| 127 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
| 128 | } |
| 129 | break; |
| 130 | default: |
| 131 | break; |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) || IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
| 137 | |
| 138 | static u8 radeon_atom_bl_level(struct backlight_device *bd) |
| 139 | { |
| 140 | u8 level; |
| 141 | |
| 142 | /* Convert brightness to hardware level */ |
| 143 | if (bd->props.brightness < 0) |
| 144 | level = 0; |
| 145 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) |
| 146 | level = RADEON_MAX_BL_LEVEL; |
| 147 | else |
| 148 | level = bd->props.brightness; |
| 149 | |
| 150 | return level; |
| 151 | } |
| 152 | |
| 153 | static int radeon_atom_backlight_update_status(struct backlight_device *bd) |
| 154 | { |
| 155 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
| 156 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
| 157 | |
| 158 | atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); |
| 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) |
| 164 | { |
| 165 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
| 166 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
| 167 | struct drm_device *dev = radeon_encoder->base.dev; |
| 168 | struct radeon_device *rdev = dev->dev_private; |
| 169 | |
| 170 | return radeon_atom_get_backlight_level_from_reg(rdev); |
| 171 | } |
| 172 | |
| 173 | static const struct backlight_ops radeon_atom_backlight_ops = { |
| 174 | .get_brightness = radeon_atom_backlight_get_brightness, |
| 175 | .update_status = radeon_atom_backlight_update_status, |
| 176 | }; |
| 177 | |
| 178 | void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, |
| 179 | struct drm_connector *drm_connector) |
| 180 | { |
| 181 | struct drm_device *dev = radeon_encoder->base.dev; |
| 182 | struct radeon_device *rdev = dev->dev_private; |
| 183 | struct backlight_device *bd; |
| 184 | struct backlight_properties props; |
| 185 | struct radeon_backlight_privdata *pdata; |
| 186 | struct radeon_encoder_atom_dig *dig; |
| 187 | u8 backlight_level; |
| 188 | char bl_name[16]; |
| 189 | |
| 190 | /* Mac laptops with multiple GPUs use the gmux driver for backlight |
| 191 | * so don't register a backlight device |
| 192 | */ |
| 193 | if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
| 194 | (rdev->pdev->device == 0x6741)) |
| 195 | return; |
| 196 | |
| 197 | if (!radeon_encoder->enc_priv) |
| 198 | return; |
| 199 | |
| 200 | if (!rdev->is_atom_bios) |
| 201 | return; |
| 202 | |
| 203 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
| 204 | return; |
| 205 | |
| 206 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); |
| 207 | if (!pdata) { |
| 208 | DRM_ERROR("Memory allocation failed\n" ); |
| 209 | goto error; |
| 210 | } |
| 211 | |
| 212 | memset(&props, 0, sizeof(props)); |
| 213 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
| 214 | props.type = BACKLIGHT_RAW; |
| 215 | snprintf(bl_name, sizeof(bl_name), |
| 216 | "radeon_bl%d" , dev->primary->index); |
| 217 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
| 218 | pdata, &radeon_atom_backlight_ops, &props); |
| 219 | if (IS_ERR(bd)) { |
| 220 | DRM_ERROR("Backlight registration failed\n" ); |
| 221 | goto error; |
| 222 | } |
| 223 | |
| 224 | pdata->encoder = radeon_encoder; |
| 225 | |
| 226 | backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); |
| 227 | |
| 228 | dig = radeon_encoder->enc_priv; |
| 229 | dig->bl_dev = bd; |
| 230 | |
| 231 | bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
| 232 | bd->props.power = FB_BLANK_UNBLANK; |
| 233 | backlight_update_status(bd); |
| 234 | |
| 235 | DRM_INFO("radeon atom DIG backlight initialized\n" ); |
| 236 | |
| 237 | return; |
| 238 | |
| 239 | error: |
| 240 | kfree(pdata); |
| 241 | return; |
| 242 | } |
| 243 | |
| 244 | static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) |
| 245 | { |
| 246 | struct drm_device *dev = radeon_encoder->base.dev; |
| 247 | struct radeon_device *rdev = dev->dev_private; |
| 248 | struct backlight_device *bd = NULL; |
| 249 | struct radeon_encoder_atom_dig *dig; |
| 250 | |
| 251 | if (!radeon_encoder->enc_priv) |
| 252 | return; |
| 253 | |
| 254 | if (!rdev->is_atom_bios) |
| 255 | return; |
| 256 | |
| 257 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) |
| 258 | return; |
| 259 | |
| 260 | dig = radeon_encoder->enc_priv; |
| 261 | bd = dig->bl_dev; |
| 262 | dig->bl_dev = NULL; |
| 263 | |
| 264 | if (bd) { |
| 265 | struct radeon_legacy_backlight_privdata *pdata; |
| 266 | |
| 267 | pdata = bl_get_data(bd); |
| 268 | backlight_device_unregister(bd); |
| 269 | kfree(pdata); |
| 270 | |
| 271 | DRM_INFO("radeon atom LVDS backlight unloaded\n" ); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ |
| 276 | |
| 277 | void radeon_atom_backlight_init(struct radeon_encoder *encoder) |
| 278 | { |
| 279 | } |
| 280 | |
| 281 | static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) |
| 282 | { |
| 283 | } |
| 284 | |
| 285 | #endif |
| 286 | |
| 287 | /* evil but including atombios.h is much worse */ |
| 288 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
| 289 | struct drm_display_mode *mode); |
| 290 | |
| 291 | |
| 292 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
| 293 | { |
| 294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 295 | switch (radeon_encoder->encoder_id) { |
| 296 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 297 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 298 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 299 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 300 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 301 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 302 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 303 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 304 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 305 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 306 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 307 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 308 | return true; |
| 309 | default: |
| 310 | return false; |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
| 315 | const struct drm_display_mode *mode, |
| 316 | struct drm_display_mode *adjusted_mode) |
| 317 | { |
| 318 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 319 | struct drm_device *dev = encoder->dev; |
| 320 | struct radeon_device *rdev = dev->dev_private; |
| 321 | |
| 322 | /* set the active encoder to connector routing */ |
| 323 | radeon_encoder_set_active_device(encoder); |
| 324 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 325 | |
| 326 | /* hw bug */ |
| 327 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 328 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
| 329 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
| 330 | |
| 331 | /* get the native mode for LVDS */ |
| 332 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
| 333 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
| 334 | |
| 335 | /* get the native mode for TV */ |
| 336 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
| 337 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 338 | if (tv_dac) { |
| 339 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 340 | tv_dac->tv_std == TV_STD_NTSC_J || |
| 341 | tv_dac->tv_std == TV_STD_PAL_M) |
| 342 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
| 343 | else |
| 344 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | if (ASIC_IS_DCE3(rdev) && |
| 349 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
| 350 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { |
| 351 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 352 | radeon_dp_set_link_config(connector, adjusted_mode); |
| 353 | } |
| 354 | |
| 355 | return true; |
| 356 | } |
| 357 | |
| 358 | static void |
| 359 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
| 360 | { |
| 361 | struct drm_device *dev = encoder->dev; |
| 362 | struct radeon_device *rdev = dev->dev_private; |
| 363 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 364 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
| 365 | int index = 0; |
| 366 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
| 367 | |
| 368 | memset(&args, 0, sizeof(args)); |
| 369 | |
| 370 | switch (radeon_encoder->encoder_id) { |
| 371 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 372 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 373 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
| 374 | break; |
| 375 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 376 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 377 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
| 378 | break; |
| 379 | } |
| 380 | |
| 381 | args.ucAction = action; |
| 382 | |
| 383 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
| 384 | args.ucDacStandard = ATOM_DAC1_PS2; |
| 385 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 386 | args.ucDacStandard = ATOM_DAC1_CV; |
| 387 | else { |
| 388 | switch (dac_info->tv_std) { |
| 389 | case TV_STD_PAL: |
| 390 | case TV_STD_PAL_M: |
| 391 | case TV_STD_SCART_PAL: |
| 392 | case TV_STD_SECAM: |
| 393 | case TV_STD_PAL_CN: |
| 394 | args.ucDacStandard = ATOM_DAC1_PAL; |
| 395 | break; |
| 396 | case TV_STD_NTSC: |
| 397 | case TV_STD_NTSC_J: |
| 398 | case TV_STD_PAL_60: |
| 399 | default: |
| 400 | args.ucDacStandard = ATOM_DAC1_NTSC; |
| 401 | break; |
| 402 | } |
| 403 | } |
| 404 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 405 | |
| 406 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 407 | |
| 408 | } |
| 409 | |
| 410 | static void |
| 411 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
| 412 | { |
| 413 | struct drm_device *dev = encoder->dev; |
| 414 | struct radeon_device *rdev = dev->dev_private; |
| 415 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 416 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
| 417 | int index = 0; |
| 418 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
| 419 | |
| 420 | memset(&args, 0, sizeof(args)); |
| 421 | |
| 422 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
| 423 | |
| 424 | args.sTVEncoder.ucAction = action; |
| 425 | |
| 426 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 427 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
| 428 | else { |
| 429 | switch (dac_info->tv_std) { |
| 430 | case TV_STD_NTSC: |
| 431 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
| 432 | break; |
| 433 | case TV_STD_PAL: |
| 434 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
| 435 | break; |
| 436 | case TV_STD_PAL_M: |
| 437 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
| 438 | break; |
| 439 | case TV_STD_PAL_60: |
| 440 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
| 441 | break; |
| 442 | case TV_STD_NTSC_J: |
| 443 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
| 444 | break; |
| 445 | case TV_STD_SCART_PAL: |
| 446 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
| 447 | break; |
| 448 | case TV_STD_SECAM: |
| 449 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
| 450 | break; |
| 451 | case TV_STD_PAL_CN: |
| 452 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
| 453 | break; |
| 454 | default: |
| 455 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
| 456 | break; |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 461 | |
| 462 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 463 | |
| 464 | } |
| 465 | |
| 466 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
| 467 | { |
| 468 | int bpc = 8; |
| 469 | |
| 470 | if (encoder->crtc) { |
| 471 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 472 | bpc = radeon_crtc->bpc; |
| 473 | } |
| 474 | |
| 475 | switch (bpc) { |
| 476 | case 0: |
| 477 | return PANEL_BPC_UNDEFINE; |
| 478 | case 6: |
| 479 | return PANEL_6BIT_PER_COLOR; |
| 480 | case 8: |
| 481 | default: |
| 482 | return PANEL_8BIT_PER_COLOR; |
| 483 | case 10: |
| 484 | return PANEL_10BIT_PER_COLOR; |
| 485 | case 12: |
| 486 | return PANEL_12BIT_PER_COLOR; |
| 487 | case 16: |
| 488 | return PANEL_16BIT_PER_COLOR; |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | union dvo_encoder_control { |
| 493 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
| 494 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
| 495 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
| 496 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
| 497 | }; |
| 498 | |
| 499 | void |
| 500 | atombios_dvo_setup(struct drm_encoder *encoder, int action) |
| 501 | { |
| 502 | struct drm_device *dev = encoder->dev; |
| 503 | struct radeon_device *rdev = dev->dev_private; |
| 504 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 505 | union dvo_encoder_control args; |
| 506 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
| 507 | uint8_t frev, crev; |
| 508 | |
| 509 | memset(&args, 0, sizeof(args)); |
| 510 | |
| 511 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 512 | return; |
| 513 | |
| 514 | /* some R4xx chips have the wrong frev */ |
| 515 | if (rdev->family <= CHIP_RV410) |
| 516 | frev = 1; |
| 517 | |
| 518 | switch (frev) { |
| 519 | case 1: |
| 520 | switch (crev) { |
| 521 | case 1: |
| 522 | /* R4xx, R5xx */ |
| 523 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; |
| 524 | |
| 525 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 526 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 527 | |
| 528 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; |
| 529 | break; |
| 530 | case 2: |
| 531 | /* RS600/690/740 */ |
| 532 | args.dvo.sDVOEncoder.ucAction = action; |
| 533 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 534 | /* DFP1, CRT1, TV1 depending on the type of port */ |
| 535 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; |
| 536 | |
| 537 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 538 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; |
| 539 | break; |
| 540 | case 3: |
| 541 | /* R6xx */ |
| 542 | args.dvo_v3.ucAction = action; |
| 543 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 544 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
| 545 | break; |
| 546 | case 4: |
| 547 | /* DCE8 */ |
| 548 | args.dvo_v4.ucAction = action; |
| 549 | args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 550 | args.dvo_v4.ucDVOConfig = 0; /* XXX */ |
| 551 | args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
| 552 | break; |
| 553 | default: |
| 554 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 555 | break; |
| 556 | } |
| 557 | break; |
| 558 | default: |
| 559 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 560 | break; |
| 561 | } |
| 562 | |
| 563 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 564 | } |
| 565 | |
| 566 | union lvds_encoder_control { |
| 567 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
| 568 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
| 569 | }; |
| 570 | |
| 571 | void |
| 572 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
| 573 | { |
| 574 | struct drm_device *dev = encoder->dev; |
| 575 | struct radeon_device *rdev = dev->dev_private; |
| 576 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 577 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 578 | union lvds_encoder_control args; |
| 579 | int index = 0; |
| 580 | int hdmi_detected = 0; |
| 581 | uint8_t frev, crev; |
| 582 | |
| 583 | if (!dig) |
| 584 | return; |
| 585 | |
| 586 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
| 587 | hdmi_detected = 1; |
| 588 | |
| 589 | memset(&args, 0, sizeof(args)); |
| 590 | |
| 591 | switch (radeon_encoder->encoder_id) { |
| 592 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 593 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
| 594 | break; |
| 595 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 596 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 597 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
| 598 | break; |
| 599 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 600 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 601 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
| 602 | else |
| 603 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
| 604 | break; |
| 605 | } |
| 606 | |
| 607 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 608 | return; |
| 609 | |
| 610 | switch (frev) { |
| 611 | case 1: |
| 612 | case 2: |
| 613 | switch (crev) { |
| 614 | case 1: |
| 615 | args.v1.ucMisc = 0; |
| 616 | args.v1.ucAction = action; |
| 617 | if (hdmi_detected) |
| 618 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 619 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 620 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 621 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
| 622 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 623 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
| 624 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
| 625 | } else { |
| 626 | if (dig->linkb) |
| 627 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 628 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 629 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 630 | /*if (pScrn->rgbBits == 8) */ |
| 631 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
| 632 | } |
| 633 | break; |
| 634 | case 2: |
| 635 | case 3: |
| 636 | args.v2.ucMisc = 0; |
| 637 | args.v2.ucAction = action; |
| 638 | if (crev == 3) { |
| 639 | if (dig->coherent_mode) |
| 640 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
| 641 | } |
| 642 | if (hdmi_detected) |
| 643 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 644 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 645 | args.v2.ucTruncate = 0; |
| 646 | args.v2.ucSpatial = 0; |
| 647 | args.v2.ucTemporal = 0; |
| 648 | args.v2.ucFRC = 0; |
| 649 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 650 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
| 651 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 652 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
| 653 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
| 654 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
| 655 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
| 656 | } |
| 657 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
| 658 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
| 659 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
| 660 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
| 661 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
| 662 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
| 663 | } |
| 664 | } else { |
| 665 | if (dig->linkb) |
| 666 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 667 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 668 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 669 | } |
| 670 | break; |
| 671 | default: |
| 672 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 673 | break; |
| 674 | } |
| 675 | break; |
| 676 | default: |
| 677 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 678 | break; |
| 679 | } |
| 680 | |
| 681 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 682 | } |
| 683 | |
| 684 | int |
| 685 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
| 686 | { |
| 687 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 688 | struct drm_connector *connector; |
| 689 | struct radeon_connector *radeon_connector; |
| 690 | struct radeon_connector_atom_dig *dig_connector; |
| 691 | |
| 692 | /* dp bridges are always DP */ |
| 693 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) |
| 694 | return ATOM_ENCODER_MODE_DP; |
| 695 | |
| 696 | /* DVO is always DVO */ |
| 697 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || |
| 698 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) |
| 699 | return ATOM_ENCODER_MODE_DVO; |
| 700 | |
| 701 | connector = radeon_get_connector_for_encoder(encoder); |
| 702 | /* if we don't have an active device yet, just use one of |
| 703 | * the connectors tied to the encoder. |
| 704 | */ |
| 705 | if (!connector) |
| 706 | connector = radeon_get_connector_for_encoder_init(encoder); |
| 707 | radeon_connector = to_radeon_connector(connector); |
| 708 | |
| 709 | switch (connector->connector_type) { |
| 710 | case DRM_MODE_CONNECTOR_DVII: |
| 711 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
| 712 | if (radeon_audio != 0) { |
| 713 | if (radeon_connector->use_digital && |
| 714 | (radeon_connector->audio == RADEON_AUDIO_ENABLE)) |
| 715 | return ATOM_ENCODER_MODE_HDMI; |
| 716 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
| 717 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
| 718 | return ATOM_ENCODER_MODE_HDMI; |
| 719 | else if (radeon_connector->use_digital) |
| 720 | return ATOM_ENCODER_MODE_DVI; |
| 721 | else |
| 722 | return ATOM_ENCODER_MODE_CRT; |
| 723 | } else if (radeon_connector->use_digital) { |
| 724 | return ATOM_ENCODER_MODE_DVI; |
| 725 | } else { |
| 726 | return ATOM_ENCODER_MODE_CRT; |
| 727 | } |
| 728 | break; |
| 729 | case DRM_MODE_CONNECTOR_DVID: |
| 730 | case DRM_MODE_CONNECTOR_HDMIA: |
| 731 | default: |
| 732 | if (radeon_audio != 0) { |
| 733 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
| 734 | return ATOM_ENCODER_MODE_HDMI; |
| 735 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
| 736 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
| 737 | return ATOM_ENCODER_MODE_HDMI; |
| 738 | else |
| 739 | return ATOM_ENCODER_MODE_DVI; |
| 740 | } else { |
| 741 | return ATOM_ENCODER_MODE_DVI; |
| 742 | } |
| 743 | break; |
| 744 | case DRM_MODE_CONNECTOR_LVDS: |
| 745 | return ATOM_ENCODER_MODE_LVDS; |
| 746 | break; |
| 747 | case DRM_MODE_CONNECTOR_DisplayPort: |
| 748 | dig_connector = radeon_connector->con_priv; |
| 749 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
| 750 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
| 751 | return ATOM_ENCODER_MODE_DP; |
| 752 | } else if (radeon_audio != 0) { |
| 753 | if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
| 754 | return ATOM_ENCODER_MODE_HDMI; |
| 755 | else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
| 756 | (radeon_connector->audio == RADEON_AUDIO_AUTO)) |
| 757 | return ATOM_ENCODER_MODE_HDMI; |
| 758 | else |
| 759 | return ATOM_ENCODER_MODE_DVI; |
| 760 | } else { |
| 761 | return ATOM_ENCODER_MODE_DVI; |
| 762 | } |
| 763 | break; |
| 764 | case DRM_MODE_CONNECTOR_eDP: |
| 765 | return ATOM_ENCODER_MODE_DP; |
| 766 | case DRM_MODE_CONNECTOR_DVIA: |
| 767 | case DRM_MODE_CONNECTOR_VGA: |
| 768 | return ATOM_ENCODER_MODE_CRT; |
| 769 | break; |
| 770 | case DRM_MODE_CONNECTOR_Composite: |
| 771 | case DRM_MODE_CONNECTOR_SVIDEO: |
| 772 | case DRM_MODE_CONNECTOR_9PinDIN: |
| 773 | /* fix me */ |
| 774 | return ATOM_ENCODER_MODE_TV; |
| 775 | /*return ATOM_ENCODER_MODE_CV;*/ |
| 776 | break; |
| 777 | } |
| 778 | } |
| 779 | |
| 780 | /* |
| 781 | * DIG Encoder/Transmitter Setup |
| 782 | * |
| 783 | * DCE 3.0/3.1 |
| 784 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. |
| 785 | * Supports up to 3 digital outputs |
| 786 | * - 2 DIG encoder blocks. |
| 787 | * DIG1 can drive UNIPHY link A or link B |
| 788 | * DIG2 can drive UNIPHY link B or LVTMA |
| 789 | * |
| 790 | * DCE 3.2 |
| 791 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). |
| 792 | * Supports up to 5 digital outputs |
| 793 | * - 2 DIG encoder blocks. |
| 794 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
| 795 | * |
| 796 | * DCE 4.0/5.0/6.0 |
| 797 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
| 798 | * Supports up to 6 digital outputs |
| 799 | * - 6 DIG encoder blocks. |
| 800 | * - DIG to PHY mapping is hardcoded |
| 801 | * DIG1 drives UNIPHY0 link A, A+B |
| 802 | * DIG2 drives UNIPHY0 link B |
| 803 | * DIG3 drives UNIPHY1 link A, A+B |
| 804 | * DIG4 drives UNIPHY1 link B |
| 805 | * DIG5 drives UNIPHY2 link A, A+B |
| 806 | * DIG6 drives UNIPHY2 link B |
| 807 | * |
| 808 | * DCE 4.1 |
| 809 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
| 810 | * Supports up to 6 digital outputs |
| 811 | * - 2 DIG encoder blocks. |
| 812 | * llano |
| 813 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
| 814 | * ontario |
| 815 | * DIG1 drives UNIPHY0/1/2 link A |
| 816 | * DIG2 drives UNIPHY0/1/2 link B |
| 817 | * |
| 818 | * Routing |
| 819 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) |
| 820 | * Examples: |
| 821 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI |
| 822 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP |
| 823 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS |
| 824 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI |
| 825 | */ |
| 826 | |
| 827 | union dig_encoder_control { |
| 828 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
| 829 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
| 830 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
| 831 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
| 832 | }; |
| 833 | |
| 834 | void |
| 835 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) |
| 836 | { |
| 837 | struct drm_device *dev = encoder->dev; |
| 838 | struct radeon_device *rdev = dev->dev_private; |
| 839 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 840 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 841 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 842 | union dig_encoder_control args; |
| 843 | int index = 0; |
| 844 | uint8_t frev, crev; |
| 845 | int dp_clock = 0; |
| 846 | int dp_lane_count = 0; |
| 847 | int hpd_id = RADEON_HPD_NONE; |
| 848 | |
| 849 | if (connector) { |
| 850 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 851 | struct radeon_connector_atom_dig *dig_connector = |
| 852 | radeon_connector->con_priv; |
| 853 | |
| 854 | dp_clock = dig_connector->dp_clock; |
| 855 | dp_lane_count = dig_connector->dp_lane_count; |
| 856 | hpd_id = radeon_connector->hpd.hpd; |
| 857 | } |
| 858 | |
| 859 | /* no dig encoder assigned */ |
| 860 | if (dig->dig_encoder == -1) |
| 861 | return; |
| 862 | |
| 863 | memset(&args, 0, sizeof(args)); |
| 864 | |
| 865 | if (ASIC_IS_DCE4(rdev)) |
| 866 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); |
| 867 | else { |
| 868 | if (dig->dig_encoder) |
| 869 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
| 870 | else |
| 871 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
| 872 | } |
| 873 | |
| 874 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 875 | return; |
| 876 | |
| 877 | switch (frev) { |
| 878 | case 1: |
| 879 | switch (crev) { |
| 880 | case 1: |
| 881 | args.v1.ucAction = action; |
| 882 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 883 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
| 884 | args.v3.ucPanelMode = panel_mode; |
| 885 | else |
| 886 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 887 | |
| 888 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) |
| 889 | args.v1.ucLaneNum = dp_lane_count; |
| 890 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 891 | args.v1.ucLaneNum = 8; |
| 892 | else |
| 893 | args.v1.ucLaneNum = 4; |
| 894 | |
| 895 | if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) |
| 896 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
| 897 | switch (radeon_encoder->encoder_id) { |
| 898 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 899 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
| 900 | break; |
| 901 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 902 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 903 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
| 904 | break; |
| 905 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 906 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
| 907 | break; |
| 908 | } |
| 909 | if (dig->linkb) |
| 910 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
| 911 | else |
| 912 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
| 913 | break; |
| 914 | case 2: |
| 915 | case 3: |
| 916 | args.v3.ucAction = action; |
| 917 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 918 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
| 919 | args.v3.ucPanelMode = panel_mode; |
| 920 | else |
| 921 | args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 922 | |
| 923 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) |
| 924 | args.v3.ucLaneNum = dp_lane_count; |
| 925 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 926 | args.v3.ucLaneNum = 8; |
| 927 | else |
| 928 | args.v3.ucLaneNum = 4; |
| 929 | |
| 930 | if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) |
| 931 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
| 932 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
| 933 | args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); |
| 934 | break; |
| 935 | case 4: |
| 936 | args.v4.ucAction = action; |
| 937 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 938 | if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) |
| 939 | args.v4.ucPanelMode = panel_mode; |
| 940 | else |
| 941 | args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 942 | |
| 943 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) |
| 944 | args.v4.ucLaneNum = dp_lane_count; |
| 945 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 946 | args.v4.ucLaneNum = 8; |
| 947 | else |
| 948 | args.v4.ucLaneNum = 4; |
| 949 | |
| 950 | if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
| 951 | if (dp_clock == 540000) |
| 952 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
| 953 | else if (dp_clock == 324000) |
| 954 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; |
| 955 | else if (dp_clock == 270000) |
| 956 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
| 957 | else |
| 958 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; |
| 959 | } |
| 960 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
| 961 | args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
| 962 | if (hpd_id == RADEON_HPD_NONE) |
| 963 | args.v4.ucHPD_ID = 0; |
| 964 | else |
| 965 | args.v4.ucHPD_ID = hpd_id + 1; |
| 966 | break; |
| 967 | default: |
| 968 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 969 | break; |
| 970 | } |
| 971 | break; |
| 972 | default: |
| 973 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 974 | break; |
| 975 | } |
| 976 | |
| 977 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 978 | |
| 979 | } |
| 980 | |
| 981 | union dig_transmitter_control { |
| 982 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
| 983 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
| 984 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
| 985 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
| 986 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; |
| 987 | }; |
| 988 | |
| 989 | void |
| 990 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
| 991 | { |
| 992 | struct drm_device *dev = encoder->dev; |
| 993 | struct radeon_device *rdev = dev->dev_private; |
| 994 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 995 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 996 | struct drm_connector *connector; |
| 997 | union dig_transmitter_control args; |
| 998 | int index = 0; |
| 999 | uint8_t frev, crev; |
| 1000 | bool is_dp = false; |
| 1001 | int pll_id = 0; |
| 1002 | int dp_clock = 0; |
| 1003 | int dp_lane_count = 0; |
| 1004 | int connector_object_id = 0; |
| 1005 | int igp_lane_info = 0; |
| 1006 | int dig_encoder = dig->dig_encoder; |
| 1007 | int hpd_id = RADEON_HPD_NONE; |
| 1008 | |
| 1009 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 1010 | connector = radeon_get_connector_for_encoder_init(encoder); |
| 1011 | /* just needed to avoid bailing in the encoder check. the encoder |
| 1012 | * isn't used for init |
| 1013 | */ |
| 1014 | dig_encoder = 0; |
| 1015 | } else |
| 1016 | connector = radeon_get_connector_for_encoder(encoder); |
| 1017 | |
| 1018 | if (connector) { |
| 1019 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 1020 | struct radeon_connector_atom_dig *dig_connector = |
| 1021 | radeon_connector->con_priv; |
| 1022 | |
| 1023 | hpd_id = radeon_connector->hpd.hpd; |
| 1024 | dp_clock = dig_connector->dp_clock; |
| 1025 | dp_lane_count = dig_connector->dp_lane_count; |
| 1026 | connector_object_id = |
| 1027 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| 1028 | igp_lane_info = dig_connector->igp_lane_info; |
| 1029 | } |
| 1030 | |
| 1031 | if (encoder->crtc) { |
| 1032 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1033 | pll_id = radeon_crtc->pll_id; |
| 1034 | } |
| 1035 | |
| 1036 | /* no dig encoder assigned */ |
| 1037 | if (dig_encoder == -1) |
| 1038 | return; |
| 1039 | |
| 1040 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) |
| 1041 | is_dp = true; |
| 1042 | |
| 1043 | memset(&args, 0, sizeof(args)); |
| 1044 | |
| 1045 | switch (radeon_encoder->encoder_id) { |
| 1046 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1047 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
| 1048 | break; |
| 1049 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1050 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1051 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1052 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 1053 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
| 1054 | break; |
| 1055 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1056 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
| 1057 | break; |
| 1058 | } |
| 1059 | |
| 1060 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 1061 | return; |
| 1062 | |
| 1063 | switch (frev) { |
| 1064 | case 1: |
| 1065 | switch (crev) { |
| 1066 | case 1: |
| 1067 | args.v1.ucAction = action; |
| 1068 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 1069 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
| 1070 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
| 1071 | args.v1.asMode.ucLaneSel = lane_num; |
| 1072 | args.v1.asMode.ucLaneSet = lane_set; |
| 1073 | } else { |
| 1074 | if (is_dp) |
| 1075 | args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 1076 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1077 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 1078 | else |
| 1079 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1080 | } |
| 1081 | |
| 1082 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
| 1083 | |
| 1084 | if (dig_encoder) |
| 1085 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
| 1086 | else |
| 1087 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
| 1088 | |
| 1089 | if ((rdev->flags & RADEON_IS_IGP) && |
| 1090 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
| 1091 | if (is_dp || |
| 1092 | !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { |
| 1093 | if (igp_lane_info & 0x1) |
| 1094 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 1095 | else if (igp_lane_info & 0x2) |
| 1096 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
| 1097 | else if (igp_lane_info & 0x4) |
| 1098 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
| 1099 | else if (igp_lane_info & 0x8) |
| 1100 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
| 1101 | } else { |
| 1102 | if (igp_lane_info & 0x3) |
| 1103 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
| 1104 | else if (igp_lane_info & 0xc) |
| 1105 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
| 1106 | } |
| 1107 | } |
| 1108 | |
| 1109 | if (dig->linkb) |
| 1110 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
| 1111 | else |
| 1112 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
| 1113 | |
| 1114 | if (is_dp) |
| 1115 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
| 1116 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 1117 | if (dig->coherent_mode) |
| 1118 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
| 1119 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1120 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; |
| 1121 | } |
| 1122 | break; |
| 1123 | case 2: |
| 1124 | args.v2.ucAction = action; |
| 1125 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 1126 | args.v2.usInitInfo = cpu_to_le16(connector_object_id); |
| 1127 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
| 1128 | args.v2.asMode.ucLaneSel = lane_num; |
| 1129 | args.v2.asMode.ucLaneSet = lane_set; |
| 1130 | } else { |
| 1131 | if (is_dp) |
| 1132 | args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 1133 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1134 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 1135 | else |
| 1136 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1137 | } |
| 1138 | |
| 1139 | args.v2.acConfig.ucEncoderSel = dig_encoder; |
| 1140 | if (dig->linkb) |
| 1141 | args.v2.acConfig.ucLinkSel = 1; |
| 1142 | |
| 1143 | switch (radeon_encoder->encoder_id) { |
| 1144 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1145 | args.v2.acConfig.ucTransmitterSel = 0; |
| 1146 | break; |
| 1147 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1148 | args.v2.acConfig.ucTransmitterSel = 1; |
| 1149 | break; |
| 1150 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1151 | args.v2.acConfig.ucTransmitterSel = 2; |
| 1152 | break; |
| 1153 | } |
| 1154 | |
| 1155 | if (is_dp) { |
| 1156 | args.v2.acConfig.fCoherentMode = 1; |
| 1157 | args.v2.acConfig.fDPConnector = 1; |
| 1158 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 1159 | if (dig->coherent_mode) |
| 1160 | args.v2.acConfig.fCoherentMode = 1; |
| 1161 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1162 | args.v2.acConfig.fDualLinkConnector = 1; |
| 1163 | } |
| 1164 | break; |
| 1165 | case 3: |
| 1166 | args.v3.ucAction = action; |
| 1167 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 1168 | args.v3.usInitInfo = cpu_to_le16(connector_object_id); |
| 1169 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
| 1170 | args.v3.asMode.ucLaneSel = lane_num; |
| 1171 | args.v3.asMode.ucLaneSet = lane_set; |
| 1172 | } else { |
| 1173 | if (is_dp) |
| 1174 | args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 1175 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1176 | args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 1177 | else |
| 1178 | args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1179 | } |
| 1180 | |
| 1181 | if (is_dp) |
| 1182 | args.v3.ucLaneNum = dp_lane_count; |
| 1183 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1184 | args.v3.ucLaneNum = 8; |
| 1185 | else |
| 1186 | args.v3.ucLaneNum = 4; |
| 1187 | |
| 1188 | if (dig->linkb) |
| 1189 | args.v3.acConfig.ucLinkSel = 1; |
| 1190 | if (dig_encoder & 1) |
| 1191 | args.v3.acConfig.ucEncoderSel = 1; |
| 1192 | |
| 1193 | /* Select the PLL for the PHY |
| 1194 | * DP PHY should be clocked from external src if there is |
| 1195 | * one. |
| 1196 | */ |
| 1197 | /* On DCE4, if there is an external clock, it generates the DP ref clock */ |
| 1198 | if (is_dp && rdev->clock.dp_extclk) |
| 1199 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ |
| 1200 | else |
| 1201 | args.v3.acConfig.ucRefClkSource = pll_id; |
| 1202 | |
| 1203 | switch (radeon_encoder->encoder_id) { |
| 1204 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1205 | args.v3.acConfig.ucTransmitterSel = 0; |
| 1206 | break; |
| 1207 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1208 | args.v3.acConfig.ucTransmitterSel = 1; |
| 1209 | break; |
| 1210 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1211 | args.v3.acConfig.ucTransmitterSel = 2; |
| 1212 | break; |
| 1213 | } |
| 1214 | |
| 1215 | if (is_dp) |
| 1216 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
| 1217 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 1218 | if (dig->coherent_mode) |
| 1219 | args.v3.acConfig.fCoherentMode = 1; |
| 1220 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1221 | args.v3.acConfig.fDualLinkConnector = 1; |
| 1222 | } |
| 1223 | break; |
| 1224 | case 4: |
| 1225 | args.v4.ucAction = action; |
| 1226 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 1227 | args.v4.usInitInfo = cpu_to_le16(connector_object_id); |
| 1228 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
| 1229 | args.v4.asMode.ucLaneSel = lane_num; |
| 1230 | args.v4.asMode.ucLaneSet = lane_set; |
| 1231 | } else { |
| 1232 | if (is_dp) |
| 1233 | args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 1234 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1235 | args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 1236 | else |
| 1237 | args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1238 | } |
| 1239 | |
| 1240 | if (is_dp) |
| 1241 | args.v4.ucLaneNum = dp_lane_count; |
| 1242 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1243 | args.v4.ucLaneNum = 8; |
| 1244 | else |
| 1245 | args.v4.ucLaneNum = 4; |
| 1246 | |
| 1247 | if (dig->linkb) |
| 1248 | args.v4.acConfig.ucLinkSel = 1; |
| 1249 | if (dig_encoder & 1) |
| 1250 | args.v4.acConfig.ucEncoderSel = 1; |
| 1251 | |
| 1252 | /* Select the PLL for the PHY |
| 1253 | * DP PHY should be clocked from external src if there is |
| 1254 | * one. |
| 1255 | */ |
| 1256 | /* On DCE5 DCPLL usually generates the DP ref clock */ |
| 1257 | if (is_dp) { |
| 1258 | if (rdev->clock.dp_extclk) |
| 1259 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; |
| 1260 | else |
| 1261 | args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; |
| 1262 | } else |
| 1263 | args.v4.acConfig.ucRefClkSource = pll_id; |
| 1264 | |
| 1265 | switch (radeon_encoder->encoder_id) { |
| 1266 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1267 | args.v4.acConfig.ucTransmitterSel = 0; |
| 1268 | break; |
| 1269 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1270 | args.v4.acConfig.ucTransmitterSel = 1; |
| 1271 | break; |
| 1272 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1273 | args.v4.acConfig.ucTransmitterSel = 2; |
| 1274 | break; |
| 1275 | } |
| 1276 | |
| 1277 | if (is_dp) |
| 1278 | args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ |
| 1279 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 1280 | if (dig->coherent_mode) |
| 1281 | args.v4.acConfig.fCoherentMode = 1; |
| 1282 | if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1283 | args.v4.acConfig.fDualLinkConnector = 1; |
| 1284 | } |
| 1285 | break; |
| 1286 | case 5: |
| 1287 | args.v5.ucAction = action; |
| 1288 | if (is_dp) |
| 1289 | args.v5.usSymClock = cpu_to_le16(dp_clock / 10); |
| 1290 | else |
| 1291 | args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1292 | |
| 1293 | switch (radeon_encoder->encoder_id) { |
| 1294 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1295 | if (dig->linkb) |
| 1296 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; |
| 1297 | else |
| 1298 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; |
| 1299 | break; |
| 1300 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1301 | if (dig->linkb) |
| 1302 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; |
| 1303 | else |
| 1304 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; |
| 1305 | break; |
| 1306 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1307 | if (dig->linkb) |
| 1308 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; |
| 1309 | else |
| 1310 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
| 1311 | break; |
| 1312 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 1313 | args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; |
| 1314 | break; |
| 1315 | } |
| 1316 | if (is_dp) |
| 1317 | args.v5.ucLaneNum = dp_lane_count; |
| 1318 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1319 | args.v5.ucLaneNum = 8; |
| 1320 | else |
| 1321 | args.v5.ucLaneNum = 4; |
| 1322 | args.v5.ucConnObjId = connector_object_id; |
| 1323 | args.v5.ucDigMode = atombios_get_encoder_mode(encoder); |
| 1324 | |
| 1325 | if (is_dp && rdev->clock.dp_extclk) |
| 1326 | args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; |
| 1327 | else |
| 1328 | args.v5.asConfig.ucPhyClkSrcId = pll_id; |
| 1329 | |
| 1330 | if (is_dp) |
| 1331 | args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ |
| 1332 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 1333 | if (dig->coherent_mode) |
| 1334 | args.v5.asConfig.ucCoherentMode = 1; |
| 1335 | } |
| 1336 | if (hpd_id == RADEON_HPD_NONE) |
| 1337 | args.v5.asConfig.ucHPDSel = 0; |
| 1338 | else |
| 1339 | args.v5.asConfig.ucHPDSel = hpd_id + 1; |
| 1340 | args.v5.ucDigEncoderSel = 1 << dig_encoder; |
| 1341 | args.v5.ucDPLaneSet = lane_set; |
| 1342 | break; |
| 1343 | default: |
| 1344 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 1345 | break; |
| 1346 | } |
| 1347 | break; |
| 1348 | default: |
| 1349 | DRM_ERROR("Unknown table version %d, %d\n" , frev, crev); |
| 1350 | break; |
| 1351 | } |
| 1352 | |
| 1353 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1354 | } |
| 1355 | |
| 1356 | bool |
| 1357 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) |
| 1358 | { |
| 1359 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 1360 | struct drm_device *dev = radeon_connector->base.dev; |
| 1361 | struct radeon_device *rdev = dev->dev_private; |
| 1362 | union dig_transmitter_control args; |
| 1363 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
| 1364 | uint8_t frev, crev; |
| 1365 | |
| 1366 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
| 1367 | goto done; |
| 1368 | |
| 1369 | if (!ASIC_IS_DCE4(rdev)) |
| 1370 | goto done; |
| 1371 | |
| 1372 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
| 1373 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
| 1374 | goto done; |
| 1375 | |
| 1376 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 1377 | goto done; |
| 1378 | |
| 1379 | memset(&args, 0, sizeof(args)); |
| 1380 | |
| 1381 | args.v1.ucAction = action; |
| 1382 | |
| 1383 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1384 | |
| 1385 | /* wait for the panel to power up */ |
| 1386 | if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { |
| 1387 | int i; |
| 1388 | |
| 1389 | for (i = 0; i < 300; i++) { |
| 1390 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) |
| 1391 | return true; |
| 1392 | mdelay(1); |
| 1393 | } |
| 1394 | return false; |
| 1395 | } |
| 1396 | done: |
| 1397 | return true; |
| 1398 | } |
| 1399 | |
| 1400 | union external_encoder_control { |
| 1401 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; |
| 1402 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
| 1403 | }; |
| 1404 | |
| 1405 | static void |
| 1406 | atombios_external_encoder_setup(struct drm_encoder *encoder, |
| 1407 | struct drm_encoder *ext_encoder, |
| 1408 | int action) |
| 1409 | { |
| 1410 | struct drm_device *dev = encoder->dev; |
| 1411 | struct radeon_device *rdev = dev->dev_private; |
| 1412 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1413 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
| 1414 | union external_encoder_control args; |
| 1415 | struct drm_connector *connector; |
| 1416 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); |
| 1417 | u8 frev, crev; |
| 1418 | int dp_clock = 0; |
| 1419 | int dp_lane_count = 0; |
| 1420 | int connector_object_id = 0; |
| 1421 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
| 1422 | |
| 1423 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
| 1424 | connector = radeon_get_connector_for_encoder_init(encoder); |
| 1425 | else |
| 1426 | connector = radeon_get_connector_for_encoder(encoder); |
| 1427 | |
| 1428 | if (connector) { |
| 1429 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 1430 | struct radeon_connector_atom_dig *dig_connector = |
| 1431 | radeon_connector->con_priv; |
| 1432 | |
| 1433 | dp_clock = dig_connector->dp_clock; |
| 1434 | dp_lane_count = dig_connector->dp_lane_count; |
| 1435 | connector_object_id = |
| 1436 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| 1437 | } |
| 1438 | |
| 1439 | memset(&args, 0, sizeof(args)); |
| 1440 | |
| 1441 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 1442 | return; |
| 1443 | |
| 1444 | switch (frev) { |
| 1445 | case 1: |
| 1446 | /* no params on frev 1 */ |
| 1447 | break; |
| 1448 | case 2: |
| 1449 | switch (crev) { |
| 1450 | case 1: |
| 1451 | case 2: |
| 1452 | args.v1.sDigEncoder.ucAction = action; |
| 1453 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1454 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 1455 | |
| 1456 | if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { |
| 1457 | if (dp_clock == 270000) |
| 1458 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
| 1459 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; |
| 1460 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1461 | args.v1.sDigEncoder.ucLaneNum = 8; |
| 1462 | else |
| 1463 | args.v1.sDigEncoder.ucLaneNum = 4; |
| 1464 | break; |
| 1465 | case 3: |
| 1466 | args.v3.sExtEncoder.ucAction = action; |
| 1467 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
| 1468 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
| 1469 | else |
| 1470 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 1471 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 1472 | |
| 1473 | if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { |
| 1474 | if (dp_clock == 270000) |
| 1475 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
| 1476 | else if (dp_clock == 540000) |
| 1477 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; |
| 1478 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; |
| 1479 | } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
| 1480 | args.v3.sExtEncoder.ucLaneNum = 8; |
| 1481 | else |
| 1482 | args.v3.sExtEncoder.ucLaneNum = 4; |
| 1483 | switch (ext_enum) { |
| 1484 | case GRAPH_OBJECT_ENUM_ID1: |
| 1485 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; |
| 1486 | break; |
| 1487 | case GRAPH_OBJECT_ENUM_ID2: |
| 1488 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; |
| 1489 | break; |
| 1490 | case GRAPH_OBJECT_ENUM_ID3: |
| 1491 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
| 1492 | break; |
| 1493 | } |
| 1494 | args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); |
| 1495 | break; |
| 1496 | default: |
| 1497 | DRM_ERROR("Unknown table version: %d, %d\n" , frev, crev); |
| 1498 | return; |
| 1499 | } |
| 1500 | break; |
| 1501 | default: |
| 1502 | DRM_ERROR("Unknown table version: %d, %d\n" , frev, crev); |
| 1503 | return; |
| 1504 | } |
| 1505 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1506 | } |
| 1507 | |
| 1508 | static void |
| 1509 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
| 1510 | { |
| 1511 | struct drm_device *dev = encoder->dev; |
| 1512 | struct radeon_device *rdev = dev->dev_private; |
| 1513 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1514 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1515 | ENABLE_YUV_PS_ALLOCATION args; |
| 1516 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
| 1517 | uint32_t temp, reg; |
| 1518 | |
| 1519 | memset(&args, 0, sizeof(args)); |
| 1520 | |
| 1521 | if (rdev->family >= CHIP_R600) |
| 1522 | reg = R600_BIOS_3_SCRATCH; |
| 1523 | else |
| 1524 | reg = RADEON_BIOS_3_SCRATCH; |
| 1525 | |
| 1526 | /* XXX: fix up scratch reg handling */ |
| 1527 | temp = RREG32(reg); |
| 1528 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1529 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
| 1530 | (radeon_crtc->crtc_id << 18))); |
| 1531 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1532 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
| 1533 | else |
| 1534 | WREG32(reg, 0); |
| 1535 | |
| 1536 | if (enable) |
| 1537 | args.ucEnable = ATOM_ENABLE; |
| 1538 | args.ucCRTC = radeon_crtc->crtc_id; |
| 1539 | |
| 1540 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1541 | |
| 1542 | WREG32(reg, temp); |
| 1543 | } |
| 1544 | |
| 1545 | static void |
| 1546 | radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) |
| 1547 | { |
| 1548 | struct drm_device *dev = encoder->dev; |
| 1549 | struct radeon_device *rdev = dev->dev_private; |
| 1550 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1551 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
| 1552 | int index = 0; |
| 1553 | |
| 1554 | memset(&args, 0, sizeof(args)); |
| 1555 | |
| 1556 | switch (radeon_encoder->encoder_id) { |
| 1557 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1558 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 1559 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
| 1560 | break; |
| 1561 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1562 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1563 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1564 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
| 1565 | break; |
| 1566 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 1567 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
| 1568 | break; |
| 1569 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 1570 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 1571 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
| 1572 | else |
| 1573 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
| 1574 | break; |
| 1575 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1576 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1577 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1578 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 1579 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1580 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 1581 | else |
| 1582 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
| 1583 | break; |
| 1584 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1585 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1586 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1587 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 1588 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1589 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 1590 | else |
| 1591 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
| 1592 | break; |
| 1593 | default: |
| 1594 | return; |
| 1595 | } |
| 1596 | |
| 1597 | switch (mode) { |
| 1598 | case DRM_MODE_DPMS_ON: |
| 1599 | args.ucAction = ATOM_ENABLE; |
| 1600 | /* workaround for DVOOutputControl on some RS690 systems */ |
| 1601 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { |
| 1602 | u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); |
| 1603 | WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); |
| 1604 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1605 | WREG32(RADEON_BIOS_3_SCRATCH, reg); |
| 1606 | } else |
| 1607 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1608 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1609 | args.ucAction = ATOM_LCD_BLON; |
| 1610 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1611 | } |
| 1612 | break; |
| 1613 | case DRM_MODE_DPMS_STANDBY: |
| 1614 | case DRM_MODE_DPMS_SUSPEND: |
| 1615 | case DRM_MODE_DPMS_OFF: |
| 1616 | args.ucAction = ATOM_DISABLE; |
| 1617 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1618 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1619 | args.ucAction = ATOM_LCD_BLOFF; |
| 1620 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1621 | } |
| 1622 | break; |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | static void |
| 1627 | radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) |
| 1628 | { |
| 1629 | struct drm_device *dev = encoder->dev; |
| 1630 | struct radeon_device *rdev = dev->dev_private; |
| 1631 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1632 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
| 1633 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 1634 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 1635 | struct radeon_connector *radeon_connector = NULL; |
| 1636 | struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
| 1637 | bool travis_quirk = false; |
| 1638 | |
| 1639 | if (connector) { |
| 1640 | radeon_connector = to_radeon_connector(connector); |
| 1641 | radeon_dig_connector = radeon_connector->con_priv; |
| 1642 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| 1643 | ENCODER_OBJECT_ID_TRAVIS) && |
| 1644 | (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
| 1645 | !ASIC_IS_DCE5(rdev)) |
| 1646 | travis_quirk = true; |
| 1647 | } |
| 1648 | |
| 1649 | switch (mode) { |
| 1650 | case DRM_MODE_DPMS_ON: |
| 1651 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
| 1652 | if (!connector) |
| 1653 | dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
| 1654 | else |
| 1655 | dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); |
| 1656 | |
| 1657 | /* setup and enable the encoder */ |
| 1658 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
| 1659 | atombios_dig_encoder_setup(encoder, |
| 1660 | ATOM_ENCODER_CMD_SETUP_PANEL_MODE, |
| 1661 | dig->panel_mode); |
| 1662 | if (ext_encoder) { |
| 1663 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
| 1664 | atombios_external_encoder_setup(encoder, ext_encoder, |
| 1665 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
| 1666 | } |
| 1667 | } else if (ASIC_IS_DCE4(rdev)) { |
| 1668 | /* setup and enable the encoder */ |
| 1669 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
| 1670 | } else { |
| 1671 | /* setup and enable the encoder and transmitter */ |
| 1672 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
| 1673 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
| 1674 | } |
| 1675 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
| 1676 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
| 1677 | atombios_set_edp_panel_power(connector, |
| 1678 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
| 1679 | radeon_dig_connector->edp_on = true; |
| 1680 | } |
| 1681 | } |
| 1682 | /* enable the transmitter */ |
| 1683 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
| 1684 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
| 1685 | /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ |
| 1686 | radeon_dp_link_train(encoder, connector); |
| 1687 | if (ASIC_IS_DCE4(rdev)) |
| 1688 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
| 1689 | } |
| 1690 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 1691 | atombios_dig_transmitter_setup(encoder, |
| 1692 | ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
| 1693 | if (ext_encoder) |
| 1694 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
| 1695 | break; |
| 1696 | case DRM_MODE_DPMS_STANDBY: |
| 1697 | case DRM_MODE_DPMS_SUSPEND: |
| 1698 | case DRM_MODE_DPMS_OFF: |
| 1699 | if (ASIC_IS_DCE4(rdev)) { |
| 1700 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) |
| 1701 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
| 1702 | } |
| 1703 | if (ext_encoder) |
| 1704 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
| 1705 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 1706 | atombios_dig_transmitter_setup(encoder, |
| 1707 | ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
| 1708 | |
| 1709 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && |
| 1710 | connector && !travis_quirk) |
| 1711 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
| 1712 | if (ASIC_IS_DCE4(rdev)) { |
| 1713 | /* disable the transmitter */ |
| 1714 | atombios_dig_transmitter_setup(encoder, |
| 1715 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
| 1716 | } else { |
| 1717 | /* disable the encoder and transmitter */ |
| 1718 | atombios_dig_transmitter_setup(encoder, |
| 1719 | ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
| 1720 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
| 1721 | } |
| 1722 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
| 1723 | if (travis_quirk) |
| 1724 | radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
| 1725 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
| 1726 | atombios_set_edp_panel_power(connector, |
| 1727 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
| 1728 | radeon_dig_connector->edp_on = false; |
| 1729 | } |
| 1730 | } |
| 1731 | break; |
| 1732 | } |
| 1733 | } |
| 1734 | |
| 1735 | static void |
| 1736 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 1737 | { |
| 1738 | struct drm_device *dev = encoder->dev; |
| 1739 | struct radeon_device *rdev = dev->dev_private; |
| 1740 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1741 | |
| 1742 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n" , |
| 1743 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
| 1744 | radeon_encoder->active_device); |
| 1745 | switch (radeon_encoder->encoder_id) { |
| 1746 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1747 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 1748 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 1749 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 1750 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1751 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1752 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1753 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1754 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
| 1755 | break; |
| 1756 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1757 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1758 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1759 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 1760 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1761 | radeon_atom_encoder_dpms_dig(encoder, mode); |
| 1762 | break; |
| 1763 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1764 | if (ASIC_IS_DCE5(rdev)) { |
| 1765 | switch (mode) { |
| 1766 | case DRM_MODE_DPMS_ON: |
| 1767 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
| 1768 | break; |
| 1769 | case DRM_MODE_DPMS_STANDBY: |
| 1770 | case DRM_MODE_DPMS_SUSPEND: |
| 1771 | case DRM_MODE_DPMS_OFF: |
| 1772 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
| 1773 | break; |
| 1774 | } |
| 1775 | } else if (ASIC_IS_DCE3(rdev)) |
| 1776 | radeon_atom_encoder_dpms_dig(encoder, mode); |
| 1777 | else |
| 1778 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
| 1779 | break; |
| 1780 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1781 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1782 | if (ASIC_IS_DCE5(rdev)) { |
| 1783 | switch (mode) { |
| 1784 | case DRM_MODE_DPMS_ON: |
| 1785 | atombios_dac_setup(encoder, ATOM_ENABLE); |
| 1786 | break; |
| 1787 | case DRM_MODE_DPMS_STANDBY: |
| 1788 | case DRM_MODE_DPMS_SUSPEND: |
| 1789 | case DRM_MODE_DPMS_OFF: |
| 1790 | atombios_dac_setup(encoder, ATOM_DISABLE); |
| 1791 | break; |
| 1792 | } |
| 1793 | } else |
| 1794 | radeon_atom_encoder_dpms_avivo(encoder, mode); |
| 1795 | break; |
| 1796 | default: |
| 1797 | return; |
| 1798 | } |
| 1799 | |
| 1800 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 1801 | |
| 1802 | } |
| 1803 | |
| 1804 | union crtc_source_param { |
| 1805 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
| 1806 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
| 1807 | }; |
| 1808 | |
| 1809 | static void |
| 1810 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
| 1811 | { |
| 1812 | struct drm_device *dev = encoder->dev; |
| 1813 | struct radeon_device *rdev = dev->dev_private; |
| 1814 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1815 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1816 | union crtc_source_param args; |
| 1817 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
| 1818 | uint8_t frev, crev; |
| 1819 | struct radeon_encoder_atom_dig *dig; |
| 1820 | |
| 1821 | memset(&args, 0, sizeof(args)); |
| 1822 | |
| 1823 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 1824 | return; |
| 1825 | |
| 1826 | switch (frev) { |
| 1827 | case 1: |
| 1828 | switch (crev) { |
| 1829 | case 1: |
| 1830 | default: |
| 1831 | if (ASIC_IS_AVIVO(rdev)) |
| 1832 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
| 1833 | else { |
| 1834 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
| 1835 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
| 1836 | } else { |
| 1837 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
| 1838 | } |
| 1839 | } |
| 1840 | switch (radeon_encoder->encoder_id) { |
| 1841 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1842 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 1843 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
| 1844 | break; |
| 1845 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 1846 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 1847 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
| 1848 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
| 1849 | else |
| 1850 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
| 1851 | break; |
| 1852 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1853 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1854 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1855 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
| 1856 | break; |
| 1857 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1858 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1859 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1860 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
| 1861 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1862 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1863 | else |
| 1864 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
| 1865 | break; |
| 1866 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1867 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1868 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1869 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
| 1870 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1871 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1872 | else |
| 1873 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
| 1874 | break; |
| 1875 | } |
| 1876 | break; |
| 1877 | case 2: |
| 1878 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
| 1879 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { |
| 1880 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 1881 | |
| 1882 | if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) |
| 1883 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
| 1884 | else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) |
| 1885 | args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
| 1886 | else |
| 1887 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
| 1888 | } else |
| 1889 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
| 1890 | switch (radeon_encoder->encoder_id) { |
| 1891 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1892 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1893 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1894 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 1895 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1896 | dig = radeon_encoder->enc_priv; |
| 1897 | switch (dig->dig_encoder) { |
| 1898 | case 0: |
| 1899 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
| 1900 | break; |
| 1901 | case 1: |
| 1902 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
| 1903 | break; |
| 1904 | case 2: |
| 1905 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; |
| 1906 | break; |
| 1907 | case 3: |
| 1908 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; |
| 1909 | break; |
| 1910 | case 4: |
| 1911 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; |
| 1912 | break; |
| 1913 | case 5: |
| 1914 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
| 1915 | break; |
| 1916 | case 6: |
| 1917 | args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; |
| 1918 | break; |
| 1919 | } |
| 1920 | break; |
| 1921 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1922 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
| 1923 | break; |
| 1924 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1925 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1926 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1927 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1928 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1929 | else |
| 1930 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
| 1931 | break; |
| 1932 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1933 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1934 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1935 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1936 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1937 | else |
| 1938 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
| 1939 | break; |
| 1940 | } |
| 1941 | break; |
| 1942 | } |
| 1943 | break; |
| 1944 | default: |
| 1945 | DRM_ERROR("Unknown table version: %d, %d\n" , frev, crev); |
| 1946 | return; |
| 1947 | } |
| 1948 | |
| 1949 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1950 | |
| 1951 | /* update scratch regs with new routing */ |
| 1952 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 1953 | } |
| 1954 | |
| 1955 | static void |
| 1956 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
| 1957 | struct drm_display_mode *mode) |
| 1958 | { |
| 1959 | struct drm_device *dev = encoder->dev; |
| 1960 | struct radeon_device *rdev = dev->dev_private; |
| 1961 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1962 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1963 | |
| 1964 | /* Funky macbooks */ |
| 1965 | if ((dev->pdev->device == 0x71C5) && |
| 1966 | (dev->pdev->subsystem_vendor == 0x106b) && |
| 1967 | (dev->pdev->subsystem_device == 0x0080)) { |
| 1968 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 1969 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
| 1970 | |
| 1971 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
| 1972 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
| 1973 | |
| 1974 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
| 1975 | } |
| 1976 | } |
| 1977 | |
| 1978 | /* set scaler clears this on some chips */ |
| 1979 | if (ASIC_IS_AVIVO(rdev) && |
| 1980 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
| 1981 | if (ASIC_IS_DCE8(rdev)) { |
| 1982 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1983 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1984 | CIK_INTERLEAVE_EN); |
| 1985 | else |
| 1986 | WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 1987 | } else if (ASIC_IS_DCE4(rdev)) { |
| 1988 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1989 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1990 | EVERGREEN_INTERLEAVE_EN); |
| 1991 | else |
| 1992 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 1993 | } else { |
| 1994 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1995 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1996 | AVIVO_D1MODE_INTERLEAVE_EN); |
| 1997 | else |
| 1998 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 1999 | } |
| 2000 | } |
| 2001 | } |
| 2002 | |
| 2003 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
| 2004 | { |
| 2005 | struct drm_device *dev = encoder->dev; |
| 2006 | struct radeon_device *rdev = dev->dev_private; |
| 2007 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 2008 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2009 | struct drm_encoder *test_encoder; |
| 2010 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 2011 | uint32_t dig_enc_in_use = 0; |
| 2012 | |
| 2013 | if (ASIC_IS_DCE6(rdev)) { |
| 2014 | /* DCE6 */ |
| 2015 | switch (radeon_encoder->encoder_id) { |
| 2016 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2017 | if (dig->linkb) |
| 2018 | return 1; |
| 2019 | else |
| 2020 | return 0; |
| 2021 | break; |
| 2022 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2023 | if (dig->linkb) |
| 2024 | return 3; |
| 2025 | else |
| 2026 | return 2; |
| 2027 | break; |
| 2028 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2029 | if (dig->linkb) |
| 2030 | return 5; |
| 2031 | else |
| 2032 | return 4; |
| 2033 | break; |
| 2034 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2035 | return 6; |
| 2036 | break; |
| 2037 | } |
| 2038 | } else if (ASIC_IS_DCE4(rdev)) { |
| 2039 | /* DCE4/5 */ |
| 2040 | if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { |
| 2041 | /* ontario follows DCE4 */ |
| 2042 | if (rdev->family == CHIP_PALM) { |
| 2043 | if (dig->linkb) |
| 2044 | return 1; |
| 2045 | else |
| 2046 | return 0; |
| 2047 | } else |
| 2048 | /* llano follows DCE3.2 */ |
| 2049 | return radeon_crtc->crtc_id; |
| 2050 | } else { |
| 2051 | switch (radeon_encoder->encoder_id) { |
| 2052 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2053 | if (dig->linkb) |
| 2054 | return 1; |
| 2055 | else |
| 2056 | return 0; |
| 2057 | break; |
| 2058 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2059 | if (dig->linkb) |
| 2060 | return 3; |
| 2061 | else |
| 2062 | return 2; |
| 2063 | break; |
| 2064 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2065 | if (dig->linkb) |
| 2066 | return 5; |
| 2067 | else |
| 2068 | return 4; |
| 2069 | break; |
| 2070 | } |
| 2071 | } |
| 2072 | } |
| 2073 | |
| 2074 | /* on DCE32 and encoder can driver any block so just crtc id */ |
| 2075 | if (ASIC_IS_DCE32(rdev)) { |
| 2076 | return radeon_crtc->crtc_id; |
| 2077 | } |
| 2078 | |
| 2079 | /* on DCE3 - LVTMA can only be driven by DIGB */ |
| 2080 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 2081 | struct radeon_encoder *radeon_test_encoder; |
| 2082 | |
| 2083 | if (encoder == test_encoder) |
| 2084 | continue; |
| 2085 | |
| 2086 | if (!radeon_encoder_is_digital(test_encoder)) |
| 2087 | continue; |
| 2088 | |
| 2089 | radeon_test_encoder = to_radeon_encoder(test_encoder); |
| 2090 | dig = radeon_test_encoder->enc_priv; |
| 2091 | |
| 2092 | if (dig->dig_encoder >= 0) |
| 2093 | dig_enc_in_use |= (1 << dig->dig_encoder); |
| 2094 | } |
| 2095 | |
| 2096 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { |
| 2097 | if (dig_enc_in_use & 0x2) |
| 2098 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n" ); |
| 2099 | return 1; |
| 2100 | } |
| 2101 | if (!(dig_enc_in_use & 1)) |
| 2102 | return 0; |
| 2103 | return 1; |
| 2104 | } |
| 2105 | |
| 2106 | /* This only needs to be called once at startup */ |
| 2107 | void |
| 2108 | radeon_atom_encoder_init(struct radeon_device *rdev) |
| 2109 | { |
| 2110 | struct drm_device *dev = rdev->ddev; |
| 2111 | struct drm_encoder *encoder; |
| 2112 | |
| 2113 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2114 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2115 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
| 2116 | |
| 2117 | switch (radeon_encoder->encoder_id) { |
| 2118 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2119 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2120 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2121 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2122 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 2123 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
| 2124 | break; |
| 2125 | default: |
| 2126 | break; |
| 2127 | } |
| 2128 | |
| 2129 | if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) |
| 2130 | atombios_external_encoder_setup(encoder, ext_encoder, |
| 2131 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); |
| 2132 | } |
| 2133 | } |
| 2134 | |
| 2135 | static void |
| 2136 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
| 2137 | struct drm_display_mode *mode, |
| 2138 | struct drm_display_mode *adjusted_mode) |
| 2139 | { |
| 2140 | struct drm_device *dev = encoder->dev; |
| 2141 | struct radeon_device *rdev = dev->dev_private; |
| 2142 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2143 | |
| 2144 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 2145 | |
| 2146 | /* need to call this here rather than in prepare() since we need some crtc info */ |
| 2147 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 2148 | |
| 2149 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
| 2150 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
| 2151 | atombios_yuv_setup(encoder, true); |
| 2152 | else |
| 2153 | atombios_yuv_setup(encoder, false); |
| 2154 | } |
| 2155 | |
| 2156 | switch (radeon_encoder->encoder_id) { |
| 2157 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 2158 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 2159 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 2160 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 2161 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
| 2162 | break; |
| 2163 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2164 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2165 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2166 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2167 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 2168 | /* handled in dpms */ |
| 2169 | break; |
| 2170 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 2171 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 2172 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 2173 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
| 2174 | break; |
| 2175 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 2176 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 2177 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 2178 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 2179 | atombios_dac_setup(encoder, ATOM_ENABLE); |
| 2180 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
| 2181 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 2182 | atombios_tv_setup(encoder, ATOM_ENABLE); |
| 2183 | else |
| 2184 | atombios_tv_setup(encoder, ATOM_DISABLE); |
| 2185 | } |
| 2186 | break; |
| 2187 | } |
| 2188 | |
| 2189 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
| 2190 | |
| 2191 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
| 2192 | if (rdev->asic->display.hdmi_enable) |
| 2193 | radeon_hdmi_enable(rdev, encoder, true); |
| 2194 | if (rdev->asic->display.hdmi_setmode) |
| 2195 | radeon_hdmi_setmode(rdev, encoder, adjusted_mode); |
| 2196 | } |
| 2197 | } |
| 2198 | |
| 2199 | static bool |
| 2200 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 2201 | { |
| 2202 | struct drm_device *dev = encoder->dev; |
| 2203 | struct radeon_device *rdev = dev->dev_private; |
| 2204 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2205 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 2206 | |
| 2207 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
| 2208 | ATOM_DEVICE_CV_SUPPORT | |
| 2209 | ATOM_DEVICE_CRT_SUPPORT)) { |
| 2210 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
| 2211 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
| 2212 | uint8_t frev, crev; |
| 2213 | |
| 2214 | memset(&args, 0, sizeof(args)); |
| 2215 | |
| 2216 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 2217 | return false; |
| 2218 | |
| 2219 | args.sDacload.ucMisc = 0; |
| 2220 | |
| 2221 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
| 2222 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
| 2223 | args.sDacload.ucDacType = ATOM_DAC_A; |
| 2224 | else |
| 2225 | args.sDacload.ucDacType = ATOM_DAC_B; |
| 2226 | |
| 2227 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
| 2228 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
| 2229 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
| 2230 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
| 2231 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 2232 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
| 2233 | if (crev >= 3) |
| 2234 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| 2235 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 2236 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
| 2237 | if (crev >= 3) |
| 2238 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| 2239 | } |
| 2240 | |
| 2241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2242 | |
| 2243 | return true; |
| 2244 | } else |
| 2245 | return false; |
| 2246 | } |
| 2247 | |
| 2248 | static enum drm_connector_status |
| 2249 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 2250 | { |
| 2251 | struct drm_device *dev = encoder->dev; |
| 2252 | struct radeon_device *rdev = dev->dev_private; |
| 2253 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2254 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 2255 | uint32_t bios_0_scratch; |
| 2256 | |
| 2257 | if (!atombios_dac_load_detect(encoder, connector)) { |
| 2258 | DRM_DEBUG_KMS("detect returned false \n" ); |
| 2259 | return connector_status_unknown; |
| 2260 | } |
| 2261 | |
| 2262 | if (rdev->family >= CHIP_R600) |
| 2263 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| 2264 | else |
| 2265 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 2266 | |
| 2267 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n" , bios_0_scratch, radeon_encoder->devices); |
| 2268 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 2269 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
| 2270 | return connector_status_connected; |
| 2271 | } |
| 2272 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 2273 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
| 2274 | return connector_status_connected; |
| 2275 | } |
| 2276 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 2277 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
| 2278 | return connector_status_connected; |
| 2279 | } |
| 2280 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 2281 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
| 2282 | return connector_status_connected; /* CTV */ |
| 2283 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
| 2284 | return connector_status_connected; /* STV */ |
| 2285 | } |
| 2286 | return connector_status_disconnected; |
| 2287 | } |
| 2288 | |
| 2289 | static enum drm_connector_status |
| 2290 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 2291 | { |
| 2292 | struct drm_device *dev = encoder->dev; |
| 2293 | struct radeon_device *rdev = dev->dev_private; |
| 2294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2295 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 2296 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
| 2297 | u32 bios_0_scratch; |
| 2298 | |
| 2299 | if (!ASIC_IS_DCE4(rdev)) |
| 2300 | return connector_status_unknown; |
| 2301 | |
| 2302 | if (!ext_encoder) |
| 2303 | return connector_status_unknown; |
| 2304 | |
| 2305 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) |
| 2306 | return connector_status_unknown; |
| 2307 | |
| 2308 | /* load detect on the dp bridge */ |
| 2309 | atombios_external_encoder_setup(encoder, ext_encoder, |
| 2310 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); |
| 2311 | |
| 2312 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| 2313 | |
| 2314 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n" , bios_0_scratch, radeon_encoder->devices); |
| 2315 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 2316 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
| 2317 | return connector_status_connected; |
| 2318 | } |
| 2319 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 2320 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
| 2321 | return connector_status_connected; |
| 2322 | } |
| 2323 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 2324 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
| 2325 | return connector_status_connected; |
| 2326 | } |
| 2327 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 2328 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
| 2329 | return connector_status_connected; /* CTV */ |
| 2330 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
| 2331 | return connector_status_connected; /* STV */ |
| 2332 | } |
| 2333 | return connector_status_disconnected; |
| 2334 | } |
| 2335 | |
| 2336 | void |
| 2337 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) |
| 2338 | { |
| 2339 | struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
| 2340 | |
| 2341 | if (ext_encoder) |
| 2342 | /* ddc_setup on the dp bridge */ |
| 2343 | atombios_external_encoder_setup(encoder, ext_encoder, |
| 2344 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); |
| 2345 | |
| 2346 | } |
| 2347 | |
| 2348 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
| 2349 | { |
| 2350 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 2351 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2352 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 2353 | |
| 2354 | if ((radeon_encoder->active_device & |
| 2355 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
| 2356 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
| 2357 | ENCODER_OBJECT_ID_NONE)) { |
| 2358 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 2359 | if (dig) { |
| 2360 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); |
| 2361 | if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { |
| 2362 | if (rdev->family >= CHIP_R600) |
| 2363 | dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; |
| 2364 | else |
| 2365 | /* RS600/690/740 have only 1 afmt block */ |
| 2366 | dig->afmt = rdev->mode_info.afmt[0]; |
| 2367 | } |
| 2368 | } |
| 2369 | } |
| 2370 | |
| 2371 | radeon_atom_output_lock(encoder, true); |
| 2372 | |
| 2373 | if (connector) { |
| 2374 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 2375 | |
| 2376 | /* select the clock/data port if it uses a router */ |
| 2377 | if (radeon_connector->router.cd_valid) |
| 2378 | radeon_router_select_cd_port(radeon_connector); |
| 2379 | |
| 2380 | /* turn eDP panel on for mode set */ |
| 2381 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
| 2382 | atombios_set_edp_panel_power(connector, |
| 2383 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
| 2384 | } |
| 2385 | |
| 2386 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
| 2387 | atombios_set_encoder_crtc_source(encoder); |
| 2388 | /* set up the FMT blocks */ |
| 2389 | if (ASIC_IS_DCE8(rdev)) |
| 2390 | dce8_program_fmt(encoder); |
| 2391 | else if (ASIC_IS_DCE4(rdev)) |
| 2392 | dce4_program_fmt(encoder); |
| 2393 | else if (ASIC_IS_DCE3(rdev)) |
| 2394 | dce3_program_fmt(encoder); |
| 2395 | else if (ASIC_IS_AVIVO(rdev)) |
| 2396 | avivo_program_fmt(encoder); |
| 2397 | } |
| 2398 | |
| 2399 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
| 2400 | { |
| 2401 | /* need to call this here as we need the crtc set up */ |
| 2402 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
| 2403 | radeon_atom_output_lock(encoder, false); |
| 2404 | } |
| 2405 | |
| 2406 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
| 2407 | { |
| 2408 | struct drm_device *dev = encoder->dev; |
| 2409 | struct radeon_device *rdev = dev->dev_private; |
| 2410 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2411 | struct radeon_encoder_atom_dig *dig; |
| 2412 | |
| 2413 | /* check for pre-DCE3 cards with shared encoders; |
| 2414 | * can't really use the links individually, so don't disable |
| 2415 | * the encoder if it's in use by another connector |
| 2416 | */ |
| 2417 | if (!ASIC_IS_DCE3(rdev)) { |
| 2418 | struct drm_encoder *other_encoder; |
| 2419 | struct radeon_encoder *other_radeon_encoder; |
| 2420 | |
| 2421 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { |
| 2422 | other_radeon_encoder = to_radeon_encoder(other_encoder); |
| 2423 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && |
| 2424 | drm_helper_encoder_in_use(other_encoder)) |
| 2425 | goto disable_done; |
| 2426 | } |
| 2427 | } |
| 2428 | |
| 2429 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 2430 | |
| 2431 | switch (radeon_encoder->encoder_id) { |
| 2432 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 2433 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 2434 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 2435 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 2436 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); |
| 2437 | break; |
| 2438 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2439 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2440 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2441 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2442 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 2443 | /* handled in dpms */ |
| 2444 | break; |
| 2445 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 2446 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 2447 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 2448 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
| 2449 | break; |
| 2450 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 2451 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 2452 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 2453 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 2454 | atombios_dac_setup(encoder, ATOM_DISABLE); |
| 2455 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 2456 | atombios_tv_setup(encoder, ATOM_DISABLE); |
| 2457 | break; |
| 2458 | } |
| 2459 | |
| 2460 | disable_done: |
| 2461 | if (radeon_encoder_is_digital(encoder)) { |
| 2462 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
| 2463 | if (rdev->asic->display.hdmi_enable) |
| 2464 | radeon_hdmi_enable(rdev, encoder, false); |
| 2465 | } |
| 2466 | dig = radeon_encoder->enc_priv; |
| 2467 | dig->dig_encoder = -1; |
| 2468 | } |
| 2469 | radeon_encoder->active_device = 0; |
| 2470 | } |
| 2471 | |
| 2472 | /* these are handled by the primary encoders */ |
| 2473 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) |
| 2474 | { |
| 2475 | |
| 2476 | } |
| 2477 | |
| 2478 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) |
| 2479 | { |
| 2480 | |
| 2481 | } |
| 2482 | |
| 2483 | static void |
| 2484 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, |
| 2485 | struct drm_display_mode *mode, |
| 2486 | struct drm_display_mode *adjusted_mode) |
| 2487 | { |
| 2488 | |
| 2489 | } |
| 2490 | |
| 2491 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) |
| 2492 | { |
| 2493 | |
| 2494 | } |
| 2495 | |
| 2496 | static void |
| 2497 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) |
| 2498 | { |
| 2499 | |
| 2500 | } |
| 2501 | |
| 2502 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, |
| 2503 | const struct drm_display_mode *mode, |
| 2504 | struct drm_display_mode *adjusted_mode) |
| 2505 | { |
| 2506 | return true; |
| 2507 | } |
| 2508 | |
| 2509 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { |
| 2510 | .dpms = radeon_atom_ext_dpms, |
| 2511 | .mode_fixup = radeon_atom_ext_mode_fixup, |
| 2512 | .prepare = radeon_atom_ext_prepare, |
| 2513 | .mode_set = radeon_atom_ext_mode_set, |
| 2514 | .commit = radeon_atom_ext_commit, |
| 2515 | .disable = radeon_atom_ext_disable, |
| 2516 | /* no detect for TMDS/LVDS yet */ |
| 2517 | }; |
| 2518 | |
| 2519 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
| 2520 | .dpms = radeon_atom_encoder_dpms, |
| 2521 | .mode_fixup = radeon_atom_mode_fixup, |
| 2522 | .prepare = radeon_atom_encoder_prepare, |
| 2523 | .mode_set = radeon_atom_encoder_mode_set, |
| 2524 | .commit = radeon_atom_encoder_commit, |
| 2525 | .disable = radeon_atom_encoder_disable, |
| 2526 | .detect = radeon_atom_dig_detect, |
| 2527 | }; |
| 2528 | |
| 2529 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
| 2530 | .dpms = radeon_atom_encoder_dpms, |
| 2531 | .mode_fixup = radeon_atom_mode_fixup, |
| 2532 | .prepare = radeon_atom_encoder_prepare, |
| 2533 | .mode_set = radeon_atom_encoder_mode_set, |
| 2534 | .commit = radeon_atom_encoder_commit, |
| 2535 | .detect = radeon_atom_dac_detect, |
| 2536 | }; |
| 2537 | |
| 2538 | void radeon_enc_destroy(struct drm_encoder *encoder) |
| 2539 | { |
| 2540 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2541 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 2542 | radeon_atom_backlight_exit(radeon_encoder); |
| 2543 | kfree(radeon_encoder->enc_priv); |
| 2544 | drm_encoder_cleanup(encoder); |
| 2545 | kfree(radeon_encoder); |
| 2546 | } |
| 2547 | |
| 2548 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
| 2549 | .destroy = radeon_enc_destroy, |
| 2550 | }; |
| 2551 | |
| 2552 | static struct radeon_encoder_atom_dac * |
| 2553 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
| 2554 | { |
| 2555 | struct drm_device *dev = radeon_encoder->base.dev; |
| 2556 | struct radeon_device *rdev = dev->dev_private; |
| 2557 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
| 2558 | |
| 2559 | if (!dac) |
| 2560 | return NULL; |
| 2561 | |
| 2562 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
| 2563 | return dac; |
| 2564 | } |
| 2565 | |
| 2566 | static struct radeon_encoder_atom_dig * |
| 2567 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
| 2568 | { |
| 2569 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
| 2570 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| 2571 | |
| 2572 | if (!dig) |
| 2573 | return NULL; |
| 2574 | |
| 2575 | /* coherent mode by default */ |
| 2576 | dig->coherent_mode = true; |
| 2577 | dig->dig_encoder = -1; |
| 2578 | |
| 2579 | if (encoder_enum == 2) |
| 2580 | dig->linkb = true; |
| 2581 | else |
| 2582 | dig->linkb = false; |
| 2583 | |
| 2584 | return dig; |
| 2585 | } |
| 2586 | |
| 2587 | void |
| 2588 | radeon_add_atom_encoder(struct drm_device *dev, |
| 2589 | uint32_t encoder_enum, |
| 2590 | uint32_t supported_device, |
| 2591 | u16 caps) |
| 2592 | { |
| 2593 | struct radeon_device *rdev = dev->dev_private; |
| 2594 | struct drm_encoder *encoder; |
| 2595 | struct radeon_encoder *radeon_encoder; |
| 2596 | |
| 2597 | /* see if we already added it */ |
| 2598 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2599 | radeon_encoder = to_radeon_encoder(encoder); |
| 2600 | if (radeon_encoder->encoder_enum == encoder_enum) { |
| 2601 | radeon_encoder->devices |= supported_device; |
| 2602 | return; |
| 2603 | } |
| 2604 | |
| 2605 | } |
| 2606 | |
| 2607 | /* add a new one */ |
| 2608 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
| 2609 | if (!radeon_encoder) |
| 2610 | return; |
| 2611 | |
| 2612 | encoder = &radeon_encoder->base; |
| 2613 | switch (rdev->num_crtc) { |
| 2614 | case 1: |
| 2615 | encoder->possible_crtcs = 0x1; |
| 2616 | break; |
| 2617 | case 2: |
| 2618 | default: |
| 2619 | encoder->possible_crtcs = 0x3; |
| 2620 | break; |
| 2621 | case 4: |
| 2622 | encoder->possible_crtcs = 0xf; |
| 2623 | break; |
| 2624 | case 6: |
| 2625 | encoder->possible_crtcs = 0x3f; |
| 2626 | break; |
| 2627 | } |
| 2628 | |
| 2629 | radeon_encoder->enc_priv = NULL; |
| 2630 | |
| 2631 | radeon_encoder->encoder_enum = encoder_enum; |
| 2632 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| 2633 | radeon_encoder->devices = supported_device; |
| 2634 | radeon_encoder->rmx_type = RMX_OFF; |
| 2635 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
| 2636 | radeon_encoder->is_ext_encoder = false; |
| 2637 | radeon_encoder->caps = caps; |
| 2638 | |
| 2639 | switch (radeon_encoder->encoder_id) { |
| 2640 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 2641 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 2642 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 2643 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 2644 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 2645 | radeon_encoder->rmx_type = RMX_FULL; |
| 2646 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 2647 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 2648 | } else { |
| 2649 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 2650 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| 2651 | } |
| 2652 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
| 2653 | break; |
| 2654 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 2655 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 2656 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
| 2657 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
| 2658 | break; |
| 2659 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 2660 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 2661 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 2662 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
| 2663 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
| 2664 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
| 2665 | break; |
| 2666 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 2667 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 2668 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 2669 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2670 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 2671 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2672 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2673 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2674 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 2675 | radeon_encoder->rmx_type = RMX_FULL; |
| 2676 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 2677 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 2678 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
| 2679 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 2680 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| 2681 | } else { |
| 2682 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 2683 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| 2684 | } |
| 2685 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
| 2686 | break; |
| 2687 | case ENCODER_OBJECT_ID_SI170B: |
| 2688 | case ENCODER_OBJECT_ID_CH7303: |
| 2689 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
| 2690 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
| 2691 | case ENCODER_OBJECT_ID_TITFP513: |
| 2692 | case ENCODER_OBJECT_ID_VT1623: |
| 2693 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
| 2694 | case ENCODER_OBJECT_ID_TRAVIS: |
| 2695 | case ENCODER_OBJECT_ID_NUTMEG: |
| 2696 | /* these are handled by the primary encoders */ |
| 2697 | radeon_encoder->is_ext_encoder = true; |
| 2698 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 2699 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 2700 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
| 2701 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 2702 | else |
| 2703 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 2704 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); |
| 2705 | break; |
| 2706 | } |
| 2707 | } |
| 2708 | |