| 1 | /* $NetBSD: if_lii.c,v 1.15 2016/06/10 13:27:14 ozaki-r Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2008 The NetBSD Foundation. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 26 | * POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Driver for Attansic/Atheros's L2 Fast Ethernet controller |
| 31 | */ |
| 32 | |
| 33 | #include <sys/cdefs.h> |
| 34 | __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.15 2016/06/10 13:27:14 ozaki-r Exp $" ); |
| 35 | |
| 36 | |
| 37 | #include <sys/param.h> |
| 38 | #include <sys/systm.h> |
| 39 | #include <sys/types.h> |
| 40 | #include <sys/device.h> |
| 41 | #include <sys/endian.h> |
| 42 | #include <sys/kernel.h> |
| 43 | #include <sys/sockio.h> |
| 44 | |
| 45 | #include <net/if.h> |
| 46 | #include <net/if_media.h> |
| 47 | #include <net/if_ether.h> |
| 48 | |
| 49 | #include <net/bpf.h> |
| 50 | |
| 51 | #include <dev/mii/mii.h> |
| 52 | #include <dev/mii/miivar.h> |
| 53 | |
| 54 | #include <dev/pci/pcireg.h> |
| 55 | #include <dev/pci/pcivar.h> |
| 56 | #include <dev/pci/pcidevs.h> |
| 57 | |
| 58 | #include <dev/pci/if_liireg.h> |
| 59 | |
| 60 | /* #define LII_DEBUG */ |
| 61 | #ifdef LII_DEBUG |
| 62 | #define DPRINTF(x) printf x |
| 63 | #else |
| 64 | #define DPRINTF(x) |
| 65 | #endif |
| 66 | |
| 67 | struct lii_softc { |
| 68 | device_t sc_dev; |
| 69 | pci_chipset_tag_t sc_pc; |
| 70 | pcitag_t sc_tag; |
| 71 | |
| 72 | bus_space_tag_t sc_mmiot; |
| 73 | bus_space_handle_t sc_mmioh; |
| 74 | |
| 75 | /* |
| 76 | * We allocate a big chunk of DMA-safe memory for all data exchanges. |
| 77 | * It is unfortunate that this chip doesn't seem to do scatter-gather. |
| 78 | */ |
| 79 | bus_dma_tag_t sc_dmat; |
| 80 | bus_dmamap_t sc_ringmap; |
| 81 | bus_dma_segment_t sc_ringseg; |
| 82 | |
| 83 | uint8_t *sc_ring; /* the whole area */ |
| 84 | size_t sc_ringsize; |
| 85 | |
| 86 | struct rx_pkt *sc_rxp; /* the part used for RX */ |
| 87 | struct tx_pkt_status *sc_txs; /* the parts used for TX */ |
| 88 | bus_addr_t sc_txsp; |
| 89 | char *sc_txdbase; |
| 90 | bus_addr_t sc_txdp; |
| 91 | |
| 92 | unsigned int sc_rxcur; |
| 93 | /* the active area is [ack; cur[ */ |
| 94 | int sc_txs_cur; |
| 95 | int sc_txs_ack; |
| 96 | int sc_txd_cur; |
| 97 | int sc_txd_ack; |
| 98 | bool sc_free_tx_slots; |
| 99 | |
| 100 | void *sc_ih; |
| 101 | |
| 102 | struct ethercom sc_ec; |
| 103 | struct mii_data sc_mii; |
| 104 | callout_t sc_tick_ch; |
| 105 | uint8_t sc_eaddr[ETHER_ADDR_LEN]; |
| 106 | |
| 107 | int (*sc_memread)(struct lii_softc *, uint32_t, |
| 108 | uint32_t *); |
| 109 | }; |
| 110 | |
| 111 | static int lii_match(device_t, cfdata_t, void *); |
| 112 | static void lii_attach(device_t, device_t, void *); |
| 113 | |
| 114 | static int lii_reset(struct lii_softc *); |
| 115 | static bool lii_eeprom_present(struct lii_softc *); |
| 116 | static int lii_read_macaddr(struct lii_softc *, uint8_t *); |
| 117 | static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); |
| 118 | static void lii_spi_configure(struct lii_softc *); |
| 119 | static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); |
| 120 | static void lii_setmulti(struct lii_softc *); |
| 121 | static void lii_tick(void *); |
| 122 | |
| 123 | static int lii_alloc_rings(struct lii_softc *); |
| 124 | static int lii_free_tx_space(struct lii_softc *); |
| 125 | |
| 126 | static int lii_mii_readreg(device_t, int, int); |
| 127 | static void lii_mii_writereg(device_t, int, int, int); |
| 128 | static void lii_mii_statchg(struct ifnet *); |
| 129 | |
| 130 | static int lii_media_change(struct ifnet *); |
| 131 | static void lii_media_status(struct ifnet *, struct ifmediareq *); |
| 132 | |
| 133 | static int lii_init(struct ifnet *); |
| 134 | static void lii_start(struct ifnet *); |
| 135 | static void lii_stop(struct ifnet *, int); |
| 136 | static void lii_watchdog(struct ifnet *); |
| 137 | static int lii_ioctl(struct ifnet *, u_long, void *); |
| 138 | |
| 139 | static int lii_intr(void *); |
| 140 | static void lii_rxintr(struct lii_softc *); |
| 141 | static void lii_txintr(struct lii_softc *); |
| 142 | |
| 143 | CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), |
| 144 | lii_match, lii_attach, NULL, NULL); |
| 145 | |
| 146 | /* #define LII_DEBUG_REGS */ |
| 147 | #ifndef LII_DEBUG_REGS |
| 148 | #define AT_READ_4(sc,reg) \ |
| 149 | bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) |
| 150 | #define AT_READ_2(sc,reg) \ |
| 151 | bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) |
| 152 | #define AT_READ_1(sc,reg) \ |
| 153 | bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) |
| 154 | #define AT_WRITE_4(sc,reg,val) \ |
| 155 | bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) |
| 156 | #define AT_WRITE_2(sc,reg,val) \ |
| 157 | bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) |
| 158 | #define AT_WRITE_1(sc,reg,val) \ |
| 159 | bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) |
| 160 | #else |
| 161 | static inline uint32_t |
| 162 | AT_READ_4(struct lii_softc *sc, bus_size_t reg) |
| 163 | { |
| 164 | uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); |
| 165 | printf("AT_READ_4(%x) = %x\n" , (unsigned int)reg, r); |
| 166 | return r; |
| 167 | } |
| 168 | |
| 169 | static inline uint16_t |
| 170 | AT_READ_2(struct lii_softc *sc, bus_size_t reg) |
| 171 | { |
| 172 | uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); |
| 173 | printf("AT_READ_2(%x) = %x\n" , (unsigned int)reg, r); |
| 174 | return r; |
| 175 | } |
| 176 | |
| 177 | static inline uint8_t |
| 178 | AT_READ_1(struct lii_softc *sc, bus_size_t reg) |
| 179 | { |
| 180 | uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); |
| 181 | printf("AT_READ_1(%x) = %x\n" , (unsigned int)reg, r); |
| 182 | return r; |
| 183 | } |
| 184 | |
| 185 | static inline void |
| 186 | AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) |
| 187 | { |
| 188 | printf("AT_WRITE_4(%x, %x)\n" , (unsigned int)reg, val); |
| 189 | bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); |
| 190 | } |
| 191 | |
| 192 | static inline void |
| 193 | AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) |
| 194 | { |
| 195 | printf("AT_WRITE_2(%x, %x)\n" , (unsigned int)reg, val); |
| 196 | bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); |
| 197 | } |
| 198 | |
| 199 | static inline void |
| 200 | AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) |
| 201 | { |
| 202 | printf("AT_WRITE_1(%x, %x)\n" , (unsigned int)reg, val); |
| 203 | bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); |
| 204 | } |
| 205 | #endif |
| 206 | |
| 207 | /* |
| 208 | * Those are the default Linux parameters. |
| 209 | */ |
| 210 | |
| 211 | #define AT_TXD_NUM 64 |
| 212 | #define AT_TXD_BUFFER_SIZE 8192 |
| 213 | #define AT_RXD_NUM 64 |
| 214 | |
| 215 | /* |
| 216 | * Assuming (you know what that word makes of you) the chunk of memory |
| 217 | * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the |
| 218 | * first 120 bytes of it, so that the space for the packets, and not the |
| 219 | * whole descriptors themselves, are on a 128-byte boundary. |
| 220 | */ |
| 221 | |
| 222 | #define AT_RXD_PADDING 120 |
| 223 | |
| 224 | static int |
| 225 | lii_match(device_t parent, cfdata_t cfmatch, void *aux) |
| 226 | { |
| 227 | struct pci_attach_args *pa = aux; |
| 228 | |
| 229 | return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && |
| 230 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); |
| 231 | } |
| 232 | |
| 233 | static void |
| 234 | lii_attach(device_t parent, device_t self, void *aux) |
| 235 | { |
| 236 | struct lii_softc *sc = device_private(self); |
| 237 | struct pci_attach_args *pa = aux; |
| 238 | uint8_t eaddr[ETHER_ADDR_LEN]; |
| 239 | struct ifnet *ifp = &sc->sc_ec.ec_if; |
| 240 | pci_intr_handle_t ih; |
| 241 | const char *intrstr; |
| 242 | pcireg_t cmd; |
| 243 | bus_size_t memsize = 0; |
| 244 | char intrbuf[PCI_INTRSTR_LEN]; |
| 245 | |
| 246 | aprint_naive("\n" ); |
| 247 | aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n" ); |
| 248 | |
| 249 | sc->sc_dev = self; |
| 250 | sc->sc_pc = pa->pa_pc; |
| 251 | sc->sc_tag = pa->pa_tag; |
| 252 | sc->sc_dmat = pa->pa_dmat; |
| 253 | |
| 254 | cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); |
| 255 | cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; |
| 256 | cmd &= ~PCI_COMMAND_IO_ENABLE; |
| 257 | pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); |
| 258 | |
| 259 | switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { |
| 260 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: |
| 261 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: |
| 262 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: |
| 263 | break; |
| 264 | default: |
| 265 | aprint_error_dev(self, "invalid base address register\n" ); |
| 266 | break; |
| 267 | } |
| 268 | if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, |
| 269 | &sc->sc_mmiot, &sc->sc_mmioh, NULL, &memsize) != 0) { |
| 270 | aprint_error_dev(self, "failed to map registers\n" ); |
| 271 | return; |
| 272 | } |
| 273 | |
| 274 | if (lii_reset(sc)) |
| 275 | return; |
| 276 | |
| 277 | lii_spi_configure(sc); |
| 278 | |
| 279 | if (lii_eeprom_present(sc)) |
| 280 | sc->sc_memread = lii_eeprom_read; |
| 281 | else |
| 282 | sc->sc_memread = lii_spi_read; |
| 283 | |
| 284 | if (lii_read_macaddr(sc, eaddr)) |
| 285 | return; |
| 286 | memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); |
| 287 | |
| 288 | aprint_normal_dev(self, "Ethernet address %s\n" , |
| 289 | ether_sprintf(eaddr)); |
| 290 | |
| 291 | if (pci_intr_map(pa, &ih) != 0) { |
| 292 | aprint_error_dev(self, "failed to map interrupt\n" ); |
| 293 | goto fail; |
| 294 | } |
| 295 | intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf)); |
| 296 | sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); |
| 297 | if (sc->sc_ih == NULL) { |
| 298 | aprint_error_dev(self, "failed to establish interrupt" ); |
| 299 | if (intrstr != NULL) |
| 300 | aprint_error(" at %s" , intrstr); |
| 301 | aprint_error("\n" ); |
| 302 | goto fail; |
| 303 | } |
| 304 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
| 305 | |
| 306 | if (lii_alloc_rings(sc)) |
| 307 | goto fail; |
| 308 | |
| 309 | callout_init(&sc->sc_tick_ch, 0); |
| 310 | callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); |
| 311 | |
| 312 | sc->sc_mii.mii_ifp = ifp; |
| 313 | sc->sc_mii.mii_readreg = lii_mii_readreg; |
| 314 | sc->sc_mii.mii_writereg = lii_mii_writereg; |
| 315 | sc->sc_mii.mii_statchg = lii_mii_statchg; |
| 316 | ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, |
| 317 | lii_media_status); |
| 318 | mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, |
| 319 | MII_OFFSET_ANY, 0); |
| 320 | ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); |
| 321 | |
| 322 | strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); |
| 323 | ifp->if_softc = sc; |
| 324 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
| 325 | ifp->if_ioctl = lii_ioctl; |
| 326 | ifp->if_start = lii_start; |
| 327 | ifp->if_watchdog = lii_watchdog; |
| 328 | ifp->if_init = lii_init; |
| 329 | ifp->if_stop = lii_stop; |
| 330 | IFQ_SET_READY(&ifp->if_snd); |
| 331 | |
| 332 | /* |
| 333 | * While the device does support HW VLAN tagging, there is no |
| 334 | * real point using that feature. |
| 335 | */ |
| 336 | sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; |
| 337 | |
| 338 | if_attach(ifp); |
| 339 | ether_ifattach(ifp, eaddr); |
| 340 | |
| 341 | if (pmf_device_register(self, NULL, NULL)) |
| 342 | pmf_class_network_register(self, ifp); |
| 343 | else |
| 344 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 345 | |
| 346 | return; |
| 347 | |
| 348 | fail: |
| 349 | if (sc->sc_ih != NULL) { |
| 350 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
| 351 | sc->sc_ih = NULL; |
| 352 | } |
| 353 | if (memsize) |
| 354 | bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, memsize); |
| 355 | } |
| 356 | |
| 357 | static int |
| 358 | lii_reset(struct lii_softc *sc) |
| 359 | { |
| 360 | int i; |
| 361 | |
| 362 | DPRINTF(("lii_reset\n" )); |
| 363 | |
| 364 | AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); |
| 365 | DELAY(1000); |
| 366 | |
| 367 | for (i = 0; i < 10; ++i) { |
| 368 | if (AT_READ_4(sc, ATL2_BIS) == 0) |
| 369 | break; |
| 370 | DELAY(1000); |
| 371 | } |
| 372 | |
| 373 | if (i == 10) { |
| 374 | aprint_error_dev(sc->sc_dev, "reset failed\n" ); |
| 375 | return 1; |
| 376 | } |
| 377 | |
| 378 | AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); |
| 379 | DELAY(10); |
| 380 | |
| 381 | /* Init PCI-Express module */ |
| 382 | /* Magic Numbers Warning */ |
| 383 | AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); |
| 384 | AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static bool |
| 390 | lii_eeprom_present(struct lii_softc *sc) |
| 391 | { |
| 392 | /* |
| 393 | * The Linux driver does this, but then it has a very weird way of |
| 394 | * checking whether the PCI configuration space exposes the Vital |
| 395 | * Product Data capability, so maybe it's not really needed. |
| 396 | */ |
| 397 | |
| 398 | #ifdef weirdloonix |
| 399 | uint32_t val; |
| 400 | |
| 401 | val = AT_READ_4(sc, ATL2_SFC); |
| 402 | if (val & SFC_EN_VPD) |
| 403 | AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); |
| 404 | #endif |
| 405 | |
| 406 | return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, |
| 407 | NULL, NULL) == 1; |
| 408 | } |
| 409 | |
| 410 | static int |
| 411 | lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) |
| 412 | { |
| 413 | int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); |
| 414 | |
| 415 | DPRINTF(("lii_eeprom_read(%x) = %x\n" , reg, *val)); |
| 416 | |
| 417 | return r; |
| 418 | } |
| 419 | |
| 420 | static void |
| 421 | lii_spi_configure(struct lii_softc *sc) |
| 422 | { |
| 423 | /* |
| 424 | * We don't offer a way to configure the SPI Flash vendor parameter, so |
| 425 | * the table is given for reference |
| 426 | */ |
| 427 | static const struct lii_spi_flash_vendor { |
| 428 | const char *sfv_name; |
| 429 | const uint8_t sfv_opcodes[9]; |
| 430 | } lii_sfv[] = { |
| 431 | { "Atmel" , { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, |
| 432 | { "SST" , { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, |
| 433 | { "ST" , { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, |
| 434 | }; |
| 435 | #define SF_OPCODE_WRSR 0 |
| 436 | #define SF_OPCODE_READ 1 |
| 437 | #define SF_OPCODE_PRGM 2 |
| 438 | #define SF_OPCODE_WREN 3 |
| 439 | #define SF_OPCODE_WRDI 4 |
| 440 | #define SF_OPCODE_RDSR 5 |
| 441 | #define SF_OPCODE_RDID 6 |
| 442 | #define SF_OPCODE_SECT_ER 7 |
| 443 | #define SF_OPCODE_CHIP_ER 8 |
| 444 | |
| 445 | #define SF_DEFAULT_VENDOR 0 |
| 446 | static const uint8_t vendor = SF_DEFAULT_VENDOR; |
| 447 | |
| 448 | /* |
| 449 | * Why isn't WRDI used? Heck if I know. |
| 450 | */ |
| 451 | |
| 452 | AT_WRITE_1(sc, ATL2_SFOP_WRSR, |
| 453 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); |
| 454 | AT_WRITE_1(sc, ATL2_SFOP_READ, |
| 455 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); |
| 456 | AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, |
| 457 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); |
| 458 | AT_WRITE_1(sc, ATL2_SFOP_WREN, |
| 459 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); |
| 460 | AT_WRITE_1(sc, ATL2_SFOP_RDSR, |
| 461 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); |
| 462 | AT_WRITE_1(sc, ATL2_SFOP_RDID, |
| 463 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); |
| 464 | AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, |
| 465 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); |
| 466 | AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, |
| 467 | lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); |
| 468 | } |
| 469 | |
| 470 | #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ |
| 471 | ( (((cssetup) & SFC_CS_SETUP_MASK) \ |
| 472 | << SFC_CS_SETUP_SHIFT) \ |
| 473 | | (((clkhi) & SFC_CLK_HI_MASK) \ |
| 474 | << SFC_CLK_HI_SHIFT) \ |
| 475 | | (((clklo) & SFC_CLK_LO_MASK) \ |
| 476 | << SFC_CLK_LO_SHIFT) \ |
| 477 | | (((cshold) & SFC_CS_HOLD_MASK) \ |
| 478 | << SFC_CS_HOLD_SHIFT) \ |
| 479 | | (((cshi) & SFC_CS_HI_MASK) \ |
| 480 | << SFC_CS_HI_SHIFT) \ |
| 481 | | (((ins) & SFC_INS_MASK) \ |
| 482 | << SFC_INS_SHIFT)) |
| 483 | |
| 484 | /* Magic settings from the Linux driver */ |
| 485 | |
| 486 | #define CUSTOM_SPI_CS_SETUP 2 |
| 487 | #define CUSTOM_SPI_CLK_HI 2 |
| 488 | #define CUSTOM_SPI_CLK_LO 2 |
| 489 | #define CUSTOM_SPI_CS_HOLD 2 |
| 490 | #define CUSTOM_SPI_CS_HI 3 |
| 491 | |
| 492 | static int |
| 493 | lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) |
| 494 | { |
| 495 | uint32_t v; |
| 496 | int i; |
| 497 | |
| 498 | AT_WRITE_4(sc, ATL2_SF_DATA, 0); |
| 499 | AT_WRITE_4(sc, ATL2_SF_ADDR, reg); |
| 500 | |
| 501 | v = SFC_WAIT_READY | |
| 502 | MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, |
| 503 | CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); |
| 504 | |
| 505 | AT_WRITE_4(sc, ATL2_SFC, v); |
| 506 | v |= SFC_START; |
| 507 | AT_WRITE_4(sc, ATL2_SFC, v); |
| 508 | |
| 509 | for (i = 0; i < 10; ++i) { |
| 510 | DELAY(1000); |
| 511 | if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) |
| 512 | break; |
| 513 | } |
| 514 | if (i == 10) |
| 515 | return EBUSY; |
| 516 | |
| 517 | *val = AT_READ_4(sc, ATL2_SF_DATA); |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | static int |
| 522 | lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) |
| 523 | { |
| 524 | uint32_t offset = 0x100; |
| 525 | uint32_t val, val1, addr0 = 0, addr1 = 0; |
| 526 | uint8_t found = 0; |
| 527 | |
| 528 | while ((*sc->sc_memread)(sc, offset, &val) == 0) { |
| 529 | offset += 4; |
| 530 | |
| 531 | /* Each chunk of data starts with a signature */ |
| 532 | if ((val & 0xff) != 0x5a) |
| 533 | break; |
| 534 | if ((*sc->sc_memread)(sc, offset, &val1)) |
| 535 | break; |
| 536 | |
| 537 | offset += 4; |
| 538 | |
| 539 | val >>= 16; |
| 540 | switch (val) { |
| 541 | case ATL2_MAC_ADDR_0: |
| 542 | addr0 = val1; |
| 543 | ++found; |
| 544 | break; |
| 545 | case ATL2_MAC_ADDR_1: |
| 546 | addr1 = val1; |
| 547 | ++found; |
| 548 | break; |
| 549 | default: |
| 550 | continue; |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | if (found < 2) { |
| 555 | /* Make sure we try the BIOS method before giving up */ |
| 556 | addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); |
| 557 | addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); |
| 558 | if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || |
| 559 | (addr0 == 0 && (addr1 & 0xffff) == 0)) { |
| 560 | aprint_error_dev(sc->sc_dev, |
| 561 | "error reading MAC address\n" ); |
| 562 | return 1; |
| 563 | } |
| 564 | } else { |
| 565 | addr0 = htole32(addr0); |
| 566 | addr1 = htole32(addr1); |
| 567 | } |
| 568 | |
| 569 | ea[0] = (addr1 & 0x0000ff00) >> 8; |
| 570 | ea[1] = (addr1 & 0x000000ff); |
| 571 | ea[2] = (addr0 & 0xff000000) >> 24; |
| 572 | ea[3] = (addr0 & 0x00ff0000) >> 16; |
| 573 | ea[4] = (addr0 & 0x0000ff00) >> 8; |
| 574 | ea[5] = (addr0 & 0x000000ff); |
| 575 | |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static int |
| 580 | lii_mii_readreg(device_t dev, int phy, int reg) |
| 581 | { |
| 582 | struct lii_softc *sc = device_private(dev); |
| 583 | uint32_t val; |
| 584 | int i; |
| 585 | |
| 586 | val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; |
| 587 | |
| 588 | val |= MDIOC_START | MDIOC_SUP_PREAMBLE; |
| 589 | val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; |
| 590 | |
| 591 | val |= MDIOC_READ; |
| 592 | |
| 593 | AT_WRITE_4(sc, ATL2_MDIOC, val); |
| 594 | |
| 595 | for (i = 0; i < MDIO_WAIT_TIMES; ++i) { |
| 596 | DELAY(2); |
| 597 | val = AT_READ_4(sc, ATL2_MDIOC); |
| 598 | if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) |
| 599 | break; |
| 600 | } |
| 601 | |
| 602 | if (i == MDIO_WAIT_TIMES) |
| 603 | aprint_error_dev(dev, "timeout reading PHY %d reg %d\n" , phy, |
| 604 | reg); |
| 605 | |
| 606 | return (val & 0x0000ffff); |
| 607 | } |
| 608 | |
| 609 | static void |
| 610 | lii_mii_writereg(device_t dev, int phy, int reg, int data) |
| 611 | { |
| 612 | struct lii_softc *sc = device_private(dev); |
| 613 | uint32_t val; |
| 614 | int i; |
| 615 | |
| 616 | val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; |
| 617 | val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; |
| 618 | |
| 619 | val |= MDIOC_START | MDIOC_SUP_PREAMBLE; |
| 620 | val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; |
| 621 | |
| 622 | /* val |= MDIOC_WRITE; */ |
| 623 | |
| 624 | AT_WRITE_4(sc, ATL2_MDIOC, val); |
| 625 | |
| 626 | for (i = 0; i < MDIO_WAIT_TIMES; ++i) { |
| 627 | DELAY(2); |
| 628 | val = AT_READ_4(sc, ATL2_MDIOC); |
| 629 | if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) |
| 630 | break; |
| 631 | } |
| 632 | |
| 633 | if (i == MDIO_WAIT_TIMES) |
| 634 | aprint_error_dev(dev, "timeout writing PHY %d reg %d\n" , phy, |
| 635 | reg); |
| 636 | } |
| 637 | |
| 638 | static void |
| 639 | lii_mii_statchg(struct ifnet *ifp) |
| 640 | { |
| 641 | struct lii_softc *sc = ifp->if_softc; |
| 642 | uint32_t val; |
| 643 | |
| 644 | DPRINTF(("lii_mii_statchg\n" )); |
| 645 | |
| 646 | val = AT_READ_4(sc, ATL2_MACC); |
| 647 | |
| 648 | if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) |
| 649 | val |= MACC_FDX; |
| 650 | else |
| 651 | val &= ~MACC_FDX; |
| 652 | |
| 653 | AT_WRITE_4(sc, ATL2_MACC, val); |
| 654 | } |
| 655 | |
| 656 | static int |
| 657 | lii_media_change(struct ifnet *ifp) |
| 658 | { |
| 659 | struct lii_softc *sc = ifp->if_softc; |
| 660 | |
| 661 | DPRINTF(("lii_media_change\n" )); |
| 662 | |
| 663 | if (ifp->if_flags & IFF_UP) |
| 664 | mii_mediachg(&sc->sc_mii); |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static void |
| 669 | lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) |
| 670 | { |
| 671 | struct lii_softc *sc = ifp->if_softc; |
| 672 | |
| 673 | DPRINTF(("lii_media_status\n" )); |
| 674 | |
| 675 | mii_pollstat(&sc->sc_mii); |
| 676 | imr->ifm_status = sc->sc_mii.mii_media_status; |
| 677 | imr->ifm_active = sc->sc_mii.mii_media_active; |
| 678 | } |
| 679 | |
| 680 | static int |
| 681 | lii_init(struct ifnet *ifp) |
| 682 | { |
| 683 | struct lii_softc *sc = ifp->if_softc; |
| 684 | uint32_t val; |
| 685 | int error; |
| 686 | |
| 687 | DPRINTF(("lii_init\n" )); |
| 688 | |
| 689 | lii_stop(ifp, 0); |
| 690 | |
| 691 | memset(sc->sc_ring, 0, sc->sc_ringsize); |
| 692 | |
| 693 | /* Disable all interrupts */ |
| 694 | AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); |
| 695 | |
| 696 | /* XXX endianness */ |
| 697 | AT_WRITE_4(sc, ATL2_MAC_ADDR_0, |
| 698 | sc->sc_eaddr[2] << 24 | |
| 699 | sc->sc_eaddr[3] << 16 | |
| 700 | sc->sc_eaddr[4] << 8 | |
| 701 | sc->sc_eaddr[5]); |
| 702 | AT_WRITE_4(sc, ATL2_MAC_ADDR_1, |
| 703 | sc->sc_eaddr[0] << 8 | |
| 704 | sc->sc_eaddr[1]); |
| 705 | |
| 706 | AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); |
| 707 | /* XXX |
| 708 | sc->sc_ringmap->dm_segs[0].ds_addr >> 32); |
| 709 | */ |
| 710 | AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, |
| 711 | (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) |
| 712 | + AT_RXD_PADDING); |
| 713 | AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, |
| 714 | sc->sc_txsp & 0xffffffff); |
| 715 | AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, |
| 716 | sc->sc_txdp & 0xffffffff); |
| 717 | |
| 718 | AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); |
| 719 | AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); |
| 720 | AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); |
| 721 | |
| 722 | /* |
| 723 | * Inter Paket Gap Time = 0x60 (IPGT) |
| 724 | * Minimum inter-frame gap for RX = 0x50 (MIFG) |
| 725 | * 64-bit Carrier-Sense window = 0x40 (IPGR1) |
| 726 | * 96-bit IPG window = 0x60 (IPGR2) |
| 727 | */ |
| 728 | AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); |
| 729 | |
| 730 | /* |
| 731 | * Collision window = 0x37 (LCOL) |
| 732 | * Maximum # of retrans = 0xf (RETRY) |
| 733 | * Maximum binary expansion # = 0xa (ABEBT) |
| 734 | * IPG to start jam = 0x7 (JAMIPG) |
| 735 | */ |
| 736 | AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | |
| 737 | MHDC_EXC_DEF_EN); |
| 738 | |
| 739 | /* 100 means 200us */ |
| 740 | AT_WRITE_2(sc, ATL2_IMTIV, 100); |
| 741 | AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); |
| 742 | |
| 743 | /* 500000 means 100ms */ |
| 744 | AT_WRITE_2(sc, ATL2_IALTIV, 50000); |
| 745 | |
| 746 | AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN |
| 747 | + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); |
| 748 | |
| 749 | /* unit unknown for TX cur-through threshold */ |
| 750 | AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); |
| 751 | |
| 752 | AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); |
| 753 | AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); |
| 754 | |
| 755 | sc->sc_rxcur = 0; |
| 756 | sc->sc_txs_cur = sc->sc_txs_ack = 0; |
| 757 | sc->sc_txd_cur = sc->sc_txd_ack = 0; |
| 758 | sc->sc_free_tx_slots = true; |
| 759 | AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); |
| 760 | AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); |
| 761 | |
| 762 | AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); |
| 763 | AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); |
| 764 | |
| 765 | AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); |
| 766 | |
| 767 | error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); |
| 768 | AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); |
| 769 | AT_WRITE_4(sc, ATL2_ISR, 0); |
| 770 | if (error) { |
| 771 | aprint_error_dev(sc->sc_dev, "init failed\n" ); |
| 772 | goto out; |
| 773 | } |
| 774 | |
| 775 | lii_setmulti(sc); |
| 776 | |
| 777 | val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; |
| 778 | |
| 779 | val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | |
| 780 | MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | |
| 781 | MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; |
| 782 | |
| 783 | if (ifp->if_flags & IFF_PROMISC) |
| 784 | val |= MACC_PROMISC_EN; |
| 785 | else if (ifp->if_flags & IFF_ALLMULTI) |
| 786 | val |= MACC_ALLMULTI_EN; |
| 787 | |
| 788 | val |= 7 << MACC_PREAMBLE_LEN_SHIFT; |
| 789 | val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; |
| 790 | |
| 791 | AT_WRITE_4(sc, ATL2_MACC, val); |
| 792 | |
| 793 | mii_mediachg(&sc->sc_mii); |
| 794 | |
| 795 | AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); |
| 796 | |
| 797 | callout_schedule(&sc->sc_tick_ch, hz); |
| 798 | |
| 799 | ifp->if_flags |= IFF_RUNNING; |
| 800 | ifp->if_flags &= ~IFF_OACTIVE; |
| 801 | |
| 802 | out: |
| 803 | return error; |
| 804 | } |
| 805 | |
| 806 | static void |
| 807 | lii_tx_put(struct lii_softc *sc, struct mbuf *m) |
| 808 | { |
| 809 | int left; |
| 810 | struct tx_pkt_header *tph = |
| 811 | (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); |
| 812 | |
| 813 | memset(tph, 0, sizeof *tph); |
| 814 | tph->txph_size = m->m_pkthdr.len; |
| 815 | |
| 816 | sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; |
| 817 | |
| 818 | /* |
| 819 | * We already know we have enough space, so if there is a part of the |
| 820 | * space ahead of txd_cur that is active, it doesn't matter because |
| 821 | * left will be large enough even without it. |
| 822 | */ |
| 823 | left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; |
| 824 | |
| 825 | if (left > m->m_pkthdr.len) { |
| 826 | m_copydata(m, 0, m->m_pkthdr.len, |
| 827 | sc->sc_txdbase + sc->sc_txd_cur); |
| 828 | sc->sc_txd_cur += m->m_pkthdr.len; |
| 829 | } else { |
| 830 | m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); |
| 831 | m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); |
| 832 | sc->sc_txd_cur = m->m_pkthdr.len - left; |
| 833 | } |
| 834 | |
| 835 | /* Round to a 32-bit boundary */ |
| 836 | sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; |
| 837 | if (sc->sc_txd_cur == sc->sc_txd_ack) |
| 838 | sc->sc_free_tx_slots = false; |
| 839 | } |
| 840 | |
| 841 | static int |
| 842 | lii_free_tx_space(struct lii_softc *sc) |
| 843 | { |
| 844 | int space; |
| 845 | |
| 846 | if (sc->sc_txd_cur >= sc->sc_txd_ack) |
| 847 | space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + |
| 848 | sc->sc_txd_ack; |
| 849 | else |
| 850 | space = sc->sc_txd_ack - sc->sc_txd_cur; |
| 851 | |
| 852 | /* Account for the tx_pkt_header */ |
| 853 | return (space - 4); |
| 854 | } |
| 855 | |
| 856 | static void |
| 857 | lii_start(struct ifnet *ifp) |
| 858 | { |
| 859 | struct lii_softc *sc = ifp->if_softc; |
| 860 | struct mbuf *m0; |
| 861 | |
| 862 | DPRINTF(("lii_start\n" )); |
| 863 | |
| 864 | if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) |
| 865 | return; |
| 866 | |
| 867 | for (;;) { |
| 868 | IFQ_POLL(&ifp->if_snd, m0); |
| 869 | if (m0 == NULL) |
| 870 | break; |
| 871 | |
| 872 | if (!sc->sc_free_tx_slots || |
| 873 | lii_free_tx_space(sc) < m0->m_pkthdr.len) { |
| 874 | ifp->if_flags |= IFF_OACTIVE; |
| 875 | break; |
| 876 | } |
| 877 | |
| 878 | lii_tx_put(sc, m0); |
| 879 | |
| 880 | DPRINTF(("lii_start: put %d\n" , sc->sc_txs_cur)); |
| 881 | |
| 882 | sc->sc_txs[sc->sc_txs_cur].txps_update = 0; |
| 883 | sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; |
| 884 | if (sc->sc_txs_cur == sc->sc_txs_ack) |
| 885 | sc->sc_free_tx_slots = false; |
| 886 | |
| 887 | AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); |
| 888 | |
| 889 | IFQ_DEQUEUE(&ifp->if_snd, m0); |
| 890 | |
| 891 | bpf_mtap(ifp, m0); |
| 892 | m_freem(m0); |
| 893 | } |
| 894 | } |
| 895 | |
| 896 | static void |
| 897 | lii_stop(struct ifnet *ifp, int disable) |
| 898 | { |
| 899 | struct lii_softc *sc = ifp->if_softc; |
| 900 | |
| 901 | callout_stop(&sc->sc_tick_ch); |
| 902 | |
| 903 | ifp->if_timer = 0; |
| 904 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
| 905 | |
| 906 | mii_down(&sc->sc_mii); |
| 907 | |
| 908 | lii_reset(sc); |
| 909 | |
| 910 | AT_WRITE_4(sc, ATL2_IMR, 0); |
| 911 | } |
| 912 | |
| 913 | static int |
| 914 | lii_intr(void *v) |
| 915 | { |
| 916 | struct lii_softc *sc = v; |
| 917 | uint32_t status; |
| 918 | |
| 919 | status = AT_READ_4(sc, ATL2_ISR); |
| 920 | if (status == 0) |
| 921 | return 0; |
| 922 | |
| 923 | DPRINTF(("lii_intr (%x)\n" , status)); |
| 924 | |
| 925 | /* Clear the interrupt and disable them */ |
| 926 | AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); |
| 927 | |
| 928 | if (status & (ISR_PHY | ISR_MANUAL)) { |
| 929 | /* Ack PHY interrupt. Magic register */ |
| 930 | if (status & ISR_PHY) |
| 931 | (void)lii_mii_readreg(sc->sc_dev, 1, 19); |
| 932 | mii_mediachg(&sc->sc_mii); |
| 933 | } |
| 934 | |
| 935 | if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { |
| 936 | lii_init(&sc->sc_ec.ec_if); |
| 937 | return 1; |
| 938 | } |
| 939 | |
| 940 | if (status & ISR_RX_EVENT) { |
| 941 | #ifdef LII_DEBUG |
| 942 | if (!(status & ISR_RS_UPDATE)) |
| 943 | printf("rxintr %08x\n" , status); |
| 944 | #endif |
| 945 | lii_rxintr(sc); |
| 946 | } |
| 947 | |
| 948 | if (status & ISR_TX_EVENT) |
| 949 | lii_txintr(sc); |
| 950 | |
| 951 | /* Re-enable interrupts */ |
| 952 | AT_WRITE_4(sc, ATL2_ISR, 0); |
| 953 | |
| 954 | return 1; |
| 955 | } |
| 956 | |
| 957 | static void |
| 958 | lii_rxintr(struct lii_softc *sc) |
| 959 | { |
| 960 | struct ifnet *ifp = &sc->sc_ec.ec_if; |
| 961 | struct rx_pkt *rxp; |
| 962 | struct mbuf *m; |
| 963 | uint16_t size; |
| 964 | |
| 965 | DPRINTF(("lii_rxintr\n" )); |
| 966 | |
| 967 | for (;;) { |
| 968 | rxp = &sc->sc_rxp[sc->sc_rxcur]; |
| 969 | if (rxp->rxp_update == 0) |
| 970 | break; |
| 971 | |
| 972 | DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n" , sc->sc_rxcur, |
| 973 | rxp->rxp_size, rxp->rxp_flags)); |
| 974 | sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; |
| 975 | rxp->rxp_update = 0; |
| 976 | if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { |
| 977 | ++ifp->if_ierrors; |
| 978 | continue; |
| 979 | } |
| 980 | |
| 981 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
| 982 | if (m == NULL) { |
| 983 | ++ifp->if_ierrors; |
| 984 | continue; |
| 985 | } |
| 986 | size = rxp->rxp_size - ETHER_CRC_LEN; |
| 987 | if (size > MHLEN) { |
| 988 | MCLGET(m, M_DONTWAIT); |
| 989 | if ((m->m_flags & M_EXT) == 0) { |
| 990 | m_freem(m); |
| 991 | ++ifp->if_ierrors; |
| 992 | continue; |
| 993 | } |
| 994 | } |
| 995 | |
| 996 | m_set_rcvif(m, ifp); |
| 997 | /* Copy the packet withhout the FCS */ |
| 998 | m->m_pkthdr.len = m->m_len = size; |
| 999 | memcpy(mtod(m, void *), &rxp->rxp_data[0], size); |
| 1000 | ++ifp->if_ipackets; |
| 1001 | |
| 1002 | bpf_mtap(ifp, m); |
| 1003 | |
| 1004 | if_percpuq_enqueue(ifp->if_percpuq, m); |
| 1005 | } |
| 1006 | |
| 1007 | AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); |
| 1008 | } |
| 1009 | |
| 1010 | static void |
| 1011 | lii_txintr(struct lii_softc *sc) |
| 1012 | { |
| 1013 | struct ifnet *ifp = &sc->sc_ec.ec_if; |
| 1014 | struct tx_pkt_status *txs; |
| 1015 | struct tx_pkt_header *txph; |
| 1016 | |
| 1017 | DPRINTF(("lii_txintr\n" )); |
| 1018 | |
| 1019 | for (;;) { |
| 1020 | txs = &sc->sc_txs[sc->sc_txs_ack]; |
| 1021 | if (txs->txps_update == 0) |
| 1022 | break; |
| 1023 | DPRINTF(("lii_txintr: ack'd %d\n" , sc->sc_txs_ack)); |
| 1024 | sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; |
| 1025 | sc->sc_free_tx_slots = true; |
| 1026 | |
| 1027 | txs->txps_update = 0; |
| 1028 | |
| 1029 | txph = (struct tx_pkt_header *) |
| 1030 | (sc->sc_txdbase + sc->sc_txd_ack); |
| 1031 | |
| 1032 | if (txph->txph_size != txs->txps_size) |
| 1033 | aprint_error_dev(sc->sc_dev, |
| 1034 | "mismatched status and packet\n" ); |
| 1035 | /* |
| 1036 | * Move ack by the packet size, taking the packet header in |
| 1037 | * account and round to the next 32-bit boundary |
| 1038 | * (7 = sizeof(header) + 3) |
| 1039 | */ |
| 1040 | sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; |
| 1041 | sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; |
| 1042 | |
| 1043 | if (txs->txps_flags & ATL2_TXF_SUCCESS) |
| 1044 | ++ifp->if_opackets; |
| 1045 | else |
| 1046 | ++ifp->if_oerrors; |
| 1047 | ifp->if_flags &= ~IFF_OACTIVE; |
| 1048 | } |
| 1049 | |
| 1050 | if (sc->sc_free_tx_slots) |
| 1051 | lii_start(ifp); |
| 1052 | } |
| 1053 | |
| 1054 | static int |
| 1055 | lii_alloc_rings(struct lii_softc *sc) |
| 1056 | { |
| 1057 | int nsegs; |
| 1058 | bus_size_t bs; |
| 1059 | |
| 1060 | /* |
| 1061 | * We need a big chunk of DMA-friendly memory because descriptors |
| 1062 | * are not separate from data on that crappy hardware, which means |
| 1063 | * we'll have to copy data from and to that memory zone to and from |
| 1064 | * the mbufs. |
| 1065 | * |
| 1066 | * How lame is that? Using the default values from the Linux driver, |
| 1067 | * we allocate space for receiving up to 64 full-size Ethernet frames, |
| 1068 | * and only 8kb for transmitting up to 64 Ethernet frames. |
| 1069 | */ |
| 1070 | |
| 1071 | sc->sc_ringsize = bs = AT_RXD_PADDING |
| 1072 | + AT_RXD_NUM * sizeof(struct rx_pkt) |
| 1073 | + AT_TXD_NUM * sizeof(struct tx_pkt_status) |
| 1074 | + AT_TXD_BUFFER_SIZE; |
| 1075 | |
| 1076 | if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), |
| 1077 | BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { |
| 1078 | aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n" ); |
| 1079 | return 1; |
| 1080 | } |
| 1081 | |
| 1082 | if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), |
| 1083 | &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { |
| 1084 | aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n" ); |
| 1085 | goto fail; |
| 1086 | } |
| 1087 | |
| 1088 | if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, |
| 1089 | (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { |
| 1090 | aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n" ); |
| 1091 | goto fail1; |
| 1092 | } |
| 1093 | |
| 1094 | if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, |
| 1095 | bs, NULL, BUS_DMA_NOWAIT) != 0) { |
| 1096 | aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n" ); |
| 1097 | goto fail2; |
| 1098 | } |
| 1099 | |
| 1100 | sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); |
| 1101 | sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING |
| 1102 | + AT_RXD_NUM * sizeof(struct rx_pkt)); |
| 1103 | sc->sc_txdbase = ((char *)sc->sc_txs) |
| 1104 | + AT_TXD_NUM * sizeof(struct tx_pkt_status); |
| 1105 | sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr |
| 1106 | + ((char *)sc->sc_txs - (char *)sc->sc_ring); |
| 1107 | sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr |
| 1108 | + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); |
| 1109 | |
| 1110 | return 0; |
| 1111 | |
| 1112 | fail2: |
| 1113 | bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); |
| 1114 | fail1: |
| 1115 | bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); |
| 1116 | fail: |
| 1117 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); |
| 1118 | return 1; |
| 1119 | } |
| 1120 | |
| 1121 | static void |
| 1122 | lii_watchdog(struct ifnet *ifp) |
| 1123 | { |
| 1124 | struct lii_softc *sc = ifp->if_softc; |
| 1125 | |
| 1126 | aprint_error_dev(sc->sc_dev, "watchdog timeout\n" ); |
| 1127 | ++ifp->if_oerrors; |
| 1128 | lii_init(ifp); |
| 1129 | } |
| 1130 | |
| 1131 | static int |
| 1132 | lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
| 1133 | { |
| 1134 | struct lii_softc *sc = ifp->if_softc; |
| 1135 | int s, error; |
| 1136 | |
| 1137 | s = splnet(); |
| 1138 | |
| 1139 | switch(cmd) { |
| 1140 | case SIOCADDMULTI: |
| 1141 | case SIOCDELMULTI: |
| 1142 | if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { |
| 1143 | if (ifp->if_flags & IFF_RUNNING) |
| 1144 | lii_setmulti(sc); |
| 1145 | error = 0; |
| 1146 | } |
| 1147 | break; |
| 1148 | case SIOCSIFMEDIA: |
| 1149 | case SIOCGIFMEDIA: |
| 1150 | error = ifmedia_ioctl(ifp, (struct ifreq *)data, |
| 1151 | &sc->sc_mii.mii_media, cmd); |
| 1152 | break; |
| 1153 | default: |
| 1154 | error = ether_ioctl(ifp, cmd, data); |
| 1155 | if (error == ENETRESET) { |
| 1156 | if (ifp->if_flags & IFF_RUNNING) |
| 1157 | lii_setmulti(sc); |
| 1158 | error = 0; |
| 1159 | } |
| 1160 | break; |
| 1161 | } |
| 1162 | |
| 1163 | splx(s); |
| 1164 | |
| 1165 | return error; |
| 1166 | } |
| 1167 | |
| 1168 | static void |
| 1169 | lii_setmulti(struct lii_softc *sc) |
| 1170 | { |
| 1171 | struct ethercom *ec = &sc->sc_ec; |
| 1172 | struct ifnet *ifp = &ec->ec_if; |
| 1173 | uint32_t mht0 = 0, mht1 = 0, crc; |
| 1174 | struct ether_multi *enm; |
| 1175 | struct ether_multistep step; |
| 1176 | |
| 1177 | /* Clear multicast hash table */ |
| 1178 | AT_WRITE_4(sc, ATL2_MHT, 0); |
| 1179 | AT_WRITE_4(sc, ATL2_MHT + 4, 0); |
| 1180 | |
| 1181 | ifp->if_flags &= ~IFF_ALLMULTI; |
| 1182 | |
| 1183 | ETHER_FIRST_MULTI(step, ec, enm); |
| 1184 | while (enm != NULL) { |
| 1185 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { |
| 1186 | ifp->if_flags |= IFF_ALLMULTI; |
| 1187 | mht0 = mht1 = 0; |
| 1188 | goto alldone; |
| 1189 | } |
| 1190 | |
| 1191 | crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); |
| 1192 | |
| 1193 | if (crc & (1 << 31)) |
| 1194 | mht1 |= (1 << ((crc >> 26) & 0x0000001f)); |
| 1195 | else |
| 1196 | mht0 |= (1 << ((crc >> 26) & 0x0000001f)); |
| 1197 | |
| 1198 | ETHER_NEXT_MULTI(step, enm); |
| 1199 | } |
| 1200 | |
| 1201 | alldone: |
| 1202 | AT_WRITE_4(sc, ATL2_MHT, mht0); |
| 1203 | AT_WRITE_4(sc, ATL2_MHT+4, mht1); |
| 1204 | } |
| 1205 | |
| 1206 | static void |
| 1207 | lii_tick(void *v) |
| 1208 | { |
| 1209 | struct lii_softc *sc = v; |
| 1210 | int s; |
| 1211 | |
| 1212 | s = splnet(); |
| 1213 | mii_tick(&sc->sc_mii); |
| 1214 | splx(s); |
| 1215 | |
| 1216 | callout_schedule(&sc->sc_tick_ch, hz); |
| 1217 | } |
| 1218 | |