| 1 | /* $NetBSD: mvsatareg.h,v 1.3 2012/08/29 16:50:10 jakllsch Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 2008 KIYOHARA Takashi |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 17 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 18 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, |
| 19 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 20 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 21 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 23 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| 24 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 25 | * POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #ifndef _MVSATAREG_H_ |
| 29 | #define _MVSATAREG_H_ |
| 30 | |
| 31 | /* |
| 32 | * SATAHC Arbiter Registers |
| 33 | */ |
| 34 | #define SATAHC_REGISTER_SIZE 0x10000 |
| 35 | #define SATAHC(hc) ((hc) * SATAHC_REGISTER_SIZE) |
| 36 | |
| 37 | #define SATAHC_C 0x000 /* Configuration */ |
| 38 | #define SATAHC_C_TIMEOUT_MASK (0xff << 0) |
| 39 | #define SATAHC_C_TIMEOUTEN (1 << 16) /* Timer Enable */ |
| 40 | #define SATAHC_C_COALDIS(p) (1 << ((p) + 24))/* Coalescing Disable*/ |
| 41 | #define SATAHC_RQOP 0x004 /* Request Queue Out-Pointer */ |
| 42 | #define SATAHC_RQIP 0x008 /* Response Queue In-Pointer */ |
| 43 | #define SATAHC_RQP_ERPQP(p, x) (((x) >> ((p) * 8)) & 0x7f) |
| 44 | #define SATAHC_ICT 0x00c /* Interrupt Coalescing Threshold */ |
| 45 | #define SATAHC_ICT_SAICOALT_MASK 0x000000ff |
| 46 | #define SATAHC_ITT 0x010 /* Interrupt Time Threshold */ |
| 47 | #define SATAHC_ITT_SAITMTH 0x00ffffff |
| 48 | #define SATAHC_IC 0x014 /* Interrupt Cause */ |
| 49 | #define SATAHC_IC_DONE(p) (1 << (p)) /* SaCrpb/DMA Done */ |
| 50 | #define SATAHC_IC_SAINTCOAL (1 << 4) /* Intr Coalescing */ |
| 51 | #define SATAHC_IC_SADEVINTERRUPT(p) (1 << ((p) + 8))/* Device Intr */ |
| 52 | |
| 53 | /* |
| 54 | * Physical Registers for Generation I |
| 55 | */ |
| 56 | #define SATAHC_I_R02(p) ((p) * 0x100 + 0x108) |
| 57 | #define SATAHC_I_PHYCONTROL(p) ((p) * 0x100 + 0x10c) |
| 58 | #define SATAHC_I_LTMODE(p) ((p) * 0x100 + 0x130) |
| 59 | #define SATAHC_I_PHYMODE(p) ((p) * 0x100 + 0x174) |
| 60 | |
| 61 | |
| 62 | /* |
| 63 | * EDMA Registers |
| 64 | */ |
| 65 | #define EDMA_REGISTERS_OFFSET 0x2000 |
| 66 | #define EDMA_REGISTERS_SIZE 0x2000 |
| 67 | |
| 68 | #define EDMA_CFG 0x000 /* Configuration */ |
| 69 | #define EDMA_CFG_RESERVED (0x1f << 0) /* Queue len ? */ |
| 70 | #define EDMA_CFG_ESATANATVCMDQUE (1 << 5) |
| 71 | #define EDMA_CFG_ERDBSZ (1 << 8) |
| 72 | #define EDMA_CFG_EQUE (1 << 9) |
| 73 | #define EDMA_CFG_ERDBSZEXT (1 << 11) |
| 74 | #define EDMA_CFG_RESERVED2 (1 << 12) |
| 75 | #define EDMA_CFG_EWRBUFFERLEN (1 << 13) |
| 76 | #define EDMA_CFG_EDEVERR (1 << 14) |
| 77 | #define EDMA_CFG_EEDMAFBS (1 << 16) |
| 78 | #define EDMA_CFG_ECUTTHROUGHEN (1 << 17) |
| 79 | #define EDMA_CFG_EEARLYCOMPLETIONEN (1 << 18) |
| 80 | #define EDMA_CFG_EEDMAQUELEN (1 << 19) |
| 81 | #define EDMA_CFG_EHOSTQUEUECACHEEN (1 << 22) |
| 82 | #define EDMA_CFG_EMASKRXPM (1 << 23) |
| 83 | #define EDMA_CFG_RESUMEDIS (1 << 24) |
| 84 | #define EDMA_CFG_EDMAFBS (1 << 26) |
| 85 | #define EDMA_T 0x004 /* Timer */ |
| 86 | #define EDMA_IEC 0x008 /* Interrupt Error Cause */ |
| 87 | #define EDMA_IEM 0x00c /* Interrupt Error Mask */ |
| 88 | #define EDMA_IE_EDEVERR (1 << 2) /* EDMA Device Error */ |
| 89 | #define EDMA_IE_EDEVDIS (1 << 3) /* EDMA Dev Disconn */ |
| 90 | #define EDMA_IE_EDEVCON (1 << 4) /* EDMA Dev Conn */ |
| 91 | #define EDMA_IE_SERRINT (1 << 5) |
| 92 | #define EDMA_IE_ESELFDIS (1 << 7) /* EDMA Self Disable */ |
| 93 | #define EDMA_IE_ETRANSINT (1 << 8) /* Transport Layer */ |
| 94 | #define EDMA_IE_EIORDYERR (1 << 12) /* EDMA IORdy Error */ |
| 95 | # define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */ |
| 96 | # define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */ |
| 97 | # define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2) |
| 98 | /* Link Layer is reset by the reception of SYNC primitive from device */ |
| 99 | # define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3) |
| 100 | /* |
| 101 | * Link state errors, coding errors, or running disparity errors occur |
| 102 | * during FIS reception. |
| 103 | */ |
| 104 | # define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */ |
| 105 | #define EDMA_IE_LINKCTLRXERR(x) ((x) << 13) /* Link Ctrl Recv Err */ |
| 106 | #define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ |
| 107 | #define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */ |
| 108 | #define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ |
| 109 | #define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */ |
| 110 | #define EDMA_REQQBAH 0x010 /* Request Queue Base Address High */ |
| 111 | #define EDMA_REQQIP 0x014 /* Request Queue In-Pointer */ |
| 112 | #define EDMA_REQQOP 0x018 /* Request Queue Out-Pointer */ |
| 113 | #define EDMA_REQQP_ERQQP_SHIFT 5 |
| 114 | #define EDMA_REQQP_ERQQP_MASK 0x000003e0 |
| 115 | #define EDMA_REQQP_ERQQBAP_MASK 0x00000c00 |
| 116 | #define EDMA_REQQP_ERQQBA_MASK 0xfffff000 |
| 117 | #define EDMA_RESQBAH 0x01c /* Response Queue Base Address High */ |
| 118 | #define EDMA_RESQIP 0x020 /* Response Queue In-Pointer */ |
| 119 | #define EDMA_RESQOP 0x024 /* Response Queue Out-Pointer */ |
| 120 | #define EDMA_RESQP_ERPQP_SHIFT 3 |
| 121 | #define EDMA_RESQP_ERPQP_MASK 0x000000f8 |
| 122 | #define EDMA_RESQP_ERPQBAP_MASK 0x00000300 |
| 123 | #define EDMA_RESQP_ERPQBA_MASK 0xfffffc00 |
| 124 | #define EDMA_CMD 0x028 /* Command */ |
| 125 | #define EDMA_CMD_EENEDMA (1 << 0) /* Enable EDMA */ |
| 126 | #define EDMA_CMD_EDSEDMA (1 << 1) /* Disable EDMA */ |
| 127 | #define EDMA_CMD_EATARST (1 << 2) /* ATA Device Reset */ |
| 128 | #define EDMA_CMD_EEDMAFRZ (1 << 4) /* EDMA Freeze */ |
| 129 | #define EDMA_TC 0x02c /* Test Control */ |
| 130 | #define EDMA_S 0x030 /* Status */ |
| 131 | #define EDMA_S_EDEVQUETAG(s) ((s) & 0x0000001f) |
| 132 | #define EDMA_S_EDEVDIR_WRITE (0 << 5) |
| 133 | #define EDMA_S_EDEVDIR_READ (1 << 5) |
| 134 | #define EDMA_S_ECACHEEMPTY (1 << 6) |
| 135 | #define EDMA_S_EDMAIDLE (1 << 7) |
| 136 | #define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8) |
| 137 | #define EDMA_S_EIOID(s) (((s) & 0x003f0000) >> 16) |
| 138 | #define EDMA_IORT 0x034 /* IORdy Timeout */ |
| 139 | #define EDMA_CDT 0x040 /* Command Delay Threshold */ |
| 140 | #define EDMA_HC 0x060 /* Halt Condition */ |
| 141 | #define EDMA_CQDCQOS(x) (0x090 + ((x) << 2) |
| 142 | /* NCQ Done/TCQ Outstanding Status */ |
| 143 | |
| 144 | /* |
| 145 | * Shadow Register Block Registers |
| 146 | */ |
| 147 | #define SHADOW_REG_BLOCK_OFFSET 0x100 |
| 148 | #define SHADOW_REG_BLOCK_SIZE 0x100 |
| 149 | |
| 150 | #define SRB_PIOD 0x000 /* PIO Data */ |
| 151 | #define SRB_FE 0x004 /* Feature/Error */ |
| 152 | #define SRB_SC 0x008 /* Sector Count */ |
| 153 | #define SRB_LBAL 0x00c /* LBA Low */ |
| 154 | #define SRB_LBAM 0x010 /* LBA Mid */ |
| 155 | #define SRB_LBAH 0x014 /* LBA High */ |
| 156 | #define SRB_H 0x018 /* Head */ |
| 157 | #define SRB_CS 0x01c /* Command/Status */ |
| 158 | #define SRB_CAS 0x020 /* Control/Alternate Status */ |
| 159 | |
| 160 | /* |
| 161 | * Basic DMA Registers |
| 162 | * Does support for this registers only 88Sx6xxx? |
| 163 | */ |
| 164 | #define DMA_C 0x224 /* Basic DMA Command */ |
| 165 | #define DMA_C_START (1 << 0) |
| 166 | #define DMA_C_READ (1 << 3) |
| 167 | #define DMA_C_DREGIONVALID (1 << 8) |
| 168 | #define DMA_C_DREGIONLAST (1 << 9) |
| 169 | #define DMA_C_CONTFROMPREV (1 << 10) |
| 170 | #define DMA_C_DRBC(n) (((n) & 0xffff) << 16) |
| 171 | #define DMA_S 0x228 /* Basic DMA Status */ |
| 172 | #define DMA_DTLBA 0x22c /* Descriptor Table Low Base Address */ |
| 173 | #define DMA_DTLBA_MASK 0xfffffff0 |
| 174 | #define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */ |
| 175 | #define DMA_DRLA 0x234 /* Data Region Low Address */ |
| 176 | #define DMA_DRHA 0x238 /* Data Region High Address */ |
| 177 | |
| 178 | /* |
| 179 | * Serial-ATA Registers |
| 180 | */ |
| 181 | #define SATA_SS 0x300 /* SStatus */ |
| 182 | #define SATA_SE 0x304 /* SError */ |
| 183 | #define SATA_SEIM 0x340 /* SError Interrupt Mask */ |
| 184 | #define SATA_SC 0x308 /* SControl */ |
| 185 | #define SATA_LTM 0x30c /* LTMode */ |
| 186 | #define SATA_PHYM3 0x310 /* PHY Mode 3 */ |
| 187 | #define SATA_PHYM4 0x314 /* PHY Mode 4 */ |
| 188 | #define SATA_PHYM1 0x32c /* PHY Mode 1 */ |
| 189 | #define SATA_PHYM2 0x330 /* PHY Mode 2 */ |
| 190 | #define SATA_BISTC 0x334 /* BIST Control */ |
| 191 | #define SATA_BISTDW1 0x338 /* BIST DW1 */ |
| 192 | #define SATA_BISTDW2 0x33c /* BIST DW2 */ |
| 193 | #define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */ |
| 194 | #define SATA_SATAICFG_REFCLKCNF_20MHZ (0 << 0) |
| 195 | #define SATA_SATAICFG_REFCLKCNF_25MHZ (1 << 0) |
| 196 | #define SATA_SATAICFG_REFCLKCNF_30MHZ (2 << 0) |
| 197 | #define SATA_SATAICFG_REFCLKCNF_40MHZ (3 << 0) |
| 198 | #define SATA_SATAICFG_REFCLKCNF_MASK (3 << 0) |
| 199 | #define SATA_SATAICFG_REFCLKDIV_1 (0 << 2) |
| 200 | #define SATA_SATAICFG_REFCLKDIV_2 (1 << 2) /* Used 20 or 25MHz */ |
| 201 | #define SATA_SATAICFG_REFCLKDIV_4 (2 << 2) /* Used 40MHz */ |
| 202 | #define SATA_SATAICFG_REFCLKDIV_3 (3 << 2) /* Used 30MHz */ |
| 203 | #define SATA_SATAICFG_REFCLKDIV_MASK (3 << 2) |
| 204 | #define SATA_SATAICFG_REFCLKFEEDDIV_50 (0 << 4) /* or 100, when Gen2En is 1 */ |
| 205 | #define SATA_SATAICFG_REFCLKFEEDDIV_60 (1 << 4) /* or 120. Used 25MHz */ |
| 206 | #define SATA_SATAICFG_REFCLKFEEDDIV_75 (2 << 4) /* or 150. Used 20MHz */ |
| 207 | #define SATA_SATAICFG_REFCLKFEEDDIV_90 (3 << 4) /* or 180 */ |
| 208 | #define SATA_SATAICFG_REFCLKFEEDDIV_MASK (3 << 4) |
| 209 | #define SATA_SATAICFG_PHYSSCEN (1 << 6) |
| 210 | #define SATA_SATAICFG_GEN2EN (1 << 7) |
| 211 | #define SATA_SATAICFG_COMMEN (1 << 8) |
| 212 | #define SATA_SATAICFG_PHYSHUTDOWN (1 << 9) |
| 213 | #define SATA_SATAICFG_TARGETMODE (1 << 10) /* 1 = Initiator */ |
| 214 | #define SATA_SATAICFG_COMCHANNEL (1 << 11) |
| 215 | #define SATA_SATAICFG_IGNOREBSY (1 << 24) |
| 216 | #define SATA_SATAICFG_LINKRSTEN (1 << 25) |
| 217 | #define SATA_SATAICFG_CMDRETXDS (1 << 26) |
| 218 | #define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */ |
| 219 | #define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */ |
| 220 | #define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */ |
| 221 | #define SATA_VU 0x35c /* Vendor Unique */ |
| 222 | #define SATA_FISC 0x360 /* FIS Configuration */ |
| 223 | #define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */ |
| 224 | #define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */ |
| 225 | #define SATA_FISC_FISWAIT4RDYEN_B2 (1 << 2) /* DMA Activate FIS */ |
| 226 | #define SATA_FISC_FISWAIT4RDYEN_B3 (1 << 3) /* DMA Setup FIS */ |
| 227 | #define SATA_FISC_FISWAIT4RDYEN_B4 (1 << 4) /* Data FIS first DW */ |
| 228 | #define SATA_FISC_FISWAIT4RDYEN_B5 (1 << 5) /* Data FIS entire FIS */ |
| 229 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B0 (1 << 8) |
| 230 | /* Device to Host FIS with <ERR> or <DF> */ |
| 231 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B1 (1 << 9) /* SDB FIS rcv with <N>bit */ |
| 232 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B2 (1 << 10) /* SDB FIS rcv with <ERR> */ |
| 233 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */ |
| 234 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B4 (1 << 12) /* PIO Setup FIS */ |
| 235 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B5 (1 << 13) /* Data FIS with Link error */ |
| 236 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B6 (1 << 14) /* Unrecognized FIS type */ |
| 237 | #define SATA_FISC_FISWAIT4HOSTRDYEN_B7 (1 << 15) /* Any FIS */ |
| 238 | #define SATA_FISC_FISDMAACTIVATESYNCRESP (1 << 16) |
| 239 | #define SATA_FISC_FISUNRECTYPECONT (1 << 17) |
| 240 | #define SATA_FISIC 0x364 /* FIS Interrupt Cause */ |
| 241 | #define SATA_FISIM 0x368 /* FIS Interrupt Mask */ |
| 242 | #define SATA_FISDW0 0x370 /* FIS DW0 */ |
| 243 | #define SATA_FISDW1 0x374 /* FIS DW1 */ |
| 244 | #define SATA_FISDW2 0x378 /* FIS DW2 */ |
| 245 | #define SATA_FISDW3 0x37c /* FIS DW3 */ |
| 246 | #define SATA_FISDW4 0x380 /* FIS DW4 */ |
| 247 | #define SATA_FISDW5 0x384 /* FIS DW5 */ |
| 248 | #define SATA_FISDW6 0x388 /* FIS DW6 */ |
| 249 | |
| 250 | |
| 251 | /* EDMA Command Request Block (CRQB) Data */ |
| 252 | struct crqb { |
| 253 | uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ |
| 254 | uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ |
| 255 | uint16_t ctrlflg; /* Control Flags */ |
| 256 | uint16_t atacommand[11]; |
| 257 | } __packed __aligned(8); |
| 258 | |
| 259 | struct crqb_gen2e { |
| 260 | uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ |
| 261 | uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ |
| 262 | uint32_t ctrlflg; /* Control Flags */ |
| 263 | uint32_t drbc; /* Data Region Byte Count */ |
| 264 | uint32_t atacommand[4]; |
| 265 | } __packed __aligned(8); |
| 266 | |
| 267 | |
| 268 | #define CRQB_CRQBL_EPRD_MASK 0xfffffff0 |
| 269 | #define CRQB_CRQBL_SDR_MASK 0xfffffffe /* Single data region mask */ |
| 270 | |
| 271 | /* Control Flags */ |
| 272 | #define CRQB_CDIR_WRITE (0 << 0) |
| 273 | #define CRQB_CDIR_READ (1 << 0) |
| 274 | #define CRQB_CDEVICEQUETAG(x) (((x) & 0x1f) << 1) /* CRQB Dev Queue Tag */ |
| 275 | #define CRQB_CHOSTQUETAG(x) (((x) & 0x7f) << 1) /* CRQB Host Q Tag */ |
| 276 | #define CRQB_CPMPORT(x) (((x) & 0xf) << 12) /* PM Port Transmit */ |
| 277 | #define CRQB_CPRDMODE_EPRD (0 << 16) /* PRD table */ |
| 278 | #define CRQB_CPRDMODE_SDR (1 << 16) /* Single data region */ |
| 279 | #define CRQB_CHOSTQUETAG_GEN2(x) (((x) & 0x7f) << 17) /* CRQB Host Q Tag G2 */ |
| 280 | |
| 281 | /* Data Region Byte Count */ |
| 282 | #define CRQB_CDRBC(x) (((x) & 0xfffe) << 0) |
| 283 | |
| 284 | #define CRQB_ATACOMMAND(reg, val) \ |
| 285 | ((reg << 8) | (val & 0xff)) |
| 286 | #define CRQB_ATACOMMAND_LAST (1 << 15) |
| 287 | #define CRQB_ATACOMMAND_REG(reg) (((reg) >> 2) + 0x10) |
| 288 | #define CRQB_ATACOMMAND_FEATURES CRQB_ATACOMMAND_REG(SRB_FE) |
| 289 | #define CRQB_ATACOMMAND_SECTORCOUNT CRQB_ATACOMMAND_REG(SRB_SC) |
| 290 | #define CRQB_ATACOMMAND_LBALOW CRQB_ATACOMMAND_REG(SRB_LBAL) |
| 291 | #define CRQB_ATACOMMAND_LBAMID CRQB_ATACOMMAND_REG(SRB_LBAM) |
| 292 | #define CRQB_ATACOMMAND_LBAHIGH CRQB_ATACOMMAND_REG(SRB_LBAH) |
| 293 | #define CRQB_ATACOMMAND_DEVICE CRQB_ATACOMMAND_REG(SRB_H) |
| 294 | #define CRQB_ATACOMMAND_COMMAND CRQB_ATACOMMAND_REG(SRB_CS) |
| 295 | |
| 296 | |
| 297 | /* EDMA Phisical Region Descriptors (ePRD) Table Data Structure */ |
| 298 | struct eprd { |
| 299 | uint32_t prdbal; /* address bits[31:1] */ |
| 300 | uint16_t bytecount; /* Byte Count */ |
| 301 | uint16_t eot; /* End Of Table */ |
| 302 | uint32_t prdbah; /* address bits[63:32] */ |
| 303 | uint32_t resv; |
| 304 | } __packed __aligned(8); |
| 305 | |
| 306 | #define EPRD_PRDBAL_MASK 0xfffffffe /* phy memory region mask */ |
| 307 | |
| 308 | #define EPRD_BYTECOUNT(x) (((x) & 0xffff) << 0) |
| 309 | #define EPRD_EOT (1 << 15) /* End Of Table */ |
| 310 | |
| 311 | |
| 312 | /* EDMA Command Response Block (CRPB) Data */ |
| 313 | struct crpb { |
| 314 | uint16_t id; /* CRPB ID */ |
| 315 | uint16_t rspflg; /* CPRB Response Flags */ |
| 316 | uint32_t ts; /* CPRB Time Stamp */ |
| 317 | } __packed __aligned(8); |
| 318 | |
| 319 | /* ID */ |
| 320 | #define CRPB_CHOSTQUETAG(x) (((x) >> 0) & 0x7f) /* CRPB Host Q Tag */ |
| 321 | |
| 322 | /* Response Flags */ |
| 323 | #define CRPB_CEDMASTS(x) (((x) >> 0) & 0x7f) /* CRPB EDMA Status */ |
| 324 | #define CRPB_CDEVSTS(x) (((x) >> 8) & 0xff) /* CRPB Device Status */ |
| 325 | |
| 326 | #endif /* _MVSATAREG_H_ */ |
| 327 | |