| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2001-2013, Intel Corporation |
| 4 | All rights reserved. |
| 5 | |
| 6 | Redistribution and use in source and binary forms, with or without |
| 7 | modification, are permitted provided that the following conditions are met: |
| 8 | |
| 9 | 1. Redistributions of source code must retain the above copyright notice, |
| 10 | this list of conditions and the following disclaimer. |
| 11 | |
| 12 | 2. Redistributions in binary form must reproduce the above copyright |
| 13 | notice, this list of conditions and the following disclaimer in the |
| 14 | documentation and/or other materials provided with the distribution. |
| 15 | |
| 16 | 3. Neither the name of the Intel Corporation nor the names of its |
| 17 | contributors may be used to endorse or promote products derived from |
| 18 | this software without specific prior written permission. |
| 19 | |
| 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 30 | POSSIBILITY OF SUCH DAMAGE. |
| 31 | |
| 32 | ******************************************************************************/ |
| 33 | /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 251964 2013-06-18 21:28:19Z jfv $*/ |
| 34 | /*$NetBSD: ixgbe_phy.c,v 1.6 2015/08/05 04:08:44 msaitoh Exp $*/ |
| 35 | |
| 36 | #include "ixgbe_api.h" |
| 37 | #include "ixgbe_common.h" |
| 38 | #include "ixgbe_phy.h" |
| 39 | |
| 40 | static void ixgbe_i2c_start(struct ixgbe_hw *hw); |
| 41 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw); |
| 42 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); |
| 43 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); |
| 44 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); |
| 45 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); |
| 46 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); |
| 47 | static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
| 48 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
| 49 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); |
| 50 | static bool ixgbe_get_i2c_data(u32 *i2cctl); |
| 51 | static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 52 | u8 *sff8472_data); |
| 53 | |
| 54 | /** |
| 55 | * ixgbe_init_phy_ops_generic - Inits PHY function ptrs |
| 56 | * @hw: pointer to the hardware structure |
| 57 | * |
| 58 | * Initialize the function pointers. |
| 59 | **/ |
| 60 | s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) |
| 61 | { |
| 62 | struct ixgbe_phy_info *phy = &hw->phy; |
| 63 | |
| 64 | DEBUGFUNC("ixgbe_init_phy_ops_generic" ); |
| 65 | |
| 66 | /* PHY */ |
| 67 | phy->ops.identify = &ixgbe_identify_phy_generic; |
| 68 | phy->ops.reset = &ixgbe_reset_phy_generic; |
| 69 | phy->ops.read_reg = &ixgbe_read_phy_reg_generic; |
| 70 | phy->ops.write_reg = &ixgbe_write_phy_reg_generic; |
| 71 | phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi; |
| 72 | phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi; |
| 73 | phy->ops.setup_link = &ixgbe_setup_phy_link_generic; |
| 74 | phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; |
| 75 | phy->ops.check_link = NULL; |
| 76 | phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; |
| 77 | phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; |
| 78 | phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; |
| 79 | phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic; |
| 80 | phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; |
| 81 | phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; |
| 82 | phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; |
| 83 | phy->ops.identify_sfp = &ixgbe_identify_module_generic; |
| 84 | phy->sfp_type = ixgbe_sfp_type_unknown; |
| 85 | phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; |
| 86 | return IXGBE_SUCCESS; |
| 87 | } |
| 88 | |
| 89 | /** |
| 90 | * ixgbe_identify_phy_generic - Get physical layer module |
| 91 | * @hw: pointer to hardware structure |
| 92 | * |
| 93 | * Determines the physical layer module found on the current adapter. |
| 94 | **/ |
| 95 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) |
| 96 | { |
| 97 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 98 | u32 phy_addr; |
| 99 | u16 ext_ability = 0; |
| 100 | |
| 101 | DEBUGFUNC("ixgbe_identify_phy_generic" ); |
| 102 | |
| 103 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 104 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { |
| 105 | if (ixgbe_validate_phy_addr(hw, phy_addr)) { |
| 106 | hw->phy.addr = phy_addr; |
| 107 | ixgbe_get_phy_id(hw); |
| 108 | hw->phy.type = |
| 109 | ixgbe_get_phy_type_from_id(hw->phy.id); |
| 110 | |
| 111 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 112 | hw->phy.ops.read_reg(hw, |
| 113 | IXGBE_MDIO_PHY_EXT_ABILITY, |
| 114 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 115 | &ext_ability); |
| 116 | if (ext_ability & |
| 117 | (IXGBE_MDIO_PHY_10GBASET_ABILITY | |
| 118 | IXGBE_MDIO_PHY_1000BASET_ABILITY)) |
| 119 | hw->phy.type = |
| 120 | ixgbe_phy_cu_unknown; |
| 121 | else |
| 122 | hw->phy.type = |
| 123 | ixgbe_phy_generic; |
| 124 | } |
| 125 | |
| 126 | status = IXGBE_SUCCESS; |
| 127 | break; |
| 128 | } |
| 129 | } |
| 130 | /* clear value if nothing found */ |
| 131 | if (status != IXGBE_SUCCESS) { |
| 132 | hw->phy.addr = 0; |
| 133 | ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, |
| 134 | "Could not identify valid PHY address" ); |
| 135 | } |
| 136 | } else { |
| 137 | status = IXGBE_SUCCESS; |
| 138 | } |
| 139 | |
| 140 | return status; |
| 141 | } |
| 142 | |
| 143 | /** |
| 144 | * ixgbe_validate_phy_addr - Determines phy address is valid |
| 145 | * @hw: pointer to hardware structure |
| 146 | * |
| 147 | **/ |
| 148 | bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) |
| 149 | { |
| 150 | u16 phy_id = 0; |
| 151 | bool valid = FALSE; |
| 152 | |
| 153 | DEBUGFUNC("ixgbe_validate_phy_addr" ); |
| 154 | |
| 155 | hw->phy.addr = phy_addr; |
| 156 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, |
| 157 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); |
| 158 | |
| 159 | if (phy_id != 0xFFFF && phy_id != 0x0) |
| 160 | valid = TRUE; |
| 161 | |
| 162 | return valid; |
| 163 | } |
| 164 | |
| 165 | /** |
| 166 | * ixgbe_get_phy_id - Get the phy type |
| 167 | * @hw: pointer to hardware structure |
| 168 | * |
| 169 | **/ |
| 170 | s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) |
| 171 | { |
| 172 | u32 status; |
| 173 | u16 phy_id_high = 0; |
| 174 | u16 phy_id_low = 0; |
| 175 | |
| 176 | DEBUGFUNC("ixgbe_get_phy_id" ); |
| 177 | |
| 178 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, |
| 179 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 180 | &phy_id_high); |
| 181 | |
| 182 | if (status == IXGBE_SUCCESS) { |
| 183 | hw->phy.id = (u32)(phy_id_high << 16); |
| 184 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, |
| 185 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 186 | &phy_id_low); |
| 187 | hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); |
| 188 | hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); |
| 189 | } |
| 190 | return status; |
| 191 | } |
| 192 | |
| 193 | /** |
| 194 | * ixgbe_get_phy_type_from_id - Get the phy type |
| 195 | * @hw: pointer to hardware structure |
| 196 | * |
| 197 | **/ |
| 198 | enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) |
| 199 | { |
| 200 | enum ixgbe_phy_type phy_type; |
| 201 | |
| 202 | DEBUGFUNC("ixgbe_get_phy_type_from_id" ); |
| 203 | |
| 204 | switch (phy_id) { |
| 205 | case TN1010_PHY_ID: |
| 206 | phy_type = ixgbe_phy_tn; |
| 207 | break; |
| 208 | case X540_PHY_ID: |
| 209 | phy_type = ixgbe_phy_aq; |
| 210 | break; |
| 211 | case QT2022_PHY_ID: |
| 212 | phy_type = ixgbe_phy_qt; |
| 213 | break; |
| 214 | case ATH_PHY_ID: |
| 215 | phy_type = ixgbe_phy_nl; |
| 216 | break; |
| 217 | default: |
| 218 | phy_type = ixgbe_phy_unknown; |
| 219 | break; |
| 220 | } |
| 221 | |
| 222 | DEBUGOUT1("phy type found is %d\n" , phy_type); |
| 223 | return phy_type; |
| 224 | } |
| 225 | |
| 226 | /** |
| 227 | * ixgbe_reset_phy_generic - Performs a PHY reset |
| 228 | * @hw: pointer to hardware structure |
| 229 | **/ |
| 230 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) |
| 231 | { |
| 232 | u32 i; |
| 233 | u16 ctrl = 0; |
| 234 | s32 status = IXGBE_SUCCESS; |
| 235 | |
| 236 | DEBUGFUNC("ixgbe_reset_phy_generic" ); |
| 237 | |
| 238 | if (hw->phy.type == ixgbe_phy_unknown) |
| 239 | status = ixgbe_identify_phy_generic(hw); |
| 240 | |
| 241 | if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) |
| 242 | goto out; |
| 243 | |
| 244 | /* Don't reset PHY if it's shut down due to overtemp. */ |
| 245 | if (!hw->phy.reset_if_overtemp && |
| 246 | (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) |
| 247 | goto out; |
| 248 | |
| 249 | /* |
| 250 | * Perform soft PHY reset to the PHY_XS. |
| 251 | * This will cause a soft reset to the PHY |
| 252 | */ |
| 253 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 254 | IXGBE_MDIO_PHY_XS_DEV_TYPE, |
| 255 | IXGBE_MDIO_PHY_XS_RESET); |
| 256 | |
| 257 | /* |
| 258 | * Poll for reset bit to self-clear indicating reset is complete. |
| 259 | * Some PHYs could take up to 3 seconds to complete and need about |
| 260 | * 1.7 usec delay after the reset is complete. |
| 261 | */ |
| 262 | for (i = 0; i < 30; i++) { |
| 263 | msec_delay(100); |
| 264 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 265 | IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); |
| 266 | if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { |
| 267 | usec_delay(2); |
| 268 | break; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { |
| 273 | status = IXGBE_ERR_RESET_FAILED; |
| 274 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
| 275 | "PHY reset polling failed to complete.\n" ); |
| 276 | } |
| 277 | |
| 278 | out: |
| 279 | return status; |
| 280 | } |
| 281 | |
| 282 | /** |
| 283 | * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without |
| 284 | * the SWFW lock |
| 285 | * @hw: pointer to hardware structure |
| 286 | * @reg_addr: 32 bit address of PHY register to read |
| 287 | * @phy_data: Pointer to read data from PHY register |
| 288 | **/ |
| 289 | s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, |
| 290 | u16 *phy_data) |
| 291 | { |
| 292 | u32 i, data, command; |
| 293 | |
| 294 | /* Setup and write the address cycle command */ |
| 295 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
| 296 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 297 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 298 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
| 299 | |
| 300 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 301 | |
| 302 | /* |
| 303 | * Check every 10 usec to see if the address cycle completed. |
| 304 | * The MDI Command bit will clear when the operation is |
| 305 | * complete |
| 306 | */ |
| 307 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
| 308 | usec_delay(10); |
| 309 | |
| 310 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 311 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 312 | break; |
| 313 | } |
| 314 | |
| 315 | |
| 316 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 317 | ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n" ); |
| 318 | return IXGBE_ERR_PHY; |
| 319 | } |
| 320 | |
| 321 | /* |
| 322 | * Address cycle complete, setup and write the read |
| 323 | * command |
| 324 | */ |
| 325 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
| 326 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 327 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 328 | (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); |
| 329 | |
| 330 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 331 | |
| 332 | /* |
| 333 | * Check every 10 usec to see if the address cycle |
| 334 | * completed. The MDI Command bit will clear when the |
| 335 | * operation is complete |
| 336 | */ |
| 337 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
| 338 | usec_delay(10); |
| 339 | |
| 340 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 341 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 342 | break; |
| 343 | } |
| 344 | |
| 345 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 346 | ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n" ); |
| 347 | return IXGBE_ERR_PHY; |
| 348 | } |
| 349 | |
| 350 | /* |
| 351 | * Read operation is complete. Get the data |
| 352 | * from MSRWD |
| 353 | */ |
| 354 | data = IXGBE_READ_REG(hw, IXGBE_MSRWD); |
| 355 | data >>= IXGBE_MSRWD_READ_DATA_SHIFT; |
| 356 | *phy_data = (u16)(data); |
| 357 | |
| 358 | return IXGBE_SUCCESS; |
| 359 | } |
| 360 | |
| 361 | /** |
| 362 | * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register |
| 363 | * using the SWFW lock - this function is needed in most cases |
| 364 | * @hw: pointer to hardware structure |
| 365 | * @reg_addr: 32 bit address of PHY register to read |
| 366 | * @phy_data: Pointer to read data from PHY register |
| 367 | **/ |
| 368 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 369 | u32 device_type, u16 *phy_data) |
| 370 | { |
| 371 | s32 status; |
| 372 | u16 gssr; |
| 373 | |
| 374 | DEBUGFUNC("ixgbe_read_phy_reg_generic" ); |
| 375 | |
| 376 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 377 | gssr = IXGBE_GSSR_PHY1_SM; |
| 378 | else |
| 379 | gssr = IXGBE_GSSR_PHY0_SM; |
| 380 | |
| 381 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { |
| 382 | status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, |
| 383 | phy_data); |
| 384 | hw->mac.ops.release_swfw_sync(hw, gssr); |
| 385 | } else { |
| 386 | status = IXGBE_ERR_SWFW_SYNC; |
| 387 | } |
| 388 | |
| 389 | return status; |
| 390 | } |
| 391 | |
| 392 | /** |
| 393 | * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register |
| 394 | * without SWFW lock |
| 395 | * @hw: pointer to hardware structure |
| 396 | * @reg_addr: 32 bit PHY register to write |
| 397 | * @device_type: 5 bit device type |
| 398 | * @phy_data: Data to write to the PHY register |
| 399 | **/ |
| 400 | s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, |
| 401 | u32 device_type, u16 phy_data) |
| 402 | { |
| 403 | u32 i, command; |
| 404 | |
| 405 | /* Put the data in the MDI single read and write data register*/ |
| 406 | IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); |
| 407 | |
| 408 | /* Setup and write the address cycle command */ |
| 409 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
| 410 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 411 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 412 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
| 413 | |
| 414 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 415 | |
| 416 | /* |
| 417 | * Check every 10 usec to see if the address cycle completed. |
| 418 | * The MDI Command bit will clear when the operation is |
| 419 | * complete |
| 420 | */ |
| 421 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
| 422 | usec_delay(10); |
| 423 | |
| 424 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 425 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 426 | break; |
| 427 | } |
| 428 | |
| 429 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 430 | ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n" ); |
| 431 | return IXGBE_ERR_PHY; |
| 432 | } |
| 433 | |
| 434 | /* |
| 435 | * Address cycle complete, setup and write the write |
| 436 | * command |
| 437 | */ |
| 438 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
| 439 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 440 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 441 | (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); |
| 442 | |
| 443 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 444 | |
| 445 | /* |
| 446 | * Check every 10 usec to see if the address cycle |
| 447 | * completed. The MDI Command bit will clear when the |
| 448 | * operation is complete |
| 449 | */ |
| 450 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
| 451 | usec_delay(10); |
| 452 | |
| 453 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 454 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 455 | break; |
| 456 | } |
| 457 | |
| 458 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 459 | ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n" ); |
| 460 | return IXGBE_ERR_PHY; |
| 461 | } |
| 462 | |
| 463 | return IXGBE_SUCCESS; |
| 464 | } |
| 465 | |
| 466 | /** |
| 467 | * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register |
| 468 | * using SWFW lock- this function is needed in most cases |
| 469 | * @hw: pointer to hardware structure |
| 470 | * @reg_addr: 32 bit PHY register to write |
| 471 | * @device_type: 5 bit device type |
| 472 | * @phy_data: Data to write to the PHY register |
| 473 | **/ |
| 474 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 475 | u32 device_type, u16 phy_data) |
| 476 | { |
| 477 | s32 status; |
| 478 | u16 gssr; |
| 479 | |
| 480 | DEBUGFUNC("ixgbe_write_phy_reg_generic" ); |
| 481 | |
| 482 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 483 | gssr = IXGBE_GSSR_PHY1_SM; |
| 484 | else |
| 485 | gssr = IXGBE_GSSR_PHY0_SM; |
| 486 | |
| 487 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { |
| 488 | status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, |
| 489 | phy_data); |
| 490 | hw->mac.ops.release_swfw_sync(hw, gssr); |
| 491 | } else { |
| 492 | status = IXGBE_ERR_SWFW_SYNC; |
| 493 | } |
| 494 | |
| 495 | return status; |
| 496 | } |
| 497 | |
| 498 | /** |
| 499 | * ixgbe_setup_phy_link_generic - Set and restart autoneg |
| 500 | * @hw: pointer to hardware structure |
| 501 | * |
| 502 | * Restart autonegotiation and PHY and waits for completion. |
| 503 | **/ |
| 504 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) |
| 505 | { |
| 506 | s32 status = IXGBE_SUCCESS; |
| 507 | u32 time_out; |
| 508 | u32 max_time_out = 10; |
| 509 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
| 510 | bool autoneg = FALSE; |
| 511 | ixgbe_link_speed speed; |
| 512 | |
| 513 | DEBUGFUNC("ixgbe_setup_phy_link_generic" ); |
| 514 | |
| 515 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); |
| 516 | |
| 517 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 518 | /* Set or unset auto-negotiation 10G advertisement */ |
| 519 | hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, |
| 520 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 521 | &autoneg_reg); |
| 522 | |
| 523 | autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; |
| 524 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
| 525 | autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; |
| 526 | |
| 527 | hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, |
| 528 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 529 | autoneg_reg); |
| 530 | } |
| 531 | |
| 532 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 533 | /* Set or unset auto-negotiation 1G advertisement */ |
| 534 | hw->phy.ops.read_reg(hw, |
| 535 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, |
| 536 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 537 | &autoneg_reg); |
| 538 | |
| 539 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; |
| 540 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) |
| 541 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; |
| 542 | |
| 543 | hw->phy.ops.write_reg(hw, |
| 544 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, |
| 545 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 546 | autoneg_reg); |
| 547 | } |
| 548 | |
| 549 | if (speed & IXGBE_LINK_SPEED_100_FULL) { |
| 550 | /* Set or unset auto-negotiation 100M advertisement */ |
| 551 | hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, |
| 552 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 553 | &autoneg_reg); |
| 554 | |
| 555 | autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | |
| 556 | IXGBE_MII_100BASE_T_ADVERTISE_HALF); |
| 557 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) |
| 558 | autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; |
| 559 | |
| 560 | hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, |
| 561 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 562 | autoneg_reg); |
| 563 | } |
| 564 | |
| 565 | /* Restart PHY autonegotiation and wait for completion */ |
| 566 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 567 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); |
| 568 | |
| 569 | autoneg_reg |= IXGBE_MII_RESTART; |
| 570 | |
| 571 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 572 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); |
| 573 | |
| 574 | /* Wait for autonegotiation to finish */ |
| 575 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 576 | usec_delay(10); |
| 577 | /* Restart PHY autonegotiation and wait for completion */ |
| 578 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, |
| 579 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 580 | &autoneg_reg); |
| 581 | |
| 582 | autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; |
| 583 | if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) |
| 584 | break; |
| 585 | } |
| 586 | |
| 587 | if (time_out == max_time_out) { |
| 588 | status = IXGBE_ERR_LINK_SETUP; |
| 589 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
| 590 | "PHY autonegotiation time out" ); |
| 591 | } |
| 592 | |
| 593 | return status; |
| 594 | } |
| 595 | |
| 596 | /** |
| 597 | * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities |
| 598 | * @hw: pointer to hardware structure |
| 599 | * @speed: new link speed |
| 600 | **/ |
| 601 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, |
| 602 | ixgbe_link_speed speed, |
| 603 | bool autoneg_wait_to_complete) |
| 604 | { |
| 605 | UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); |
| 606 | |
| 607 | DEBUGFUNC("ixgbe_setup_phy_link_speed_generic" ); |
| 608 | |
| 609 | /* |
| 610 | * Clear autoneg_advertised and set new values based on input link |
| 611 | * speed. |
| 612 | */ |
| 613 | hw->phy.autoneg_advertised = 0; |
| 614 | |
| 615 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 616 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 617 | |
| 618 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 619 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 620 | |
| 621 | if (speed & IXGBE_LINK_SPEED_100_FULL) |
| 622 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; |
| 623 | |
| 624 | /* Setup link based on the new speed settings */ |
| 625 | hw->phy.ops.setup_link(hw); |
| 626 | |
| 627 | return IXGBE_SUCCESS; |
| 628 | } |
| 629 | |
| 630 | /** |
| 631 | * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities |
| 632 | * @hw: pointer to hardware structure |
| 633 | * @speed: pointer to link speed |
| 634 | * @autoneg: boolean auto-negotiation value |
| 635 | * |
| 636 | * Determines the link capabilities by reading the AUTOC register. |
| 637 | **/ |
| 638 | s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, |
| 639 | ixgbe_link_speed *speed, |
| 640 | bool *autoneg) |
| 641 | { |
| 642 | s32 status = IXGBE_ERR_LINK_SETUP; |
| 643 | u16 speed_ability; |
| 644 | |
| 645 | DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic" ); |
| 646 | |
| 647 | *speed = 0; |
| 648 | *autoneg = TRUE; |
| 649 | |
| 650 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, |
| 651 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 652 | &speed_ability); |
| 653 | |
| 654 | if (status == IXGBE_SUCCESS) { |
| 655 | if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) |
| 656 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
| 657 | if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) |
| 658 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 659 | if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) |
| 660 | *speed |= IXGBE_LINK_SPEED_100_FULL; |
| 661 | } |
| 662 | |
| 663 | return status; |
| 664 | } |
| 665 | |
| 666 | /** |
| 667 | * ixgbe_check_phy_link_tnx - Determine link and speed status |
| 668 | * @hw: pointer to hardware structure |
| 669 | * |
| 670 | * Reads the VS1 register to determine if link is up and the current speed for |
| 671 | * the PHY. |
| 672 | **/ |
| 673 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
| 674 | bool *link_up) |
| 675 | { |
| 676 | s32 status = IXGBE_SUCCESS; |
| 677 | u32 time_out; |
| 678 | u32 max_time_out = 10; |
| 679 | u16 phy_link = 0; |
| 680 | u16 phy_speed = 0; |
| 681 | u16 phy_data = 0; |
| 682 | |
| 683 | DEBUGFUNC("ixgbe_check_phy_link_tnx" ); |
| 684 | |
| 685 | /* Initialize speed and link to default case */ |
| 686 | *link_up = FALSE; |
| 687 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 688 | |
| 689 | /* |
| 690 | * Check current speed and link status of the PHY register. |
| 691 | * This is a vendor specific register and may have to |
| 692 | * be changed for other copper PHYs. |
| 693 | */ |
| 694 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 695 | usec_delay(10); |
| 696 | status = hw->phy.ops.read_reg(hw, |
| 697 | IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, |
| 698 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, |
| 699 | &phy_data); |
| 700 | phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; |
| 701 | phy_speed = phy_data & |
| 702 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; |
| 703 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { |
| 704 | *link_up = TRUE; |
| 705 | if (phy_speed == |
| 706 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) |
| 707 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 708 | break; |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | return status; |
| 713 | } |
| 714 | |
| 715 | /** |
| 716 | * ixgbe_setup_phy_link_tnx - Set and restart autoneg |
| 717 | * @hw: pointer to hardware structure |
| 718 | * |
| 719 | * Restart autonegotiation and PHY and waits for completion. |
| 720 | **/ |
| 721 | s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) |
| 722 | { |
| 723 | s32 status = IXGBE_SUCCESS; |
| 724 | u32 time_out; |
| 725 | u32 max_time_out = 10; |
| 726 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
| 727 | bool autoneg = FALSE; |
| 728 | ixgbe_link_speed speed; |
| 729 | |
| 730 | DEBUGFUNC("ixgbe_setup_phy_link_tnx" ); |
| 731 | |
| 732 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); |
| 733 | |
| 734 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 735 | /* Set or unset auto-negotiation 10G advertisement */ |
| 736 | hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, |
| 737 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 738 | &autoneg_reg); |
| 739 | |
| 740 | autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; |
| 741 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
| 742 | autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; |
| 743 | |
| 744 | hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, |
| 745 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 746 | autoneg_reg); |
| 747 | } |
| 748 | |
| 749 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 750 | /* Set or unset auto-negotiation 1G advertisement */ |
| 751 | hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, |
| 752 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 753 | &autoneg_reg); |
| 754 | |
| 755 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; |
| 756 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) |
| 757 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; |
| 758 | |
| 759 | hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, |
| 760 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 761 | autoneg_reg); |
| 762 | } |
| 763 | |
| 764 | if (speed & IXGBE_LINK_SPEED_100_FULL) { |
| 765 | /* Set or unset auto-negotiation 100M advertisement */ |
| 766 | hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, |
| 767 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 768 | &autoneg_reg); |
| 769 | |
| 770 | autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; |
| 771 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) |
| 772 | autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; |
| 773 | |
| 774 | hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, |
| 775 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 776 | autoneg_reg); |
| 777 | } |
| 778 | |
| 779 | /* Restart PHY autonegotiation and wait for completion */ |
| 780 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 781 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); |
| 782 | |
| 783 | autoneg_reg |= IXGBE_MII_RESTART; |
| 784 | |
| 785 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 786 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); |
| 787 | |
| 788 | /* Wait for autonegotiation to finish */ |
| 789 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 790 | usec_delay(10); |
| 791 | /* Restart PHY autonegotiation and wait for completion */ |
| 792 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, |
| 793 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 794 | &autoneg_reg); |
| 795 | |
| 796 | autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; |
| 797 | if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) |
| 798 | break; |
| 799 | } |
| 800 | |
| 801 | if (time_out == max_time_out) { |
| 802 | status = IXGBE_ERR_LINK_SETUP; |
| 803 | DEBUGOUT("ixgbe_setup_phy_link_tnx: time out" ); |
| 804 | } |
| 805 | |
| 806 | return status; |
| 807 | } |
| 808 | |
| 809 | /** |
| 810 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version |
| 811 | * @hw: pointer to hardware structure |
| 812 | * @firmware_version: pointer to the PHY Firmware Version |
| 813 | **/ |
| 814 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, |
| 815 | u16 *firmware_version) |
| 816 | { |
| 817 | s32 status = IXGBE_SUCCESS; |
| 818 | |
| 819 | DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx" ); |
| 820 | |
| 821 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, |
| 822 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, |
| 823 | firmware_version); |
| 824 | |
| 825 | return status; |
| 826 | } |
| 827 | |
| 828 | /** |
| 829 | * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version |
| 830 | * @hw: pointer to hardware structure |
| 831 | * @firmware_version: pointer to the PHY Firmware Version |
| 832 | **/ |
| 833 | s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, |
| 834 | u16 *firmware_version) |
| 835 | { |
| 836 | s32 status = IXGBE_SUCCESS; |
| 837 | |
| 838 | DEBUGFUNC("ixgbe_get_phy_firmware_version_generic" ); |
| 839 | |
| 840 | status = hw->phy.ops.read_reg(hw, AQ_FW_REV, |
| 841 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, |
| 842 | firmware_version); |
| 843 | |
| 844 | return status; |
| 845 | } |
| 846 | |
| 847 | /** |
| 848 | * ixgbe_reset_phy_nl - Performs a PHY reset |
| 849 | * @hw: pointer to hardware structure |
| 850 | **/ |
| 851 | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) |
| 852 | { |
| 853 | u16 phy_offset, control, eword, edata, block_crc; |
| 854 | bool end_data = FALSE; |
| 855 | u16 list_offset, data_offset; |
| 856 | u16 phy_data = 0; |
| 857 | s32 ret_val = IXGBE_SUCCESS; |
| 858 | u32 i; |
| 859 | |
| 860 | DEBUGFUNC("ixgbe_reset_phy_nl" ); |
| 861 | |
| 862 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 863 | IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); |
| 864 | |
| 865 | /* reset the PHY and poll for completion */ |
| 866 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 867 | IXGBE_MDIO_PHY_XS_DEV_TYPE, |
| 868 | (phy_data | IXGBE_MDIO_PHY_XS_RESET)); |
| 869 | |
| 870 | for (i = 0; i < 100; i++) { |
| 871 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 872 | IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); |
| 873 | if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) |
| 874 | break; |
| 875 | msec_delay(10); |
| 876 | } |
| 877 | |
| 878 | if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { |
| 879 | DEBUGOUT("PHY reset did not complete.\n" ); |
| 880 | ret_val = IXGBE_ERR_PHY; |
| 881 | goto out; |
| 882 | } |
| 883 | |
| 884 | /* Get init offsets */ |
| 885 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 886 | &data_offset); |
| 887 | if (ret_val != IXGBE_SUCCESS) |
| 888 | goto out; |
| 889 | |
| 890 | ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); |
| 891 | data_offset++; |
| 892 | while (!end_data) { |
| 893 | /* |
| 894 | * Read control word from PHY init contents offset |
| 895 | */ |
| 896 | ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); |
| 897 | if (ret_val) |
| 898 | goto err_eeprom; |
| 899 | control = (eword & IXGBE_CONTROL_MASK_NL) >> |
| 900 | IXGBE_CONTROL_SHIFT_NL; |
| 901 | edata = eword & IXGBE_DATA_MASK_NL; |
| 902 | switch (control) { |
| 903 | case IXGBE_DELAY_NL: |
| 904 | data_offset++; |
| 905 | DEBUGOUT1("DELAY: %d MS\n" , edata); |
| 906 | msec_delay(edata); |
| 907 | break; |
| 908 | case IXGBE_DATA_NL: |
| 909 | DEBUGOUT("DATA:\n" ); |
| 910 | data_offset++; |
| 911 | ret_val = hw->eeprom.ops.read(hw, data_offset, |
| 912 | &phy_offset); |
| 913 | if (ret_val) |
| 914 | goto err_eeprom; |
| 915 | data_offset++; |
| 916 | for (i = 0; i < edata; i++) { |
| 917 | ret_val = hw->eeprom.ops.read(hw, data_offset, |
| 918 | &eword); |
| 919 | if (ret_val) |
| 920 | goto err_eeprom; |
| 921 | hw->phy.ops.write_reg(hw, phy_offset, |
| 922 | IXGBE_TWINAX_DEV, eword); |
| 923 | DEBUGOUT2("Wrote %4.4x to %4.4x\n" , eword, |
| 924 | phy_offset); |
| 925 | data_offset++; |
| 926 | phy_offset++; |
| 927 | } |
| 928 | break; |
| 929 | case IXGBE_CONTROL_NL: |
| 930 | data_offset++; |
| 931 | DEBUGOUT("CONTROL:\n" ); |
| 932 | if (edata == IXGBE_CONTROL_EOL_NL) { |
| 933 | DEBUGOUT("EOL\n" ); |
| 934 | end_data = TRUE; |
| 935 | } else if (edata == IXGBE_CONTROL_SOL_NL) { |
| 936 | DEBUGOUT("SOL\n" ); |
| 937 | } else { |
| 938 | DEBUGOUT("Bad control value\n" ); |
| 939 | ret_val = IXGBE_ERR_PHY; |
| 940 | goto out; |
| 941 | } |
| 942 | break; |
| 943 | default: |
| 944 | DEBUGOUT("Bad control type\n" ); |
| 945 | ret_val = IXGBE_ERR_PHY; |
| 946 | goto out; |
| 947 | } |
| 948 | } |
| 949 | |
| 950 | out: |
| 951 | return ret_val; |
| 952 | |
| 953 | err_eeprom: |
| 954 | ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, |
| 955 | "eeprom read at offset %d failed" , data_offset); |
| 956 | return IXGBE_ERR_PHY; |
| 957 | } |
| 958 | |
| 959 | /** |
| 960 | * ixgbe_identify_module_generic - Identifies module type |
| 961 | * @hw: pointer to hardware structure |
| 962 | * |
| 963 | * Determines HW type and calls appropriate function. |
| 964 | **/ |
| 965 | s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) |
| 966 | { |
| 967 | s32 status = IXGBE_ERR_SFP_NOT_PRESENT; |
| 968 | |
| 969 | DEBUGFUNC("ixgbe_identify_module_generic" ); |
| 970 | |
| 971 | switch (hw->mac.ops.get_media_type(hw)) { |
| 972 | case ixgbe_media_type_fiber: |
| 973 | status = ixgbe_identify_sfp_module_generic(hw); |
| 974 | break; |
| 975 | |
| 976 | |
| 977 | default: |
| 978 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 979 | status = IXGBE_ERR_SFP_NOT_PRESENT; |
| 980 | break; |
| 981 | } |
| 982 | |
| 983 | return status; |
| 984 | } |
| 985 | |
| 986 | /** |
| 987 | * ixgbe_identify_sfp_module_generic - Identifies SFP modules |
| 988 | * @hw: pointer to hardware structure |
| 989 | * |
| 990 | * Searches for and identifies the SFP module and assigns appropriate PHY type. |
| 991 | **/ |
| 992 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) |
| 993 | { |
| 994 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 995 | u32 vendor_oui = 0; |
| 996 | enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; |
| 997 | u8 identifier = 0; |
| 998 | u8 comp_codes_1g = 0; |
| 999 | u8 comp_codes_10g = 0; |
| 1000 | u8 oui_bytes[3] = {0, 0, 0}; |
| 1001 | u8 cable_tech = 0; |
| 1002 | u8 cable_spec = 0; |
| 1003 | u16 enforce_sfp = 0; |
| 1004 | |
| 1005 | DEBUGFUNC("ixgbe_identify_sfp_module_generic" ); |
| 1006 | |
| 1007 | if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { |
| 1008 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 1009 | status = IXGBE_ERR_SFP_NOT_PRESENT; |
| 1010 | goto out; |
| 1011 | } |
| 1012 | |
| 1013 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1014 | IXGBE_SFF_IDENTIFIER, |
| 1015 | &identifier); |
| 1016 | |
| 1017 | if (status != IXGBE_SUCCESS) |
| 1018 | goto err_read_i2c_eeprom; |
| 1019 | |
| 1020 | /* LAN ID is needed for sfp_type determination */ |
| 1021 | hw->mac.ops.set_lan_id(hw); |
| 1022 | |
| 1023 | if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { |
| 1024 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
| 1025 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1026 | } else { |
| 1027 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1028 | IXGBE_SFF_1GBE_COMP_CODES, |
| 1029 | &comp_codes_1g); |
| 1030 | |
| 1031 | if (status != IXGBE_SUCCESS) |
| 1032 | goto err_read_i2c_eeprom; |
| 1033 | |
| 1034 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1035 | IXGBE_SFF_10GBE_COMP_CODES, |
| 1036 | &comp_codes_10g); |
| 1037 | |
| 1038 | if (status != IXGBE_SUCCESS) |
| 1039 | goto err_read_i2c_eeprom; |
| 1040 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1041 | IXGBE_SFF_CABLE_TECHNOLOGY, |
| 1042 | &cable_tech); |
| 1043 | |
| 1044 | if (status != IXGBE_SUCCESS) |
| 1045 | goto err_read_i2c_eeprom; |
| 1046 | |
| 1047 | /* ID Module |
| 1048 | * ========= |
| 1049 | * 0 SFP_DA_CU |
| 1050 | * 1 SFP_SR |
| 1051 | * 2 SFP_LR |
| 1052 | * 3 SFP_DA_CORE0 - 82599-specific |
| 1053 | * 4 SFP_DA_CORE1 - 82599-specific |
| 1054 | * 5 SFP_SR/LR_CORE0 - 82599-specific |
| 1055 | * 6 SFP_SR/LR_CORE1 - 82599-specific |
| 1056 | * 7 SFP_act_lmt_DA_CORE0 - 82599-specific |
| 1057 | * 8 SFP_act_lmt_DA_CORE1 - 82599-specific |
| 1058 | * 9 SFP_1g_cu_CORE0 - 82599-specific |
| 1059 | * 10 SFP_1g_cu_CORE1 - 82599-specific |
| 1060 | * 11 SFP_1g_sx_CORE0 - 82599-specific |
| 1061 | * 12 SFP_1g_sx_CORE1 - 82599-specific |
| 1062 | */ |
| 1063 | if (hw->mac.type == ixgbe_mac_82598EB) { |
| 1064 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
| 1065 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; |
| 1066 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 1067 | hw->phy.sfp_type = ixgbe_sfp_type_sr; |
| 1068 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 1069 | hw->phy.sfp_type = ixgbe_sfp_type_lr; |
| 1070 | else |
| 1071 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
| 1072 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
| 1073 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { |
| 1074 | if (hw->bus.lan_id == 0) |
| 1075 | hw->phy.sfp_type = |
| 1076 | ixgbe_sfp_type_da_cu_core0; |
| 1077 | else |
| 1078 | hw->phy.sfp_type = |
| 1079 | ixgbe_sfp_type_da_cu_core1; |
| 1080 | } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { |
| 1081 | hw->phy.ops.read_i2c_eeprom( |
| 1082 | hw, IXGBE_SFF_CABLE_SPEC_COMP, |
| 1083 | &cable_spec); |
| 1084 | if (cable_spec & |
| 1085 | IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { |
| 1086 | if (hw->bus.lan_id == 0) |
| 1087 | hw->phy.sfp_type = |
| 1088 | ixgbe_sfp_type_da_act_lmt_core0; |
| 1089 | else |
| 1090 | hw->phy.sfp_type = |
| 1091 | ixgbe_sfp_type_da_act_lmt_core1; |
| 1092 | } else { |
| 1093 | hw->phy.sfp_type = |
| 1094 | ixgbe_sfp_type_unknown; |
| 1095 | } |
| 1096 | } else if (comp_codes_10g & |
| 1097 | (IXGBE_SFF_10GBASESR_CAPABLE | |
| 1098 | IXGBE_SFF_10GBASELR_CAPABLE)) { |
| 1099 | if (hw->bus.lan_id == 0) |
| 1100 | hw->phy.sfp_type = |
| 1101 | ixgbe_sfp_type_srlr_core0; |
| 1102 | else |
| 1103 | hw->phy.sfp_type = |
| 1104 | ixgbe_sfp_type_srlr_core1; |
| 1105 | } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { |
| 1106 | if (hw->bus.lan_id == 0) |
| 1107 | hw->phy.sfp_type = |
| 1108 | ixgbe_sfp_type_1g_cu_core0; |
| 1109 | else |
| 1110 | hw->phy.sfp_type = |
| 1111 | ixgbe_sfp_type_1g_cu_core1; |
| 1112 | } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { |
| 1113 | if (hw->bus.lan_id == 0) |
| 1114 | hw->phy.sfp_type = |
| 1115 | ixgbe_sfp_type_1g_sx_core0; |
| 1116 | else |
| 1117 | hw->phy.sfp_type = |
| 1118 | ixgbe_sfp_type_1g_sx_core1; |
| 1119 | } else { |
| 1120 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
| 1121 | } |
| 1122 | } |
| 1123 | |
| 1124 | if (hw->phy.sfp_type != stored_sfp_type) |
| 1125 | hw->phy.sfp_setup_needed = TRUE; |
| 1126 | |
| 1127 | /* Determine if the SFP+ PHY is dual speed or not. */ |
| 1128 | hw->phy.multispeed_fiber = FALSE; |
| 1129 | if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && |
| 1130 | (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || |
| 1131 | ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && |
| 1132 | (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) |
| 1133 | hw->phy.multispeed_fiber = TRUE; |
| 1134 | |
| 1135 | /* Determine PHY vendor */ |
| 1136 | if (hw->phy.type != ixgbe_phy_nl) { |
| 1137 | hw->phy.id = identifier; |
| 1138 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1139 | IXGBE_SFF_VENDOR_OUI_BYTE0, |
| 1140 | &oui_bytes[0]); |
| 1141 | |
| 1142 | if (status != IXGBE_SUCCESS) |
| 1143 | goto err_read_i2c_eeprom; |
| 1144 | |
| 1145 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1146 | IXGBE_SFF_VENDOR_OUI_BYTE1, |
| 1147 | &oui_bytes[1]); |
| 1148 | |
| 1149 | if (status != IXGBE_SUCCESS) |
| 1150 | goto err_read_i2c_eeprom; |
| 1151 | |
| 1152 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 1153 | IXGBE_SFF_VENDOR_OUI_BYTE2, |
| 1154 | &oui_bytes[2]); |
| 1155 | |
| 1156 | if (status != IXGBE_SUCCESS) |
| 1157 | goto err_read_i2c_eeprom; |
| 1158 | |
| 1159 | vendor_oui = |
| 1160 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | |
| 1161 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | |
| 1162 | (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); |
| 1163 | |
| 1164 | switch (vendor_oui) { |
| 1165 | case IXGBE_SFF_VENDOR_OUI_TYCO: |
| 1166 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
| 1167 | hw->phy.type = |
| 1168 | ixgbe_phy_sfp_passive_tyco; |
| 1169 | break; |
| 1170 | case IXGBE_SFF_VENDOR_OUI_FTL: |
| 1171 | if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
| 1172 | hw->phy.type = ixgbe_phy_sfp_ftl_active; |
| 1173 | else |
| 1174 | hw->phy.type = ixgbe_phy_sfp_ftl; |
| 1175 | break; |
| 1176 | case IXGBE_SFF_VENDOR_OUI_AVAGO: |
| 1177 | hw->phy.type = ixgbe_phy_sfp_avago; |
| 1178 | break; |
| 1179 | case IXGBE_SFF_VENDOR_OUI_INTEL: |
| 1180 | hw->phy.type = ixgbe_phy_sfp_intel; |
| 1181 | break; |
| 1182 | default: |
| 1183 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
| 1184 | hw->phy.type = |
| 1185 | ixgbe_phy_sfp_passive_unknown; |
| 1186 | else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
| 1187 | hw->phy.type = |
| 1188 | ixgbe_phy_sfp_active_unknown; |
| 1189 | else |
| 1190 | hw->phy.type = ixgbe_phy_sfp_unknown; |
| 1191 | break; |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | /* Allow any DA cable vendor */ |
| 1196 | if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | |
| 1197 | IXGBE_SFF_DA_ACTIVE_CABLE)) { |
| 1198 | status = IXGBE_SUCCESS; |
| 1199 | goto out; |
| 1200 | } |
| 1201 | |
| 1202 | /* Verify supported 1G SFP modules */ |
| 1203 | if (comp_codes_10g == 0 && |
| 1204 | !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || |
| 1205 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 1206 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || |
| 1207 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { |
| 1208 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
| 1209 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1210 | goto out; |
| 1211 | } |
| 1212 | |
| 1213 | /* Anything else 82598-based is supported */ |
| 1214 | if (hw->mac.type == ixgbe_mac_82598EB) { |
| 1215 | status = IXGBE_SUCCESS; |
| 1216 | goto out; |
| 1217 | } |
| 1218 | |
| 1219 | ixgbe_get_device_caps(hw, &enforce_sfp); |
| 1220 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && |
| 1221 | !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 1222 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || |
| 1223 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || |
| 1224 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { |
| 1225 | /* Make sure we're a supported PHY type */ |
| 1226 | if (hw->phy.type == ixgbe_phy_sfp_intel) { |
| 1227 | status = IXGBE_SUCCESS; |
| 1228 | } else { |
| 1229 | if (hw->allow_unsupported_sfp == TRUE) { |
| 1230 | EWARN(hw, "WARNING: Intel (R) Network " |
| 1231 | "Connections are quality tested " |
| 1232 | "using Intel (R) Ethernet Optics." |
| 1233 | " Using untested modules is not " |
| 1234 | "supported and may cause unstable" |
| 1235 | " operation or damage to the " |
| 1236 | "module or the adapter. Intel " |
| 1237 | "Corporation is not responsible " |
| 1238 | "for any harm caused by using " |
| 1239 | "untested modules.\n" , status); |
| 1240 | status = IXGBE_SUCCESS; |
| 1241 | } else { |
| 1242 | DEBUGOUT("SFP+ module not supported\n" ); |
| 1243 | hw->phy.type = |
| 1244 | ixgbe_phy_sfp_unsupported; |
| 1245 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1246 | } |
| 1247 | } |
| 1248 | } else { |
| 1249 | status = IXGBE_SUCCESS; |
| 1250 | } |
| 1251 | } |
| 1252 | |
| 1253 | out: |
| 1254 | return status; |
| 1255 | |
| 1256 | err_read_i2c_eeprom: |
| 1257 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 1258 | if (hw->phy.type != ixgbe_phy_nl) { |
| 1259 | hw->phy.id = 0; |
| 1260 | hw->phy.type = ixgbe_phy_unknown; |
| 1261 | } |
| 1262 | return IXGBE_ERR_SFP_NOT_PRESENT; |
| 1263 | } |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | /** |
| 1268 | * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence |
| 1269 | * @hw: pointer to hardware structure |
| 1270 | * @list_offset: offset to the SFP ID list |
| 1271 | * @data_offset: offset to the SFP data block |
| 1272 | * |
| 1273 | * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if |
| 1274 | * so it returns the offsets to the phy init sequence block. |
| 1275 | **/ |
| 1276 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, |
| 1277 | u16 *list_offset, |
| 1278 | u16 *data_offset) |
| 1279 | { |
| 1280 | u16 sfp_id; |
| 1281 | u16 sfp_type = hw->phy.sfp_type; |
| 1282 | |
| 1283 | DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets" ); |
| 1284 | |
| 1285 | if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) |
| 1286 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1287 | |
| 1288 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 1289 | return IXGBE_ERR_SFP_NOT_PRESENT; |
| 1290 | |
| 1291 | if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && |
| 1292 | (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) |
| 1293 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1294 | |
| 1295 | /* |
| 1296 | * Limiting active cables and 1G Phys must be initialized as |
| 1297 | * SR modules |
| 1298 | */ |
| 1299 | if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || |
| 1300 | sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 1301 | sfp_type == ixgbe_sfp_type_1g_sx_core0) |
| 1302 | sfp_type = ixgbe_sfp_type_srlr_core0; |
| 1303 | else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || |
| 1304 | sfp_type == ixgbe_sfp_type_1g_cu_core1 || |
| 1305 | sfp_type == ixgbe_sfp_type_1g_sx_core1) |
| 1306 | sfp_type = ixgbe_sfp_type_srlr_core1; |
| 1307 | |
| 1308 | /* Read offset to PHY init contents */ |
| 1309 | if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { |
| 1310 | ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, |
| 1311 | "eeprom read at offset %d failed" , |
| 1312 | IXGBE_PHY_INIT_OFFSET_NL); |
| 1313 | return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; |
| 1314 | } |
| 1315 | |
| 1316 | if ((!*list_offset) || (*list_offset == 0xFFFF)) |
| 1317 | return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; |
| 1318 | |
| 1319 | /* Shift offset to first ID word */ |
| 1320 | (*list_offset)++; |
| 1321 | |
| 1322 | /* |
| 1323 | * Find the matching SFP ID in the EEPROM |
| 1324 | * and program the init sequence |
| 1325 | */ |
| 1326 | if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) |
| 1327 | goto err_phy; |
| 1328 | |
| 1329 | while (sfp_id != IXGBE_PHY_INIT_END_NL) { |
| 1330 | if (sfp_id == sfp_type) { |
| 1331 | (*list_offset)++; |
| 1332 | if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) |
| 1333 | goto err_phy; |
| 1334 | if ((!*data_offset) || (*data_offset == 0xFFFF)) { |
| 1335 | DEBUGOUT("SFP+ module not supported\n" ); |
| 1336 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1337 | } else { |
| 1338 | break; |
| 1339 | } |
| 1340 | } else { |
| 1341 | (*list_offset) += 2; |
| 1342 | if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) |
| 1343 | goto err_phy; |
| 1344 | } |
| 1345 | } |
| 1346 | |
| 1347 | if (sfp_id == IXGBE_PHY_INIT_END_NL) { |
| 1348 | DEBUGOUT("No matching SFP+ module found\n" ); |
| 1349 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1350 | } |
| 1351 | |
| 1352 | return IXGBE_SUCCESS; |
| 1353 | |
| 1354 | err_phy: |
| 1355 | ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, |
| 1356 | "eeprom read at offset %d failed" , *list_offset); |
| 1357 | return IXGBE_ERR_PHY; |
| 1358 | } |
| 1359 | |
| 1360 | /** |
| 1361 | * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface |
| 1362 | * @hw: pointer to hardware structure |
| 1363 | * @byte_offset: EEPROM byte offset to read |
| 1364 | * @eeprom_data: value read |
| 1365 | * |
| 1366 | * Performs byte read operation to SFP module's EEPROM over I2C interface. |
| 1367 | **/ |
| 1368 | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1369 | u8 *eeprom_data) |
| 1370 | { |
| 1371 | DEBUGFUNC("ixgbe_read_i2c_eeprom_generic" ); |
| 1372 | |
| 1373 | return hw->phy.ops.read_i2c_byte(hw, byte_offset, |
| 1374 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 1375 | eeprom_data); |
| 1376 | } |
| 1377 | |
| 1378 | /** |
| 1379 | * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface |
| 1380 | * @hw: pointer to hardware structure |
| 1381 | * @byte_offset: byte offset at address 0xA2 |
| 1382 | * @eeprom_data: value read |
| 1383 | * |
| 1384 | * Performs byte read operation to SFP module's SFF-8472 data over I2C |
| 1385 | **/ |
| 1386 | static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1387 | u8 *sff8472_data) |
| 1388 | { |
| 1389 | return hw->phy.ops.read_i2c_byte(hw, byte_offset, |
| 1390 | IXGBE_I2C_EEPROM_DEV_ADDR2, |
| 1391 | sff8472_data); |
| 1392 | } |
| 1393 | |
| 1394 | /** |
| 1395 | * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface |
| 1396 | * @hw: pointer to hardware structure |
| 1397 | * @byte_offset: EEPROM byte offset to write |
| 1398 | * @eeprom_data: value to write |
| 1399 | * |
| 1400 | * Performs byte write operation to SFP module's EEPROM over I2C interface. |
| 1401 | **/ |
| 1402 | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1403 | u8 eeprom_data) |
| 1404 | { |
| 1405 | DEBUGFUNC("ixgbe_write_i2c_eeprom_generic" ); |
| 1406 | |
| 1407 | return hw->phy.ops.write_i2c_byte(hw, byte_offset, |
| 1408 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 1409 | eeprom_data); |
| 1410 | } |
| 1411 | |
| 1412 | /** |
| 1413 | * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C |
| 1414 | * @hw: pointer to hardware structure |
| 1415 | * @byte_offset: byte offset to read |
| 1416 | * @data: value read |
| 1417 | * |
| 1418 | * Performs byte read operation to SFP module's EEPROM over I2C interface at |
| 1419 | * a specified device address. |
| 1420 | **/ |
| 1421 | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1422 | u8 dev_addr, u8 *data) |
| 1423 | { |
| 1424 | s32 status = IXGBE_SUCCESS; |
| 1425 | u32 max_retry = 10; |
| 1426 | u32 retry = 0; |
| 1427 | u16 swfw_mask = 0; |
| 1428 | bool nack = 1; |
| 1429 | *data = 0; |
| 1430 | |
| 1431 | DEBUGFUNC("ixgbe_read_i2c_byte_generic" ); |
| 1432 | |
| 1433 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 1434 | swfw_mask = IXGBE_GSSR_PHY1_SM; |
| 1435 | else |
| 1436 | swfw_mask = IXGBE_GSSR_PHY0_SM; |
| 1437 | |
| 1438 | do { |
| 1439 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) |
| 1440 | != IXGBE_SUCCESS) { |
| 1441 | status = IXGBE_ERR_SWFW_SYNC; |
| 1442 | goto read_byte_out; |
| 1443 | } |
| 1444 | |
| 1445 | ixgbe_i2c_start(hw); |
| 1446 | |
| 1447 | /* Device Address and write indication */ |
| 1448 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 1449 | if (status != IXGBE_SUCCESS) |
| 1450 | goto fail; |
| 1451 | |
| 1452 | status = ixgbe_get_i2c_ack(hw); |
| 1453 | if (status != IXGBE_SUCCESS) |
| 1454 | goto fail; |
| 1455 | |
| 1456 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 1457 | if (status != IXGBE_SUCCESS) |
| 1458 | goto fail; |
| 1459 | |
| 1460 | status = ixgbe_get_i2c_ack(hw); |
| 1461 | if (status != IXGBE_SUCCESS) |
| 1462 | goto fail; |
| 1463 | |
| 1464 | ixgbe_i2c_start(hw); |
| 1465 | |
| 1466 | /* Device Address and read indication */ |
| 1467 | status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); |
| 1468 | if (status != IXGBE_SUCCESS) |
| 1469 | goto fail; |
| 1470 | |
| 1471 | status = ixgbe_get_i2c_ack(hw); |
| 1472 | if (status != IXGBE_SUCCESS) |
| 1473 | goto fail; |
| 1474 | |
| 1475 | status = ixgbe_clock_in_i2c_byte(hw, data); |
| 1476 | if (status != IXGBE_SUCCESS) |
| 1477 | goto fail; |
| 1478 | |
| 1479 | status = ixgbe_clock_out_i2c_bit(hw, nack); |
| 1480 | if (status != IXGBE_SUCCESS) |
| 1481 | goto fail; |
| 1482 | |
| 1483 | ixgbe_i2c_stop(hw); |
| 1484 | break; |
| 1485 | |
| 1486 | fail: |
| 1487 | ixgbe_i2c_bus_clear(hw); |
| 1488 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
| 1489 | msec_delay(100); |
| 1490 | retry++; |
| 1491 | if (retry < max_retry) |
| 1492 | DEBUGOUT("I2C byte read error - Retrying.\n" ); |
| 1493 | else |
| 1494 | DEBUGOUT("I2C byte read error.\n" ); |
| 1495 | |
| 1496 | } while (retry < max_retry); |
| 1497 | |
| 1498 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
| 1499 | |
| 1500 | read_byte_out: |
| 1501 | return status; |
| 1502 | } |
| 1503 | |
| 1504 | /** |
| 1505 | * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C |
| 1506 | * @hw: pointer to hardware structure |
| 1507 | * @byte_offset: byte offset to write |
| 1508 | * @data: value to write |
| 1509 | * |
| 1510 | * Performs byte write operation to SFP module's EEPROM over I2C interface at |
| 1511 | * a specified device address. |
| 1512 | **/ |
| 1513 | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1514 | u8 dev_addr, u8 data) |
| 1515 | { |
| 1516 | s32 status = IXGBE_SUCCESS; |
| 1517 | u32 max_retry = 2; |
| 1518 | u32 retry = 0; |
| 1519 | u16 swfw_mask = 0; |
| 1520 | |
| 1521 | DEBUGFUNC("ixgbe_write_i2c_byte_generic" ); |
| 1522 | |
| 1523 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 1524 | swfw_mask = IXGBE_GSSR_PHY1_SM; |
| 1525 | else |
| 1526 | swfw_mask = IXGBE_GSSR_PHY0_SM; |
| 1527 | |
| 1528 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { |
| 1529 | status = IXGBE_ERR_SWFW_SYNC; |
| 1530 | goto write_byte_out; |
| 1531 | } |
| 1532 | |
| 1533 | do { |
| 1534 | ixgbe_i2c_start(hw); |
| 1535 | |
| 1536 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 1537 | if (status != IXGBE_SUCCESS) |
| 1538 | goto fail; |
| 1539 | |
| 1540 | status = ixgbe_get_i2c_ack(hw); |
| 1541 | if (status != IXGBE_SUCCESS) |
| 1542 | goto fail; |
| 1543 | |
| 1544 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 1545 | if (status != IXGBE_SUCCESS) |
| 1546 | goto fail; |
| 1547 | |
| 1548 | status = ixgbe_get_i2c_ack(hw); |
| 1549 | if (status != IXGBE_SUCCESS) |
| 1550 | goto fail; |
| 1551 | |
| 1552 | status = ixgbe_clock_out_i2c_byte(hw, data); |
| 1553 | if (status != IXGBE_SUCCESS) |
| 1554 | goto fail; |
| 1555 | |
| 1556 | status = ixgbe_get_i2c_ack(hw); |
| 1557 | if (status != IXGBE_SUCCESS) |
| 1558 | goto fail; |
| 1559 | |
| 1560 | ixgbe_i2c_stop(hw); |
| 1561 | break; |
| 1562 | |
| 1563 | fail: |
| 1564 | ixgbe_i2c_bus_clear(hw); |
| 1565 | retry++; |
| 1566 | if (retry < max_retry) |
| 1567 | DEBUGOUT("I2C byte write error - Retrying.\n" ); |
| 1568 | else |
| 1569 | DEBUGOUT("I2C byte write error.\n" ); |
| 1570 | } while (retry < max_retry); |
| 1571 | |
| 1572 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
| 1573 | |
| 1574 | write_byte_out: |
| 1575 | return status; |
| 1576 | } |
| 1577 | |
| 1578 | /** |
| 1579 | * ixgbe_i2c_start - Sets I2C start condition |
| 1580 | * @hw: pointer to hardware structure |
| 1581 | * |
| 1582 | * Sets I2C start condition (High -> Low on SDA while SCL is High) |
| 1583 | **/ |
| 1584 | static void ixgbe_i2c_start(struct ixgbe_hw *hw) |
| 1585 | { |
| 1586 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1587 | |
| 1588 | DEBUGFUNC("ixgbe_i2c_start" ); |
| 1589 | |
| 1590 | /* Start condition must begin with data and clock high */ |
| 1591 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1592 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1593 | |
| 1594 | /* Setup time for start condition (4.7us) */ |
| 1595 | usec_delay(IXGBE_I2C_T_SU_STA); |
| 1596 | |
| 1597 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 1598 | |
| 1599 | /* Hold time for start condition (4us) */ |
| 1600 | usec_delay(IXGBE_I2C_T_HD_STA); |
| 1601 | |
| 1602 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1603 | |
| 1604 | /* Minimum low period of clock is 4.7 us */ |
| 1605 | usec_delay(IXGBE_I2C_T_LOW); |
| 1606 | |
| 1607 | } |
| 1608 | |
| 1609 | /** |
| 1610 | * ixgbe_i2c_stop - Sets I2C stop condition |
| 1611 | * @hw: pointer to hardware structure |
| 1612 | * |
| 1613 | * Sets I2C stop condition (Low -> High on SDA while SCL is High) |
| 1614 | **/ |
| 1615 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw) |
| 1616 | { |
| 1617 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1618 | |
| 1619 | DEBUGFUNC("ixgbe_i2c_stop" ); |
| 1620 | |
| 1621 | /* Stop condition must begin with data low and clock high */ |
| 1622 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 1623 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1624 | |
| 1625 | /* Setup time for stop condition (4us) */ |
| 1626 | usec_delay(IXGBE_I2C_T_SU_STO); |
| 1627 | |
| 1628 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1629 | |
| 1630 | /* bus free time between stop and start (4.7us)*/ |
| 1631 | usec_delay(IXGBE_I2C_T_BUF); |
| 1632 | } |
| 1633 | |
| 1634 | /** |
| 1635 | * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C |
| 1636 | * @hw: pointer to hardware structure |
| 1637 | * @data: data byte to clock in |
| 1638 | * |
| 1639 | * Clocks in one byte data via I2C data/clock |
| 1640 | **/ |
| 1641 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) |
| 1642 | { |
| 1643 | s32 i; |
| 1644 | bool bit = 0; |
| 1645 | |
| 1646 | DEBUGFUNC("ixgbe_clock_in_i2c_byte" ); |
| 1647 | |
| 1648 | for (i = 7; i >= 0; i--) { |
| 1649 | ixgbe_clock_in_i2c_bit(hw, &bit); |
| 1650 | *data |= bit << i; |
| 1651 | } |
| 1652 | |
| 1653 | return IXGBE_SUCCESS; |
| 1654 | } |
| 1655 | |
| 1656 | /** |
| 1657 | * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C |
| 1658 | * @hw: pointer to hardware structure |
| 1659 | * @data: data byte clocked out |
| 1660 | * |
| 1661 | * Clocks out one byte data via I2C data/clock |
| 1662 | **/ |
| 1663 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) |
| 1664 | { |
| 1665 | s32 status = IXGBE_SUCCESS; |
| 1666 | s32 i; |
| 1667 | u32 i2cctl; |
| 1668 | bool bit = 0; |
| 1669 | |
| 1670 | DEBUGFUNC("ixgbe_clock_out_i2c_byte" ); |
| 1671 | |
| 1672 | for (i = 7; i >= 0; i--) { |
| 1673 | bit = (data >> i) & 0x1; |
| 1674 | status = ixgbe_clock_out_i2c_bit(hw, bit); |
| 1675 | |
| 1676 | if (status != IXGBE_SUCCESS) |
| 1677 | break; |
| 1678 | } |
| 1679 | |
| 1680 | /* Release SDA line (set high) */ |
| 1681 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1682 | i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1683 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); |
| 1684 | IXGBE_WRITE_FLUSH(hw); |
| 1685 | |
| 1686 | return status; |
| 1687 | } |
| 1688 | |
| 1689 | /** |
| 1690 | * ixgbe_get_i2c_ack - Polls for I2C ACK |
| 1691 | * @hw: pointer to hardware structure |
| 1692 | * |
| 1693 | * Clocks in/out one bit via I2C data/clock |
| 1694 | **/ |
| 1695 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) |
| 1696 | { |
| 1697 | s32 status = IXGBE_SUCCESS; |
| 1698 | u32 i = 0; |
| 1699 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1700 | u32 timeout = 10; |
| 1701 | bool ack = 1; |
| 1702 | |
| 1703 | DEBUGFUNC("ixgbe_get_i2c_ack" ); |
| 1704 | |
| 1705 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1706 | |
| 1707 | |
| 1708 | /* Minimum high period of clock is 4us */ |
| 1709 | usec_delay(IXGBE_I2C_T_HIGH); |
| 1710 | |
| 1711 | /* Poll for ACK. Note that ACK in I2C spec is |
| 1712 | * transition from 1 to 0 */ |
| 1713 | for (i = 0; i < timeout; i++) { |
| 1714 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1715 | ack = ixgbe_get_i2c_data(&i2cctl); |
| 1716 | |
| 1717 | usec_delay(1); |
| 1718 | if (ack == 0) |
| 1719 | break; |
| 1720 | } |
| 1721 | |
| 1722 | if (ack == 1) { |
| 1723 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
| 1724 | "I2C ack was not received.\n" ); |
| 1725 | status = IXGBE_ERR_I2C; |
| 1726 | } |
| 1727 | |
| 1728 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1729 | |
| 1730 | /* Minimum low period of clock is 4.7 us */ |
| 1731 | usec_delay(IXGBE_I2C_T_LOW); |
| 1732 | |
| 1733 | return status; |
| 1734 | } |
| 1735 | |
| 1736 | /** |
| 1737 | * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock |
| 1738 | * @hw: pointer to hardware structure |
| 1739 | * @data: read data value |
| 1740 | * |
| 1741 | * Clocks in one bit via I2C data/clock |
| 1742 | **/ |
| 1743 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) |
| 1744 | { |
| 1745 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1746 | |
| 1747 | DEBUGFUNC("ixgbe_clock_in_i2c_bit" ); |
| 1748 | |
| 1749 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1750 | |
| 1751 | /* Minimum high period of clock is 4us */ |
| 1752 | usec_delay(IXGBE_I2C_T_HIGH); |
| 1753 | |
| 1754 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1755 | *data = ixgbe_get_i2c_data(&i2cctl); |
| 1756 | |
| 1757 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1758 | |
| 1759 | /* Minimum low period of clock is 4.7 us */ |
| 1760 | usec_delay(IXGBE_I2C_T_LOW); |
| 1761 | |
| 1762 | return IXGBE_SUCCESS; |
| 1763 | } |
| 1764 | |
| 1765 | /** |
| 1766 | * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock |
| 1767 | * @hw: pointer to hardware structure |
| 1768 | * @data: data value to write |
| 1769 | * |
| 1770 | * Clocks out one bit via I2C data/clock |
| 1771 | **/ |
| 1772 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) |
| 1773 | { |
| 1774 | s32 status; |
| 1775 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1776 | |
| 1777 | DEBUGFUNC("ixgbe_clock_out_i2c_bit" ); |
| 1778 | |
| 1779 | status = ixgbe_set_i2c_data(hw, &i2cctl, data); |
| 1780 | if (status == IXGBE_SUCCESS) { |
| 1781 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1782 | |
| 1783 | /* Minimum high period of clock is 4us */ |
| 1784 | usec_delay(IXGBE_I2C_T_HIGH); |
| 1785 | |
| 1786 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1787 | |
| 1788 | /* Minimum low period of clock is 4.7 us. |
| 1789 | * This also takes care of the data hold time. |
| 1790 | */ |
| 1791 | usec_delay(IXGBE_I2C_T_LOW); |
| 1792 | } else { |
| 1793 | status = IXGBE_ERR_I2C; |
| 1794 | ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, |
| 1795 | "I2C data was not set to %X\n" , data); |
| 1796 | } |
| 1797 | |
| 1798 | return status; |
| 1799 | } |
| 1800 | /** |
| 1801 | * ixgbe_raise_i2c_clk - Raises the I2C SCL clock |
| 1802 | * @hw: pointer to hardware structure |
| 1803 | * @i2cctl: Current value of I2CCTL register |
| 1804 | * |
| 1805 | * Raises the I2C clock line '0'->'1' |
| 1806 | **/ |
| 1807 | static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
| 1808 | { |
| 1809 | u32 i = 0; |
| 1810 | u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; |
| 1811 | u32 i2cctl_r = 0; |
| 1812 | |
| 1813 | DEBUGFUNC("ixgbe_raise_i2c_clk" ); |
| 1814 | |
| 1815 | for (i = 0; i < timeout; i++) { |
| 1816 | *i2cctl |= IXGBE_I2C_CLK_OUT; |
| 1817 | |
| 1818 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1819 | IXGBE_WRITE_FLUSH(hw); |
| 1820 | /* SCL rise time (1000ns) */ |
| 1821 | usec_delay(IXGBE_I2C_T_RISE); |
| 1822 | |
| 1823 | i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1824 | if (i2cctl_r & IXGBE_I2C_CLK_IN) |
| 1825 | break; |
| 1826 | } |
| 1827 | } |
| 1828 | |
| 1829 | /** |
| 1830 | * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock |
| 1831 | * @hw: pointer to hardware structure |
| 1832 | * @i2cctl: Current value of I2CCTL register |
| 1833 | * |
| 1834 | * Lowers the I2C clock line '1'->'0' |
| 1835 | **/ |
| 1836 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
| 1837 | { |
| 1838 | |
| 1839 | DEBUGFUNC("ixgbe_lower_i2c_clk" ); |
| 1840 | |
| 1841 | *i2cctl &= ~IXGBE_I2C_CLK_OUT; |
| 1842 | |
| 1843 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1844 | IXGBE_WRITE_FLUSH(hw); |
| 1845 | |
| 1846 | /* SCL fall time (300ns) */ |
| 1847 | usec_delay(IXGBE_I2C_T_FALL); |
| 1848 | } |
| 1849 | |
| 1850 | /** |
| 1851 | * ixgbe_set_i2c_data - Sets the I2C data bit |
| 1852 | * @hw: pointer to hardware structure |
| 1853 | * @i2cctl: Current value of I2CCTL register |
| 1854 | * @data: I2C data value (0 or 1) to set |
| 1855 | * |
| 1856 | * Sets the I2C data bit |
| 1857 | **/ |
| 1858 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) |
| 1859 | { |
| 1860 | s32 status = IXGBE_SUCCESS; |
| 1861 | |
| 1862 | DEBUGFUNC("ixgbe_set_i2c_data" ); |
| 1863 | |
| 1864 | if (data) |
| 1865 | *i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1866 | else |
| 1867 | *i2cctl &= ~IXGBE_I2C_DATA_OUT; |
| 1868 | |
| 1869 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1870 | IXGBE_WRITE_FLUSH(hw); |
| 1871 | |
| 1872 | /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ |
| 1873 | usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); |
| 1874 | |
| 1875 | /* Verify data was set correctly */ |
| 1876 | *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1877 | if (data != ixgbe_get_i2c_data(i2cctl)) { |
| 1878 | status = IXGBE_ERR_I2C; |
| 1879 | ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, |
| 1880 | "Error - I2C data was not set to %X.\n" , |
| 1881 | data); |
| 1882 | } |
| 1883 | |
| 1884 | return status; |
| 1885 | } |
| 1886 | |
| 1887 | /** |
| 1888 | * ixgbe_get_i2c_data - Reads the I2C SDA data bit |
| 1889 | * @hw: pointer to hardware structure |
| 1890 | * @i2cctl: Current value of I2CCTL register |
| 1891 | * |
| 1892 | * Returns the I2C data bit value |
| 1893 | **/ |
| 1894 | static bool ixgbe_get_i2c_data(u32 *i2cctl) |
| 1895 | { |
| 1896 | bool data; |
| 1897 | |
| 1898 | DEBUGFUNC("ixgbe_get_i2c_data" ); |
| 1899 | |
| 1900 | if (*i2cctl & IXGBE_I2C_DATA_IN) |
| 1901 | data = 1; |
| 1902 | else |
| 1903 | data = 0; |
| 1904 | |
| 1905 | return data; |
| 1906 | } |
| 1907 | |
| 1908 | /** |
| 1909 | * ixgbe_i2c_bus_clear - Clears the I2C bus |
| 1910 | * @hw: pointer to hardware structure |
| 1911 | * |
| 1912 | * Clears the I2C bus by sending nine clock pulses. |
| 1913 | * Used when data line is stuck low. |
| 1914 | **/ |
| 1915 | void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) |
| 1916 | { |
| 1917 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1918 | u32 i; |
| 1919 | |
| 1920 | DEBUGFUNC("ixgbe_i2c_bus_clear" ); |
| 1921 | |
| 1922 | ixgbe_i2c_start(hw); |
| 1923 | |
| 1924 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1925 | |
| 1926 | for (i = 0; i < 9; i++) { |
| 1927 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1928 | |
| 1929 | /* Min high period of clock is 4us */ |
| 1930 | usec_delay(IXGBE_I2C_T_HIGH); |
| 1931 | |
| 1932 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1933 | |
| 1934 | /* Min low period of clock is 4.7us*/ |
| 1935 | usec_delay(IXGBE_I2C_T_LOW); |
| 1936 | } |
| 1937 | |
| 1938 | ixgbe_i2c_start(hw); |
| 1939 | |
| 1940 | /* Put the i2c bus back to default state */ |
| 1941 | ixgbe_i2c_stop(hw); |
| 1942 | } |
| 1943 | |
| 1944 | /** |
| 1945 | * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. |
| 1946 | * @hw: pointer to hardware structure |
| 1947 | * |
| 1948 | * Checks if the LASI temp alarm status was triggered due to overtemp |
| 1949 | **/ |
| 1950 | s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) |
| 1951 | { |
| 1952 | s32 status = IXGBE_SUCCESS; |
| 1953 | u16 phy_data = 0; |
| 1954 | |
| 1955 | DEBUGFUNC("ixgbe_tn_check_overtemp" ); |
| 1956 | |
| 1957 | if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) |
| 1958 | goto out; |
| 1959 | |
| 1960 | /* Check that the LASI temp alarm status was triggered */ |
| 1961 | hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, |
| 1962 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); |
| 1963 | |
| 1964 | if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) |
| 1965 | goto out; |
| 1966 | |
| 1967 | status = IXGBE_ERR_OVERTEMP; |
| 1968 | ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature" ); |
| 1969 | out: |
| 1970 | return status; |
| 1971 | } |
| 1972 | |