| 1 | /*- |
| 2 | * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice unmodified, this list of conditions, and the following |
| 10 | * disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 16 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 19 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 21 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 23 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 24 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 25 | * SUCH DAMAGE. |
| 26 | * |
| 27 | * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.3 2008/09/22 06:17:21 yongari Exp $ |
| 28 | */ |
| 29 | |
| 30 | #ifndef _IF_JMEREG_H |
| 31 | #define _IF_JMEREG_H |
| 32 | |
| 33 | /* |
| 34 | * JMC250 PCI revisions |
| 35 | */ |
| 36 | #define DEVICEREVID_JMC250_A0 0x00 |
| 37 | #define DEVICEREVID_JMC250_A2 0x11 |
| 38 | |
| 39 | /* |
| 40 | * JMC260 PCI revisions |
| 41 | */ |
| 42 | #define DEVICEREVID_JMC260_A0 0x00 |
| 43 | |
| 44 | /* JMC250 PCI configuration register. */ |
| 45 | #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ |
| 46 | |
| 47 | #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ |
| 48 | |
| 49 | #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ |
| 50 | |
| 51 | #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ |
| 52 | |
| 53 | #define JME_PCI_EROM 0x30 |
| 54 | |
| 55 | #define JME_PCI_DBG 0x9C |
| 56 | |
| 57 | #define JME_PCI_SPI 0xB0 |
| 58 | |
| 59 | #define SPI_ENB 0x00000010 |
| 60 | #define SPI_SO_STATUS 0x00000008 |
| 61 | #define SPI_SI_CTRL 0x00000004 |
| 62 | #define SPI_SCK_CTRL 0x00000002 |
| 63 | #define SPI_CS_N_CTRL 0x00000001 |
| 64 | |
| 65 | #define JME_PCI_PHYCFG0 0xC0 |
| 66 | |
| 67 | #define JME_PCI_PHYCFG1 0xC4 |
| 68 | |
| 69 | #define JME_PCI_PHYCFG2 0xC8 |
| 70 | |
| 71 | #define JME_PCI_PHYCFG3 0xCC |
| 72 | |
| 73 | #define JME_PCI_PIPECTL1 0xD0 |
| 74 | |
| 75 | #define JME_PCI_PIPECTL2 0xD4 |
| 76 | |
| 77 | /* PCIe link error/status. */ |
| 78 | #define JME_PCI_LES 0xD8 |
| 79 | |
| 80 | /* propeietary register 0. */ |
| 81 | #define JME_PCI_PE0 0xE0 |
| 82 | #define PE0_SPI_EXIST 0x00200000 |
| 83 | #define PE0_PME_D0 0x00100000 |
| 84 | #define PE0_PME_D3H 0x00080000 |
| 85 | #define PE0_PME_SPI_PAD 0x00040000 |
| 86 | #define PE0_MASK_ASPM 0x00020000 |
| 87 | #define PE0_EEPROM_RW_DIS 0x00008000 |
| 88 | #define PE0_PCI_INTA 0x00001000 |
| 89 | #define PE0_PCI_INTB 0x00002000 |
| 90 | #define PE0_PCI_INTC 0x00003000 |
| 91 | #define PE0_PCI_INTD 0x00004000 |
| 92 | #define PE0_PCI_SVSSID_WR_ENB 0x00000800 |
| 93 | #define PE0_MSIX_SIZE_8 0x00000700 |
| 94 | #define PE0_MSIX_SIZE_7 0x00000600 |
| 95 | #define PE0_MSIX_SIZE_6 0x00000500 |
| 96 | #define PE0_MSIX_SIZE_5 0x00000400 |
| 97 | #define PE0_MSIX_SIZE_4 0x00000300 |
| 98 | #define PE0_MSIX_SIZE_3 0x00000200 |
| 99 | #define PE0_MSIX_SIZE_2 0x00000100 |
| 100 | #define PE0_MSIX_SIZE_1 0x00000000 |
| 101 | #define PE0_MSIX_SIZE_DEF 0x00000700 |
| 102 | #define PE0_MSIX_CAP_DIS 0x00000080 |
| 103 | #define PE0_MSI_PVMC_ENB 0x00000040 |
| 104 | #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 |
| 105 | #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 |
| 106 | #define PE0_PM_AUXC_MASK 0x00000007 |
| 107 | #define PE0_PM_AUXC_DEF 0x00000007 |
| 108 | |
| 109 | #define JME_PCI_PE1 0xE4 |
| 110 | |
| 111 | #define JME_PCI_PHYTEST 0xF8 |
| 112 | |
| 113 | #define JME_PCI_GPR 0xFC |
| 114 | |
| 115 | /* |
| 116 | * JMC Register Map. |
| 117 | * ----------------------------------------------------------------------- |
| 118 | * Register Size IO space Memory space |
| 119 | * ----------------------------------------------------------------------- |
| 120 | * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ |
| 121 | * BAR1 + 0x7F BAR0 + 0x7F |
| 122 | * ----------------------------------------------------------------------- |
| 123 | * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ |
| 124 | * BAR2 + 0x7F BAR0 + 0x47F |
| 125 | * ----------------------------------------------------------------------- |
| 126 | * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ |
| 127 | * BAR2 + 0xfF BAR0 + 0x87F |
| 128 | * ----------------------------------------------------------------------- |
| 129 | * We use bus_space_subregion() to get handle for the 3 different |
| 130 | * register space. Register address are relative to the base of each |
| 131 | * region. |
| 132 | */ |
| 133 | |
| 134 | /* Tx control and status. */ |
| 135 | #define JME_TXCSR 0x0000 |
| 136 | #define TXCSR_QWEIGHT_MASK 0x0F000000 |
| 137 | #define TXCSR_QWEIGHT_SHIFT 24 |
| 138 | #define TXCSR_TXQ_SEL_MASK 0x00070000 |
| 139 | #define TXCSR_TXQ_SEL_SHIFT 16 |
| 140 | #define TXCSR_TXQ_START 0x00000001 |
| 141 | #define TXCSR_TXQ_START_SHIFT 8 |
| 142 | #define TXCSR_FIFO_THRESH_4QW 0x00000000 |
| 143 | #define TXCSR_FIFO_THRESH_8QW 0x00000040 |
| 144 | #define TXCSR_FIFO_THRESH_12QW 0x00000080 |
| 145 | #define TXCSR_FIFO_THRESH_16QW 0x000000C0 |
| 146 | #define TXCSR_DMA_SIZE_64 0x00000000 |
| 147 | #define TXCSR_DMA_SIZE_128 0x00000010 |
| 148 | #define TXCSR_DMA_SIZE_256 0x00000020 |
| 149 | #define TXCSR_DMA_SIZE_512 0x00000030 |
| 150 | #define TXCSR_DMA_BURST 0x00000004 |
| 151 | #define TXCSR_TX_SUSPEND 0x00000002 |
| 152 | #define TXCSR_TX_ENB 0x00000001 |
| 153 | #define TXCSR_TXQ0 0 |
| 154 | #define TXCSR_TXQ1 1 |
| 155 | #define TXCSR_TXQ2 2 |
| 156 | #define TXCSR_TXQ3 3 |
| 157 | #define TXCSR_TXQ4 4 |
| 158 | #define TXCSR_TXQ5 5 |
| 159 | #define TXCSR_TXQ6 6 |
| 160 | #define TXCSR_TXQ7 7 |
| 161 | #define TXCSR_TXQ_WEIGHT(x) \ |
| 162 | (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) |
| 163 | #define TXCSR_TXQ_WEIGHT_MIN 0 |
| 164 | #define TXCSR_TXQ_WEIGHT_MAX 15 |
| 165 | #define TXCSR_TXQ_N_SEL(x) \ |
| 166 | (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) |
| 167 | #define TXCSR_TXQ_N_START(x) \ |
| 168 | (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) |
| 169 | |
| 170 | /* Tx queue descriptor base address. 16bytes alignment required. */ |
| 171 | #define JME_TXDBA_LO 0x0004 |
| 172 | #define JME_TXDBA_HI 0x0008 |
| 173 | |
| 174 | /* Tx queue descriptor count. multiple of 16(max = 1024). */ |
| 175 | #define JME_TXQDC 0x000C |
| 176 | #define TXQDC_MASK 0x0000007F0 |
| 177 | |
| 178 | /* Tx queue next descriptor address. */ |
| 179 | #define JME_TXNDA 0x0010 |
| 180 | #define TXNDA_ADDR_MASK 0xFFFFFFF0 |
| 181 | #define TXNDA_DESC_EMPTY 0x00000008 |
| 182 | #define TXNDA_DESC_VALID 0x00000004 |
| 183 | #define TXNDA_DESC_WAIT 0x00000002 |
| 184 | #define TXNDA_DESC_FETCH 0x00000001 |
| 185 | |
| 186 | /* Tx MAC control ans status. */ |
| 187 | #define JME_TXMAC 0x0014 |
| 188 | #define TXMAC_IFG2_MASK 0xC0000000 |
| 189 | #define TXMAC_IFG2_DEFAULT 0x40000000 |
| 190 | #define TXMAC_IFG1_MASK 0x30000000 |
| 191 | #define TXMAC_IFG1_DEFAULT 0x20000000 |
| 192 | #define TXMAC_THRESH_1_PKT 0x00000300 |
| 193 | #define TXMAC_THRESH_1_2_PKT 0x00000200 |
| 194 | #define TXMAC_THRESH_1_4_PKT 0x00000100 |
| 195 | #define TXMAC_THRESH_1_8_PKT 0x00000000 |
| 196 | #define TXMAC_FRAME_BURST 0x00000080 |
| 197 | #define TXMAC_CARRIER_EXT 0x00000040 |
| 198 | #define TXMAC_IFG_ENB 0x00000020 |
| 199 | #define TXMAC_BACKOFF 0x00000010 |
| 200 | #define TXMAC_CARRIER_SENSE 0x00000008 |
| 201 | #define TXMAC_COLL_ENB 0x00000004 |
| 202 | #define TXMAC_CRC_ENB 0x00000002 |
| 203 | #define TXMAC_PAD_ENB 0x00000001 |
| 204 | |
| 205 | /* Tx pause frame control. */ |
| 206 | #define JME_TXPFC 0x0018 |
| 207 | #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 |
| 208 | #define TXPFC_VLAN_TAG_SHIFT 16 |
| 209 | #define TXPFC_VLAN_ENB 0x00008000 |
| 210 | #define TXPFC_PAUSE_ENB 0x00000001 |
| 211 | |
| 212 | /* Tx timer/retry at half duplex. */ |
| 213 | #define JME_TXTRHD 0x001C |
| 214 | #define TXTRHD_RT_PERIOD_ENB 0x80000000 |
| 215 | #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 |
| 216 | #define TXTRHD_RT_PERIOD_SHIFT 8 |
| 217 | #define TXTRHD_RT_LIMIT_ENB 0x00000080 |
| 218 | #define TXTRHD_RT_LIMIT_MASK 0x0000007F |
| 219 | #define TXTRHD_RT_LIMIT_SHIFT 0 |
| 220 | #define TXTRHD_RT_PERIOD_DEFAULT 8192 |
| 221 | #define TXTRHD_RT_LIMIT_DEFAULT 8 |
| 222 | |
| 223 | /* Rx control & status. */ |
| 224 | #define JME_RXCSR 0x0020 |
| 225 | #define RXCSR_FIFO_FTHRESH_16T 0x00000000 |
| 226 | #define RXCSR_FIFO_FTHRESH_32T 0x10000000 |
| 227 | #define RXCSR_FIFO_FTHRESH_64T 0x20000000 |
| 228 | #define RXCSR_FIFO_FTHRESH_128T 0x30000000 |
| 229 | #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 |
| 230 | #define RXCSR_FIFO_THRESH_16QW 0x00000000 |
| 231 | #define RXCSR_FIFO_THRESH_32QW 0x04000000 |
| 232 | #define RXCSR_FIFO_THRESH_64QW 0x08000000 |
| 233 | #define RXCSR_FIFO_THRESH_128QW 0x0C000000 |
| 234 | #define RXCSR_FIFO_THRESH_MASK 0x0C000000 |
| 235 | #define RXCSR_DMA_SIZE_16 0x00000000 |
| 236 | #define RXCSR_DMA_SIZE_32 0x01000000 |
| 237 | #define RXCSR_DMA_SIZE_64 0x02000000 |
| 238 | #define RXCSR_DMA_SIZE_128 0x03000000 |
| 239 | #define RXCSR_RXQ_SEL_MASK 0x00030000 |
| 240 | #define RXCSR_RXQ_SEL_SHIFT 16 |
| 241 | #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 |
| 242 | #define RXCSR_DESC_RT_GAP_SHIFT 12 |
| 243 | #define RXCSR_DESC_RT_GAP_256 0x00000000 |
| 244 | #define RXCSR_DESC_RT_GAP_512 0x00001000 |
| 245 | #define RXCSR_DESC_RT_GAP_1024 0x00002000 |
| 246 | #define RXCSR_DESC_RT_GAP_2048 0x00003000 |
| 247 | #define RXCSR_DESC_RT_GAP_4096 0x00004000 |
| 248 | #define RXCSR_DESC_RT_GAP_8192 0x00005000 |
| 249 | #define RXCSR_DESC_RT_GAP_16384 0x00006000 |
| 250 | #define RXCSR_DESC_RT_GAP_32768 0x00007000 |
| 251 | #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 |
| 252 | #define RXCSR_DESC_RT_CNT_SHIFT 8 |
| 253 | #define RXCSR_PASS_WAKEUP_PKT 0x00000040 |
| 254 | #define RXCSR_PASS_MAGIC_PKT 0x00000020 |
| 255 | #define RXCSR_PASS_RUNT_PKT 0x00000010 |
| 256 | #define RXCSR_PASS_BAD_PKT 0x00000008 |
| 257 | #define RXCSR_RXQ_START 0x00000004 |
| 258 | #define RXCSR_RX_SUSPEND 0x00000002 |
| 259 | #define RXCSR_RX_ENB 0x00000001 |
| 260 | |
| 261 | #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) |
| 262 | #define RXCSR_RXQ0 0 |
| 263 | #define RXCSR_RXQ1 1 |
| 264 | #define RXCSR_RXQ2 2 |
| 265 | #define RXCSR_RXQ3 3 |
| 266 | #define RXCSR_DESC_RT_CNT(x) \ |
| 267 | ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) |
| 268 | #define RXCSR_DESC_RT_CNT_DEFAULT 32 |
| 269 | |
| 270 | /* Rx queue descriptor base address. 16bytes alignment needed. */ |
| 271 | #define JME_RXDBA_LO 0x0024 |
| 272 | #define JME_RXDBA_HI 0x0028 |
| 273 | |
| 274 | /* Rx queue descriptor count. multiple of 16(max = 1024). */ |
| 275 | #define JME_RXQDC 0x002C |
| 276 | #define RXQDC_MASK 0x0000007F0 |
| 277 | |
| 278 | /* Rx queue next descriptor address. */ |
| 279 | #define JME_RXNDA 0x0030 |
| 280 | #define RXNDA_ADDR_MASK 0xFFFFFFF0 |
| 281 | #define RXNDA_DESC_EMPTY 0x00000008 |
| 282 | #define RXNDA_DESC_VALID 0x00000004 |
| 283 | #define RXNDA_DESC_WAIT 0x00000002 |
| 284 | #define RXNDA_DESC_FETCH 0x00000001 |
| 285 | |
| 286 | /* Rx MAC control and status. */ |
| 287 | #define JME_RXMAC 0x0034 |
| 288 | #define 0x00000000 |
| 289 | #define 0x00010000 |
| 290 | #define 0x00020000 |
| 291 | #define 0x00030000 |
| 292 | #define RXMAC_PROMISC 0x00000800 |
| 293 | #define RXMAC_BROADCAST 0x00000400 |
| 294 | #define RXMAC_MULTICAST 0x00000200 |
| 295 | #define RXMAC_UNICAST 0x00000100 |
| 296 | #define RXMAC_ALLMULTI 0x00000080 |
| 297 | #define RXMAC_MULTICAST_FILTER 0x00000040 |
| 298 | #define RXMAC_COLL_DET_ENB 0x00000020 |
| 299 | #define RXMAC_FC_ENB 0x00000008 |
| 300 | #define RXMAC_VLAN_ENB 0x00000004 |
| 301 | #define RXMAC_PAD_10BYTES 0x00000002 |
| 302 | #define RXMAC_CSUM_ENB 0x00000001 |
| 303 | |
| 304 | /* Rx unicast MAC address. */ |
| 305 | #define JME_PAR0 0x0038 |
| 306 | #define JME_PAR1 0x003C |
| 307 | |
| 308 | /* Rx multicast address hash table. */ |
| 309 | #define JME_MAR0 0x0040 |
| 310 | #define JME_MAR1 0x0044 |
| 311 | |
| 312 | /* Wakeup frame output data port. */ |
| 313 | #define JME_WFODP 0x0048 |
| 314 | |
| 315 | /* Wakeup frame output interface. */ |
| 316 | #define JME_WFOI 0x004C |
| 317 | #define WFOI_MASK_0_31 0x00000000 |
| 318 | #define WFOI_MASK_31_63 0x00000010 |
| 319 | #define WFOI_MASK_64_95 0x00000020 |
| 320 | #define WFOI_MASK_96_127 0x00000030 |
| 321 | #define WFOI_MASK_SEL 0x00000008 |
| 322 | #define WFOI_CRC_SEL 0x00000000 |
| 323 | #define WFOI_WAKEUP_FRAME_MASK 0x00000007 |
| 324 | #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) |
| 325 | |
| 326 | /* Station management interface. */ |
| 327 | #define JME_SMI 0x0050 |
| 328 | #define SMI_DATA_MASK 0xFFFF0000 |
| 329 | #define SMI_DATA_SHIFT 16 |
| 330 | #define SMI_REG_ADDR_MASK 0x0000F800 |
| 331 | #define SMI_REG_ADDR_SHIFT 11 |
| 332 | #define SMI_PHY_ADDR_MASK 0x000007C0 |
| 333 | #define SMI_PHY_ADDR_SHIFT 6 |
| 334 | #define SMI_OP_WRITE 0x00000020 |
| 335 | #define SMI_OP_READ 0x00000000 |
| 336 | #define SMI_OP_EXECUTE 0x00000010 |
| 337 | #define SMI_MDIO 0x00000008 |
| 338 | #define SMI_MDOE 0x00000004 |
| 339 | #define SMI_MDC 0x00000002 |
| 340 | #define SMI_MDEN 0x00000001 |
| 341 | #define SMI_REG_ADDR(x) \ |
| 342 | (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) |
| 343 | #define SMI_PHY_ADDR(x) \ |
| 344 | (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) |
| 345 | |
| 346 | /* Global host control. */ |
| 347 | #define JME_GHC 0x0054 |
| 348 | #define GHC_LOOPBACK 0x80000000 |
| 349 | #define GHC_RESET 0x40000000 |
| 350 | #define GHC_CLKSRC_10_100 0x00a00000 |
| 351 | #define GHC_CLKSRC_1000 0x00500000 |
| 352 | #define GHC_CLKSRC_MASK 0x00f00000 |
| 353 | #define GHC_FULL_DUPLEX 0x00000040 |
| 354 | #define GHC_SPEED_UNKNOWN 0x00000000 |
| 355 | #define GHC_SPEED_10 0x00000010 |
| 356 | #define GHC_SPEED_100 0x00000020 |
| 357 | #define GHC_SPEED_1000 0x00000030 |
| 358 | #define GHC_SPEED_MASK 0x00000030 |
| 359 | #define GHC_LINK_OFF 0x00000004 |
| 360 | #define GHC_LINK_ON 0x00000002 |
| 361 | #define GHC_LINK_STAT_POLLING 0x00000001 |
| 362 | |
| 363 | /* Power management control and status. */ |
| 364 | #define JME_PMCS 0x0060 |
| 365 | #define PMCS_WAKEUP_FRAME_7 0x80000000 |
| 366 | #define PMCS_WAKEUP_FRAME_6 0x40000000 |
| 367 | #define PMCS_WAKEUP_FRAME_5 0x20000000 |
| 368 | #define PMCS_WAKEUP_FRAME_4 0x10000000 |
| 369 | #define PMCS_WAKEUP_FRAME_3 0x08000000 |
| 370 | #define PMCS_WAKEUP_FRAME_2 0x04000000 |
| 371 | #define PMCS_WAKEUP_FRAME_1 0x02000000 |
| 372 | #define PMCS_WAKEUP_FRAME_0 0x01000000 |
| 373 | #define PMCS_LINK_FAIL 0x00040000 |
| 374 | #define PMCS_LINK_RISING 0x00020000 |
| 375 | #define PMCS_MAGIC_FRAME 0x00010000 |
| 376 | #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 |
| 377 | #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 |
| 378 | #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 |
| 379 | #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 |
| 380 | #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 |
| 381 | #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 |
| 382 | #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 |
| 383 | #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 |
| 384 | #define PMCS_LINK_FAIL_ENB 0x00000004 |
| 385 | #define PMCS_LINK_RISING_ENB 0x00000002 |
| 386 | #define PMCS_MAGIC_FRAME_ENB 0x00000001 |
| 387 | #define PMCS_WOL_ENB_MASK 0x0000FFFF |
| 388 | |
| 389 | |
| 390 | #define JME_PHY_EEPROM_BASE_MEMOFF 0x0400 |
| 391 | #define JME_PHY_EEPROM_BASE_IOOFF 0x0000 |
| 392 | #define JME_PHY_EEPROM_SIZE 0x0080 |
| 393 | /* Giga PHY & EEPROM registers. */ |
| 394 | #define JME_PHY_EEPROM_BASE_ADDR 0x00 |
| 395 | |
| 396 | #define JME_GIGAR0LO 0x00 |
| 397 | #define JME_GIGAR0HI 0x04 |
| 398 | #define JME_GIGARALO 0x08 |
| 399 | #define JME_GIGARAHI 0x0C |
| 400 | #define JME_GIGARBLO 0x10 |
| 401 | #define JME_GIGARBHI 0x14 |
| 402 | #define JME_GIGARCLO 0x18 |
| 403 | #define JME_GIGARCHI 0x1C |
| 404 | #define JME_GIGARDLO 0x20 |
| 405 | #define JME_GIGARDHI 0x24 |
| 406 | |
| 407 | /* BIST status and control. */ |
| 408 | #define JME_GIGACSR 0x28 |
| 409 | #define GIGACSR_STATUS 0x40000000 |
| 410 | #define GIGACSR_CTRL_MASK 0x30000000 |
| 411 | #define GIGACSR_CTRL_DEFAULT 0x30000000 |
| 412 | #define GIGACSR_TX_CLK_MASK 0x0F000000 |
| 413 | #define GIGACSR_RX_CLK_MASK 0x00F00000 |
| 414 | #define GIGACSR_TX_CLK_INV 0x00080000 |
| 415 | #define GIGACSR_RX_CLK_INV 0x00040000 |
| 416 | #define GIGACSR_PHY_RST 0x00010000 |
| 417 | #define GIGACSR_IRQ_N_O 0x00001000 |
| 418 | #define GIGACSR_BIST_OK 0x00000200 |
| 419 | #define GIGACSR_BIST_DONE 0x00000100 |
| 420 | #define GIGACSR_BIST_LED_ENB 0x00000010 |
| 421 | #define GIGACSR_BIST_MASK 0x00000003 |
| 422 | |
| 423 | /* PHY Link Status. */ |
| 424 | #define JME_LNKSTS 0x30 |
| 425 | #define LINKSTS_SPEED_10 0x00000000 |
| 426 | #define LINKSTS_SPEED_100 0x00004000 |
| 427 | #define LINKSTS_SPEED_1000 0x00008000 |
| 428 | #define LINKSTS_FULL_DUPLEX 0x00002000 |
| 429 | #define LINKSTS_PAGE_RCVD 0x00001000 |
| 430 | #define LINKSTS_SPDDPX_RESOLVED 0x00000800 |
| 431 | #define LINKSTS_UP 0x00000400 |
| 432 | #define LINKSTS_ANEG_COMP 0x00000200 |
| 433 | #define LINKSTS_MDI_CROSSOVR 0x00000040 |
| 434 | #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 |
| 435 | #define LINKSTS_LPAR_PAUSE 0x00000001 |
| 436 | |
| 437 | /* SMB control and status. */ |
| 438 | #define JME_SMBCSR 0x40 |
| 439 | #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 |
| 440 | #define SMBCSR_WR_DATA_NACK 0x00040000 |
| 441 | #define SMBCSR_CMD_NACK 0x00020000 |
| 442 | #define SMBCSR_RELOAD 0x00010000 |
| 443 | #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 |
| 444 | #define SMBCSR_SCL_STAT 0x00000080 |
| 445 | #define SMBCSR_SDA_STAT 0x00000040 |
| 446 | #define SMBCSR_EEPROM_PRESENT 0x00000020 |
| 447 | #define SMBCSR_INIT_LD_DONE 0x00000010 |
| 448 | #define SMBCSR_HW_BUSY_MASK 0x0000000F |
| 449 | #define SMBCSR_HW_IDLE 0x00000000 |
| 450 | |
| 451 | /* SMB interface. */ |
| 452 | #define JME_SMBINTF 0x44 |
| 453 | #define SMBINTF_RD_DATA_MASK 0xFF000000 |
| 454 | #define SMBINTF_RD_DATA_SHIFT 24 |
| 455 | #define SMBINTF_WR_DATA_MASK 0x00FF0000 |
| 456 | #define SMBINTF_WR_DATA_SHIFT 16 |
| 457 | #define SMBINTF_ADDR_MASK 0x0000FF00 |
| 458 | #define SMBINTF_ADDR_SHIFT 8 |
| 459 | #define SMBINTF_RD 0x00000020 |
| 460 | #define SMBINTF_WR 0x00000000 |
| 461 | #define SMBINTF_CMD_TRIGGER 0x00000010 |
| 462 | #define SMBINTF_BUSY 0x00000010 |
| 463 | #define SMBINTF_FAST_MODE 0x00000008 |
| 464 | #define SMBINTF_GPIO_SCL 0x00000004 |
| 465 | #define SMBINTF_GPIO_SDA 0x00000002 |
| 466 | #define SMBINTF_GPIO_ENB 0x00000001 |
| 467 | |
| 468 | #define JME_EEPROM_SIG0 0x55 |
| 469 | #define JME_EEPROM_SIG1 0xAA |
| 470 | #define JME_EEPROM_DESC_BYTES 3 |
| 471 | #define JME_EEPROM_DESC_END 0x80 |
| 472 | #define JME_EEPROM_FUNC_MASK 0x70 |
| 473 | #define JME_EEPROM_FUNC_SHIFT 4 |
| 474 | #define JME_EEPROM_PAGE_MASK 0x0F |
| 475 | #define JME_EEPROM_PAGE_SHIFT 0 |
| 476 | |
| 477 | #define JME_EEPROM_FUNC0 0 |
| 478 | /* PCI configuration space. */ |
| 479 | #define JME_EEPROM_PAGE_BAR0 0 |
| 480 | /* 128 bytes I/O window. */ |
| 481 | #define JME_EEPROM_PAGE_BAR1 1 |
| 482 | /* 256 bytes I/O window. */ |
| 483 | #define JME_EEPROM_PAGE_BAR2 2 |
| 484 | |
| 485 | #define JME_EEPROM_END 0xFF |
| 486 | |
| 487 | #define JME_EEPROM_MKDESC(f, p) \ |
| 488 | ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ |
| 489 | (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) |
| 490 | |
| 491 | /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ |
| 492 | #define JME_EEPINTF 0x48 |
| 493 | #define EEPINTF_DATA_MASK 0xFFFF0000 |
| 494 | #define EEPINTF_DATA_SHIFT 16 |
| 495 | #define EEPINTF_ADDR_MASK 0x0000FC00 |
| 496 | #define EEPINTF_ADDR_SHIFT 10 |
| 497 | #define EEPRINTF_OP_MASK 0x00000300 |
| 498 | #define EEPINTF_OP_EXECUTE 0x00000080 |
| 499 | #define EEPINTF_DATA_OUT 0x00000008 |
| 500 | #define EEPINTF_DATA_IN 0x00000004 |
| 501 | #define EEPINTF_CLK 0x00000002 |
| 502 | #define EEPINTF_SEL 0x00000001 |
| 503 | |
| 504 | /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ |
| 505 | #define JME_EEPCSR 0x4C |
| 506 | #define EEPCSR_EEPROM_RELOAD 0x00000002 |
| 507 | #define EEPCSR_EEPROM_PRESENT 0x00000001 |
| 508 | |
| 509 | /* Misc registers. */ |
| 510 | #define JME_MISC_BASE_MEMOFF 0x800 |
| 511 | #define JME_MISC_BASE_IOOFF 0x080 |
| 512 | #define JME_MISC_SIZE 0x080 |
| 513 | |
| 514 | /* Timer control and status. */ |
| 515 | #define JME_TMCSR 0x00 |
| 516 | #define TMCSR_SW_INTR 0x80000000 |
| 517 | #define TMCSR_TIMER_INTR 0x10000000 |
| 518 | #define TMCSR_TIMER_ENB 0x01000000 |
| 519 | #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF |
| 520 | |
| 521 | /* GPIO control and status. */ |
| 522 | #define JME_GPIO 0x04 |
| 523 | #define GPIO_4_SPI_IN 0x80000000 |
| 524 | #define GPIO_3_SPI_IN 0x40000000 |
| 525 | #define GPIO_4_SPI_OUT 0x20000000 |
| 526 | #define GPIO_4_SPI_OUT_ENB 0x10000000 |
| 527 | #define GPIO_3_SPI_OUT 0x08000000 |
| 528 | #define GPIO_3_SPI_OUT_ENB 0x04000000 |
| 529 | #define GPIO_3_4_LED 0x00000000 |
| 530 | #define GPIO_3_4_GPIO 0x02000000 |
| 531 | #define GPIO_2_CLKREQN_IN 0x00100000 |
| 532 | #define GPIO_2_CLKREQN_OUT 0x00040000 |
| 533 | #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 |
| 534 | #define GPIO_1_LED42_IN 0x00001000 |
| 535 | #define GPIO_1_LED42_OUT 0x00000400 |
| 536 | #define GPIO_1_LED42_OUT_ENB 0x00000200 |
| 537 | #define GPIO_1_LED42_ENB 0x00000100 |
| 538 | #define GPIO_0_SDA_IN 0x00000010 |
| 539 | #define GPIO_0_SDA_OUT 0x00000004 |
| 540 | #define GPIO_0_SDA_OUT_ENB 0x00000002 |
| 541 | #define GPIO_0_SDA_ENB 0x00000001 |
| 542 | |
| 543 | /* General purpose register 0. */ |
| 544 | #define JME_GPREG0 0x08 |
| 545 | #define GPREG0_SH_POST_DW7_DIS 0x80000000 |
| 546 | #define GPREG0_SH_POST_DW6_DIS 0x40000000 |
| 547 | #define GPREG0_SH_POST_DW5_DIS 0x20000000 |
| 548 | #define GPREG0_SH_POST_DW4_DIS 0x10000000 |
| 549 | #define GPREG0_SH_POST_DW3_DIS 0x08000000 |
| 550 | #define GPREG0_SH_POST_DW2_DIS 0x04000000 |
| 551 | #define GPREG0_SH_POST_DW1_DIS 0x02000000 |
| 552 | #define GPREG0_SH_POST_DW0_DIS 0x01000000 |
| 553 | #define GPREG0_DMA_RD_REQ_8 0x00000000 |
| 554 | #define GPREG0_DMA_RD_REQ_6 0x00100000 |
| 555 | #define GPREG0_DMA_RD_REQ_5 0x00200000 |
| 556 | #define GPREG0_DMA_RD_REQ_4 0x00300000 |
| 557 | #define GPREG0_POST_DW0_ENB 0x00040000 |
| 558 | #define GPREG0_PCC_CLR_DIS 0x00020000 |
| 559 | #define GPREG0_FORCE_SCL_OUT 0x00010000 |
| 560 | #define GPREG0_DL_RSTB_DIS 0x00008000 |
| 561 | #define GPREG0_STICKY_RESET 0x00004000 |
| 562 | #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 |
| 563 | #define GPREG0_LINK_CHG_POLL 0x00001000 |
| 564 | #define GPREG0_LINK_CHG_DIRECT 0x00000000 |
| 565 | #define GPREG0_MSI_GEN_SEL 0x00000800 |
| 566 | #define GPREG0_SMB_PAD_PU_DIS 0x00000400 |
| 567 | #define GPREG0_PCC_UNIT_16US 0x00000000 |
| 568 | #define GPREG0_PCC_UNIT_256US 0x00000100 |
| 569 | #define GPREG0_PCC_UNIT_US 0x00000200 |
| 570 | #define GPREG0_PCC_UNIT_MS 0x00000300 |
| 571 | #define GPREG0_PCC_UNIT_MASK 0x00000300 |
| 572 | #define GPREG0_INTR_EVENT_ENB 0x00000080 |
| 573 | #define GPREG0_PME_ENB 0x00000020 |
| 574 | #define GPREG0_PHY_ADDR_MASK 0x0000001F |
| 575 | #define GPREG0_PHY_ADDR_SHIFT 0 |
| 576 | #define GPREG0_PHY_ADDR 1 |
| 577 | |
| 578 | /* General purpose register 1. */ |
| 579 | #define JME_GPREG1 0x0C |
| 580 | #define 0x00000040 /* JMC250 A2 */ |
| 581 | #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ |
| 582 | #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ |
| 583 | #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ |
| 584 | #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ |
| 585 | #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ |
| 586 | #define GPREG1_INTDLY_MASK 0x00000007 |
| 587 | |
| 588 | /* MSIX entry number of interrupt source. */ |
| 589 | #define JME_MSINUM_BASE 0x10 |
| 590 | #define JME_MSINUM_END 0x1F |
| 591 | #define MSINUM_MASK 0x7FFFFFFF |
| 592 | #define MSINUM_ENTRY_MASK 7 |
| 593 | #define MSINUM_REG_INDEX(x) ((x) / 8) |
| 594 | #define MSINUM_INTR_SOURCE(x, y) \ |
| 595 | (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) |
| 596 | #define MSINUM_NUM_INTR_SOURCE 32 |
| 597 | |
| 598 | /* Interrupt event status. */ |
| 599 | #define JME_INTR_STATUS 0x20 |
| 600 | #define INTR_SW 0x80000000 |
| 601 | #define INTR_TIMER 0x40000000 |
| 602 | #define INTR_LINKCHG 0x20000000 |
| 603 | #define INTR_PAUSE 0x10000000 |
| 604 | #define INTR_MAGIC_PKT 0x08000000 |
| 605 | #define INTR_WAKEUP_PKT 0x04000000 |
| 606 | #define INTR_RXQ0_COAL_TO 0x02000000 |
| 607 | #define INTR_RXQ1_COAL_TO 0x01000000 |
| 608 | #define INTR_RXQ2_COAL_TO 0x00800000 |
| 609 | #define INTR_RXQ3_COAL_TO 0x00400000 |
| 610 | #define INTR_TXQ_COAL_TO 0x00200000 |
| 611 | #define INTR_RXQ0_COAL 0x00100000 |
| 612 | #define INTR_RXQ1_COAL 0x00080000 |
| 613 | #define INTR_RXQ2_COAL 0x00040000 |
| 614 | #define INTR_RXQ3_COAL 0x00020000 |
| 615 | #define INTR_TXQ_COAL 0x00010000 |
| 616 | #define INTR_RXQ3_DESC_EMPTY 0x00008000 |
| 617 | #define INTR_RXQ2_DESC_EMPTY 0x00004000 |
| 618 | #define INTR_RXQ1_DESC_EMPTY 0x00002000 |
| 619 | #define INTR_RXQ0_DESC_EMPTY 0x00001000 |
| 620 | #define INTR_RXQ3_COMP 0x00000800 |
| 621 | #define INTR_RXQ2_COMP 0x00000400 |
| 622 | #define INTR_RXQ1_COMP 0x00000200 |
| 623 | #define INTR_RXQ0_COMP 0x00000100 |
| 624 | #define INTR_TXQ7_COMP 0x00000080 |
| 625 | #define INTR_TXQ6_COMP 0x00000040 |
| 626 | #define INTR_TXQ5_COMP 0x00000020 |
| 627 | #define INTR_TXQ4_COMP 0x00000010 |
| 628 | #define INTR_TXQ3_COMP 0x00000008 |
| 629 | #define INTR_TXQ2_COMP 0x00000004 |
| 630 | #define INTR_TXQ1_COMP 0x00000002 |
| 631 | #define INTR_TXQ0_COMP 0x00000001 |
| 632 | |
| 633 | #define INTR_RXQ_COAL_TO \ |
| 634 | (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ |
| 635 | INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) |
| 636 | |
| 637 | #define INTR_RXQ_COAL \ |
| 638 | (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ |
| 639 | INTR_RXQ3_COAL) |
| 640 | |
| 641 | #define INTR_RXQ_COMP \ |
| 642 | (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ |
| 643 | INTR_RXQ3_COMP) |
| 644 | |
| 645 | #define INTR_RXQ_DESC_EMPTY \ |
| 646 | (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ |
| 647 | INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) |
| 648 | |
| 649 | #define INTR_RXQ_COMP \ |
| 650 | (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ |
| 651 | INTR_RXQ3_COMP) |
| 652 | |
| 653 | #define INTR_TXQ_COMP \ |
| 654 | (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ |
| 655 | INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ |
| 656 | INTR_TXQ6_COMP | INTR_TXQ7_COMP) |
| 657 | |
| 658 | #define JME_INTRS_ENABLE \ |
| 659 | (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ |
| 660 | INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) |
| 661 | |
| 662 | #define JME_INTRS_CHECK (JME_INTRS_ENABLE | INTR_TXQ_COMP | INTR_RXQ_COMP) |
| 663 | |
| 664 | |
| 665 | #define N_INTR_SW 31 |
| 666 | #define N_INTR_TIMER 30 |
| 667 | #define N_INTR_LINKCHG 29 |
| 668 | #define N_INTR_PAUSE 28 |
| 669 | #define N_INTR_MAGIC_PKT 27 |
| 670 | #define N_INTR_WAKEUP_PKT 26 |
| 671 | #define N_INTR_RXQ0_COAL_TO 25 |
| 672 | #define N_INTR_RXQ1_COAL_TO 24 |
| 673 | #define N_INTR_RXQ2_COAL_TO 23 |
| 674 | #define N_INTR_RXQ3_COAL_TO 22 |
| 675 | #define N_INTR_TXQ_COAL_TO 21 |
| 676 | #define N_INTR_RXQ0_COAL 20 |
| 677 | #define N_INTR_RXQ1_COAL 19 |
| 678 | #define N_INTR_RXQ2_COAL 18 |
| 679 | #define N_INTR_RXQ3_COAL 17 |
| 680 | #define N_INTR_TXQ_COAL 16 |
| 681 | #define N_INTR_RXQ3_DESC_EMPTY 15 |
| 682 | #define N_INTR_RXQ2_DESC_EMPTY 14 |
| 683 | #define N_INTR_RXQ1_DESC_EMPTY 13 |
| 684 | #define N_INTR_RXQ0_DESC_EMPTY 12 |
| 685 | #define N_INTR_RXQ3_COMP 11 |
| 686 | #define N_INTR_RXQ2_COMP 10 |
| 687 | #define N_INTR_RXQ1_COMP 9 |
| 688 | #define N_INTR_RXQ0_COMP 8 |
| 689 | #define N_INTR_TXQ7_COMP 7 |
| 690 | #define N_INTR_TXQ6_COMP 6 |
| 691 | #define N_INTR_TXQ5_COMP 5 |
| 692 | #define N_INTR_TXQ4_COMP 4 |
| 693 | #define N_INTR_TXQ3_COMP 3 |
| 694 | #define N_INTR_TXQ2_COMP 2 |
| 695 | #define N_INTR_TXQ1_COMP 1 |
| 696 | #define N_INTR_TXQ0_COMP 0 |
| 697 | |
| 698 | /* Interrupt request status. */ |
| 699 | #define JME_INTR_REQ_STATUS 0x24 |
| 700 | |
| 701 | /* Interrupt enable - setting port. */ |
| 702 | #define JME_INTR_MASK_SET 0x28 |
| 703 | |
| 704 | /* Interrupt enable - clearing port. */ |
| 705 | #define JME_INTR_MASK_CLR 0x2C |
| 706 | |
| 707 | /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ |
| 708 | #define JME_PCCRX0 0x30 |
| 709 | #define JME_PCCRX1 0x34 |
| 710 | #define JME_PCCRX2 0x38 |
| 711 | #define JME_PCCRX3 0x3C |
| 712 | #define PCCRX_COAL_TO_MASK 0xFFFF0000 |
| 713 | #define PCCRX_COAL_TO_SHIFT 16 |
| 714 | #define PCCRX_COAL_PKT_MASK 0x0000FF00 |
| 715 | #define PCCRX_COAL_PKT_SHIFT 8 |
| 716 | |
| 717 | #define PCCRX_COAL_TO_MIN 1 |
| 718 | #define PCCRX_COAL_TO_DEFAULT 100 |
| 719 | #define PCCRX_COAL_TO_MAX 65535 |
| 720 | |
| 721 | #define PCCRX_COAL_PKT_MIN 1 |
| 722 | #define PCCRX_COAL_PKT_DEFAULT 128 |
| 723 | #define PCCRX_COAL_PKT_MAX 255 |
| 724 | |
| 725 | /* Packet completion coalescing control of Tx queue. */ |
| 726 | #define JME_PCCTX 0x40 |
| 727 | #define PCCTX_COAL_TO_MASK 0xFFFF0000 |
| 728 | #define PCCTX_COAL_TO_SHIFT 16 |
| 729 | #define PCCTX_COAL_PKT_MASK 0x0000FF00 |
| 730 | #define PCCTX_COAL_PKT_SHIFT 8 |
| 731 | #define PCCTX_COAL_TXQ7 0x00000080 |
| 732 | #define PCCTX_COAL_TXQ6 0x00000040 |
| 733 | #define PCCTX_COAL_TXQ5 0x00000020 |
| 734 | #define PCCTX_COAL_TXQ4 0x00000010 |
| 735 | #define PCCTX_COAL_TXQ3 0x00000008 |
| 736 | #define PCCTX_COAL_TXQ2 0x00000004 |
| 737 | #define PCCTX_COAL_TXQ1 0x00000002 |
| 738 | #define PCCTX_COAL_TXQ0 0x00000001 |
| 739 | |
| 740 | #define PCCTX_COAL_TO_MIN 1 |
| 741 | #define PCCTX_COAL_TO_DEFAULT 100 |
| 742 | #define PCCTX_COAL_TO_MAX 65535 |
| 743 | |
| 744 | #define PCCTX_COAL_PKT_MIN 1 |
| 745 | #define PCCTX_COAL_PKT_DEFAULT 128 |
| 746 | #define PCCTX_COAL_PKT_MAX 255 |
| 747 | |
| 748 | /* Chip mode and FPGA version. */ |
| 749 | #define JME_CHIPMODE 0x44 |
| 750 | #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 |
| 751 | #define CHIPMODE_FPGA_REV_SHIFT 16 |
| 752 | #define CHIPMODE_NOT_FPGA 0 |
| 753 | #define CHIPMODE_REV_MASK 0x0000FF00 |
| 754 | #define CHIPMODE_REV_SHIFT 8 |
| 755 | #define CHIPMODE_MODE_48P 0x0000000C |
| 756 | #define CHIPMODE_MODE_64P 0x00000004 |
| 757 | #define CHIPMODE_MODE_128P_MAC 0x00000003 |
| 758 | #define CHIPMODE_MODE_128P_DBG 0x00000002 |
| 759 | #define CHIPMODE_MODE_128P_PHY 0x00000000 |
| 760 | |
| 761 | /* Shadow status base address high/low. */ |
| 762 | #define JME_SHBASE_ADDR_HI 0x48 |
| 763 | #define JME_SHBASE_ADDR_LO 0x4C |
| 764 | #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 |
| 765 | #define SHBASE_POST_FORCE 0x00000002 |
| 766 | #define SHBASE_POST_ENB 0x00000001 |
| 767 | |
| 768 | /* Timer 1 and 2. */ |
| 769 | #define JME_TIMER1 0x70 |
| 770 | #define JME_TIMER2 0x74 |
| 771 | #define TIMER_ENB 0x01000000 |
| 772 | #define TIMER_CNT_MASK 0x00FFFFFF |
| 773 | #define TIMER_CNT_SHIFT 0 |
| 774 | #define TIMER_UNIT 1024 /* 1024us */ |
| 775 | |
| 776 | /* Aggresive power mode control. */ |
| 777 | #define JME_APMC 0x7C |
| 778 | #define APMC_PCIE_SDOWN_STAT 0x80000000 |
| 779 | #define APMC_PCIE_SDOWN_ENB 0x40000000 |
| 780 | #define APMC_PSEUDO_HOT_PLUG 0x20000000 |
| 781 | #define APMC_EXT_PLUGIN_ENB 0x04000000 |
| 782 | #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 |
| 783 | #define APMC_DIS_SRAM 0x00000004 |
| 784 | #define APMC_DIS_CLKPM 0x00000002 |
| 785 | #define APMC_DIS_CLKTX 0x00000001 |
| 786 | |
| 787 | /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ |
| 788 | #define JME_PCCSRX_BASE 0x80 |
| 789 | #define JME_PCCSRX_END 0x8F |
| 790 | #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) |
| 791 | #define PCCSRX_TO_MASK 0xFFFF0000 |
| 792 | #define PCCSRX_TO_SHIFT 16 |
| 793 | #define PCCSRX_PKT_CNT_MASK 0x0000FF00 |
| 794 | #define PCCSRX_PKT_CNT_SHIFT 8 |
| 795 | |
| 796 | /* Packet completion coalesing status of Tx queue. */ |
| 797 | #define JME_PCCSTX 0x90 |
| 798 | #define PCCSTX_TO_MASK 0xFFFF0000 |
| 799 | #define PCCSTX_TO_SHIFT 16 |
| 800 | #define PCCSTX_PKT_CNT_MASK 0x0000FF00 |
| 801 | #define PCCSTX_PKT_CNT_SHIFT 8 |
| 802 | |
| 803 | /* Tx queues empty indicator. */ |
| 804 | #define JME_TXQEMPTY 0x94 |
| 805 | #define TXQEMPTY_TXQ7 0x00000080 |
| 806 | #define TXQEMPTY_TXQ6 0x00000040 |
| 807 | #define TXQEMPTY_TXQ5 0x00000020 |
| 808 | #define TXQEMPTY_TXQ4 0x00000010 |
| 809 | #define TXQEMPTY_TXQ3 0x00000008 |
| 810 | #define TXQEMPTY_TXQ2 0x00000004 |
| 811 | #define TXQEMPTY_TXQ1 0x00000002 |
| 812 | #define TXQEMPTY_TXQ0 0x00000001 |
| 813 | #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) |
| 814 | |
| 815 | /* RSS control registers. */ |
| 816 | #define 0x0C00 |
| 817 | |
| 818 | #define 0x0C00 |
| 819 | #define 0x0000E000 |
| 820 | #define 0x0000A000 |
| 821 | #define 0x0000E000 |
| 822 | #define 0x00001000 |
| 823 | #define 0x00000800 |
| 824 | #define 0x00000400 |
| 825 | #define 0x00000200 |
| 826 | #define 0x00000100 |
| 827 | #define 0x000000F8 |
| 828 | #define 3 |
| 829 | #define 0x00000000 |
| 830 | #define 0x00000001 |
| 831 | #define 0x00000002 |
| 832 | |
| 833 | /* CPU vector. */ |
| 834 | #define 0x0C04 |
| 835 | #define (x) ((1 << (x)) |
| 836 | |
| 837 | /* RSS Hash value. */ |
| 838 | #define 0x0C10 |
| 839 | |
| 840 | #define 0x0C14 |
| 841 | |
| 842 | #define 0x0C18 |
| 843 | |
| 844 | #define 0x0C1C |
| 845 | |
| 846 | /* RSS secret key. */ |
| 847 | #define 0x0C40 |
| 848 | #define 0x0C64 |
| 849 | #define 0x0C67 |
| 850 | #define HASHKEY_NBYTES 40 |
| 851 | #define (x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) |
| 852 | #define (x, y) ((x) << (24 - 8 * ((y) % 4))) |
| 853 | |
| 854 | /* RSS indirection table entries. */ |
| 855 | #define 0x0C80 |
| 856 | #define 0x0CFF |
| 857 | #define 128 |
| 858 | #define (x) (JME_RSSTBL_BASE + ((x) / 4)) |
| 859 | #define (x, y) ((x) << (8 * ((y) % 4))) |
| 860 | |
| 861 | /* MSI-X table. */ |
| 862 | #define JME_MSIX_BASE_ADDR 0x2000 |
| 863 | |
| 864 | #define JME_MSIX_BASE 0x2000 |
| 865 | #define JME_MSIX_END 0x207F |
| 866 | #define JME_MSIX_NENTRY 8 |
| 867 | #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) |
| 868 | #define MSIX_ADDR_HI_OFF 0x00 |
| 869 | #define MSIX_ADDR_LO_OFF 0x04 |
| 870 | #define MSIX_ADDR_LO_MASK 0xFFFFFFFC |
| 871 | #define MSIX_DATA_OFF 0x08 |
| 872 | #define MSIX_VECTOR_OFF 0x0C |
| 873 | #define MSIX_VECTOR_RSVD 0x80000000 |
| 874 | #define MSIX_VECTOR_DIS 0x00000001 |
| 875 | |
| 876 | /* MSI-X PBA. */ |
| 877 | #define JME_MSIX_PBA_BASE_ADDR 0x3000 |
| 878 | |
| 879 | #define JME_MSIX_PBA 0x3000 |
| 880 | #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 |
| 881 | #define MSIX_PBA_RSVD_SHIFT 8 |
| 882 | #define MSIX_PBA_PEND_MASK 0x000000FF |
| 883 | #define MSIX_PBA_PEND_SHIFT 0 |
| 884 | #define MSIX_PBA_PEND_ENTRY7 0x00000080 |
| 885 | #define MSIX_PBA_PEND_ENTRY6 0x00000040 |
| 886 | #define MSIX_PBA_PEND_ENTRY5 0x00000020 |
| 887 | #define MSIX_PBA_PEND_ENTRY4 0x00000010 |
| 888 | #define MSIX_PBA_PEND_ENTRY3 0x00000008 |
| 889 | #define MSIX_PBA_PEND_ENTRY2 0x00000004 |
| 890 | #define MSIX_PBA_PEND_ENTRY1 0x00000002 |
| 891 | #define MSIX_PBA_PEND_ENTRY0 0x00000001 |
| 892 | |
| 893 | #define JME_PHY_OUI 0x001B8C |
| 894 | #define JME_PHY_MODEL 0x21 |
| 895 | #define JME_PHY_REV 0x01 |
| 896 | #define JME_PHY_ADDR 1 |
| 897 | |
| 898 | /* JMC250 shadow status block. */ |
| 899 | struct jme_ssb { |
| 900 | uint32_t dw0; |
| 901 | uint32_t dw1; |
| 902 | uint32_t dw2; |
| 903 | uint32_t dw3; |
| 904 | uint32_t dw4; |
| 905 | uint32_t dw5; |
| 906 | uint32_t dw6; |
| 907 | uint32_t dw7; |
| 908 | }; |
| 909 | |
| 910 | /* JMC250 descriptor structures. */ |
| 911 | struct jme_desc { |
| 912 | uint32_t flags; |
| 913 | uint32_t buflen; |
| 914 | uint32_t addr_hi; |
| 915 | uint32_t addr_lo; |
| 916 | }; |
| 917 | |
| 918 | #define JME_TD_OWN 0x80000000 |
| 919 | #define JME_TD_INTR 0x40000000 |
| 920 | #define JME_TD_64BIT 0x20000000 |
| 921 | #define JME_TD_TCPCSUM 0x10000000 |
| 922 | #define JME_TD_UDPCSUM 0x08000000 |
| 923 | #define JME_TD_IPCSUM 0x04000000 |
| 924 | #define JME_TD_TSO 0x02000000 |
| 925 | #define JME_TD_VLAN_TAG 0x01000000 |
| 926 | #define JME_TD_VLAN_MASK 0x0000FFFF |
| 927 | |
| 928 | #define JME_TD_MSS_MASK 0xFFFC0000 |
| 929 | #define JME_TD_MSS_SHIFT 18 |
| 930 | #define JME_TD_BUF_LEN_MASK 0x0000FFFF |
| 931 | #define JME_TD_BUF_LEN_SHIFT 0 |
| 932 | |
| 933 | #define JME_TD_FRAME_LEN_MASK 0x0000FFFF |
| 934 | #define JME_TD_FRAME_LEN_SHIFT 0 |
| 935 | |
| 936 | /* |
| 937 | * Only the first Tx descriptor of a packet is updated |
| 938 | * after packet transmission. |
| 939 | */ |
| 940 | #define JME_TD_TMOUT 0x20000000 |
| 941 | #define JME_TD_RETRY_EXP 0x10000000 |
| 942 | #define JME_TD_COLLISION 0x08000000 |
| 943 | #define JME_TD_UNDERRUN 0x04000000 |
| 944 | #define JME_TD_EHDR_SIZE_MASK 0x000000FF |
| 945 | #define JME_TD_EHDR_SIZE_SHIFT 0 |
| 946 | |
| 947 | #define JME_TD_SEG_CNT_MASK 0xFFFF0000 |
| 948 | #define JME_TD_SEG_CNT_SHIFT 16 |
| 949 | #define JME_TD_RETRY_CNT_MASK 0x0000FFFF |
| 950 | #define JME_TD_RETRY_CNT_SHIFT 0 |
| 951 | |
| 952 | #define JME_RD_OWN 0x80000000 |
| 953 | #define JME_RD_INTR 0x40000000 |
| 954 | #define JME_RD_64BIT 0x20000000 |
| 955 | |
| 956 | #define JME_RD_BUF_LEN_MASK 0x0000FFFF |
| 957 | #define JME_RD_BUF_LEN_SHIFT 0 |
| 958 | |
| 959 | /* |
| 960 | * Only the first Rx descriptor of a packet is updated |
| 961 | * after packet reception. |
| 962 | */ |
| 963 | #define JME_RD_MORE_FRAG 0x20000000 |
| 964 | #define JME_RD_TCP 0x10000000 |
| 965 | #define JME_RD_UDP 0x08000000 |
| 966 | #define JME_RD_IPCSUM 0x04000000 |
| 967 | #define JME_RD_TCPCSUM 0x02000000 |
| 968 | #define JME_RD_UDPCSUM 0x01000000 |
| 969 | #define JME_RD_VLAN_TAG 0x00800000 |
| 970 | #define JME_RD_IPV4 0x00400000 |
| 971 | #define JME_RD_IPV6 0x00200000 |
| 972 | #define JME_RD_PAUSE 0x00100000 |
| 973 | #define JME_RD_MAGIC 0x00080000 |
| 974 | #define JME_RD_WAKEUP 0x00040000 |
| 975 | #define JME_RD_BCAST 0x00030000 |
| 976 | #define JME_RD_MCAST 0x00020000 |
| 977 | #define JME_RD_UCAST 0x00010000 |
| 978 | #define JME_RD_VLAN_MASK 0x0000FFFF |
| 979 | #define JME_RD_VLAN_SHIFT 0 |
| 980 | #define JME_RD_TCPV4 (JME_RD_IPV4|JME_RD_TCP) |
| 981 | #define JME_RD_UDPV4 (JME_RD_IPV4|JME_RD_UDP) |
| 982 | #define JME_RD_TCPV6 (JME_RD_IPV6|JME_RD_TCP) |
| 983 | #define JME_RD_UDPV6 (JME_RD_IPV6|JME_RD_UDP) |
| 984 | |
| 985 | #define JME_RD_VALID 0x80000000 |
| 986 | #define JME_RD_CNT_MASK 0x7F000000 |
| 987 | #define JME_RD_CNT_SHIFT 24 |
| 988 | #define JME_RD_GIANT 0x00800000 |
| 989 | #define JME_RD_GMII_ERR 0x00400000 |
| 990 | #define JME_RD_NBL_RCVD 0x00200000 |
| 991 | #define JME_RD_COLL 0x00100000 |
| 992 | #define JME_RD_ABORT 0x00080000 |
| 993 | #define JME_RD_RUNT 0x00040000 |
| 994 | #define JME_RD_FIFO_OVRN 0x00020000 |
| 995 | #define JME_RD_CRC_ERR 0x00010000 |
| 996 | #define JME_RD_FRAME_LEN_MASK 0x0000FFFF |
| 997 | |
| 998 | #define JME_RX_ERR_STAT \ |
| 999 | (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ |
| 1000 | JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ |
| 1001 | JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) |
| 1002 | |
| 1003 | #define JME_RD_ERR_MASK 0x00FF0000 |
| 1004 | #define JME_RD_ERR_SHIFT 16 |
| 1005 | #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) |
| 1006 | #define JME_RX_ERR_BITS "\20" \ |
| 1007 | "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ |
| 1008 | "\5COLL\6NBLRCVD\7GMIIERR\10" |
| 1009 | |
| 1010 | #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) |
| 1011 | #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) |
| 1012 | #define JME_RX_PAD_BYTES 10 |
| 1013 | |
| 1014 | #define 0xFFFFFFFF |
| 1015 | |
| 1016 | #define 0x00003F00 |
| 1017 | #define 8 |
| 1018 | #define 0x00000000 |
| 1019 | #define 0x00000100 |
| 1020 | #define 0x00000200 |
| 1021 | #define 0x00000400 |
| 1022 | #define 0x00001000 |
| 1023 | #define JME_RD_HASH_FN_NONE 0x00000000 |
| 1024 | #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 |
| 1025 | |
| 1026 | #define JME_MAX_TX_LEN 65535 |
| 1027 | #define JME_MAX_RX_LEN 65535 |
| 1028 | |
| 1029 | #define JME_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) |
| 1030 | #define JME_ADDR_HI(x) ((uint64_t) (x) >> 32) |
| 1031 | |
| 1032 | /* |
| 1033 | * JMC250 can't handle Tx checksum offload/TSO if frame length |
| 1034 | * is larger than its FIFO size(2K). It's also good idea to not |
| 1035 | * use jumbo frame if hardware is running at half-duplex media. |
| 1036 | * Because the jumbo frame may not fit into the Tx FIFO, |
| 1037 | * collisions make hardware fetch frame from host memory with |
| 1038 | * DMA again which in turn slows down Tx performance |
| 1039 | * significantly. |
| 1040 | */ |
| 1041 | #define JME_TX_FIFO_SIZE 2000 |
| 1042 | /* |
| 1043 | * JMC250 has just 4K Rx FIFO. To support jumbo frame that is |
| 1044 | * larger than 4K bytes in length, Rx FIFO threshold should be |
| 1045 | * adjusted to minimize Rx FIFO overrun. |
| 1046 | */ |
| 1047 | #define JME_RX_FIFO_SIZE 4000 |
| 1048 | |
| 1049 | #endif |
| 1050 | |