| 1 | /* $NetBSD: cs4280.c,v 1.69 2016/07/07 06:55:41 msaitoh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by Tatoku Ogaito |
| 17 | * for the NetBSD Project. |
| 18 | * 4. The name of the author may not be used to endorse or promote products |
| 19 | * derived from this software without specific prior written permission |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 31 | */ |
| 32 | |
| 33 | /* |
| 34 | * Cirrus Logic CS4280 (and maybe CS461x) driver. |
| 35 | * Data sheets can be found |
| 36 | * http://www.cirrus.com/ftp/pubs/4280.pdf |
| 37 | * http://www.cirrus.com/ftp/pubs/4297.pdf |
| 38 | * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf |
| 39 | * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc |
| 40 | * |
| 41 | * Note: CS4610/CS4611 + CS423x ISA codec should be worked with |
| 42 | * wss* at pnpbios? |
| 43 | * or |
| 44 | * sb* at pnpbios? |
| 45 | * Since I could not find any documents on handling ISA codec, |
| 46 | * clcs does not support those chips. |
| 47 | */ |
| 48 | |
| 49 | /* |
| 50 | * TODO |
| 51 | * Joystick support |
| 52 | */ |
| 53 | |
| 54 | #include <sys/cdefs.h> |
| 55 | __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.69 2016/07/07 06:55:41 msaitoh Exp $" ); |
| 56 | |
| 57 | #include "midi.h" |
| 58 | |
| 59 | #include <sys/param.h> |
| 60 | #include <sys/systm.h> |
| 61 | #include <sys/kernel.h> |
| 62 | #include <sys/fcntl.h> |
| 63 | #include <sys/malloc.h> |
| 64 | #include <sys/device.h> |
| 65 | #include <sys/proc.h> |
| 66 | #include <sys/systm.h> |
| 67 | #include <sys/audioio.h> |
| 68 | #include <sys/bus.h> |
| 69 | #include <sys/bswap.h> |
| 70 | |
| 71 | #include <dev/audio_if.h> |
| 72 | #include <dev/midi_if.h> |
| 73 | #include <dev/mulaw.h> |
| 74 | #include <dev/auconv.h> |
| 75 | |
| 76 | #include <dev/ic/ac97reg.h> |
| 77 | #include <dev/ic/ac97var.h> |
| 78 | |
| 79 | #include <dev/pci/pcidevs.h> |
| 80 | #include <dev/pci/pcivar.h> |
| 81 | #include <dev/pci/cs4280reg.h> |
| 82 | #include <dev/pci/cs4280_image.h> |
| 83 | #include <dev/pci/cs428xreg.h> |
| 84 | #include <dev/pci/cs428x.h> |
| 85 | |
| 86 | #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) |
| 87 | #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) |
| 88 | |
| 89 | /* IF functions for audio driver */ |
| 90 | static int cs4280_match(device_t, cfdata_t, void *); |
| 91 | static void cs4280_attach(device_t, device_t, void *); |
| 92 | static int cs4280_intr(void *); |
| 93 | static int cs4280_query_encoding(void *, struct audio_encoding *); |
| 94 | static int cs4280_set_params(void *, int, int, audio_params_t *, |
| 95 | audio_params_t *, stream_filter_list_t *, |
| 96 | stream_filter_list_t *); |
| 97 | static int cs4280_halt_output(void *); |
| 98 | static int cs4280_halt_input(void *); |
| 99 | static int cs4280_getdev(void *, struct audio_device *); |
| 100 | static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), |
| 101 | void *, const audio_params_t *); |
| 102 | static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), |
| 103 | void *, const audio_params_t *); |
| 104 | static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); |
| 105 | static int cs4280_write_codec(void *, u_int8_t, u_int16_t); |
| 106 | #if 0 |
| 107 | static int cs4280_reset_codec(void *); |
| 108 | #endif |
| 109 | static enum ac97_host_flags cs4280_flags_codec(void *); |
| 110 | |
| 111 | static bool cs4280_resume(device_t, const pmf_qual_t *); |
| 112 | static bool cs4280_suspend(device_t, const pmf_qual_t *); |
| 113 | |
| 114 | /* Internal functions */ |
| 115 | static const struct cs4280_card_t * cs4280_identify_card( |
| 116 | const struct pci_attach_args *); |
| 117 | static int cs4280_piix4_match(const struct pci_attach_args *); |
| 118 | static void cs4280_clkrun_hack(struct cs428x_softc *, int); |
| 119 | static void cs4280_clkrun_hack_init(struct cs428x_softc *); |
| 120 | static void cs4280_set_adc_rate(struct cs428x_softc *, int ); |
| 121 | static void cs4280_set_dac_rate(struct cs428x_softc *, int ); |
| 122 | static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, |
| 123 | uint32_t); |
| 124 | static int cs4280_download_image(struct cs428x_softc *); |
| 125 | static void cs4280_reset(void *); |
| 126 | static int cs4280_init(struct cs428x_softc *, int); |
| 127 | static void cs4280_clear_fifos(struct cs428x_softc *); |
| 128 | |
| 129 | #if CS4280_DEBUG > 10 |
| 130 | /* Thease two function is only for checking image loading is succeeded or not. */ |
| 131 | static int cs4280_check_images(struct cs428x_softc *); |
| 132 | static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, |
| 133 | uint32_t); |
| 134 | #endif |
| 135 | |
| 136 | /* Special cards */ |
| 137 | struct cs4280_card_t |
| 138 | { |
| 139 | pcireg_t id; |
| 140 | enum cs428x_flags flags; |
| 141 | }; |
| 142 | |
| 143 | #define _card(vend, prod, flags) \ |
| 144 | {PCI_ID_CODE(vend, prod), flags} |
| 145 | |
| 146 | static const struct cs4280_card_t cs4280_cards[] = { |
| 147 | #if 0 /* untested, from ALSA driver */ |
| 148 | _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, |
| 149 | CS428X_FLAG_INVAC97EAMP), |
| 150 | #endif |
| 151 | _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, |
| 152 | CS428X_FLAG_INVAC97EAMP), |
| 153 | _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, |
| 154 | CS428X_FLAG_CLKRUNHACK) |
| 155 | }; |
| 156 | |
| 157 | #undef _card |
| 158 | |
| 159 | #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) |
| 160 | |
| 161 | static const struct audio_hw_if cs4280_hw_if = { |
| 162 | NULL, /* open */ |
| 163 | NULL, /* close */ |
| 164 | NULL, |
| 165 | cs4280_query_encoding, |
| 166 | cs4280_set_params, |
| 167 | cs428x_round_blocksize, |
| 168 | NULL, |
| 169 | NULL, |
| 170 | NULL, |
| 171 | NULL, |
| 172 | NULL, |
| 173 | cs4280_halt_output, |
| 174 | cs4280_halt_input, |
| 175 | NULL, |
| 176 | cs4280_getdev, |
| 177 | NULL, |
| 178 | cs428x_mixer_set_port, |
| 179 | cs428x_mixer_get_port, |
| 180 | cs428x_query_devinfo, |
| 181 | cs428x_malloc, |
| 182 | cs428x_free, |
| 183 | cs428x_round_buffersize, |
| 184 | cs428x_mappage, |
| 185 | cs428x_get_props, |
| 186 | cs4280_trigger_output, |
| 187 | cs4280_trigger_input, |
| 188 | NULL, |
| 189 | cs428x_get_locks, |
| 190 | }; |
| 191 | |
| 192 | #if NMIDI > 0 |
| 193 | /* Midi Interface */ |
| 194 | static int cs4280_midi_open(void *, int, void (*)(void *, int), |
| 195 | void (*)(void *), void *); |
| 196 | static void cs4280_midi_close(void*); |
| 197 | static int cs4280_midi_output(void *, int); |
| 198 | static void cs4280_midi_getinfo(void *, struct midi_info *); |
| 199 | |
| 200 | static const struct midi_hw_if cs4280_midi_hw_if = { |
| 201 | cs4280_midi_open, |
| 202 | cs4280_midi_close, |
| 203 | cs4280_midi_output, |
| 204 | cs4280_midi_getinfo, |
| 205 | 0, |
| 206 | cs428x_get_locks, |
| 207 | }; |
| 208 | #endif |
| 209 | |
| 210 | CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), |
| 211 | cs4280_match, cs4280_attach, NULL, NULL); |
| 212 | |
| 213 | static struct audio_device cs4280_device = { |
| 214 | "CS4280" , |
| 215 | "" , |
| 216 | "cs4280" |
| 217 | }; |
| 218 | |
| 219 | |
| 220 | static int |
| 221 | cs4280_match(device_t parent, cfdata_t match, void *aux) |
| 222 | { |
| 223 | struct pci_attach_args *pa; |
| 224 | |
| 225 | pa = (struct pci_attach_args *)aux; |
| 226 | if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) |
| 227 | return 0; |
| 228 | if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 |
| 229 | #if 0 /* I can't confirm */ |
| 230 | || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 |
| 231 | #endif |
| 232 | ) |
| 233 | return 1; |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | static void |
| 238 | cs4280_attach(device_t parent, device_t self, void *aux) |
| 239 | { |
| 240 | struct cs428x_softc *sc; |
| 241 | struct pci_attach_args *pa; |
| 242 | pci_chipset_tag_t pc; |
| 243 | const struct cs4280_card_t *cs_card; |
| 244 | char const *intrstr; |
| 245 | pcireg_t reg; |
| 246 | uint32_t mem; |
| 247 | int error; |
| 248 | char vendor[PCI_VENDORSTR_LEN]; |
| 249 | char product[PCI_PRODUCTSTR_LEN]; |
| 250 | char intrbuf[PCI_INTRSTR_LEN]; |
| 251 | |
| 252 | sc = device_private(self); |
| 253 | sc->sc_dev = self; |
| 254 | pa = (struct pci_attach_args *)aux; |
| 255 | pc = pa->pa_pc; |
| 256 | |
| 257 | pci_aprint_devinfo(pa, "Audio controller" ); |
| 258 | |
| 259 | cs_card = cs4280_identify_card(pa); |
| 260 | if (cs_card != NULL) { |
| 261 | pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); |
| 262 | pci_findproduct(product, sizeof(product), |
| 263 | PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); |
| 264 | aprint_normal_dev(sc->sc_dev, "%s %s\n" , vendor, product); |
| 265 | sc->sc_flags = cs_card->flags; |
| 266 | } else { |
| 267 | sc->sc_flags = CS428X_FLAG_NONE; |
| 268 | } |
| 269 | |
| 270 | sc->sc_pc = pa->pa_pc; |
| 271 | sc->sc_pt = pa->pa_tag; |
| 272 | |
| 273 | /* Map I/O register */ |
| 274 | if (pci_mapreg_map(pa, PCI_BA0, |
| 275 | PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, |
| 276 | &sc->ba0t, &sc->ba0h, NULL, NULL)) { |
| 277 | aprint_error_dev(sc->sc_dev, "can't map BA0 space\n" ); |
| 278 | return; |
| 279 | } |
| 280 | if (pci_mapreg_map(pa, PCI_BA1, |
| 281 | PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, |
| 282 | &sc->ba1t, &sc->ba1h, NULL, NULL)) { |
| 283 | aprint_error_dev(sc->sc_dev, "can't map BA1 space\n" ); |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | sc->sc_dmatag = pa->pa_dmat; |
| 288 | |
| 289 | /* power up chip */ |
| 290 | if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, |
| 291 | pci_activate_null)) && error != EOPNOTSUPP) { |
| 292 | aprint_error_dev(sc->sc_dev, "cannot activate %d\n" , error); |
| 293 | return; |
| 294 | } |
| 295 | |
| 296 | /* Enable the device (set bus master flag) */ |
| 297 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
| 298 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, |
| 299 | reg | PCI_COMMAND_MASTER_ENABLE); |
| 300 | |
| 301 | /* LATENCY_TIMER setting */ |
| 302 | mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); |
| 303 | if ( PCI_LATTIMER(mem) < 32 ) { |
| 304 | mem &= 0xffff00ff; |
| 305 | mem |= 0x00002000; |
| 306 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); |
| 307 | } |
| 308 | |
| 309 | /* CLKRUN hack initialization */ |
| 310 | cs4280_clkrun_hack_init(sc); |
| 311 | |
| 312 | /* Map and establish the interrupt. */ |
| 313 | if (pci_intr_map(pa, &sc->intrh)) { |
| 314 | aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n" ); |
| 315 | return; |
| 316 | } |
| 317 | intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); |
| 318 | |
| 319 | mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); |
| 320 | mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); |
| 321 | |
| 322 | sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, |
| 323 | cs4280_intr, sc); |
| 324 | if (sc->sc_ih == NULL) { |
| 325 | aprint_error_dev(sc->sc_dev, "couldn't establish interrupt" ); |
| 326 | if (intrstr != NULL) |
| 327 | aprint_error(" at %s" , intrstr); |
| 328 | aprint_error("\n" ); |
| 329 | mutex_destroy(&sc->sc_lock); |
| 330 | mutex_destroy(&sc->sc_intr_lock); |
| 331 | return; |
| 332 | } |
| 333 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n" , intrstr); |
| 334 | |
| 335 | /* Initialization */ |
| 336 | if(cs4280_init(sc, 1) != 0) { |
| 337 | mutex_destroy(&sc->sc_lock); |
| 338 | mutex_destroy(&sc->sc_intr_lock); |
| 339 | return; |
| 340 | } |
| 341 | |
| 342 | sc->type = TYPE_CS4280; |
| 343 | sc->halt_input = cs4280_halt_input; |
| 344 | sc->halt_output = cs4280_halt_output; |
| 345 | |
| 346 | /* setup buffer related parameters */ |
| 347 | sc->dma_size = CS4280_DCHUNK; |
| 348 | sc->dma_align = CS4280_DALIGN; |
| 349 | sc->hw_blocksize = CS4280_ICHUNK; |
| 350 | |
| 351 | /* AC 97 attachment */ |
| 352 | sc->host_if.arg = sc; |
| 353 | sc->host_if.attach = cs428x_attach_codec; |
| 354 | sc->host_if.read = cs4280_read_codec; |
| 355 | sc->host_if.write = cs4280_write_codec; |
| 356 | #if 0 |
| 357 | sc->host_if.reset = cs4280_reset_codec; |
| 358 | #else |
| 359 | sc->host_if.reset = NULL; |
| 360 | #endif |
| 361 | sc->host_if.flags = cs4280_flags_codec; |
| 362 | if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { |
| 363 | aprint_error_dev(sc->sc_dev, "ac97_attach failed\n" ); |
| 364 | return; |
| 365 | } |
| 366 | |
| 367 | audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); |
| 368 | |
| 369 | #if NMIDI > 0 |
| 370 | midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); |
| 371 | #endif |
| 372 | |
| 373 | if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) |
| 374 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 375 | } |
| 376 | |
| 377 | /* Interrupt handling function */ |
| 378 | static int |
| 379 | cs4280_intr(void *p) |
| 380 | { |
| 381 | /* |
| 382 | * XXX |
| 383 | * |
| 384 | * Since CS4280 has only 4kB DMA buffer and |
| 385 | * interrupt occurs every 2kB block, I create dummy buffer |
| 386 | * which returns to audio driver and actual DMA buffer |
| 387 | * using in DMA transfer. |
| 388 | * |
| 389 | * |
| 390 | * ring buffer in audio.c is pointed by BUFADDR |
| 391 | * <------ ring buffer size == 64kB ------> |
| 392 | * <-----> blksize == 2048*(sc->sc_[pr]count) kB |
| 393 | * |= = = =|= = = =|= = = =|= = = =|= = = =| |
| 394 | * | | | | | | <- call audio_intp every |
| 395 | * sc->sc_[pr]_count time. |
| 396 | * |
| 397 | * actual DMA buffer is pointed by KERNADDR |
| 398 | * <-> DMA buffer size = 4kB |
| 399 | * |= =| |
| 400 | * |
| 401 | * |
| 402 | */ |
| 403 | struct cs428x_softc *sc; |
| 404 | uint32_t intr, mem; |
| 405 | char * empty_dma; |
| 406 | int handled; |
| 407 | |
| 408 | sc = p; |
| 409 | handled = 0; |
| 410 | |
| 411 | mutex_spin_enter(&sc->sc_intr_lock); |
| 412 | |
| 413 | /* grab interrupt register then clear it */ |
| 414 | intr = BA0READ4(sc, CS4280_HISR); |
| 415 | BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); |
| 416 | |
| 417 | /* not for us ? */ |
| 418 | if ((intr & HISR_INTENA) == 0) { |
| 419 | mutex_spin_exit(&sc->sc_intr_lock); |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | /* Playback Interrupt */ |
| 424 | if (intr & HISR_PINT) { |
| 425 | handled = 1; |
| 426 | mem = BA1READ4(sc, CS4280_PFIE); |
| 427 | BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); |
| 428 | if (sc->sc_prun) { |
| 429 | if ((sc->sc_pi%sc->sc_pcount) == 0) |
| 430 | sc->sc_pintr(sc->sc_parg); |
| 431 | /* copy buffer */ |
| 432 | ++sc->sc_pi; |
| 433 | empty_dma = sc->sc_pdma->addr; |
| 434 | if (sc->sc_pi&1) |
| 435 | empty_dma += sc->hw_blocksize; |
| 436 | memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); |
| 437 | sc->sc_pn += sc->hw_blocksize; |
| 438 | if (sc->sc_pn >= sc->sc_pe) |
| 439 | sc->sc_pn = sc->sc_ps; |
| 440 | } else { |
| 441 | aprint_error_dev(sc->sc_dev, "unexpected play intr\n" ); |
| 442 | } |
| 443 | BA1WRITE4(sc, CS4280_PFIE, mem); |
| 444 | } |
| 445 | /* Capture Interrupt */ |
| 446 | if (intr & HISR_CINT) { |
| 447 | int i; |
| 448 | int16_t rdata; |
| 449 | |
| 450 | handled = 1; |
| 451 | mem = BA1READ4(sc, CS4280_CIE); |
| 452 | BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); |
| 453 | |
| 454 | if (sc->sc_rrun) { |
| 455 | ++sc->sc_ri; |
| 456 | empty_dma = sc->sc_rdma->addr; |
| 457 | if ((sc->sc_ri&1) == 0) |
| 458 | empty_dma += sc->hw_blocksize; |
| 459 | |
| 460 | /* |
| 461 | * XXX |
| 462 | * I think this audio data conversion should be |
| 463 | * happend in upper layer, but I put this here |
| 464 | * since there is no conversion function available. |
| 465 | */ |
| 466 | switch(sc->sc_rparam) { |
| 467 | case CF_16BIT_STEREO: |
| 468 | /* just copy it */ |
| 469 | memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); |
| 470 | sc->sc_rn += sc->hw_blocksize; |
| 471 | break; |
| 472 | case CF_16BIT_MONO: |
| 473 | for (i = 0; i < 512; i++) { |
| 474 | rdata = *((int16_t *)empty_dma)>>1; |
| 475 | empty_dma += 2; |
| 476 | rdata += *((int16_t *)empty_dma)>>1; |
| 477 | empty_dma += 2; |
| 478 | *((int16_t *)sc->sc_rn) = rdata; |
| 479 | sc->sc_rn += 2; |
| 480 | } |
| 481 | break; |
| 482 | case CF_8BIT_STEREO: |
| 483 | for (i = 0; i < 512; i++) { |
| 484 | rdata = *((int16_t*)empty_dma); |
| 485 | empty_dma += 2; |
| 486 | *sc->sc_rn++ = rdata >> 8; |
| 487 | rdata = *((int16_t*)empty_dma); |
| 488 | empty_dma += 2; |
| 489 | *sc->sc_rn++ = rdata >> 8; |
| 490 | } |
| 491 | break; |
| 492 | case CF_8BIT_MONO: |
| 493 | for (i = 0; i < 512; i++) { |
| 494 | rdata = *((int16_t*)empty_dma) >>1; |
| 495 | empty_dma += 2; |
| 496 | rdata += *((int16_t*)empty_dma) >>1; |
| 497 | empty_dma += 2; |
| 498 | *sc->sc_rn++ = rdata >>8; |
| 499 | } |
| 500 | break; |
| 501 | default: |
| 502 | /* Should not reach here */ |
| 503 | aprint_error_dev(sc->sc_dev, |
| 504 | "unknown sc->sc_rparam: %d\n" , |
| 505 | sc->sc_rparam); |
| 506 | } |
| 507 | if (sc->sc_rn >= sc->sc_re) |
| 508 | sc->sc_rn = sc->sc_rs; |
| 509 | } |
| 510 | BA1WRITE4(sc, CS4280_CIE, mem); |
| 511 | |
| 512 | if (sc->sc_rrun) { |
| 513 | if ((sc->sc_ri%(sc->sc_rcount)) == 0) |
| 514 | sc->sc_rintr(sc->sc_rarg); |
| 515 | } else { |
| 516 | aprint_error_dev(sc->sc_dev, |
| 517 | "unexpected record intr\n" ); |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | #if NMIDI > 0 |
| 522 | /* Midi port Interrupt */ |
| 523 | if (intr & HISR_MIDI) { |
| 524 | int data; |
| 525 | |
| 526 | handled = 1; |
| 527 | DPRINTF(("i: %d: " , |
| 528 | BA0READ4(sc, CS4280_MIDSR))); |
| 529 | /* Read the received data */ |
| 530 | while ((sc->sc_iintr != NULL) && |
| 531 | ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { |
| 532 | data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; |
| 533 | DPRINTF(("r:%x\n" ,data)); |
| 534 | sc->sc_iintr(sc->sc_arg, data); |
| 535 | } |
| 536 | |
| 537 | /* Write the data */ |
| 538 | #if 1 |
| 539 | /* XXX: |
| 540 | * It seems "Transmit Buffer Full" never activate until EOI |
| 541 | * is deliverd. Shall I throw EOI top of this routine ? |
| 542 | */ |
| 543 | if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { |
| 544 | DPRINTF(("w: " )); |
| 545 | if (sc->sc_ointr != NULL) |
| 546 | sc->sc_ointr(sc->sc_arg); |
| 547 | } |
| 548 | #else |
| 549 | while ((sc->sc_ointr != NULL) && |
| 550 | ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { |
| 551 | DPRINTF(("w: " )); |
| 552 | sc->sc_ointr(sc->sc_arg); |
| 553 | } |
| 554 | #endif |
| 555 | DPRINTF(("\n" )); |
| 556 | } |
| 557 | #endif |
| 558 | |
| 559 | mutex_spin_exit(&sc->sc_intr_lock); |
| 560 | return handled; |
| 561 | } |
| 562 | |
| 563 | static int |
| 564 | cs4280_query_encoding(void *addr, struct audio_encoding *fp) |
| 565 | { |
| 566 | switch (fp->index) { |
| 567 | case 0: |
| 568 | strcpy(fp->name, AudioEulinear); |
| 569 | fp->encoding = AUDIO_ENCODING_ULINEAR; |
| 570 | fp->precision = 8; |
| 571 | fp->flags = 0; |
| 572 | break; |
| 573 | case 1: |
| 574 | strcpy(fp->name, AudioEmulaw); |
| 575 | fp->encoding = AUDIO_ENCODING_ULAW; |
| 576 | fp->precision = 8; |
| 577 | fp->flags = AUDIO_ENCODINGFLAG_EMULATED; |
| 578 | break; |
| 579 | case 2: |
| 580 | strcpy(fp->name, AudioEalaw); |
| 581 | fp->encoding = AUDIO_ENCODING_ALAW; |
| 582 | fp->precision = 8; |
| 583 | fp->flags = AUDIO_ENCODINGFLAG_EMULATED; |
| 584 | break; |
| 585 | case 3: |
| 586 | strcpy(fp->name, AudioEslinear); |
| 587 | fp->encoding = AUDIO_ENCODING_SLINEAR; |
| 588 | fp->precision = 8; |
| 589 | fp->flags = 0; |
| 590 | break; |
| 591 | case 4: |
| 592 | strcpy(fp->name, AudioEslinear_le); |
| 593 | fp->encoding = AUDIO_ENCODING_SLINEAR_LE; |
| 594 | fp->precision = 16; |
| 595 | fp->flags = 0; |
| 596 | break; |
| 597 | case 5: |
| 598 | strcpy(fp->name, AudioEulinear_le); |
| 599 | fp->encoding = AUDIO_ENCODING_ULINEAR_LE; |
| 600 | fp->precision = 16; |
| 601 | fp->flags = 0; |
| 602 | break; |
| 603 | case 6: |
| 604 | strcpy(fp->name, AudioEslinear_be); |
| 605 | fp->encoding = AUDIO_ENCODING_SLINEAR_BE; |
| 606 | fp->precision = 16; |
| 607 | fp->flags = 0; |
| 608 | break; |
| 609 | case 7: |
| 610 | strcpy(fp->name, AudioEulinear_be); |
| 611 | fp->encoding = AUDIO_ENCODING_ULINEAR_BE; |
| 612 | fp->precision = 16; |
| 613 | fp->flags = 0; |
| 614 | break; |
| 615 | default: |
| 616 | return EINVAL; |
| 617 | } |
| 618 | return 0; |
| 619 | } |
| 620 | |
| 621 | static int |
| 622 | cs4280_set_params(void *addr, int setmode, int usemode, |
| 623 | audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, |
| 624 | stream_filter_list_t *rfil) |
| 625 | { |
| 626 | audio_params_t hw; |
| 627 | struct cs428x_softc *sc; |
| 628 | struct audio_params *p; |
| 629 | stream_filter_list_t *fil; |
| 630 | int mode; |
| 631 | |
| 632 | sc = addr; |
| 633 | for (mode = AUMODE_RECORD; mode != -1; |
| 634 | mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { |
| 635 | if ((setmode & mode) == 0) |
| 636 | continue; |
| 637 | |
| 638 | p = mode == AUMODE_PLAY ? play : rec; |
| 639 | |
| 640 | if (p == play) { |
| 641 | DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n" , |
| 642 | p->sample_rate, p->precision, p->channels)); |
| 643 | /* play back data format may be 8- or 16-bit and |
| 644 | * either stereo or mono. |
| 645 | * playback rate may range from 8000Hz to 48000Hz |
| 646 | */ |
| 647 | if (p->sample_rate < 8000 || p->sample_rate > 48000 || |
| 648 | (p->precision != 8 && p->precision != 16) || |
| 649 | (p->channels != 1 && p->channels != 2) ) { |
| 650 | return EINVAL; |
| 651 | } |
| 652 | } else { |
| 653 | DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n" , |
| 654 | p->sample_rate, p->precision, p->channels)); |
| 655 | /* capture data format must be 16bit stereo |
| 656 | * and sample rate range from 11025Hz to 48000Hz. |
| 657 | * |
| 658 | * XXX: it looks like to work with 8000Hz, |
| 659 | * although data sheets say lower limit is |
| 660 | * 11025 Hz. |
| 661 | */ |
| 662 | |
| 663 | if (p->sample_rate < 8000 || p->sample_rate > 48000 || |
| 664 | (p->precision != 8 && p->precision != 16) || |
| 665 | (p->channels != 1 && p->channels != 2) ) { |
| 666 | return EINVAL; |
| 667 | } |
| 668 | } |
| 669 | fil = mode == AUMODE_PLAY ? pfil : rfil; |
| 670 | hw = *p; |
| 671 | hw.encoding = AUDIO_ENCODING_SLINEAR_LE; |
| 672 | |
| 673 | /* capturing data is slinear */ |
| 674 | switch (p->encoding) { |
| 675 | case AUDIO_ENCODING_SLINEAR_BE: |
| 676 | if (mode == AUMODE_RECORD && p->precision == 16) { |
| 677 | fil->append(fil, swap_bytes, &hw); |
| 678 | } |
| 679 | break; |
| 680 | case AUDIO_ENCODING_SLINEAR_LE: |
| 681 | break; |
| 682 | case AUDIO_ENCODING_ULINEAR_BE: |
| 683 | if (mode == AUMODE_RECORD) { |
| 684 | fil->append(fil, p->precision == 16 |
| 685 | ? swap_bytes_change_sign16 |
| 686 | : change_sign8, &hw); |
| 687 | } |
| 688 | break; |
| 689 | case AUDIO_ENCODING_ULINEAR_LE: |
| 690 | if (mode == AUMODE_RECORD) { |
| 691 | fil->append(fil, p->precision == 16 |
| 692 | ? change_sign16 : change_sign8, |
| 693 | &hw); |
| 694 | } |
| 695 | break; |
| 696 | case AUDIO_ENCODING_ULAW: |
| 697 | if (mode == AUMODE_PLAY) { |
| 698 | hw.precision = 16; |
| 699 | hw.validbits = 16; |
| 700 | fil->append(fil, mulaw_to_linear16, &hw); |
| 701 | } else { |
| 702 | fil->append(fil, linear8_to_mulaw, &hw); |
| 703 | } |
| 704 | break; |
| 705 | case AUDIO_ENCODING_ALAW: |
| 706 | if (mode == AUMODE_PLAY) { |
| 707 | hw.precision = 16; |
| 708 | hw.validbits = 16; |
| 709 | fil->append(fil, alaw_to_linear16, &hw); |
| 710 | } else { |
| 711 | fil->append(fil, linear8_to_alaw, &hw); |
| 712 | } |
| 713 | break; |
| 714 | default: |
| 715 | return EINVAL; |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | /* set sample rate */ |
| 720 | cs4280_set_dac_rate(sc, play->sample_rate); |
| 721 | cs4280_set_adc_rate(sc, rec->sample_rate); |
| 722 | return 0; |
| 723 | } |
| 724 | |
| 725 | static int |
| 726 | cs4280_halt_output(void *addr) |
| 727 | { |
| 728 | struct cs428x_softc *sc; |
| 729 | uint32_t mem; |
| 730 | |
| 731 | sc = addr; |
| 732 | mem = BA1READ4(sc, CS4280_PCTL); |
| 733 | BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); |
| 734 | sc->sc_prun = 0; |
| 735 | cs4280_clkrun_hack(sc, -1); |
| 736 | |
| 737 | return 0; |
| 738 | } |
| 739 | |
| 740 | static int |
| 741 | cs4280_halt_input(void *addr) |
| 742 | { |
| 743 | struct cs428x_softc *sc; |
| 744 | uint32_t mem; |
| 745 | |
| 746 | sc = addr; |
| 747 | mem = BA1READ4(sc, CS4280_CCTL); |
| 748 | BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); |
| 749 | sc->sc_rrun = 0; |
| 750 | cs4280_clkrun_hack(sc, -1); |
| 751 | |
| 752 | return 0; |
| 753 | } |
| 754 | |
| 755 | static int |
| 756 | cs4280_getdev(void *addr, struct audio_device *retp) |
| 757 | { |
| 758 | |
| 759 | *retp = cs4280_device; |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | static int |
| 764 | cs4280_trigger_output(void *addr, void *start, void *end, int blksize, |
| 765 | void (*intr)(void *), void *arg, |
| 766 | const audio_params_t *param) |
| 767 | { |
| 768 | struct cs428x_softc *sc; |
| 769 | uint32_t pfie, pctl, pdtc; |
| 770 | struct cs428x_dma *p; |
| 771 | |
| 772 | sc = addr; |
| 773 | #ifdef DIAGNOSTIC |
| 774 | if (sc->sc_prun) |
| 775 | printf("cs4280_trigger_output: already running\n" ); |
| 776 | #endif |
| 777 | sc->sc_prun = 1; |
| 778 | cs4280_clkrun_hack(sc, 1); |
| 779 | |
| 780 | DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " |
| 781 | "blksize=%d intr=%p(%p)\n" , addr, start, end, blksize, intr, arg)); |
| 782 | sc->sc_pintr = intr; |
| 783 | sc->sc_parg = arg; |
| 784 | |
| 785 | /* stop playback DMA */ |
| 786 | BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); |
| 787 | |
| 788 | /* setup PDTC */ |
| 789 | pdtc = BA1READ4(sc, CS4280_PDTC); |
| 790 | pdtc &= ~PDTC_MASK; |
| 791 | pdtc |= CS4280_MK_PDTC(param->precision * param->channels); |
| 792 | BA1WRITE4(sc, CS4280_PDTC, pdtc); |
| 793 | |
| 794 | DPRINTF(("param: precision=%d channels=%d encoding=%d\n" , |
| 795 | param->precision, param->channels, param->encoding)); |
| 796 | for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) |
| 797 | continue; |
| 798 | if (p == NULL) { |
| 799 | printf("cs4280_trigger_output: bad addr %p\n" , start); |
| 800 | return EINVAL; |
| 801 | } |
| 802 | if (DMAADDR(p) % sc->dma_align != 0 ) { |
| 803 | printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" |
| 804 | "4kB align\n" , (ulong)DMAADDR(p)); |
| 805 | return EINVAL; |
| 806 | } |
| 807 | |
| 808 | sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ |
| 809 | sc->sc_ps = (char *)start; |
| 810 | sc->sc_pe = (char *)end; |
| 811 | sc->sc_pdma = p; |
| 812 | sc->sc_pbuf = KERNADDR(p); |
| 813 | sc->sc_pi = 0; |
| 814 | sc->sc_pn = sc->sc_ps; |
| 815 | if (blksize >= sc->dma_size) { |
| 816 | sc->sc_pn = sc->sc_ps + sc->dma_size; |
| 817 | memcpy(sc->sc_pbuf, start, sc->dma_size); |
| 818 | ++sc->sc_pi; |
| 819 | } else { |
| 820 | sc->sc_pn = sc->sc_ps + sc->hw_blocksize; |
| 821 | memcpy(sc->sc_pbuf, start, sc->hw_blocksize); |
| 822 | } |
| 823 | |
| 824 | /* initiate playback DMA */ |
| 825 | BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); |
| 826 | |
| 827 | /* set PFIE */ |
| 828 | pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; |
| 829 | |
| 830 | if (param->precision == 8) |
| 831 | pfie |= PFIE_8BIT; |
| 832 | if (param->channels == 1) |
| 833 | pfie |= PFIE_MONO; |
| 834 | |
| 835 | if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || |
| 836 | param->encoding == AUDIO_ENCODING_SLINEAR_BE) |
| 837 | pfie |= PFIE_SWAPPED; |
| 838 | if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || |
| 839 | param->encoding == AUDIO_ENCODING_ULINEAR_LE) |
| 840 | pfie |= PFIE_UNSIGNED; |
| 841 | |
| 842 | BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); |
| 843 | |
| 844 | sc->sc_prate = param->sample_rate; |
| 845 | cs4280_set_dac_rate(sc, param->sample_rate); |
| 846 | |
| 847 | pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; |
| 848 | pctl |= sc->pctl; |
| 849 | BA1WRITE4(sc, CS4280_PCTL, pctl); |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | static int |
| 854 | cs4280_trigger_input(void *addr, void *start, void *end, int blksize, |
| 855 | void (*intr)(void *), void *arg, |
| 856 | const audio_params_t *param) |
| 857 | { |
| 858 | struct cs428x_softc *sc; |
| 859 | uint32_t cctl, cie; |
| 860 | struct cs428x_dma *p; |
| 861 | |
| 862 | sc = addr; |
| 863 | #ifdef DIAGNOSTIC |
| 864 | if (sc->sc_rrun) |
| 865 | printf("cs4280_trigger_input: already running\n" ); |
| 866 | #endif |
| 867 | sc->sc_rrun = 1; |
| 868 | cs4280_clkrun_hack(sc, 1); |
| 869 | |
| 870 | DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " |
| 871 | "blksize=%d intr=%p(%p)\n" , addr, start, end, blksize, intr, arg)); |
| 872 | sc->sc_rintr = intr; |
| 873 | sc->sc_rarg = arg; |
| 874 | |
| 875 | /* stop capture DMA */ |
| 876 | BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); |
| 877 | |
| 878 | for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) |
| 879 | continue; |
| 880 | if (p == NULL) { |
| 881 | printf("cs4280_trigger_input: bad addr %p\n" , start); |
| 882 | return EINVAL; |
| 883 | } |
| 884 | if (DMAADDR(p) % sc->dma_align != 0) { |
| 885 | printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" |
| 886 | "4kB align\n" , (ulong)DMAADDR(p)); |
| 887 | return EINVAL; |
| 888 | } |
| 889 | |
| 890 | sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ |
| 891 | sc->sc_rs = (char *)start; |
| 892 | sc->sc_re = (char *)end; |
| 893 | sc->sc_rdma = p; |
| 894 | sc->sc_rbuf = KERNADDR(p); |
| 895 | sc->sc_ri = 0; |
| 896 | sc->sc_rn = sc->sc_rs; |
| 897 | |
| 898 | /* initiate capture DMA */ |
| 899 | BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); |
| 900 | |
| 901 | /* setup format information for internal converter */ |
| 902 | sc->sc_rparam = 0; |
| 903 | if (param->precision == 8) { |
| 904 | sc->sc_rparam += CF_8BIT; |
| 905 | sc->sc_rcount <<= 1; |
| 906 | } |
| 907 | if (param->channels == 1) { |
| 908 | sc->sc_rparam += CF_MONO; |
| 909 | sc->sc_rcount <<= 1; |
| 910 | } |
| 911 | |
| 912 | /* set CIE */ |
| 913 | cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; |
| 914 | BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); |
| 915 | |
| 916 | sc->sc_rrate = param->sample_rate; |
| 917 | cs4280_set_adc_rate(sc, param->sample_rate); |
| 918 | |
| 919 | cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; |
| 920 | cctl |= sc->cctl; |
| 921 | BA1WRITE4(sc, CS4280_CCTL, cctl); |
| 922 | return 0; |
| 923 | } |
| 924 | |
| 925 | static bool |
| 926 | cs4280_suspend(device_t dv, const pmf_qual_t *qual) |
| 927 | { |
| 928 | struct cs428x_softc *sc = device_private(dv); |
| 929 | |
| 930 | mutex_exit(&sc->sc_lock); |
| 931 | mutex_spin_enter(&sc->sc_intr_lock); |
| 932 | |
| 933 | if (sc->sc_prun) { |
| 934 | sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); |
| 935 | sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); |
| 936 | sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); |
| 937 | sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); |
| 938 | DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n" , |
| 939 | sc->sc_suspend_state.cs4280.pctl, |
| 940 | sc->sc_suspend_state.cs4280.pfie, |
| 941 | sc->sc_suspend_state.cs4280.pba, |
| 942 | sc->sc_suspend_state.cs4280.pdtc)); |
| 943 | } |
| 944 | |
| 945 | /* save current capture status */ |
| 946 | if (sc->sc_rrun) { |
| 947 | sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); |
| 948 | sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); |
| 949 | sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); |
| 950 | DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n" , |
| 951 | sc->sc_suspend_state.cs4280.cctl, |
| 952 | sc->sc_suspend_state.cs4280.cie, |
| 953 | sc->sc_suspend_state.cs4280.cba)); |
| 954 | } |
| 955 | |
| 956 | /* Stop DMA */ |
| 957 | BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); |
| 958 | BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); |
| 959 | |
| 960 | mutex_spin_exit(&sc->sc_intr_lock); |
| 961 | mutex_exit(&sc->sc_lock); |
| 962 | |
| 963 | return true; |
| 964 | } |
| 965 | |
| 966 | static bool |
| 967 | cs4280_resume(device_t dv, const pmf_qual_t *qual) |
| 968 | { |
| 969 | struct cs428x_softc *sc = device_private(dv); |
| 970 | |
| 971 | mutex_exit(&sc->sc_lock); |
| 972 | mutex_spin_enter(&sc->sc_intr_lock); |
| 973 | cs4280_init(sc, 0); |
| 974 | #if 0 |
| 975 | cs4280_reset_codec(sc); |
| 976 | #endif |
| 977 | |
| 978 | /* restore DMA related status */ |
| 979 | if(sc->sc_prun) { |
| 980 | DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n" , |
| 981 | sc->sc_suspend_state.cs4280.pctl, |
| 982 | sc->sc_suspend_state.cs4280.pfie, |
| 983 | sc->sc_suspend_state.cs4280.pba, |
| 984 | sc->sc_suspend_state.cs4280.pdtc)); |
| 985 | cs4280_set_dac_rate(sc, sc->sc_prate); |
| 986 | BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); |
| 987 | BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); |
| 988 | BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); |
| 989 | BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); |
| 990 | } |
| 991 | |
| 992 | if (sc->sc_rrun) { |
| 993 | DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n" , |
| 994 | sc->sc_suspend_state.cs4280.cctl, |
| 995 | sc->sc_suspend_state.cs4280.cie, |
| 996 | sc->sc_suspend_state.cs4280.cba)); |
| 997 | cs4280_set_adc_rate(sc, sc->sc_rrate); |
| 998 | BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); |
| 999 | BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); |
| 1000 | BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); |
| 1001 | } |
| 1002 | |
| 1003 | mutex_spin_exit(&sc->sc_intr_lock); |
| 1004 | |
| 1005 | /* restore ac97 registers */ |
| 1006 | (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); |
| 1007 | |
| 1008 | mutex_exit(&sc->sc_lock); |
| 1009 | |
| 1010 | return true; |
| 1011 | } |
| 1012 | |
| 1013 | static int |
| 1014 | cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) |
| 1015 | { |
| 1016 | struct cs428x_softc *sc = addr; |
| 1017 | int rv; |
| 1018 | |
| 1019 | cs4280_clkrun_hack(sc, 1); |
| 1020 | rv = cs428x_read_codec(addr, reg, result); |
| 1021 | cs4280_clkrun_hack(sc, -1); |
| 1022 | |
| 1023 | return rv; |
| 1024 | } |
| 1025 | |
| 1026 | static int |
| 1027 | cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) |
| 1028 | { |
| 1029 | struct cs428x_softc *sc = addr; |
| 1030 | int rv; |
| 1031 | |
| 1032 | cs4280_clkrun_hack(sc, 1); |
| 1033 | rv = cs428x_write_codec(addr, reg, data); |
| 1034 | cs4280_clkrun_hack(sc, -1); |
| 1035 | |
| 1036 | return rv; |
| 1037 | } |
| 1038 | |
| 1039 | #if 0 /* XXX buggy and not required */ |
| 1040 | /* control AC97 codec */ |
| 1041 | static int |
| 1042 | cs4280_reset_codec(void *addr) |
| 1043 | { |
| 1044 | struct cs428x_softc *sc; |
| 1045 | int n; |
| 1046 | |
| 1047 | sc = addr; |
| 1048 | |
| 1049 | /* Reset codec */ |
| 1050 | BA0WRITE4(sc, CS428X_ACCTL, 0); |
| 1051 | delay(100); /* delay 100us */ |
| 1052 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); |
| 1053 | |
| 1054 | /* |
| 1055 | * It looks like we do the following procedure, too |
| 1056 | */ |
| 1057 | |
| 1058 | /* Enable AC-link sync generation */ |
| 1059 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); |
| 1060 | delay(50*1000); /* XXX delay 50ms */ |
| 1061 | |
| 1062 | /* Assert valid frame signal */ |
| 1063 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); |
| 1064 | |
| 1065 | /* Wait for valid AC97 input slot */ |
| 1066 | n = 0; |
| 1067 | while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != |
| 1068 | (ACISV_ISV3 | ACISV_ISV4)) { |
| 1069 | delay(1000); |
| 1070 | if (++n > 1000) { |
| 1071 | printf("reset_codec: AC97 inputs slot ready timeout\n" ); |
| 1072 | return ETIMEDOUT; |
| 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | #endif |
| 1079 | |
| 1080 | static enum ac97_host_flags |
| 1081 | cs4280_flags_codec(void *addr) |
| 1082 | { |
| 1083 | struct cs428x_softc *sc; |
| 1084 | |
| 1085 | sc = addr; |
| 1086 | if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) |
| 1087 | return AC97_HOST_INVERTED_EAMP; |
| 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | /* Internal functions */ |
| 1093 | |
| 1094 | static const struct cs4280_card_t * |
| 1095 | cs4280_identify_card(const struct pci_attach_args *pa) |
| 1096 | { |
| 1097 | pcireg_t idreg; |
| 1098 | u_int16_t i; |
| 1099 | |
| 1100 | idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); |
| 1101 | for (i = 0; i < CS4280_CARDS_SIZE; i++) { |
| 1102 | if (idreg == cs4280_cards[i].id) |
| 1103 | return &cs4280_cards[i]; |
| 1104 | } |
| 1105 | |
| 1106 | return NULL; |
| 1107 | } |
| 1108 | |
| 1109 | static int |
| 1110 | cs4280_piix4_match(const struct pci_attach_args *pa) |
| 1111 | { |
| 1112 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && |
| 1113 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { |
| 1114 | return 1; |
| 1115 | } |
| 1116 | |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | static void |
| 1121 | cs4280_clkrun_hack(struct cs428x_softc *sc, int change) |
| 1122 | { |
| 1123 | uint16_t control, val; |
| 1124 | |
| 1125 | if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) |
| 1126 | return; |
| 1127 | |
| 1128 | sc->sc_active += change; |
| 1129 | val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); |
| 1130 | if (!sc->sc_active) |
| 1131 | val |= 0x2000; |
| 1132 | else |
| 1133 | val &= ~0x2000; |
| 1134 | if (val != control) |
| 1135 | bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); |
| 1136 | } |
| 1137 | |
| 1138 | static void |
| 1139 | cs4280_clkrun_hack_init(struct cs428x_softc *sc) |
| 1140 | { |
| 1141 | struct pci_attach_args smbuspa; |
| 1142 | uint16_t reg; |
| 1143 | pcireg_t port; |
| 1144 | |
| 1145 | if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) |
| 1146 | return; |
| 1147 | |
| 1148 | if (pci_find_device(&smbuspa, cs4280_piix4_match)) { |
| 1149 | sc->sc_active = 0; |
| 1150 | aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n" ); |
| 1151 | |
| 1152 | reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); |
| 1153 | port = reg & 0xffc0; |
| 1154 | aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n" , |
| 1155 | port); |
| 1156 | |
| 1157 | sc->sc_pm_iot = smbuspa.pa_iot; |
| 1158 | if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, |
| 1159 | &sc->sc_pm_ioh) == 0) |
| 1160 | return; |
| 1161 | } |
| 1162 | |
| 1163 | /* handle error */ |
| 1164 | sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; |
| 1165 | aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n" ); |
| 1166 | } |
| 1167 | |
| 1168 | static void |
| 1169 | cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) |
| 1170 | { |
| 1171 | /* calculate capture rate: |
| 1172 | * |
| 1173 | * capture_coefficient_increment = -round(rate*128*65536/48000; |
| 1174 | * capture_phase_increment = floor(48000*65536*1024/rate); |
| 1175 | * cx = round(48000*65536*1024 - capture_phase_increment*rate); |
| 1176 | * cy = floor(cx/200); |
| 1177 | * capture_sample_rate_correction = cx - 200*cy; |
| 1178 | * capture_delay = ceil(24*48000/rate); |
| 1179 | * capture_num_triplets = floor(65536*rate/24000); |
| 1180 | * capture_group_length = 24000/GCD(rate, 24000); |
| 1181 | * where GCD means "Greatest Common Divisor". |
| 1182 | * |
| 1183 | * capture_coefficient_increment, capture_phase_increment and |
| 1184 | * capture_num_triplets are 32-bit signed quantities. |
| 1185 | * capture_sample_rate_correction and capture_group_length are |
| 1186 | * 16-bit signed quantities. |
| 1187 | * capture_delay is a 14-bit unsigned quantity. |
| 1188 | */ |
| 1189 | uint32_t cci, cpi, cnt, cx, cy, tmp1; |
| 1190 | uint16_t csrc, cgl, cdlay; |
| 1191 | |
| 1192 | /* XXX |
| 1193 | * Even though, embedded_audio_spec says capture rate range 11025 to |
| 1194 | * 48000, dhwiface.cpp says, |
| 1195 | * |
| 1196 | * "We can only decimate by up to a factor of 1/9th the hardware rate. |
| 1197 | * Return an error if an attempt is made to stray outside that limit." |
| 1198 | * |
| 1199 | * so assume range as 48000/9 to 48000 |
| 1200 | */ |
| 1201 | |
| 1202 | if (rate < 8000) |
| 1203 | rate = 8000; |
| 1204 | if (rate > 48000) |
| 1205 | rate = 48000; |
| 1206 | |
| 1207 | cx = rate << 16; |
| 1208 | cci = cx / 48000; |
| 1209 | cx -= cci * 48000; |
| 1210 | cx <<= 7; |
| 1211 | cci <<= 7; |
| 1212 | cci += cx / 48000; |
| 1213 | cci = - cci; |
| 1214 | |
| 1215 | cx = 48000 << 16; |
| 1216 | cpi = cx / rate; |
| 1217 | cx -= cpi * rate; |
| 1218 | cx <<= 10; |
| 1219 | cpi <<= 10; |
| 1220 | cy = cx / rate; |
| 1221 | cpi += cy; |
| 1222 | cx -= cy * rate; |
| 1223 | |
| 1224 | cy = cx / 200; |
| 1225 | csrc = cx - 200*cy; |
| 1226 | |
| 1227 | cdlay = ((48000 * 24) + rate - 1) / rate; |
| 1228 | #if 0 |
| 1229 | cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ |
| 1230 | #endif |
| 1231 | |
| 1232 | cnt = rate << 16; |
| 1233 | cnt /= 24000; |
| 1234 | |
| 1235 | cgl = 1; |
| 1236 | for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { |
| 1237 | if (((rate / tmp1) * tmp1) != rate) |
| 1238 | cgl *= 2; |
| 1239 | } |
| 1240 | if (((rate / 3) * 3) != rate) |
| 1241 | cgl *= 3; |
| 1242 | for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { |
| 1243 | if (((rate / tmp1) * tmp1) != rate) |
| 1244 | cgl *= 5; |
| 1245 | } |
| 1246 | #if 0 |
| 1247 | /* XXX what manual says */ |
| 1248 | tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; |
| 1249 | tmp1 |= csrc<<16; |
| 1250 | BA1WRITE4(sc, CS4280_CSRC, tmp1); |
| 1251 | #else |
| 1252 | /* suggested by cs461x.c (ALSA driver) */ |
| 1253 | BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); |
| 1254 | #endif |
| 1255 | |
| 1256 | #if 0 |
| 1257 | /* I am confused. The sample rate calculation section says |
| 1258 | * cci *is* 32-bit signed quantity but in the parameter description |
| 1259 | * section, CCI only assigned 16bit. |
| 1260 | * I believe size of the variable. |
| 1261 | */ |
| 1262 | tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; |
| 1263 | tmp1 |= cci<<16; |
| 1264 | BA1WRITE4(sc, CS4280_CCI, tmp1); |
| 1265 | #else |
| 1266 | BA1WRITE4(sc, CS4280_CCI, cci); |
| 1267 | #endif |
| 1268 | |
| 1269 | tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; |
| 1270 | tmp1 |= cdlay <<18; |
| 1271 | BA1WRITE4(sc, CS4280_CD, tmp1); |
| 1272 | |
| 1273 | BA1WRITE4(sc, CS4280_CPI, cpi); |
| 1274 | |
| 1275 | tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; |
| 1276 | tmp1 |= cgl; |
| 1277 | BA1WRITE4(sc, CS4280_CGL, tmp1); |
| 1278 | |
| 1279 | BA1WRITE4(sc, CS4280_CNT, cnt); |
| 1280 | |
| 1281 | tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; |
| 1282 | tmp1 |= cgl; |
| 1283 | BA1WRITE4(sc, CS4280_CGC, tmp1); |
| 1284 | } |
| 1285 | |
| 1286 | static void |
| 1287 | cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) |
| 1288 | { |
| 1289 | /* |
| 1290 | * playback rate may range from 8000Hz to 48000Hz |
| 1291 | * |
| 1292 | * play_phase_increment = floor(rate*65536*1024/48000) |
| 1293 | * px = round(rate*65536*1024 - play_phase_incremnt*48000) |
| 1294 | * py=floor(px/200) |
| 1295 | * play_sample_rate_correction = px - 200*py |
| 1296 | * |
| 1297 | * play_phase_increment is a 32bit signed quantity. |
| 1298 | * play_sample_rate_correction is a 16bit signed quantity. |
| 1299 | */ |
| 1300 | int32_t ppi; |
| 1301 | int16_t psrc; |
| 1302 | uint32_t px, py; |
| 1303 | |
| 1304 | if (rate < 8000) |
| 1305 | rate = 8000; |
| 1306 | if (rate > 48000) |
| 1307 | rate = 48000; |
| 1308 | px = rate << 16; |
| 1309 | ppi = px/48000; |
| 1310 | px -= ppi*48000; |
| 1311 | ppi <<= 10; |
| 1312 | px <<= 10; |
| 1313 | py = px / 48000; |
| 1314 | ppi += py; |
| 1315 | px -= py*48000; |
| 1316 | py = px/200; |
| 1317 | px -= py*200; |
| 1318 | psrc = px; |
| 1319 | #if 0 |
| 1320 | /* what manual says */ |
| 1321 | px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; |
| 1322 | BA1WRITE4(sc, CS4280_PSRC, |
| 1323 | ( ((psrc<<16) & PSRC_MASK) | px )); |
| 1324 | #else |
| 1325 | /* suggested by cs461x.c (ALSA driver) */ |
| 1326 | BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); |
| 1327 | #endif |
| 1328 | BA1WRITE4(sc, CS4280_PPI, ppi); |
| 1329 | } |
| 1330 | |
| 1331 | /* Download Processor Code and Data image */ |
| 1332 | static int |
| 1333 | cs4280_download(struct cs428x_softc *sc, const uint32_t *src, |
| 1334 | uint32_t offset, uint32_t len) |
| 1335 | { |
| 1336 | uint32_t ctr; |
| 1337 | #if CS4280_DEBUG > 10 |
| 1338 | uint32_t con, data; |
| 1339 | uint8_t c0, c1, c2, c3; |
| 1340 | #endif |
| 1341 | if ((offset & 3) || (len & 3)) |
| 1342 | return -1; |
| 1343 | |
| 1344 | len /= sizeof(uint32_t); |
| 1345 | for (ctr = 0; ctr < len; ctr++) { |
| 1346 | /* XXX: |
| 1347 | * I cannot confirm this is the right thing or not |
| 1348 | * on BIG-ENDIAN machines. |
| 1349 | */ |
| 1350 | BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); |
| 1351 | #if CS4280_DEBUG > 10 |
| 1352 | data = htole32(*(src+ctr)); |
| 1353 | c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); |
| 1354 | c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); |
| 1355 | c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); |
| 1356 | c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); |
| 1357 | con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; |
| 1358 | if (data != con ) { |
| 1359 | printf("0x%06x: write=0x%08x read=0x%08x\n" , |
| 1360 | offset+ctr*4, data, con); |
| 1361 | return -1; |
| 1362 | } |
| 1363 | #endif |
| 1364 | } |
| 1365 | return 0; |
| 1366 | } |
| 1367 | |
| 1368 | static int |
| 1369 | cs4280_download_image(struct cs428x_softc *sc) |
| 1370 | { |
| 1371 | int idx, err; |
| 1372 | uint32_t offset = 0; |
| 1373 | |
| 1374 | err = 0; |
| 1375 | for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { |
| 1376 | err = cs4280_download(sc, &BA1Struct.map[offset], |
| 1377 | BA1Struct.memory[idx].offset, |
| 1378 | BA1Struct.memory[idx].size); |
| 1379 | if (err != 0) { |
| 1380 | aprint_error_dev(sc->sc_dev, |
| 1381 | "load_image failed at %d\n" , idx); |
| 1382 | return -1; |
| 1383 | } |
| 1384 | offset += BA1Struct.memory[idx].size / sizeof(uint32_t); |
| 1385 | } |
| 1386 | return err; |
| 1387 | } |
| 1388 | |
| 1389 | /* Processor Soft Reset */ |
| 1390 | static void |
| 1391 | cs4280_reset(void *sc_) |
| 1392 | { |
| 1393 | struct cs428x_softc *sc; |
| 1394 | |
| 1395 | sc = sc_; |
| 1396 | /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ |
| 1397 | BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); |
| 1398 | delay(100); |
| 1399 | /* Clear RSTSP bit in SPCR */ |
| 1400 | BA1WRITE4(sc, CS4280_SPCR, 0); |
| 1401 | /* enable DMA reqest */ |
| 1402 | BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); |
| 1403 | } |
| 1404 | |
| 1405 | static int |
| 1406 | cs4280_init(struct cs428x_softc *sc, int init) |
| 1407 | { |
| 1408 | int n; |
| 1409 | uint32_t mem; |
| 1410 | int rv; |
| 1411 | |
| 1412 | rv = 1; |
| 1413 | cs4280_clkrun_hack(sc, 1); |
| 1414 | |
| 1415 | /* Start PLL out in known state */ |
| 1416 | BA0WRITE4(sc, CS4280_CLKCR1, 0); |
| 1417 | /* Start serial ports out in known state */ |
| 1418 | BA0WRITE4(sc, CS4280_SERMC1, 0); |
| 1419 | |
| 1420 | /* Specify type of CODEC */ |
| 1421 | /* XXX should not be here */ |
| 1422 | #define SERACC_CODEC_TYPE_1_03 |
| 1423 | #ifdef SERACC_CODEC_TYPE_1_03 |
| 1424 | BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ |
| 1425 | #else |
| 1426 | BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ |
| 1427 | #endif |
| 1428 | |
| 1429 | /* Reset codec */ |
| 1430 | BA0WRITE4(sc, CS428X_ACCTL, 0); |
| 1431 | delay(100); /* delay 100us */ |
| 1432 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); |
| 1433 | |
| 1434 | /* Enable AC-link sync generation */ |
| 1435 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); |
| 1436 | delay(50*1000); /* delay 50ms */ |
| 1437 | |
| 1438 | /* Set the serial port timing configuration */ |
| 1439 | BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); |
| 1440 | |
| 1441 | /* Setup clock control */ |
| 1442 | BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); |
| 1443 | BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); |
| 1444 | BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); |
| 1445 | |
| 1446 | /* Power up the PLL */ |
| 1447 | BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); |
| 1448 | delay(50*1000); /* delay 50ms */ |
| 1449 | |
| 1450 | /* Turn on clock */ |
| 1451 | mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; |
| 1452 | BA0WRITE4(sc, CS4280_CLKCR1, mem); |
| 1453 | |
| 1454 | /* Set the serial port FIFO pointer to the |
| 1455 | * first sample in FIFO. (not documented) */ |
| 1456 | cs4280_clear_fifos(sc); |
| 1457 | |
| 1458 | #if 0 |
| 1459 | /* Set the serial port FIFO pointer to the first sample in the FIFO */ |
| 1460 | BA0WRITE4(sc, CS4280_SERBSP, 0); |
| 1461 | #endif |
| 1462 | |
| 1463 | /* Configure the serial port */ |
| 1464 | BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); |
| 1465 | BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); |
| 1466 | BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); |
| 1467 | |
| 1468 | /* Wait for CODEC ready */ |
| 1469 | n = 0; |
| 1470 | while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { |
| 1471 | delay(125); |
| 1472 | if (++n > 1000) { |
| 1473 | aprint_error_dev(sc->sc_dev, "codec ready timeout\n" ); |
| 1474 | goto exit; |
| 1475 | } |
| 1476 | } |
| 1477 | |
| 1478 | /* Assert valid frame signal */ |
| 1479 | BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); |
| 1480 | |
| 1481 | /* Wait for valid AC97 input slot */ |
| 1482 | n = 0; |
| 1483 | while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != |
| 1484 | (ACISV_ISV3 | ACISV_ISV4)) { |
| 1485 | delay(1000); |
| 1486 | if (++n > 1000) { |
| 1487 | printf("AC97 inputs slot ready timeout\n" ); |
| 1488 | goto exit; |
| 1489 | } |
| 1490 | } |
| 1491 | |
| 1492 | /* Set AC97 output slot valid signals */ |
| 1493 | BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); |
| 1494 | |
| 1495 | /* reset the processor */ |
| 1496 | cs4280_reset(sc); |
| 1497 | |
| 1498 | /* Download the image to the processor */ |
| 1499 | if (cs4280_download_image(sc) != 0) { |
| 1500 | aprint_error_dev(sc->sc_dev, "image download error\n" ); |
| 1501 | goto exit; |
| 1502 | } |
| 1503 | |
| 1504 | /* Save playback parameter and then write zero. |
| 1505 | * this ensures that DMA doesn't immediately occur upon |
| 1506 | * starting the processor core |
| 1507 | */ |
| 1508 | mem = BA1READ4(sc, CS4280_PCTL); |
| 1509 | sc->pctl = mem & PCTL_MASK; /* save startup value */ |
| 1510 | BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); |
| 1511 | if (init != 0) |
| 1512 | sc->sc_prun = 0; |
| 1513 | |
| 1514 | /* Save capture parameter and then write zero. |
| 1515 | * this ensures that DMA doesn't immediately occur upon |
| 1516 | * starting the processor core |
| 1517 | */ |
| 1518 | mem = BA1READ4(sc, CS4280_CCTL); |
| 1519 | sc->cctl = mem & CCTL_MASK; /* save startup value */ |
| 1520 | BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); |
| 1521 | if (init != 0) |
| 1522 | sc->sc_rrun = 0; |
| 1523 | |
| 1524 | /* Processor Startup Procedure */ |
| 1525 | BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); |
| 1526 | BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); |
| 1527 | |
| 1528 | /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ |
| 1529 | n = 0; |
| 1530 | while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { |
| 1531 | delay(10); |
| 1532 | if (++n > 1000) { |
| 1533 | printf("SPCR 1->0 transition timeout\n" ); |
| 1534 | goto exit; |
| 1535 | } |
| 1536 | } |
| 1537 | |
| 1538 | n = 0; |
| 1539 | while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { |
| 1540 | delay(10); |
| 1541 | if (++n > 1000) { |
| 1542 | printf("SPCS 0->1 transition timeout\n" ); |
| 1543 | goto exit; |
| 1544 | } |
| 1545 | } |
| 1546 | /* Processor is now running !!! */ |
| 1547 | |
| 1548 | /* Setup volume */ |
| 1549 | BA1WRITE4(sc, CS4280_PVOL, 0x80008000); |
| 1550 | BA1WRITE4(sc, CS4280_CVOL, 0x80008000); |
| 1551 | |
| 1552 | /* Interrupt enable */ |
| 1553 | BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); |
| 1554 | |
| 1555 | /* playback interrupt enable */ |
| 1556 | mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; |
| 1557 | mem |= PFIE_PI_ENABLE; |
| 1558 | BA1WRITE4(sc, CS4280_PFIE, mem); |
| 1559 | /* capture interrupt enable */ |
| 1560 | mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; |
| 1561 | mem |= CIE_CI_ENABLE; |
| 1562 | BA1WRITE4(sc, CS4280_CIE, mem); |
| 1563 | |
| 1564 | #if NMIDI > 0 |
| 1565 | /* Reset midi port */ |
| 1566 | mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; |
| 1567 | BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); |
| 1568 | DPRINTF(("midi reset: 0x%x\n" , BA0READ4(sc, CS4280_MIDCR))); |
| 1569 | /* midi interrupt enable */ |
| 1570 | mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; |
| 1571 | BA0WRITE4(sc, CS4280_MIDCR, mem); |
| 1572 | #endif |
| 1573 | |
| 1574 | rv = 0; |
| 1575 | |
| 1576 | exit: |
| 1577 | cs4280_clkrun_hack(sc, -1); |
| 1578 | return rv; |
| 1579 | } |
| 1580 | |
| 1581 | static void |
| 1582 | cs4280_clear_fifos(struct cs428x_softc *sc) |
| 1583 | { |
| 1584 | int pd, cnt, n; |
| 1585 | uint32_t mem; |
| 1586 | |
| 1587 | pd = 0; |
| 1588 | /* |
| 1589 | * If device power down, power up the device and keep power down |
| 1590 | * state. |
| 1591 | */ |
| 1592 | mem = BA0READ4(sc, CS4280_CLKCR1); |
| 1593 | if (!(mem & CLKCR1_SWCE)) { |
| 1594 | printf("cs4280_clear_fifo: power down found.\n" ); |
| 1595 | BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); |
| 1596 | pd = 1; |
| 1597 | } |
| 1598 | BA0WRITE4(sc, CS4280_SERBWP, 0); |
| 1599 | for (cnt = 0; cnt < 256; cnt++) { |
| 1600 | n = 0; |
| 1601 | while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { |
| 1602 | delay(1000); |
| 1603 | if (++n > 1000) { |
| 1604 | printf("clear_fifo: fist timeout cnt=%d\n" , cnt); |
| 1605 | break; |
| 1606 | } |
| 1607 | } |
| 1608 | BA0WRITE4(sc, CS4280_SERBAD, cnt); |
| 1609 | BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); |
| 1610 | } |
| 1611 | if (pd) |
| 1612 | BA0WRITE4(sc, CS4280_CLKCR1, mem); |
| 1613 | } |
| 1614 | |
| 1615 | #if NMIDI > 0 |
| 1616 | static int |
| 1617 | cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), |
| 1618 | void (*ointr)(void *), void *arg) |
| 1619 | { |
| 1620 | struct cs428x_softc *sc; |
| 1621 | uint32_t mem; |
| 1622 | |
| 1623 | DPRINTF(("midi_open\n" )); |
| 1624 | sc = addr; |
| 1625 | sc->sc_iintr = iintr; |
| 1626 | sc->sc_ointr = ointr; |
| 1627 | sc->sc_arg = arg; |
| 1628 | |
| 1629 | /* midi interrupt enable */ |
| 1630 | mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; |
| 1631 | mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; |
| 1632 | BA0WRITE4(sc, CS4280_MIDCR, mem); |
| 1633 | #ifdef CS4280_DEBUG |
| 1634 | if (mem != BA0READ4(sc, CS4280_MIDCR)) { |
| 1635 | DPRINTF(("midi_open: MIDCR=%d\n" , BA0READ4(sc, CS4280_MIDCR))); |
| 1636 | return(EINVAL); |
| 1637 | } |
| 1638 | DPRINTF(("MIDCR=0x%x\n" , BA0READ4(sc, CS4280_MIDCR))); |
| 1639 | #endif |
| 1640 | return 0; |
| 1641 | } |
| 1642 | |
| 1643 | static void |
| 1644 | cs4280_midi_close(void *addr) |
| 1645 | { |
| 1646 | struct cs428x_softc *sc; |
| 1647 | uint32_t mem; |
| 1648 | |
| 1649 | DPRINTF(("midi_close\n" )); |
| 1650 | sc = addr; |
| 1651 | /* give uart a chance to drain */ |
| 1652 | kpause("cs0clm" , false, hz/10, &sc->sc_intr_lock); |
| 1653 | mem = BA0READ4(sc, CS4280_MIDCR); |
| 1654 | mem &= ~MIDCR_MASK; |
| 1655 | BA0WRITE4(sc, CS4280_MIDCR, mem); |
| 1656 | |
| 1657 | sc->sc_iintr = 0; |
| 1658 | sc->sc_ointr = 0; |
| 1659 | } |
| 1660 | |
| 1661 | static int |
| 1662 | cs4280_midi_output(void *addr, int d) |
| 1663 | { |
| 1664 | struct cs428x_softc *sc; |
| 1665 | uint32_t mem; |
| 1666 | int x; |
| 1667 | |
| 1668 | sc = addr; |
| 1669 | for (x = 0; x != MIDI_BUSY_WAIT; x++) { |
| 1670 | if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { |
| 1671 | mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; |
| 1672 | mem |= d & MIDWP_MASK; |
| 1673 | DPRINTFN(5,("midi_output d=0x%08x" ,d)); |
| 1674 | BA0WRITE4(sc, CS4280_MIDWP, mem); |
| 1675 | #ifdef DIAGNOSTIC |
| 1676 | if (mem != BA0READ4(sc, CS4280_MIDWP)) { |
| 1677 | DPRINTF(("Bad write data: %d %d" , |
| 1678 | mem, BA0READ4(sc, CS4280_MIDWP))); |
| 1679 | return EIO; |
| 1680 | } |
| 1681 | #endif |
| 1682 | return 0; |
| 1683 | } |
| 1684 | delay(MIDI_BUSY_DELAY); |
| 1685 | } |
| 1686 | return EIO; |
| 1687 | } |
| 1688 | |
| 1689 | static void |
| 1690 | cs4280_midi_getinfo(void *addr, struct midi_info *mi) |
| 1691 | { |
| 1692 | |
| 1693 | mi->name = "CS4280 MIDI UART" ; |
| 1694 | mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; |
| 1695 | } |
| 1696 | |
| 1697 | #endif /* NMIDI */ |
| 1698 | |
| 1699 | /* DEBUG functions */ |
| 1700 | #if CS4280_DEBUG > 10 |
| 1701 | static int |
| 1702 | cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, |
| 1703 | uint32_t offset, uint32_t len) |
| 1704 | { |
| 1705 | uint32_t ctr, data; |
| 1706 | int err; |
| 1707 | |
| 1708 | if ((offset & 3) || (len & 3)) |
| 1709 | return -1; |
| 1710 | |
| 1711 | err = 0; |
| 1712 | len /= sizeof(uint32_t); |
| 1713 | for (ctr = 0; ctr < len; ctr++) { |
| 1714 | /* I cannot confirm this is the right thing |
| 1715 | * on BIG-ENDIAN machines |
| 1716 | */ |
| 1717 | data = BA1READ4(sc, offset+ctr*4); |
| 1718 | if (data != htole32(*(src+ctr))) { |
| 1719 | printf("0x%06x: 0x%08x(0x%08x)\n" , |
| 1720 | offset+ctr*4, data, *(src+ctr)); |
| 1721 | *(src+ctr) = data; |
| 1722 | ++err; |
| 1723 | } |
| 1724 | } |
| 1725 | return err; |
| 1726 | } |
| 1727 | |
| 1728 | static int |
| 1729 | cs4280_check_images(struct cs428x_softc *sc) |
| 1730 | { |
| 1731 | int idx, err; |
| 1732 | uint32_t offset; |
| 1733 | |
| 1734 | offset = 0; |
| 1735 | err = 0; |
| 1736 | /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ |
| 1737 | for (idx = 0; idx < 1; ++idx) { |
| 1738 | err = cs4280_checkimage(sc, &BA1Struct.map[offset], |
| 1739 | BA1Struct.memory[idx].offset, |
| 1740 | BA1Struct.memory[idx].size); |
| 1741 | if (err != 0) { |
| 1742 | aprint_error_dev(sc->sc_dev, |
| 1743 | "check_image failed at %d\n" , idx); |
| 1744 | } |
| 1745 | offset += BA1Struct.memory[idx].size / sizeof(uint32_t); |
| 1746 | } |
| 1747 | return err; |
| 1748 | } |
| 1749 | |
| 1750 | #endif /* CS4280_DEBUG */ |
| 1751 | |