| 1 | /* $NetBSD: arcmsrvar.h,v 1.15 2016/06/12 02:16:15 christos Exp $ */ |
| 2 | /* Derived from $OpenBSD: arc.c,v 1.68 2007/10/27 03:28:27 dlg Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 2007 Juan Romero Pardines <xtraeme@netbsd.org> |
| 6 | * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _PCI_ARCMSRVAR_H_ |
| 22 | #define _PCI_ARCMSRVAR_H_ |
| 23 | |
| 24 | #define ARC_PCI_BAR PCI_MAPREG_START |
| 25 | |
| 26 | #define ARC_REG_INB_MSG0 0x0010 |
| 27 | #define ARC_REG_INB_MSG0_NOP (0x00000000) |
| 28 | #define ARC_REG_INB_MSG0_GET_CONFIG (0x00000001) |
| 29 | #define ARC_REG_INB_MSG0_SET_CONFIG (0x00000002) |
| 30 | #define ARC_REG_INB_MSG0_ABORT_CMD (0x00000003) |
| 31 | #define ARC_REG_INB_MSG0_STOP_BGRB (0x00000004) |
| 32 | #define ARC_REG_INB_MSG0_FLUSH_CACHE (0x00000005) |
| 33 | #define ARC_REG_INB_MSG0_START_BGRB (0x00000006) |
| 34 | #define ARC_REG_INB_MSG0_CHK331PENDING (0x00000007) |
| 35 | #define ARC_REG_INB_MSG0_SYNC_TIMER (0x00000008) |
| 36 | #define ARC_REG_INB_MSG1 0x0014 |
| 37 | #define ARC_REG_OUTB_ADDR0 0x0018 |
| 38 | #define ARC_REG_OUTB_ADDR1 0x001c |
| 39 | #define ARC_REG_OUTB_ADDR1_FIRMWARE_OK (1<<31) |
| 40 | #define ARC_REG_INB_DOORBELL 0x0020 |
| 41 | #define ARC_REG_INB_DOORBELL_WRITE_OK (1<<0) |
| 42 | #define ARC_REG_INB_DOORBELL_READ_OK (1<<1) |
| 43 | #define ARC_REG_OUTB_DOORBELL 0x002c |
| 44 | #define ARC_REG_OUTB_DOORBELL_WRITE_OK (1<<0) |
| 45 | #define ARC_REG_OUTB_DOORBELL_READ_OK (1<<1) |
| 46 | #define ARC_REG_INTRSTAT 0x0030 |
| 47 | #define ARC_REG_INTRSTAT_MSG0 (1<<0) |
| 48 | #define ARC_REG_INTRSTAT_MSG1 (1<<1) |
| 49 | #define ARC_REG_INTRSTAT_DOORBELL (1<<2) |
| 50 | #define ARC_REG_INTRSTAT_POSTQUEUE (1<<3) |
| 51 | #define ARC_REG_INTRSTAT_PCI (1<<4) |
| 52 | #define ARC_REG_INTRMASK 0x0034 |
| 53 | #define ARC_REG_INTRMASK_MSG0 (1<<0) |
| 54 | #define ARC_REG_INTRMASK_MSG1 (1<<1) |
| 55 | #define ARC_REG_INTRMASK_DOORBELL (1<<2) |
| 56 | #define ARC_REG_INTRMASK_POSTQUEUE (1<<3) |
| 57 | #define ARC_REG_INTRMASK_PCI (1<<4) |
| 58 | #define ARC_REG_POST_QUEUE 0x0040 |
| 59 | #define ARC_REG_POST_QUEUE_ADDR_SHIFT 5 |
| 60 | #define ARC_REG_POST_QUEUE_IAMBIOS (1<<30) |
| 61 | #define ARC_REG_POST_QUEUE_BIGFRAME (1<<31) |
| 62 | #define ARC_REG_REPLY_QUEUE 0x0044 |
| 63 | #define ARC_REG_REPLY_QUEUE_ADDR_SHIFT 5 |
| 64 | #define ARC_REG_REPLY_QUEUE_ERR (1<<28) |
| 65 | #define ARC_REG_REPLY_QUEUE_IAMBIOS (1<<30) |
| 66 | #define ARC_REG_MSGBUF 0x0a00 |
| 67 | #define ARC_REG_MSGBUF_LEN 1024 |
| 68 | #define ARC_REG_IOC_WBUF_LEN 0x0e00 |
| 69 | #define ARC_REG_IOC_WBUF 0x0e04 |
| 70 | #define ARC_REG_IOC_RBUF_LEN 0x0f00 |
| 71 | #define ARC_REG_IOC_RBUF 0x0f04 |
| 72 | #define ARC_REG_IOC_RWBUF_MAXLEN 124 /* for both RBUF and WBUF */ |
| 73 | |
| 74 | struct arc_msg_firmware_info { |
| 75 | uint32_t signature; |
| 76 | #define ARC_FWINFO_SIGNATURE_GET_CONFIG (0x87974060) |
| 77 | uint32_t request_len; |
| 78 | uint32_t queue_len; |
| 79 | uint32_t sdram_size; |
| 80 | uint32_t sata_ports; |
| 81 | uint8_t vendor[40]; |
| 82 | uint8_t model[8]; |
| 83 | uint8_t fw_version[16]; |
| 84 | uint8_t device_map[16]; |
| 85 | } __packed; |
| 86 | |
| 87 | struct arc_msg_scsicmd { |
| 88 | uint8_t bus; |
| 89 | uint8_t target; |
| 90 | uint8_t lun; |
| 91 | uint8_t function; |
| 92 | |
| 93 | uint8_t cdb_len; |
| 94 | uint8_t sgl_len; |
| 95 | uint8_t flags; |
| 96 | #define ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512 (1<<0) |
| 97 | #define ARC_MSG_SCSICMD_FLAG_FROM_BIOS (1<<1) |
| 98 | #define ARC_MSG_SCSICMD_FLAG_WRITE (1<<2) |
| 99 | #define ARC_MSG_SCSICMD_FLAG_SIMPLEQ (0x00) |
| 100 | #define ARC_MSG_SCSICMD_FLAG_HEADQ (0x08) |
| 101 | #define ARC_MSG_SCSICMD_FLAG_ORDERQ (0x10) |
| 102 | uint8_t reserved; |
| 103 | |
| 104 | uint32_t context; |
| 105 | uint32_t data_len; |
| 106 | |
| 107 | #define ARC_MSG_CDBLEN 16 |
| 108 | uint8_t cdb[ARC_MSG_CDBLEN]; |
| 109 | |
| 110 | uint8_t status; |
| 111 | #define ARC_MSG_STATUS_SELTIMEOUT 0xf0 |
| 112 | #define ARC_MSG_STATUS_ABORTED 0xf1 |
| 113 | #define ARC_MSG_STATUS_INIT_FAIL 0xf2 |
| 114 | #define ARC_MSG_SENSELEN 15 |
| 115 | uint8_t sense_data[ARC_MSG_SENSELEN]; |
| 116 | |
| 117 | /* followed by an sgl */ |
| 118 | } __packed; |
| 119 | |
| 120 | struct arc_sge { |
| 121 | uint32_t sg_hdr; |
| 122 | #define ARC_SGE_64BIT (1<<24) |
| 123 | uint32_t sg_lo_addr; |
| 124 | uint32_t sg_hi_addr; |
| 125 | } __packed; |
| 126 | |
| 127 | #define ARC_MAX_TARGET 16 |
| 128 | #define ARC_MAX_LUN 8 |
| 129 | #define ARC_MAX_IOCMDLEN 512 |
| 130 | #define ARC_BLOCKSIZE 512 |
| 131 | |
| 132 | /* |
| 133 | * the firmware deals with up to 256 or 512 byte command frames. |
| 134 | */ |
| 135 | |
| 136 | /* |
| 137 | * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 38) == 508. |
| 138 | */ |
| 139 | #define ARC_SGL_MAXLEN 38 |
| 140 | /* |
| 141 | * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 17) == 252. |
| 142 | */ |
| 143 | #define ARC_SGL_256LEN 17 |
| 144 | |
| 145 | struct arc_io_cmd { |
| 146 | struct arc_msg_scsicmd cmd; |
| 147 | struct arc_sge sgl[ARC_SGL_MAXLEN]; |
| 148 | } __packed; |
| 149 | |
| 150 | /* |
| 151 | * definitions of the firmware commands sent via the doorbells. |
| 152 | */ |
| 153 | struct arc_fw_hdr { |
| 154 | uint8_t byte1; |
| 155 | uint8_t byte2; |
| 156 | uint8_t byte3; |
| 157 | } __packed; |
| 158 | |
| 159 | struct arc_fw_bufhdr { |
| 160 | struct arc_fw_hdr hdr; |
| 161 | uint16_t len; |
| 162 | } __packed; |
| 163 | |
| 164 | /* Firmware command codes */ |
| 165 | #define ARC_FW_CHECK_PASS 0x14 /* opcode + 1 byte length + password */ |
| 166 | #define ARC_FW_GETEVENTS 0x1a /* opcode + 1 byte for page 0/1/2/3 */ |
| 167 | #define ARC_FW_GETHWMON 0x1b /* opcode + arc_fw_hwmon */ |
| 168 | #define ARC_FW_RAIDINFO 0x20 /* opcode + raid# */ |
| 169 | #define ARC_FW_VOLINFO 0x21 /* opcode + vol# */ |
| 170 | #define ARC_FW_DISKINFO 0x22 /* opcode + physdisk# */ |
| 171 | #define ARC_FW_SYSINFO 0x23 /* opcode. reply is fw_sysinfo */ |
| 172 | #define ARC_FW_CLEAREVENTS 0x24 /* opcode only */ |
| 173 | #define ARC_FW_MUTE_ALARM 0x30 /* opcode only */ |
| 174 | #define ARC_FW_SET_ALARM 0x31 /* opcode + 1 byte for setting */ |
| 175 | #define ARC_FW_SET_ALARM_DISABLE 0x00 |
| 176 | #define ARC_FW_SET_ALARM_ENABLE 0x01 |
| 177 | #define ARC_FW_SET_PASS 0x32 /* opcode + 1 byte length + password */ |
| 178 | #define ARC_FW_REBUILD_PRIO 0x34 /* Rebuild priority for disks */ |
| 179 | #define ARC_FW_REBUILD_PRIO_ULTRALOW (1<<0) |
| 180 | #define ARC_FW_REBUILD_PRIO_LOW (1<<1) |
| 181 | #define ARC_FW_REBUILD_PRIO_NORMAL (1<<2) |
| 182 | #define ARC_FW_REBUILD_PRIO_HIGH (1<<3) |
| 183 | #define ARC_FW_SET_MAXATA_MODE 0x35 /* opcode + 1 byte mode */ |
| 184 | #define ARC_FW_SET_MAXATA_MODE_133 (1<<0) |
| 185 | #define ARC_FW_SET_MAXATA_MODE_100 (1<<1) |
| 186 | #define ARC_FW_SET_MAXATA_MODE_66 (1<<2) |
| 187 | #define ARC_FW_SET_MAXATA_MODE_33 (1<<3) |
| 188 | #define ARC_FW_NOP 0x38 /* opcode only */ |
| 189 | /* |
| 190 | * Structure for ARC_FW_CREATE_PASSTHRU: |
| 191 | * |
| 192 | * byte 2 command code 0x40 |
| 193 | * byte 3 device # |
| 194 | * byte 4 scsi channel (0/1) |
| 195 | * byte 5 scsi id (0/15) |
| 196 | * byte 6 scsi lun (0/7) |
| 197 | * byte 7 tagged queue (1 enabled) |
| 198 | * byte 8 cache mode (1 enabled) |
| 199 | * byte 9 max speed ((0/1/2/3/4 -> 33/66/100/133/150) |
| 200 | */ |
| 201 | #define ARC_FW_CREATE_PASSTHRU 0x40 |
| 202 | #define ARC_FW_DELETE_PASSTHRU 0x42 /* opcode + device# */ |
| 203 | |
| 204 | /* |
| 205 | * Structure for ARC_FW_CREATE_RAIDSET: |
| 206 | * |
| 207 | * byte 2 command code 0x50 |
| 208 | * byte 3-6 device mask |
| 209 | * byte 7-22 raidset name (byte 7 == 0 use default) |
| 210 | */ |
| 211 | #define ARC_FW_CREATE_RAIDSET 0x50 |
| 212 | #define ARC_FW_DELETE_RAIDSET 0x51 /* opcode + raidset# */ |
| 213 | #define ARC_FW_CREATE_HOTSPARE 0x54 /* opcode + 4 bytes device mask */ |
| 214 | #define ARC_FW_DELETE_HOTSPARE 0x55 /* opcode + 4 bytes device mask */ |
| 215 | |
| 216 | /* |
| 217 | * Structure for ARC_FW_CREATE_VOLUME/ARC_FW_MODIFY_VOLUME: |
| 218 | * |
| 219 | * byte 2 command code 0x60 |
| 220 | * byte 3 raidset# |
| 221 | * byte 4-19 volume set name (byte 4 == 0 use default) |
| 222 | * byte 20-27 volume capacity in blocks |
| 223 | * byte 28 raid level |
| 224 | * byte 29 stripe size |
| 225 | * byte 30 channel |
| 226 | * byte 31 ID |
| 227 | * byte 32 LUN |
| 228 | * byte 33 1 enable tag queuing |
| 229 | * byte 33 1 enable cache |
| 230 | * byte 35 speed 0/1/2/3/4 -> 33/66/100/133/150 |
| 231 | * byte 36 1 for quick init (only for CREATE_VOLUME) |
| 232 | */ |
| 233 | #define ARC_FW_CREATE_VOLUME 0x60 |
| 234 | #define ARC_FW_MODIFY_VOLUME 0x61 |
| 235 | #define ARC_FW_DELETE_VOLUME 0x62 /* opcode + vol# */ |
| 236 | #define ARC_FW_START_CHECKVOL 0x63 /* opcode + vol# */ |
| 237 | #define ARC_FW_STOP_CHECKVOL 0x64 /* opcode only */ |
| 238 | |
| 239 | /* Status codes for the firmware command codes */ |
| 240 | #define ARC_FW_CMD_OK 0x41 |
| 241 | #define ARC_FW_CMD_RAIDINVAL 0x42 |
| 242 | #define ARC_FW_CMD_VOLINVAL 0x43 |
| 243 | #define ARC_FW_CMD_NORAID 0x44 |
| 244 | #define ARC_FW_CMD_NOVOLUME 0x45 |
| 245 | #define ARC_FW_CMD_NOPHYSDRV 0x46 |
| 246 | #define ARC_FW_CMD_PARAM_ERR 0x47 |
| 247 | #define ARC_FW_CMD_UNSUPPORTED 0x48 |
| 248 | #define ARC_FW_CMD_DISKCFG_CHGD 0x49 |
| 249 | #define ARC_FW_CMD_PASS_INVAL 0x4a |
| 250 | #define ARC_FW_CMD_NODISKSPACE 0x4b |
| 251 | #define ARC_FW_CMD_CHECKSUM_ERR 0x4c |
| 252 | #define ARC_FW_CMD_PASS_REQD 0x4d |
| 253 | |
| 254 | struct arc_fw_hwmon { |
| 255 | uint8_t nfans; |
| 256 | uint8_t nvoltages; |
| 257 | uint8_t ntemps; |
| 258 | uint8_t npower; |
| 259 | uint16_t fan0; /* RPM */ |
| 260 | uint16_t fan1; /* RPM */ |
| 261 | uint16_t voltage_orig0; /* original value * 1000 */ |
| 262 | uint16_t voltage_val0; /* value */ |
| 263 | uint16_t voltage_orig1; /* original value * 1000 */ |
| 264 | uint16_t voltage_val1; /* value */ |
| 265 | uint16_t voltage_orig2; |
| 266 | uint16_t voltage_val2; |
| 267 | uint8_t temp0; |
| 268 | uint8_t temp1; |
| 269 | uint8_t pwr_indicator; /* (bit0 : power#0, bit1 : power#1) */ |
| 270 | uint8_t ups_indicator; |
| 271 | } __packed; |
| 272 | |
| 273 | struct arc_fw_comminfo { |
| 274 | uint8_t baud_rate; |
| 275 | uint8_t data_bits; |
| 276 | uint8_t stop_bits; |
| 277 | uint8_t parity; |
| 278 | uint8_t flow_control; |
| 279 | } __packed; |
| 280 | |
| 281 | struct arc_fw_scsiattr { |
| 282 | uint8_t channel; /* channel for SCSI target (0/1) */ |
| 283 | uint8_t target; |
| 284 | uint8_t lun; |
| 285 | uint8_t tagged; |
| 286 | uint8_t cache; |
| 287 | uint8_t speed; |
| 288 | } __packed; |
| 289 | |
| 290 | struct arc_fw_raidinfo { |
| 291 | uint8_t set_name[16]; |
| 292 | uint32_t capacity; |
| 293 | uint32_t capacity2; |
| 294 | uint32_t fail_mask; |
| 295 | uint8_t device_array[32]; |
| 296 | uint8_t member_devices; |
| 297 | uint8_t new_member_devices; |
| 298 | uint8_t raid_state; |
| 299 | uint8_t volumes; |
| 300 | uint8_t volume_list[16]; |
| 301 | uint8_t reserved1[3]; |
| 302 | uint8_t free_segments; |
| 303 | uint32_t raw_stripes[8]; |
| 304 | uint8_t reserved2[12]; |
| 305 | } __packed; |
| 306 | |
| 307 | struct arc_fw_volinfo { |
| 308 | uint8_t set_name[16]; |
| 309 | uint32_t capacity; |
| 310 | uint32_t capacity2; |
| 311 | uint32_t fail_mask; |
| 312 | uint32_t stripe_size; /* in blocks */ |
| 313 | uint32_t new_fail_mask; |
| 314 | uint32_t new_stripe_size; |
| 315 | uint32_t volume_status; |
| 316 | #define ARC_FW_VOL_STATUS_NORMAL 0x00 |
| 317 | #define ARC_FW_VOL_STATUS_INITTING (1<<0) |
| 318 | #define ARC_FW_VOL_STATUS_FAILED (1<<1) |
| 319 | #define ARC_FW_VOL_STATUS_MIGRATING (1<<2) |
| 320 | #define ARC_FW_VOL_STATUS_REBUILDING (1<<3) |
| 321 | #define ARC_FW_VOL_STATUS_NEED_INIT (1<<4) |
| 322 | #define ARC_FW_VOL_STATUS_NEED_MIGRATE (1<<5) |
| 323 | #define ARC_FW_VOL_STATUS_INIT_FLAG (1<<6) |
| 324 | #define ARC_FW_VOL_STATUS_NEED_REGEN (1<<7) |
| 325 | #define ARC_FW_VOL_STATUS_CHECKING (1<<8) |
| 326 | #define ARC_FW_VOL_STATUS_NEED_CHECK (1<<9) |
| 327 | uint32_t progress; |
| 328 | struct arc_fw_scsiattr scsi_attr; |
| 329 | uint8_t member_disks; |
| 330 | uint8_t raid_level; |
| 331 | #define ARC_FW_VOL_RAIDLEVEL_0 0x00 |
| 332 | #define ARC_FW_VOL_RAIDLEVEL_1 0x01 |
| 333 | #define ARC_FW_VOL_RAIDLEVEL_3 0x02 |
| 334 | #define ARC_FW_VOL_RAIDLEVEL_5 0x03 |
| 335 | #define ARC_FW_VOL_RAIDLEVEL_6 0x04 |
| 336 | #define ARC_FW_VOL_RAIDLEVEL_PASSTHRU 0x05 |
| 337 | uint8_t new_member_disks; |
| 338 | uint8_t new_raid_level; |
| 339 | uint8_t raid_set_number; |
| 340 | uint8_t reserved[5]; |
| 341 | } __packed; |
| 342 | |
| 343 | struct arc_fw_diskinfo { |
| 344 | uint8_t model[40]; |
| 345 | uint8_t serial[20]; |
| 346 | uint8_t firmware_rev[8]; |
| 347 | uint32_t capacity; |
| 348 | uint32_t capacity2; |
| 349 | uint8_t device_state; |
| 350 | #define ARC_FW_DISK_NORMAL 0x88 /* disk attached/initialized */ |
| 351 | #define ARC_FW_DISK_PASSTHRU 0x8a /* pass through disk in normal state */ |
| 352 | #define ARC_FW_DISK_HOTSPARE 0xa8 /* hotspare disk in normal state */ |
| 353 | #define ARC_FW_DISK_UNUSED 0xc8 /* free/unused disk in normal state */ |
| 354 | #define ARC_FW_DISK_FAILED 0x10 /* disk in failed state */ |
| 355 | uint8_t pio_mode; |
| 356 | uint8_t current_udma_mode; |
| 357 | uint8_t udma_mode; |
| 358 | uint8_t drive_select; |
| 359 | uint8_t raid_number; /* 0xff unowned */ |
| 360 | struct arc_fw_scsiattr scsi_attr; |
| 361 | uint8_t reserved[40]; |
| 362 | } __packed; |
| 363 | |
| 364 | struct arc_fw_sysinfo { |
| 365 | uint8_t vendor_name[40]; |
| 366 | uint8_t serial_number[16]; |
| 367 | uint8_t firmware_version[16]; |
| 368 | uint8_t boot_version[16]; |
| 369 | uint8_t mb_version[16]; |
| 370 | uint8_t model_name[8]; |
| 371 | |
| 372 | uint8_t local_ip[4]; |
| 373 | uint8_t current_ip[4]; |
| 374 | |
| 375 | uint32_t time_tick; |
| 376 | uint32_t cpu_speed; |
| 377 | uint32_t icache; |
| 378 | uint32_t dcache; |
| 379 | uint32_t scache; |
| 380 | uint32_t memory_size; |
| 381 | uint32_t memory_speed; |
| 382 | uint32_t events; |
| 383 | |
| 384 | uint8_t gsiMacAddress[6]; |
| 385 | uint8_t gsiDhcp; |
| 386 | |
| 387 | uint8_t alarm; |
| 388 | uint8_t channel_usage; |
| 389 | uint8_t max_ata_mode; |
| 390 | uint8_t sdram_ecc; |
| 391 | uint8_t rebuild_priority; |
| 392 | struct arc_fw_comminfo comm_a; |
| 393 | struct arc_fw_comminfo comm_b; |
| 394 | uint8_t ide_channels; |
| 395 | uint8_t scsi_host_channels; |
| 396 | uint8_t ide_host_channels; |
| 397 | uint8_t max_volume_set; |
| 398 | uint8_t max_raid_set; |
| 399 | uint8_t ether_port; |
| 400 | uint8_t raid6_engine; |
| 401 | uint8_t reserved[75]; |
| 402 | } __packed; |
| 403 | |
| 404 | /* |
| 405 | * autconf(9) glue. |
| 406 | */ |
| 407 | struct arc_ccb; |
| 408 | TAILQ_HEAD(arc_ccb_list, arc_ccb); |
| 409 | |
| 410 | typedef struct arc_edata { |
| 411 | envsys_data_t arc_sensor; |
| 412 | int arc_diskid; |
| 413 | int arc_volid; |
| 414 | } arc_edata_t; |
| 415 | |
| 416 | struct arc_softc { |
| 417 | struct scsipi_channel sc_chan; |
| 418 | struct scsipi_adapter sc_adapter; |
| 419 | |
| 420 | pci_chipset_tag_t sc_pc; |
| 421 | pcitag_t sc_tag; |
| 422 | |
| 423 | bus_space_tag_t sc_iot; |
| 424 | bus_space_handle_t sc_ioh; |
| 425 | bus_size_t sc_ios; |
| 426 | bus_dma_tag_t sc_dmat; |
| 427 | |
| 428 | void *sc_ih; |
| 429 | |
| 430 | int sc_req_count; |
| 431 | |
| 432 | struct arc_dmamem *sc_requests; |
| 433 | struct arc_ccb *sc_ccbs; |
| 434 | struct arc_ccb_list sc_ccb_free; |
| 435 | |
| 436 | struct lwp *sc_lwp; |
| 437 | volatile int sc_talking; |
| 438 | kmutex_t sc_mutex; |
| 439 | kcondvar_t sc_condvar; |
| 440 | krwlock_t sc_rwlock; |
| 441 | |
| 442 | struct sysmon_envsys *sc_sme; |
| 443 | arc_edata_t *sc_arc_sensors; |
| 444 | int sc_nsensors; |
| 445 | |
| 446 | size_t sc_maxraidset; /* max raid sets */ |
| 447 | size_t sc_maxvolset; /* max volume sets */ |
| 448 | size_t sc_cchans; /* connected channels */ |
| 449 | |
| 450 | device_t sc_dev; /* self */ |
| 451 | device_t sc_scsibus_dv; |
| 452 | }; |
| 453 | |
| 454 | /* |
| 455 | * wrap up the bus_dma api. |
| 456 | */ |
| 457 | struct arc_dmamem { |
| 458 | bus_dmamap_t adm_map; |
| 459 | bus_dma_segment_t adm_seg; |
| 460 | size_t adm_size; |
| 461 | void *adm_kva; |
| 462 | }; |
| 463 | #define ARC_DMA_MAP(_adm) ((_adm)->adm_map) |
| 464 | #define ARC_DMA_DVA(_adm) ((_adm)->adm_map->dm_segs[0].ds_addr) |
| 465 | #define ARC_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) |
| 466 | |
| 467 | /* |
| 468 | * stuff to manage a scsi command. |
| 469 | */ |
| 470 | struct arc_ccb { |
| 471 | struct arc_softc *ccb_sc; |
| 472 | int ccb_id; |
| 473 | |
| 474 | struct scsipi_xfer *ccb_xs; |
| 475 | |
| 476 | bus_dmamap_t ccb_dmamap; |
| 477 | bus_addr_t ccb_offset; |
| 478 | struct arc_io_cmd *ccb_cmd; |
| 479 | uint32_t ccb_cmd_post; |
| 480 | |
| 481 | TAILQ_ENTRY(arc_ccb) ccb_link; |
| 482 | }; |
| 483 | |
| 484 | #endif /* ! _PCI_ARCMSRVAR_H_ */ |
| 485 | |