| 1 | /* $NetBSD: if_otusreg.h,v 1.4 2013/01/20 21:50:41 christos Exp $ */ |
| 2 | /* $OpenBSD: if_otusreg.h,v 1.6 2009/04/06 18:17:01 damien Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> |
| 6 | * Copyright (c) 2007-2008 Atheros Communications, Inc. |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | #ifndef _IF_OTUSREG_H_ |
| 21 | #define _IF_OTUSREG_H_ |
| 22 | |
| 23 | /* USB Endpoints addresses. */ |
| 24 | #define AR_EPT_BULK_TX_NO (UE_DIR_OUT | 1) |
| 25 | #define AR_EPT_BULK_RX_NO (UE_DIR_IN | 2) |
| 26 | #define AR_EPT_INTR_RX_NO (UE_DIR_IN | 3) |
| 27 | #define AR_EPT_INTR_TX_NO (UE_DIR_OUT | 4) |
| 28 | |
| 29 | /* USB Requests. */ |
| 30 | #define AR_FW_DOWNLOAD 0x30 |
| 31 | #define AR_FW_DOWNLOAD_COMPLETE 0x31 |
| 32 | |
| 33 | /* Maximum number of writes that can fit in a single FW command is 7. */ |
| 34 | #define AR_FW_MAX_WRITES 7 /* 56 bytes */ |
| 35 | |
| 36 | #define AR_FW_INIT_ADDR 0x102800 |
| 37 | #define AR_FW_MAIN_ADDR 0x200000 |
| 38 | |
| 39 | /* |
| 40 | * AR9170 MAC registers. |
| 41 | */ |
| 42 | #define AR_MAC_REG_BASE 0x1c3000 |
| 43 | #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610) |
| 44 | #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614) |
| 45 | #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618) |
| 46 | #define AR_MAC_REG_BSSID_H (AR_MAC_REG_BASE + 0x61c) |
| 47 | #define AR_MAC_REG_GROUP_HASH_TBL_L (AR_MAC_REG_BASE + 0x624) |
| 48 | #define AR_MAC_REG_GROUP_HASH_TBL_H (AR_MAC_REG_BASE + 0x628) |
| 49 | #define AR_MAC_REG_RX_TIMEOUT (AR_MAC_REG_BASE + 0x62c) |
| 50 | #define AR_MAC_REG_BASIC_RATE (AR_MAC_REG_BASE + 0x630) |
| 51 | #define AR_MAC_REG_MANDATORY_RATE (AR_MAC_REG_BASE + 0x634) |
| 52 | #define AR_MAC_REG_RTS_CTS_RATE (AR_MAC_REG_BASE + 0x638) |
| 53 | #define AR_MAC_REG_BACKOFF_PROTECT (AR_MAC_REG_BASE + 0x63c) |
| 54 | #define AR_MAC_REG_RX_THRESHOLD (AR_MAC_REG_BASE + 0x640) |
| 55 | #define AR_MAC_REG_RX_PE_DELAY (AR_MAC_REG_BASE + 0x64c) |
| 56 | #define AR_MAC_REG_DYNAMIC_SIFS_ACK (AR_MAC_REG_BASE + 0x658) |
| 57 | #define AR_MAC_REG_SNIFFER (AR_MAC_REG_BASE + 0x674) |
| 58 | #define AR_MAC_REG_SNIFFER_ENABLE_PROMISC (1 << 0) |
| 59 | #define AR_MAC_REG_SNIFFER_HW_MIC_CHECK 0x02000000 |
| 60 | #define AR_MAC_REG_SNIFFER_DEFAULTS 0x02000000 |
| 61 | #define AR_MAC_REG_ENCRYPTION (AR_MAC_REG_BASE + 0x678) |
| 62 | #define AR_MAC_REG_ENCRYPTION_RX_SOFTWARE (1 << 3) |
| 63 | #define AR_MAC_REG_ENCRYPTION_DEFAULTS 0x00000070 |
| 64 | |
| 65 | #define AR_MAC_REG_MISC_680 (AR_MAC_REG_BASE + 0x680) |
| 66 | #define AR_MAC_REG_TX_UNDERRUN (AR_MAC_REG_BASE + 0x688) |
| 67 | |
| 68 | #define AR_MAC_REG_FRAMETYPE_FILTER (AR_MAC_REG_BASE + 0x68c) |
| 69 | #define AR_MAC_REG_FTF_ASSOC_REQ (1 << 0) |
| 70 | #define AR_MAC_REG_FTF_ASSOC_RESP (1 << 1) |
| 71 | #define AR_MAC_REG_FTF_REASSOC_REQ (1 << 2) |
| 72 | #define AR_MAC_REG_FTF_REASSOC_RESP (1 << 3) |
| 73 | #define AR_MAC_REG_FTF_PRB_REQ (1 << 4) |
| 74 | #define AR_MAC_REG_FTF_PRB_RESP (1 << 5) |
| 75 | #define AR_MAC_REG_FTF_BIT6 (1 << 6) |
| 76 | #define AR_MAC_REG_FTF_BIT7 (1 << 7) |
| 77 | #define AR_MAC_REG_FTF_BEACON (1 << 8) |
| 78 | #define AR_MAC_REG_FTF_ATIM (1 << 9) |
| 79 | #define AR_MAC_REG_FTF_DEASSOC (1 << 10) |
| 80 | #define AR_MAC_REG_FTF_AUTH (1 << 11) |
| 81 | #define AR_MAC_REG_FTF_DEAUTH (1 << 12) |
| 82 | #define AR_MAC_REG_FTF_BIT13 (1 << 13) |
| 83 | #define AR_MAC_REG_FTF_BIT14 (1 << 14) |
| 84 | #define AR_MAC_REG_FTF_BIT15 (1 << 15) |
| 85 | #define AR_MAC_REG_FTF_BAR (1 << 24) |
| 86 | #define AR_MAC_REG_FTF_BA (1 << 25) |
| 87 | #define AR_MAC_REG_FTF_PSPOLL (1 << 26) |
| 88 | #define AR_MAC_REG_FTF_RTS (1 << 27) |
| 89 | #define AR_MAC_REG_FTF_CTS (1 << 28) |
| 90 | #define AR_MAC_REG_FTF_ACK (1 << 29) |
| 91 | #define AR_MAC_REG_FTF_CFE (1 << 30) |
| 92 | #define AR_MAC_REG_FTF_CFE_ACK (1 << 31) |
| 93 | #define AR_MAC_REG_FTF_DEFAULTS 0x0700ffff |
| 94 | #define AR_MAC_REG_FTF_MONITOR 0xfd00ffff |
| 95 | //#define AR_MAC_REG_FTF_MONITOR 0xff00ffff |
| 96 | |
| 97 | #define AR_MAC_REG_ACK_EXTENSION (AR_MAC_REG_BASE + 0x690) |
| 98 | #define AR_MAC_REG_EIFS_AND_SIFS (AR_MAC_REG_BASE + 0x698) |
| 99 | #define AR_MAC_REG_BUSY (AR_MAC_REG_BASE + 0x6e8) |
| 100 | #define AR_MAC_REG_BUSY_EXT (AR_MAC_REG_BASE + 0x6ec) |
| 101 | #define AR_MAC_REG_SLOT_TIME (AR_MAC_REG_BASE + 0x6f0) |
| 102 | #define AR_MAC_REG_POWERMANAGEMENT (AR_MAC_REG_BASE + 0x700) |
| 103 | #define AR_MAC_REG_POWERMGT_IBSS 0xe0 |
| 104 | #define AR_MAC_REG_POWERMGT_AP 0xa1 |
| 105 | #define AR_MAC_REG_POWERMGT_STA 0x02 |
| 106 | #define AR_MAC_REG_POWERMGT_AP_WDS 0x03 |
| 107 | #define AR_MAC_REG_POWERMGT_DEFAULTS 0x0f000000 |
| 108 | |
| 109 | #define AR_MAC_REG_AC0_CW (AR_MAC_REG_BASE + 0xb00) |
| 110 | #define AR_MAC_REG_AC1_CW (AR_MAC_REG_BASE + 0xb04) |
| 111 | #define AR_MAC_REG_AC2_CW (AR_MAC_REG_BASE + 0xb08) |
| 112 | #define AR_MAC_REG_AC3_CW (AR_MAC_REG_BASE + 0xb0c) |
| 113 | #define AR_MAC_REG_AC4_CW (AR_MAC_REG_BASE + 0xb10) |
| 114 | #define AR_MAC_REG_AC1_AC0_AIFS (AR_MAC_REG_BASE + 0xb14) |
| 115 | #define AR_MAC_REG_AC3_AC2_AIFS (AR_MAC_REG_BASE + 0xb18) |
| 116 | #define AR_MAC_REG_RETRY_MAX (AR_MAC_REG_BASE + 0xb28) |
| 117 | #define AR_MAC_REG_FCS_SELECT (AR_MAC_REG_BASE + 0xbb0) |
| 118 | #define AR_MAC_FCS_SWFCS (1 << 0) |
| 119 | #define AR_MAC_FCS_FIFO_PROT (1 << 2) |
| 120 | |
| 121 | #define AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION \ |
| 122 | (AR_MAC_REG_BASE + 0xb30) |
| 123 | #define AR_MAC_REG_AC1_AC0_TXOP (AR_MAC_REG_BASE + 0xb44) |
| 124 | #define AR_MAC_REG_AC3_AC2_TXOP (AR_MAC_REG_BASE + 0xb48) |
| 125 | |
| 126 | #define AR_MAC_REG_AMPDU_FACTOR (AR_MAC_REG_BASE + 0xb9c) |
| 127 | #define AR_MAC_REG_AMPDU_DENSITY (AR_MAC_REG_BASE + 0xba0) |
| 128 | |
| 129 | #define AR_MAC_REG_ACK_TABLE (AR_MAC_REG_BASE + 0xc00) |
| 130 | #define AR_MAC_REG_AMPDU_RX_THRESH (AR_MAC_REG_BASE + 0xc50) |
| 131 | |
| 132 | #define AR_MAC_REG_OFDM_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb4) |
| 133 | #define AR_MAC_REG_CCK_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb8) |
| 134 | |
| 135 | #define AR_MAC_REG_DMA (AR_MAC_REG_BASE + 0xd30) |
| 136 | #define AR_MAC_REG_DMA_OFF 0 |
| 137 | #define AR_MAC_REG_DMA_ENABLE (1 << 8) |
| 138 | |
| 139 | #define AR_MAC_REG_TXRX_MPI (AR_MAC_REG_BASE + 0xd7c) |
| 140 | #define AR_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f |
| 141 | #define AR_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 |
| 142 | #define AR_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000 |
| 143 | #define AR_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000 |
| 144 | |
| 145 | #define AR_MAC_REG_BCN_ADDR (AR_MAC_REG_BASE + 0xd84) |
| 146 | #define AR_MAC_REG_BCN_LENGTH (AR_MAC_REG_BASE + 0xd88) |
| 147 | #define AR_MAC_REG_BCN_PLCP (AR_MAC_REG_BASE + 0xd90) |
| 148 | #define AR_MAC_REG_BCN_CTRL (AR_MAC_REG_BASE + 0xd94) |
| 149 | #define AR_MAC_REG_BCN_HT1 (AR_MAC_REG_BASE + 0xda0) |
| 150 | #define AR_MAC_REG_BCN_HT2 (AR_MAC_REG_BASE + 0xda4) |
| 151 | |
| 152 | /* |
| 153 | * GPIO register |
| 154 | */ |
| 155 | #define AR_GPIO_REG_BASE 0x1d0100 |
| 156 | #define AR_GPIO_REG_PORT_TYPE (AR_GPIO_REG_BASE + 0) |
| 157 | #define AR_GPIO_REG_DATA (AR_GPIO_REG_BASE + 4) |
| 158 | #define AR_GPIO_REG_DATA_LED0_ON (1 << 0) |
| 159 | #define AR_GPIO_REG_DATA_LED0_OFF (0 << 0) |
| 160 | #define AR_GPIO_REG_DATA_LED1_ON (1 << 1) |
| 161 | #define AR_GPIO_REG_DATA_LED1_OFF (0 << 1) |
| 162 | #define AR_NUM_LEDS 2 |
| 163 | |
| 164 | /* |
| 165 | * Power register |
| 166 | */ |
| 167 | #define AR_PWR_REG_BASE 0x1d4000 |
| 168 | #define AR_PWR_REG_CLOCK_SEL (AR_PWR_REG_BASE + 0x008) |
| 169 | #define AR_PWR_CLK_AHB_40MHZ 0 |
| 170 | #define AR_PWR_CLK_AHB_20_22MHZ 1 |
| 171 | #define AR_PWR_CLK_AHB_40_44MHZ 2 |
| 172 | #define AR_PWR_CLK_AHB_80_88MHZ 3 |
| 173 | #define AR_PWR_CLK_DAC_160_INV_DLY 0x70 |
| 174 | |
| 175 | /* |
| 176 | * USB register |
| 177 | */ |
| 178 | #define AR_USB_REG_BASE 0x1e1000 |
| 179 | #define AR_USB_REG_DMA_CTL (AR_USB_REG_BASE + 0x108) |
| 180 | #define AR_USB_REG_DMA_CTL_ENABLE_TO_DEVICE (1 << 0) |
| 181 | #define AR_USB_REG_DMA_CTL_ENABLE_FROM_DEVICE (1 << 1) |
| 182 | #define AR_USB_REG_DMA_CTL_HIGH_SPEED (1 << 2) |
| 183 | #define AR_USB_REG_DMA_CTL_PACKET_MODE (1 << 3) |
| 184 | #define AR_USB_REG_DMA_CTL_RX_STREAM_4K (0 << 4) |
| 185 | #define AR_USB_REG_DMA_CTL_RX_STREAM_8K (1 << 4) |
| 186 | #define AR_USB_REG_DMA_CTL_RX_STREAM_16K (2 << 4) |
| 187 | #define AR_USB_REG_DMA_CTL_RX_STREAM_32K (3 << 4) |
| 188 | #define AR_USB_REG_DMA_CTL_TX_STREAM_MODE (1 << 6) |
| 189 | |
| 190 | #define AR_USB_REG_MAX_AGG_UPLOAD (AR_USB_REG_BASE + 0x110) |
| 191 | #define AR_USB_REG_UPLOAD_TIME_CTL (AR_USB_REG_BASE + 0x114) |
| 192 | |
| 193 | /* Possible values for register AR_USB_MODE_CTRL. */ |
| 194 | #define AR_USB_DS_ENA (1 << 0) |
| 195 | #define AR_USB_US_ENA (1 << 1) |
| 196 | #define AR_USB_US_PACKET_MODE (1 << 3) |
| 197 | |
| 198 | /* |
| 199 | * PHY registers. |
| 200 | */ |
| 201 | #define AR_PHY_BASE 0x1c5800 |
| 202 | #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4) |
| 203 | #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004) |
| 204 | #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028) |
| 205 | #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034) |
| 206 | #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044) |
| 207 | #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048) |
| 208 | #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050) |
| 209 | #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058) |
| 210 | #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c) |
| 211 | #define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068) |
| 212 | #define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c) |
| 213 | #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) |
| 214 | #define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124) |
| 215 | #define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134) |
| 216 | #define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138) |
| 217 | #define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c) |
| 218 | #define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160) |
| 219 | #define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164) |
| 220 | #define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0) |
| 221 | #define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08) |
| 222 | #define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c) |
| 223 | #define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34) |
| 224 | #define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38) |
| 225 | #define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58) |
| 226 | #define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c) |
| 227 | #define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90) |
| 228 | #define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc) |
| 229 | #define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0) |
| 230 | #define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4) |
| 231 | #define AR_PHY_CCA (AR_PHY_BASE + 0x3064) |
| 232 | |
| 233 | #define AR_SEEPROM_HW_TYPE_OFFSET 0x1374 |
| 234 | #define AR_EEPROM_OFFSET 0x1600 |
| 235 | |
| 236 | #define AR_BANK4_CHUP (1 << 0) |
| 237 | #define AR_BANK4_BMODE_LF_SYNTH_FREQ (1 << 1) |
| 238 | #define AR_BANK4_AMODE_REFSEL(x) ((x) << 2) |
| 239 | #define AR_BANK4_ADDR(x) ((x) << 5) |
| 240 | |
| 241 | /* Tx descriptor. */ |
| 242 | struct ar_tx_head { |
| 243 | uint16_t len; |
| 244 | uint16_t macctl; |
| 245 | #define AR_TX_MAC_RTS (1 << 0) |
| 246 | #define AR_TX_MAC_CTS (1 << 1) |
| 247 | #define AR_TX_MAC_BACKOFF (1 << 3) |
| 248 | #define AR_TX_MAC_NOACK (1 << 2) |
| 249 | #define AR_TX_MAC_HW_DUR (1 << 9) |
| 250 | #define AR_TX_MAC_QID(qid) ((qid) << 10) |
| 251 | #define AR_TX_MAC_RATE_PROBING (1 << 15) |
| 252 | |
| 253 | uint32_t phyctl; |
| 254 | /* Modulation type. */ |
| 255 | #define AR_TX_PHY_MT_CCK 0 |
| 256 | #define AR_TX_PHY_MT_OFDM 1 |
| 257 | #define AR_TX_PHY_MT_HT 2 |
| 258 | #define AR_TX_PHY_GF (1 << 2) |
| 259 | #define AR_TX_PHY_BW_SHIFT 3 |
| 260 | #define AR_TX_PHY_TPC_SHIFT 9 |
| 261 | #define AR_TX_PHY_ANTMSK(msk) ((msk) << 15) |
| 262 | #define AR_TX_PHY_MCS(mcs) ((mcs) << 18) |
| 263 | #define AR_TX_PHY_SHGI (1 << 31) |
| 264 | } __packed; |
| 265 | |
| 266 | /* USB Rx stream mode header. */ |
| 267 | struct ar_rx_head { |
| 268 | uint16_t len; |
| 269 | uint16_t tag; |
| 270 | #define AR_RX_HEAD_TAG 0x4e00 |
| 271 | } __packed; |
| 272 | |
| 273 | /* Rx descriptor. */ |
| 274 | struct ar_rx_tail { |
| 275 | uint8_t [3]; |
| 276 | uint8_t [3]; |
| 277 | uint8_t ; /* Combined RSSI. */ |
| 278 | uint8_t evm[2][6]; /* Error Vector Magnitude. */ |
| 279 | uint8_t phy_err; |
| 280 | uint8_t sa_idx; |
| 281 | uint8_t da_idx; |
| 282 | uint8_t error; |
| 283 | #define AR_RX_ERROR_TIMEOUT (1 << 0) |
| 284 | #define AR_RX_ERROR_OVERRUN (1 << 1) |
| 285 | #define AR_RX_ERROR_DECRYPT (1 << 2) |
| 286 | #define AR_RX_ERROR_FCS (1 << 3) |
| 287 | #define AR_RX_ERROR_BAD_RA (1 << 4) |
| 288 | #define AR_RX_ERROR_PLCP (1 << 5) |
| 289 | #define AR_RX_ERROR_MMIC (1 << 6) |
| 290 | |
| 291 | uint8_t status; |
| 292 | /* Modulation type (same as AR_TX_PHY_MT). */ |
| 293 | #define AR_RX_STATUS_MT_MASK 0x3 |
| 294 | #define AR_RX_STATUS_MT_CCK 0 |
| 295 | #define AR_RX_STATUS_MT_OFDM 1 |
| 296 | #define AR_RX_STATUS_MT_HT 2 |
| 297 | #define AR_RX_STATUS_SHPREAMBLE (1 << 3) |
| 298 | } __packed; |
| 299 | |
| 300 | #define AR_PLCP_HDR_LEN 12 |
| 301 | /* Magic PLCP header for firmware notifications through Rx bulk pipe. */ |
| 302 | static uint8_t AR_PLCP_HDR_INTR[] = { |
| 303 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
| 304 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff |
| 305 | }; |
| 306 | |
| 307 | /* Firmware command/reply header. */ |
| 308 | struct ar_cmd_hdr { |
| 309 | uint8_t len; |
| 310 | uint8_t code; |
| 311 | #define AR_CMD_RREG 0x00 |
| 312 | #define AR_CMD_WREG 0x01 |
| 313 | #define AR_CMD_RMEM 0x02 |
| 314 | #define AR_CMD_WMEM 0x03 |
| 315 | #define AR_CMD_BITAND 0x04 |
| 316 | #define AR_CMD_BITOR 0x05 |
| 317 | #define AR_CMD_EKEY 0x28 |
| 318 | #define AR_CMD_DKEY 0x29 |
| 319 | #define AR_CMD_FREQUENCY 0x30 |
| 320 | #define AR_CMD_RF_INIT 0x31 |
| 321 | #define AR_CMD_SYNTH 0x32 |
| 322 | #define AR_CMD_FREQ_STRAT 0x33 |
| 323 | #define AR_CMD_ECHO 0x80 |
| 324 | #define AR_CMD_TALLY 0x81 |
| 325 | #define AR_CMD_TALLY_APD 0x82 |
| 326 | #define AR_CMD_CONFIG 0x83 |
| 327 | #define AR_CMD_RESET 0x90 |
| 328 | #define AR_CMD_DKRESET 0x91 |
| 329 | #define AR_CMD_DKTX_STATUS 0x92 |
| 330 | #define AR_CMD_FDC 0xa0 |
| 331 | #define AR_CMD_WREEPROM 0xb0 |
| 332 | #define AR_CMD_WFLASH AR_CMD_WREEPROM |
| 333 | #define AR_CMD_FLASH_ERASE 0xb1 |
| 334 | #define AR_CMD_FLASH_PROG 0xb2 |
| 335 | #define AR_CMD_FLASH_CHKSUM 0xb3 |
| 336 | #define AR_CMD_FLASH_READ 0xb4 |
| 337 | #define AR_CMD_FW_DL_INIT 0xb5 |
| 338 | #define AR_CMD_MEM_WREEPROM 0xbb |
| 339 | /* Those have the 2 MSB set to 1. */ |
| 340 | #define AR_EVT_BEACON 0x00 |
| 341 | #define AR_EVT_TX_COMP 0x01 |
| 342 | #define AR_EVT_TBTT 0x02 |
| 343 | #define AR_EVT_ATIM 0x03 |
| 344 | |
| 345 | uint16_t token; /* Driver private data. */ |
| 346 | } __packed; |
| 347 | |
| 348 | /* Structure for command AR_CMD_RF_INIT/AR_CMD_FREQUENCY. */ |
| 349 | struct ar_cmd_frequency { |
| 350 | uint32_t freq; |
| 351 | uint32_t dynht2040; |
| 352 | uint32_t htena; |
| 353 | uint32_t dsc_exp; |
| 354 | uint32_t dsc_man; |
| 355 | uint32_t dsc_shgi_exp; |
| 356 | uint32_t dsc_shgi_man; |
| 357 | uint32_t check_loop_count; |
| 358 | } __packed; |
| 359 | |
| 360 | /* Firmware reply for command AR_CMD_FREQUENCY. */ |
| 361 | struct ar_rsp_frequency { |
| 362 | uint32_t status; |
| 363 | #define AR_CAL_ERR_AGC (1 << 0) /* AGC cal unfinished. */ |
| 364 | #define AR_CAL_ERR_NF (1 << 1) /* Noise cal unfinished. */ |
| 365 | #define AR_CAL_ERR_NF_VAL (1 << 2) /* NF value unexpected. */ |
| 366 | |
| 367 | uint32_t nf[3]; /* Noisefloor. */ |
| 368 | uint32_t nf_ext[3]; /* Noisefloor ext. */ |
| 369 | } __packed; |
| 370 | |
| 371 | /* Structure for command AR_CMD_EKEY. */ |
| 372 | struct ar_cmd_ekey { |
| 373 | uint16_t uid; /* user ID */ |
| 374 | uint16_t kix; |
| 375 | uint16_t cipher; |
| 376 | #define AR_CIPHER_NONE 0 |
| 377 | #define AR_CIPHER_WEP64 1 |
| 378 | #define AR_CIPHER_TKIP 2 |
| 379 | #define AR_CIPHER_AES 4 |
| 380 | #define AR_CIPHER_WEP128 5 |
| 381 | #define AR_CIPHER_WEP256 6 |
| 382 | #define AR_CIPHER_CENC 7 |
| 383 | |
| 384 | uint8_t macaddr[IEEE80211_ADDR_LEN]; |
| 385 | uint8_t key[16]; |
| 386 | } __packed; |
| 387 | |
| 388 | /* Structure for event AR_EVT_TX_COMP. */ |
| 389 | struct ar_evt_tx_comp { |
| 390 | uint8_t macaddr[IEEE80211_ADDR_LEN]; |
| 391 | uint32_t phy; |
| 392 | uint16_t status; |
| 393 | #define AR_TX_STATUS_COMP 0 |
| 394 | #define AR_TX_STATUS_RETRY_COMP 1 |
| 395 | #define AR_TX_STATUS_FAILED 2 |
| 396 | } __packed; |
| 397 | |
| 398 | /* |
| 399 | * EEPROM. |
| 400 | */ |
| 401 | /* Possible flags for opCapFlags. */ |
| 402 | #define AR5416_OPFLAGS_11A 0x01 |
| 403 | #define AR5416_OPFLAGS_11G 0x02 |
| 404 | #define AR5416_OPFLAGS_5G_HT40 0x04 |
| 405 | #define AR5416_OPFLAGS_2G_HT40 0x08 |
| 406 | #define AR5416_OPFLAGS_5G_HT20 0x10 |
| 407 | #define AR5416_OPFLAGS_2G_HT20 0x20 |
| 408 | |
| 409 | #define AR5416_NUM_5G_CAL_PIERS 8 |
| 410 | #define AR5416_NUM_2G_CAL_PIERS 4 |
| 411 | #define AR5416_NUM_5G_20_TARGET_POWERS 8 |
| 412 | #define AR5416_NUM_5G_40_TARGET_POWERS 8 |
| 413 | #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 |
| 414 | #define AR5416_NUM_2G_20_TARGET_POWERS 4 |
| 415 | #define AR5416_NUM_2G_40_TARGET_POWERS 4 |
| 416 | #define AR5416_NUM_CTLS 24 |
| 417 | #define AR5416_NUM_BAND_EDGES 8 |
| 418 | #define AR5416_NUM_PD_GAINS 4 |
| 419 | #define AR5416_PD_GAIN_ICEPTS 5 |
| 420 | #define AR5416_EEPROM_MODAL_SPURS 5 |
| 421 | #define AR5416_MAX_CHAINS 2 |
| 422 | |
| 423 | typedef struct { |
| 424 | uint16_t ; |
| 425 | uint16_t ; |
| 426 | uint16_t ; |
| 427 | uint8_t ; |
| 428 | uint8_t ; |
| 429 | uint16_t [2]; |
| 430 | uint8_t [6]; |
| 431 | uint8_t ; |
| 432 | uint8_t ; |
| 433 | uint16_t ; |
| 434 | uint16_t ; |
| 435 | uint16_t ; |
| 436 | uint32_t ; |
| 437 | uint8_t ; |
| 438 | uint8_t [33]; |
| 439 | } __packed ; |
| 440 | |
| 441 | typedef struct spurChanStruct { |
| 442 | uint16_t spurChan; |
| 443 | uint8_t spurRangeLow; |
| 444 | uint8_t spurRangeHigh; |
| 445 | } __packed SPUR_CHAN; |
| 446 | |
| 447 | typedef struct { |
| 448 | uint32_t [AR5416_MAX_CHAINS]; |
| 449 | uint32_t ; |
| 450 | int8_t [AR5416_MAX_CHAINS]; |
| 451 | uint8_t ; |
| 452 | uint8_t [AR5416_MAX_CHAINS]; |
| 453 | uint8_t [AR5416_MAX_CHAINS]; |
| 454 | uint8_t ; |
| 455 | int8_t ; |
| 456 | uint8_t [AR5416_MAX_CHAINS]; |
| 457 | uint8_t ; |
| 458 | uint8_t ; |
| 459 | uint8_t ; |
| 460 | uint8_t ; |
| 461 | uint8_t [AR5416_MAX_CHAINS]; |
| 462 | uint8_t ; |
| 463 | uint8_t ; |
| 464 | int8_t [AR5416_MAX_CHAINS]; |
| 465 | int8_t [AR5416_MAX_CHAINS]; |
| 466 | uint8_t ; |
| 467 | uint8_t ; |
| 468 | uint8_t ; |
| 469 | uint8_t ; |
| 470 | uint8_t ; |
| 471 | uint8_t ; |
| 472 | uint8_t ; |
| 473 | uint8_t ; |
| 474 | uint8_t ; |
| 475 | uint8_t [AR5416_MAX_CHAINS]; |
| 476 | uint8_t [AR5416_MAX_CHAINS]; |
| 477 | uint8_t ; |
| 478 | uint8_t [22]; |
| 479 | SPUR_CHAN [AR5416_EEPROM_MODAL_SPURS]; |
| 480 | } __packed ; |
| 481 | |
| 482 | typedef struct calDataPerFreq { |
| 483 | uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
| 484 | uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
| 485 | } __packed CAL_DATA_PER_FREQ; |
| 486 | |
| 487 | typedef struct CalTargetPowerLegacy { |
| 488 | uint8_t bChannel; |
| 489 | uint8_t tPow2x[4]; |
| 490 | } __packed CAL_TARGET_POWER_LEG; |
| 491 | |
| 492 | typedef struct CalTargetPowerHt { |
| 493 | uint8_t bChannel; |
| 494 | uint8_t tPow2x[8]; |
| 495 | } __packed CAL_TARGET_POWER_HT; |
| 496 | |
| 497 | typedef struct CalCtlEdges { |
| 498 | uint8_t bChannel; |
| 499 | uint8_t tPowerFlag; |
| 500 | } __packed CAL_CTL_EDGES; |
| 501 | |
| 502 | typedef struct CalCtlData { |
| 503 | CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; |
| 504 | } __packed CAL_CTL_DATA; |
| 505 | |
| 506 | typedef struct ar5416eeprom { |
| 507 | BASE_EEP_HEADER ; |
| 508 | uint8_t custData[64]; |
| 509 | MODAL_EEP_HEADER [2]; |
| 510 | uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; |
| 511 | uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; |
| 512 | CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS] |
| 513 | [AR5416_NUM_5G_CAL_PIERS]; |
| 514 | CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS] |
| 515 | [AR5416_NUM_2G_CAL_PIERS]; |
| 516 | CAL_TARGET_POWER_LEG calTPow5G[AR5416_NUM_5G_20_TARGET_POWERS]; |
| 517 | CAL_TARGET_POWER_HT calTPow5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; |
| 518 | CAL_TARGET_POWER_HT calTPow5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; |
| 519 | CAL_TARGET_POWER_LEG calTPowCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; |
| 520 | CAL_TARGET_POWER_LEG calTPow2G[AR5416_NUM_2G_20_TARGET_POWERS]; |
| 521 | CAL_TARGET_POWER_HT calTPow2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; |
| 522 | CAL_TARGET_POWER_HT calTPow2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; |
| 523 | uint8_t ctlIndex[AR5416_NUM_CTLS]; |
| 524 | CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; |
| 525 | uint8_t padding[3]; |
| 526 | } __packed AR5416_EEPROM; |
| 527 | |
| 528 | #endif /* _IF_OTUSREG_H_ */ |
| 529 | |
| 530 | |