| 1 | /* $NetBSD: if_msk.c,v 1.52 2016/11/06 21:51:31 christos Exp $ */ |
| 2 | /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 1997, 1998, 1999, 2000 |
| 6 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. All advertising materials mentioning features or use of this software |
| 17 | * must display the following acknowledgement: |
| 18 | * This product includes software developed by Bill Paul. |
| 19 | * 4. Neither the name of the author nor the names of any co-contributors |
| 20 | * may be used to endorse or promote products derived from this software |
| 21 | * without specific prior written permission. |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 26 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 27 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 33 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 34 | * |
| 35 | * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ |
| 36 | */ |
| 37 | |
| 38 | /* |
| 39 | * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> |
| 40 | * |
| 41 | * Permission to use, copy, modify, and distribute this software for any |
| 42 | * purpose with or without fee is hereby granted, provided that the above |
| 43 | * copyright notice and this permission notice appear in all copies. |
| 44 | * |
| 45 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 46 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 47 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 48 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 49 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 50 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 51 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 52 | */ |
| 53 | |
| 54 | #include <sys/cdefs.h> |
| 55 | __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.52 2016/11/06 21:51:31 christos Exp $" ); |
| 56 | |
| 57 | #include <sys/param.h> |
| 58 | #include <sys/systm.h> |
| 59 | #include <sys/sockio.h> |
| 60 | #include <sys/mbuf.h> |
| 61 | #include <sys/malloc.h> |
| 62 | #include <sys/mutex.h> |
| 63 | #include <sys/kernel.h> |
| 64 | #include <sys/socket.h> |
| 65 | #include <sys/device.h> |
| 66 | #include <sys/queue.h> |
| 67 | #include <sys/callout.h> |
| 68 | #include <sys/sysctl.h> |
| 69 | #include <sys/endian.h> |
| 70 | #ifdef __NetBSD__ |
| 71 | #define letoh16 htole16 |
| 72 | #define letoh32 htole32 |
| 73 | #endif |
| 74 | |
| 75 | #include <net/if.h> |
| 76 | #include <net/if_dl.h> |
| 77 | #include <net/if_types.h> |
| 78 | |
| 79 | #include <net/if_media.h> |
| 80 | |
| 81 | #include <net/bpf.h> |
| 82 | #include <sys/rndsource.h> |
| 83 | |
| 84 | #include <dev/mii/mii.h> |
| 85 | #include <dev/mii/miivar.h> |
| 86 | #include <dev/mii/brgphyreg.h> |
| 87 | |
| 88 | #include <dev/pci/pcireg.h> |
| 89 | #include <dev/pci/pcivar.h> |
| 90 | #include <dev/pci/pcidevs.h> |
| 91 | |
| 92 | #include <dev/pci/if_skreg.h> |
| 93 | #include <dev/pci/if_mskvar.h> |
| 94 | |
| 95 | int mskc_probe(device_t, cfdata_t, void *); |
| 96 | void mskc_attach(device_t, device_t, void *); |
| 97 | static bool mskc_suspend(device_t, const pmf_qual_t *); |
| 98 | static bool mskc_resume(device_t, const pmf_qual_t *); |
| 99 | int msk_probe(device_t, cfdata_t, void *); |
| 100 | void msk_attach(device_t, device_t, void *); |
| 101 | int mskcprint(void *, const char *); |
| 102 | int msk_intr(void *); |
| 103 | void msk_intr_yukon(struct sk_if_softc *); |
| 104 | void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); |
| 105 | void msk_txeof(struct sk_if_softc *, int); |
| 106 | int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); |
| 107 | void msk_start(struct ifnet *); |
| 108 | int msk_ioctl(struct ifnet *, u_long, void *); |
| 109 | int msk_init(struct ifnet *); |
| 110 | void msk_init_yukon(struct sk_if_softc *); |
| 111 | void msk_stop(struct ifnet *, int); |
| 112 | void msk_watchdog(struct ifnet *); |
| 113 | void msk_reset(struct sk_softc *); |
| 114 | int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); |
| 115 | int msk_alloc_jumbo_mem(struct sk_if_softc *); |
| 116 | void *msk_jalloc(struct sk_if_softc *); |
| 117 | void msk_jfree(struct mbuf *, void *, size_t, void *); |
| 118 | int msk_init_rx_ring(struct sk_if_softc *); |
| 119 | int msk_init_tx_ring(struct sk_if_softc *); |
| 120 | |
| 121 | void msk_update_int_mod(struct sk_softc *, int); |
| 122 | |
| 123 | int msk_miibus_readreg(device_t, int, int); |
| 124 | void msk_miibus_writereg(device_t, int, int, int); |
| 125 | void msk_miibus_statchg(struct ifnet *); |
| 126 | |
| 127 | void msk_setfilt(struct sk_if_softc *, void *, int); |
| 128 | void msk_setmulti(struct sk_if_softc *); |
| 129 | void msk_setpromisc(struct sk_if_softc *); |
| 130 | void msk_tick(void *); |
| 131 | |
| 132 | /* #define MSK_DEBUG 1 */ |
| 133 | #ifdef MSK_DEBUG |
| 134 | #define DPRINTF(x) if (mskdebug) printf x |
| 135 | #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x |
| 136 | int mskdebug = MSK_DEBUG; |
| 137 | |
| 138 | void msk_dump_txdesc(struct msk_tx_desc *, int); |
| 139 | void msk_dump_mbuf(struct mbuf *); |
| 140 | void msk_dump_bytes(const char *, int); |
| 141 | #else |
| 142 | #define DPRINTF(x) |
| 143 | #define DPRINTFN(n,x) |
| 144 | #endif |
| 145 | |
| 146 | static int msk_sysctl_handler(SYSCTLFN_PROTO); |
| 147 | static int msk_root_num; |
| 148 | |
| 149 | /* supported device vendors */ |
| 150 | static const struct msk_product { |
| 151 | pci_vendor_id_t msk_vendor; |
| 152 | pci_product_id_t msk_product; |
| 153 | } msk_products[] = { |
| 154 | { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, |
| 155 | { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, |
| 156 | { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, |
| 157 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, |
| 158 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, |
| 159 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, |
| 160 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, |
| 161 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, |
| 162 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, |
| 163 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, |
| 164 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, |
| 165 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, |
| 166 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, |
| 167 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, |
| 168 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, |
| 169 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, |
| 170 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, |
| 171 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, |
| 172 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, |
| 173 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, |
| 174 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, |
| 175 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, |
| 176 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, |
| 177 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, |
| 178 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, |
| 179 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, |
| 180 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, |
| 181 | { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, |
| 182 | { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, |
| 183 | { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } |
| 184 | }; |
| 185 | |
| 186 | static inline u_int32_t |
| 187 | sk_win_read_4(struct sk_softc *sc, u_int32_t reg) |
| 188 | { |
| 189 | return CSR_READ_4(sc, reg); |
| 190 | } |
| 191 | |
| 192 | static inline u_int16_t |
| 193 | sk_win_read_2(struct sk_softc *sc, u_int32_t reg) |
| 194 | { |
| 195 | return CSR_READ_2(sc, reg); |
| 196 | } |
| 197 | |
| 198 | static inline u_int8_t |
| 199 | sk_win_read_1(struct sk_softc *sc, u_int32_t reg) |
| 200 | { |
| 201 | return CSR_READ_1(sc, reg); |
| 202 | } |
| 203 | |
| 204 | static inline void |
| 205 | sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) |
| 206 | { |
| 207 | CSR_WRITE_4(sc, reg, x); |
| 208 | } |
| 209 | |
| 210 | static inline void |
| 211 | sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) |
| 212 | { |
| 213 | CSR_WRITE_2(sc, reg, x); |
| 214 | } |
| 215 | |
| 216 | static inline void |
| 217 | sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) |
| 218 | { |
| 219 | CSR_WRITE_1(sc, reg, x); |
| 220 | } |
| 221 | |
| 222 | int |
| 223 | msk_miibus_readreg(device_t dev, int phy, int reg) |
| 224 | { |
| 225 | struct sk_if_softc *sc_if = device_private(dev); |
| 226 | u_int16_t val; |
| 227 | int i; |
| 228 | |
| 229 | SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | |
| 230 | YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); |
| 231 | |
| 232 | for (i = 0; i < SK_TIMEOUT; i++) { |
| 233 | DELAY(1); |
| 234 | val = SK_YU_READ_2(sc_if, YUKON_SMICR); |
| 235 | if (val & YU_SMICR_READ_VALID) |
| 236 | break; |
| 237 | } |
| 238 | |
| 239 | if (i == SK_TIMEOUT) { |
| 240 | aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n" ); |
| 241 | return (0); |
| 242 | } |
| 243 | |
| 244 | DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n" , i, |
| 245 | SK_TIMEOUT)); |
| 246 | |
| 247 | val = SK_YU_READ_2(sc_if, YUKON_SMIDR); |
| 248 | |
| 249 | DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n" , |
| 250 | phy, reg, val)); |
| 251 | |
| 252 | return (val); |
| 253 | } |
| 254 | |
| 255 | void |
| 256 | msk_miibus_writereg(device_t dev, int phy, int reg, int val) |
| 257 | { |
| 258 | struct sk_if_softc *sc_if = device_private(dev); |
| 259 | int i; |
| 260 | |
| 261 | DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n" , |
| 262 | phy, reg, val)); |
| 263 | |
| 264 | SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); |
| 265 | SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | |
| 266 | YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); |
| 267 | |
| 268 | for (i = 0; i < SK_TIMEOUT; i++) { |
| 269 | DELAY(1); |
| 270 | if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) |
| 271 | break; |
| 272 | } |
| 273 | |
| 274 | if (i == SK_TIMEOUT) |
| 275 | aprint_error_dev(sc_if->sk_dev, "phy write timed out\n" ); |
| 276 | } |
| 277 | |
| 278 | void |
| 279 | msk_miibus_statchg(struct ifnet *ifp) |
| 280 | { |
| 281 | struct sk_if_softc *sc_if = ifp->if_softc; |
| 282 | struct mii_data *mii = &sc_if->sk_mii; |
| 283 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; |
| 284 | int gpcr; |
| 285 | |
| 286 | gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); |
| 287 | gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); |
| 288 | |
| 289 | if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { |
| 290 | /* Set speed. */ |
| 291 | gpcr |= YU_GPCR_SPEED_DIS; |
| 292 | switch (IFM_SUBTYPE(mii->mii_media_active)) { |
| 293 | case IFM_1000_SX: |
| 294 | case IFM_1000_LX: |
| 295 | case IFM_1000_CX: |
| 296 | case IFM_1000_T: |
| 297 | gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); |
| 298 | break; |
| 299 | case IFM_100_TX: |
| 300 | gpcr |= YU_GPCR_SPEED; |
| 301 | break; |
| 302 | } |
| 303 | |
| 304 | /* Set duplex. */ |
| 305 | gpcr |= YU_GPCR_DPLX_DIS; |
| 306 | if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) |
| 307 | gpcr |= YU_GPCR_DUPLEX; |
| 308 | |
| 309 | /* Disable flow control. */ |
| 310 | gpcr |= YU_GPCR_FCTL_DIS; |
| 311 | gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); |
| 312 | } |
| 313 | |
| 314 | SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); |
| 315 | |
| 316 | DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n" , |
| 317 | SK_YU_READ_2(sc_if, YUKON_GPCR))); |
| 318 | } |
| 319 | |
| 320 | #define HASH_BITS 6 |
| 321 | |
| 322 | void |
| 323 | msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) |
| 324 | { |
| 325 | char *addr = addrv; |
| 326 | int base = XM_RXFILT_ENTRY(slot); |
| 327 | |
| 328 | SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); |
| 329 | SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); |
| 330 | SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); |
| 331 | } |
| 332 | |
| 333 | void |
| 334 | msk_setmulti(struct sk_if_softc *sc_if) |
| 335 | { |
| 336 | struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; |
| 337 | u_int32_t hashes[2] = { 0, 0 }; |
| 338 | int h; |
| 339 | struct ethercom *ec = &sc_if->sk_ethercom; |
| 340 | struct ether_multi *enm; |
| 341 | struct ether_multistep step; |
| 342 | u_int16_t reg; |
| 343 | |
| 344 | /* First, zot all the existing filters. */ |
| 345 | SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); |
| 346 | SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); |
| 347 | SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); |
| 348 | SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); |
| 349 | |
| 350 | |
| 351 | /* Now program new ones. */ |
| 352 | reg = SK_YU_READ_2(sc_if, YUKON_RCR); |
| 353 | reg |= YU_RCR_UFLEN; |
| 354 | allmulti: |
| 355 | if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { |
| 356 | if ((ifp->if_flags & IFF_PROMISC) != 0) |
| 357 | reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); |
| 358 | else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { |
| 359 | hashes[0] = 0xFFFFFFFF; |
| 360 | hashes[1] = 0xFFFFFFFF; |
| 361 | } |
| 362 | } else { |
| 363 | /* First find the tail of the list. */ |
| 364 | ETHER_FIRST_MULTI(step, ec, enm); |
| 365 | while (enm != NULL) { |
| 366 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, |
| 367 | ETHER_ADDR_LEN)) { |
| 368 | ifp->if_flags |= IFF_ALLMULTI; |
| 369 | goto allmulti; |
| 370 | } |
| 371 | h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & |
| 372 | ((1 << HASH_BITS) - 1); |
| 373 | if (h < 32) |
| 374 | hashes[0] |= (1 << h); |
| 375 | else |
| 376 | hashes[1] |= (1 << (h - 32)); |
| 377 | |
| 378 | ETHER_NEXT_MULTI(step, enm); |
| 379 | } |
| 380 | reg |= YU_RCR_MUFLEN; |
| 381 | } |
| 382 | |
| 383 | SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); |
| 384 | SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); |
| 385 | SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); |
| 386 | SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); |
| 387 | SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); |
| 388 | } |
| 389 | |
| 390 | void |
| 391 | msk_setpromisc(struct sk_if_softc *sc_if) |
| 392 | { |
| 393 | struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; |
| 394 | |
| 395 | if (ifp->if_flags & IFF_PROMISC) |
| 396 | SK_YU_CLRBIT_2(sc_if, YUKON_RCR, |
| 397 | YU_RCR_UFLEN | YU_RCR_MUFLEN); |
| 398 | else |
| 399 | SK_YU_SETBIT_2(sc_if, YUKON_RCR, |
| 400 | YU_RCR_UFLEN | YU_RCR_MUFLEN); |
| 401 | } |
| 402 | |
| 403 | int |
| 404 | msk_init_rx_ring(struct sk_if_softc *sc_if) |
| 405 | { |
| 406 | struct msk_chain_data *cd = &sc_if->sk_cdata; |
| 407 | struct msk_ring_data *rd = sc_if->sk_rdata; |
| 408 | int i, nexti; |
| 409 | |
| 410 | memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); |
| 411 | |
| 412 | for (i = 0; i < MSK_RX_RING_CNT; i++) { |
| 413 | cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; |
| 414 | if (i == (MSK_RX_RING_CNT - 1)) |
| 415 | nexti = 0; |
| 416 | else |
| 417 | nexti = i + 1; |
| 418 | cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; |
| 419 | } |
| 420 | |
| 421 | for (i = 0; i < MSK_RX_RING_CNT; i++) { |
| 422 | if (msk_newbuf(sc_if, i, NULL, |
| 423 | sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { |
| 424 | aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n" , i); |
| 425 | return (ENOBUFS); |
| 426 | } |
| 427 | } |
| 428 | |
| 429 | sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; |
| 430 | sc_if->sk_cdata.sk_rx_cons = 0; |
| 431 | |
| 432 | return (0); |
| 433 | } |
| 434 | |
| 435 | int |
| 436 | msk_init_tx_ring(struct sk_if_softc *sc_if) |
| 437 | { |
| 438 | struct sk_softc *sc = sc_if->sk_softc; |
| 439 | struct msk_chain_data *cd = &sc_if->sk_cdata; |
| 440 | struct msk_ring_data *rd = sc_if->sk_rdata; |
| 441 | bus_dmamap_t dmamap; |
| 442 | struct sk_txmap_entry *entry; |
| 443 | int i, nexti; |
| 444 | |
| 445 | memset(sc_if->sk_rdata->sk_tx_ring, 0, |
| 446 | sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); |
| 447 | |
| 448 | SIMPLEQ_INIT(&sc_if->sk_txmap_head); |
| 449 | for (i = 0; i < MSK_TX_RING_CNT; i++) { |
| 450 | cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; |
| 451 | if (i == (MSK_TX_RING_CNT - 1)) |
| 452 | nexti = 0; |
| 453 | else |
| 454 | nexti = i + 1; |
| 455 | cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; |
| 456 | |
| 457 | if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, |
| 458 | SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) |
| 459 | return (ENOBUFS); |
| 460 | |
| 461 | entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); |
| 462 | if (!entry) { |
| 463 | bus_dmamap_destroy(sc->sc_dmatag, dmamap); |
| 464 | return (ENOBUFS); |
| 465 | } |
| 466 | entry->dmamap = dmamap; |
| 467 | SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); |
| 468 | } |
| 469 | |
| 470 | sc_if->sk_cdata.sk_tx_prod = 0; |
| 471 | sc_if->sk_cdata.sk_tx_cons = 0; |
| 472 | sc_if->sk_cdata.sk_tx_cnt = 0; |
| 473 | |
| 474 | MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, |
| 475 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 476 | |
| 477 | return (0); |
| 478 | } |
| 479 | |
| 480 | int |
| 481 | msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, |
| 482 | bus_dmamap_t dmamap) |
| 483 | { |
| 484 | struct mbuf *m_new = NULL; |
| 485 | struct sk_chain *c; |
| 486 | struct msk_rx_desc *r; |
| 487 | |
| 488 | if (m == NULL) { |
| 489 | void *buf = NULL; |
| 490 | |
| 491 | MGETHDR(m_new, M_DONTWAIT, MT_DATA); |
| 492 | if (m_new == NULL) |
| 493 | return (ENOBUFS); |
| 494 | |
| 495 | /* Allocate the jumbo buffer */ |
| 496 | buf = msk_jalloc(sc_if); |
| 497 | if (buf == NULL) { |
| 498 | m_freem(m_new); |
| 499 | DPRINTFN(1, ("%s jumbo allocation failed -- packet " |
| 500 | "dropped!\n" , sc_if->sk_ethercom.ec_if.if_xname)); |
| 501 | return (ENOBUFS); |
| 502 | } |
| 503 | |
| 504 | /* Attach the buffer to the mbuf */ |
| 505 | m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; |
| 506 | MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); |
| 507 | } else { |
| 508 | /* |
| 509 | * We're re-using a previously allocated mbuf; |
| 510 | * be sure to re-init pointers and lengths to |
| 511 | * default values. |
| 512 | */ |
| 513 | m_new = m; |
| 514 | m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; |
| 515 | m_new->m_data = m_new->m_ext.ext_buf; |
| 516 | } |
| 517 | m_adj(m_new, ETHER_ALIGN); |
| 518 | |
| 519 | c = &sc_if->sk_cdata.sk_rx_chain[i]; |
| 520 | r = c->sk_le; |
| 521 | c->sk_mbuf = m_new; |
| 522 | r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + |
| 523 | (((vaddr_t)m_new->m_data |
| 524 | - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); |
| 525 | r->sk_len = htole16(SK_JLEN); |
| 526 | r->sk_ctl = 0; |
| 527 | r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; |
| 528 | |
| 529 | MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); |
| 530 | |
| 531 | return (0); |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * Memory management for jumbo frames. |
| 536 | */ |
| 537 | |
| 538 | int |
| 539 | msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) |
| 540 | { |
| 541 | struct sk_softc *sc = sc_if->sk_softc; |
| 542 | char *ptr, *kva; |
| 543 | bus_dma_segment_t seg; |
| 544 | int i, rseg, state, error; |
| 545 | struct sk_jpool_entry *entry; |
| 546 | |
| 547 | state = error = 0; |
| 548 | |
| 549 | /* Grab a big chunk o' storage. */ |
| 550 | if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, |
| 551 | &seg, 1, &rseg, BUS_DMA_NOWAIT)) { |
| 552 | aprint_error(": can't alloc rx buffers" ); |
| 553 | return (ENOBUFS); |
| 554 | } |
| 555 | |
| 556 | state = 1; |
| 557 | if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, |
| 558 | BUS_DMA_NOWAIT)) { |
| 559 | aprint_error(": can't map dma buffers (%d bytes)" , MSK_JMEM); |
| 560 | error = ENOBUFS; |
| 561 | goto out; |
| 562 | } |
| 563 | |
| 564 | state = 2; |
| 565 | if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, |
| 566 | BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { |
| 567 | aprint_error(": can't create dma map" ); |
| 568 | error = ENOBUFS; |
| 569 | goto out; |
| 570 | } |
| 571 | |
| 572 | state = 3; |
| 573 | if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, |
| 574 | kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { |
| 575 | aprint_error(": can't load dma map" ); |
| 576 | error = ENOBUFS; |
| 577 | goto out; |
| 578 | } |
| 579 | |
| 580 | state = 4; |
| 581 | sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; |
| 582 | DPRINTFN(1,("msk_jumbo_buf = %p\n" , (void *)sc_if->sk_cdata.sk_jumbo_buf)); |
| 583 | |
| 584 | LIST_INIT(&sc_if->sk_jfree_listhead); |
| 585 | LIST_INIT(&sc_if->sk_jinuse_listhead); |
| 586 | mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); |
| 587 | |
| 588 | /* |
| 589 | * Now divide it up into 9K pieces and save the addresses |
| 590 | * in an array. |
| 591 | */ |
| 592 | ptr = sc_if->sk_cdata.sk_jumbo_buf; |
| 593 | for (i = 0; i < MSK_JSLOTS; i++) { |
| 594 | sc_if->sk_cdata.sk_jslots[i] = ptr; |
| 595 | ptr += SK_JLEN; |
| 596 | entry = malloc(sizeof(struct sk_jpool_entry), |
| 597 | M_DEVBUF, M_NOWAIT); |
| 598 | if (entry == NULL) { |
| 599 | sc_if->sk_cdata.sk_jumbo_buf = NULL; |
| 600 | aprint_error(": no memory for jumbo buffer queue!" ); |
| 601 | error = ENOBUFS; |
| 602 | goto out; |
| 603 | } |
| 604 | entry->slot = i; |
| 605 | LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, |
| 606 | entry, jpool_entries); |
| 607 | } |
| 608 | out: |
| 609 | if (error != 0) { |
| 610 | switch (state) { |
| 611 | case 4: |
| 612 | bus_dmamap_unload(sc->sc_dmatag, |
| 613 | sc_if->sk_cdata.sk_rx_jumbo_map); |
| 614 | case 3: |
| 615 | bus_dmamap_destroy(sc->sc_dmatag, |
| 616 | sc_if->sk_cdata.sk_rx_jumbo_map); |
| 617 | case 2: |
| 618 | bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); |
| 619 | case 1: |
| 620 | bus_dmamem_free(sc->sc_dmatag, &seg, rseg); |
| 621 | break; |
| 622 | default: |
| 623 | break; |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | return error; |
| 628 | } |
| 629 | |
| 630 | /* |
| 631 | * Allocate a jumbo buffer. |
| 632 | */ |
| 633 | void * |
| 634 | msk_jalloc(struct sk_if_softc *sc_if) |
| 635 | { |
| 636 | struct sk_jpool_entry *entry; |
| 637 | |
| 638 | mutex_enter(&sc_if->sk_jpool_mtx); |
| 639 | entry = LIST_FIRST(&sc_if->sk_jfree_listhead); |
| 640 | |
| 641 | if (entry == NULL) { |
| 642 | mutex_exit(&sc_if->sk_jpool_mtx); |
| 643 | return NULL; |
| 644 | } |
| 645 | |
| 646 | LIST_REMOVE(entry, jpool_entries); |
| 647 | LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); |
| 648 | mutex_exit(&sc_if->sk_jpool_mtx); |
| 649 | return (sc_if->sk_cdata.sk_jslots[entry->slot]); |
| 650 | } |
| 651 | |
| 652 | /* |
| 653 | * Release a jumbo buffer. |
| 654 | */ |
| 655 | void |
| 656 | msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) |
| 657 | { |
| 658 | struct sk_jpool_entry *entry; |
| 659 | struct sk_if_softc *sc; |
| 660 | int i; |
| 661 | |
| 662 | /* Extract the softc struct pointer. */ |
| 663 | sc = (struct sk_if_softc *)arg; |
| 664 | |
| 665 | if (sc == NULL) |
| 666 | panic("msk_jfree: can't find softc pointer!" ); |
| 667 | |
| 668 | /* calculate the slot this buffer belongs to */ |
| 669 | i = ((vaddr_t)buf |
| 670 | - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; |
| 671 | |
| 672 | if ((i < 0) || (i >= MSK_JSLOTS)) |
| 673 | panic("msk_jfree: asked to free buffer that we don't manage!" ); |
| 674 | |
| 675 | mutex_enter(&sc->sk_jpool_mtx); |
| 676 | entry = LIST_FIRST(&sc->sk_jinuse_listhead); |
| 677 | if (entry == NULL) |
| 678 | panic("msk_jfree: buffer not in use!" ); |
| 679 | entry->slot = i; |
| 680 | LIST_REMOVE(entry, jpool_entries); |
| 681 | LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); |
| 682 | mutex_exit(&sc->sk_jpool_mtx); |
| 683 | |
| 684 | if (__predict_true(m != NULL)) |
| 685 | pool_cache_put(mb_cache, m); |
| 686 | } |
| 687 | |
| 688 | int |
| 689 | msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
| 690 | { |
| 691 | struct sk_if_softc *sc = ifp->if_softc; |
| 692 | int s, error; |
| 693 | |
| 694 | s = splnet(); |
| 695 | |
| 696 | DPRINTFN(2, ("msk_ioctl ETHER\n" )); |
| 697 | switch (cmd) { |
| 698 | case SIOCSIFFLAGS: |
| 699 | if ((error = ifioctl_common(ifp, cmd, data)) != 0) |
| 700 | break; |
| 701 | |
| 702 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
| 703 | case IFF_RUNNING: |
| 704 | msk_stop(ifp, 1); |
| 705 | break; |
| 706 | case IFF_UP: |
| 707 | msk_init(ifp); |
| 708 | break; |
| 709 | case IFF_UP | IFF_RUNNING: |
| 710 | if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { |
| 711 | msk_setpromisc(sc); |
| 712 | msk_setmulti(sc); |
| 713 | } else |
| 714 | msk_init(ifp); |
| 715 | break; |
| 716 | } |
| 717 | sc->sk_if_flags = ifp->if_flags; |
| 718 | break; |
| 719 | default: |
| 720 | error = ether_ioctl(ifp, cmd, data); |
| 721 | if (error == ENETRESET) { |
| 722 | error = 0; |
| 723 | if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) |
| 724 | ; |
| 725 | else if (ifp->if_flags & IFF_RUNNING) { |
| 726 | /* |
| 727 | * Multicast list has changed; set the hardware |
| 728 | * filter accordingly. |
| 729 | */ |
| 730 | msk_setmulti(sc); |
| 731 | } |
| 732 | } |
| 733 | break; |
| 734 | } |
| 735 | |
| 736 | splx(s); |
| 737 | return error; |
| 738 | } |
| 739 | |
| 740 | void |
| 741 | msk_update_int_mod(struct sk_softc *sc, int verbose) |
| 742 | { |
| 743 | u_int32_t imtimer_ticks; |
| 744 | |
| 745 | /* |
| 746 | * Configure interrupt moderation. The moderation timer |
| 747 | * defers interrupts specified in the interrupt moderation |
| 748 | * timer mask based on the timeout specified in the interrupt |
| 749 | * moderation timer init register. Each bit in the timer |
| 750 | * register represents one tick, so to specify a timeout in |
| 751 | * microseconds, we have to multiply by the correct number of |
| 752 | * ticks-per-microsecond. |
| 753 | */ |
| 754 | switch (sc->sk_type) { |
| 755 | case SK_YUKON_EC: |
| 756 | case SK_YUKON_EC_U: |
| 757 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; |
| 758 | break; |
| 759 | case SK_YUKON_FE: |
| 760 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; |
| 761 | break; |
| 762 | case SK_YUKON_XL: |
| 763 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; |
| 764 | break; |
| 765 | default: |
| 766 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON; |
| 767 | } |
| 768 | if (verbose) |
| 769 | aprint_verbose_dev(sc->sk_dev, |
| 770 | "interrupt moderation is %d us\n" , sc->sk_int_mod); |
| 771 | sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); |
| 772 | sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| |
| 773 | SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); |
| 774 | sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); |
| 775 | sc->sk_int_mod_pending = 0; |
| 776 | } |
| 777 | |
| 778 | static int |
| 779 | msk_lookup(const struct pci_attach_args *pa) |
| 780 | { |
| 781 | const struct msk_product *pmsk; |
| 782 | |
| 783 | for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { |
| 784 | if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && |
| 785 | PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) |
| 786 | return 1; |
| 787 | } |
| 788 | return 0; |
| 789 | } |
| 790 | |
| 791 | /* |
| 792 | * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device |
| 793 | * IDs against our list and return a device name if we find a match. |
| 794 | */ |
| 795 | int |
| 796 | mskc_probe(device_t parent, cfdata_t match, void *aux) |
| 797 | { |
| 798 | struct pci_attach_args *pa = (struct pci_attach_args *)aux; |
| 799 | |
| 800 | return msk_lookup(pa); |
| 801 | } |
| 802 | |
| 803 | /* |
| 804 | * Force the GEnesis into reset, then bring it out of reset. |
| 805 | */ |
| 806 | void msk_reset(struct sk_softc *sc) |
| 807 | { |
| 808 | u_int32_t imtimer_ticks, reg1; |
| 809 | int reg; |
| 810 | |
| 811 | DPRINTFN(2, ("msk_reset\n" )); |
| 812 | |
| 813 | CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); |
| 814 | CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); |
| 815 | |
| 816 | DELAY(1000); |
| 817 | CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); |
| 818 | DELAY(2); |
| 819 | CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); |
| 820 | sk_win_write_1(sc, SK_TESTCTL1, 2); |
| 821 | |
| 822 | reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); |
| 823 | if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) |
| 824 | reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); |
| 825 | else |
| 826 | reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); |
| 827 | |
| 828 | if (sc->sk_type == SK_YUKON_EC_U) { |
| 829 | uint32_t our; |
| 830 | |
| 831 | CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); |
| 832 | |
| 833 | /* enable all clocks. */ |
| 834 | sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); |
| 835 | our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); |
| 836 | our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| |
| 837 | SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| |
| 838 | SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| |
| 839 | SK_Y2_REG4_ASPM_CLKRUN_REQUEST); |
| 840 | /* Set all bits to 0 except bits 15..12 */ |
| 841 | sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); |
| 842 | /* Set to default value */ |
| 843 | sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); |
| 844 | } |
| 845 | |
| 846 | /* release PHY from PowerDown/Coma mode. */ |
| 847 | sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); |
| 848 | |
| 849 | if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) |
| 850 | sk_win_write_1(sc, SK_Y2_CLKGATE, |
| 851 | SK_Y2_CLKGATE_LINK1_GATE_DIS | |
| 852 | SK_Y2_CLKGATE_LINK2_GATE_DIS | |
| 853 | SK_Y2_CLKGATE_LINK1_CORE_DIS | |
| 854 | SK_Y2_CLKGATE_LINK2_CORE_DIS | |
| 855 | SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); |
| 856 | else |
| 857 | sk_win_write_1(sc, SK_Y2_CLKGATE, 0); |
| 858 | |
| 859 | CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); |
| 860 | CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); |
| 861 | DELAY(1000); |
| 862 | CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); |
| 863 | CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); |
| 864 | |
| 865 | sk_win_write_1(sc, SK_TESTCTL1, 1); |
| 866 | |
| 867 | DPRINTFN(2, ("msk_reset: sk_csr=%x\n" , CSR_READ_1(sc, SK_CSR))); |
| 868 | DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n" , |
| 869 | CSR_READ_2(sc, SK_LINK_CTRL))); |
| 870 | |
| 871 | /* Disable ASF */ |
| 872 | CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); |
| 873 | CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); |
| 874 | |
| 875 | /* Clear I2C IRQ noise */ |
| 876 | CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); |
| 877 | |
| 878 | /* Disable hardware timer */ |
| 879 | CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); |
| 880 | CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); |
| 881 | |
| 882 | /* Disable descriptor polling */ |
| 883 | CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); |
| 884 | |
| 885 | /* Disable time stamps */ |
| 886 | CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); |
| 887 | CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); |
| 888 | |
| 889 | /* Enable RAM interface */ |
| 890 | sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); |
| 891 | for (reg = SK_TO0;reg <= SK_TO11; reg++) |
| 892 | sk_win_write_1(sc, reg, 36); |
| 893 | sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); |
| 894 | for (reg = SK_TO0;reg <= SK_TO11; reg++) |
| 895 | sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); |
| 896 | |
| 897 | /* |
| 898 | * Configure interrupt moderation. The moderation timer |
| 899 | * defers interrupts specified in the interrupt moderation |
| 900 | * timer mask based on the timeout specified in the interrupt |
| 901 | * moderation timer init register. Each bit in the timer |
| 902 | * register represents one tick, so to specify a timeout in |
| 903 | * microseconds, we have to multiply by the correct number of |
| 904 | * ticks-per-microsecond. |
| 905 | */ |
| 906 | switch (sc->sk_type) { |
| 907 | case SK_YUKON_EC: |
| 908 | case SK_YUKON_EC_U: |
| 909 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; |
| 910 | break; |
| 911 | case SK_YUKON_FE: |
| 912 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; |
| 913 | break; |
| 914 | case SK_YUKON_XL: |
| 915 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; |
| 916 | break; |
| 917 | default: |
| 918 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON; |
| 919 | } |
| 920 | |
| 921 | /* Reset status ring. */ |
| 922 | memset(sc->sk_status_ring, 0, |
| 923 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); |
| 924 | bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, |
| 925 | sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); |
| 926 | sc->sk_status_idx = 0; |
| 927 | sc->sk_status_own_idx = 0; |
| 928 | |
| 929 | sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); |
| 930 | sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); |
| 931 | |
| 932 | sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); |
| 933 | sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, |
| 934 | sc->sk_status_map->dm_segs[0].ds_addr); |
| 935 | sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, |
| 936 | (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); |
| 937 | if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { |
| 938 | sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); |
| 939 | sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); |
| 940 | sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); |
| 941 | } else { |
| 942 | sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); |
| 943 | sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); |
| 944 | sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, |
| 945 | ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); |
| 946 | sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ |
| 947 | } |
| 948 | |
| 949 | #if 0 |
| 950 | sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); |
| 951 | #endif |
| 952 | sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); |
| 953 | |
| 954 | sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); |
| 955 | |
| 956 | sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); |
| 957 | sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); |
| 958 | sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); |
| 959 | |
| 960 | msk_update_int_mod(sc, 0); |
| 961 | } |
| 962 | |
| 963 | int |
| 964 | msk_probe(device_t parent, cfdata_t match, void *aux) |
| 965 | { |
| 966 | struct skc_attach_args *sa = aux; |
| 967 | |
| 968 | if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) |
| 969 | return (0); |
| 970 | |
| 971 | switch (sa->skc_type) { |
| 972 | case SK_YUKON_XL: |
| 973 | case SK_YUKON_EC_U: |
| 974 | case SK_YUKON_EC: |
| 975 | case SK_YUKON_FE: |
| 976 | case SK_YUKON_FE_P: |
| 977 | return (1); |
| 978 | } |
| 979 | |
| 980 | return (0); |
| 981 | } |
| 982 | |
| 983 | static bool |
| 984 | msk_resume(device_t dv, const pmf_qual_t *qual) |
| 985 | { |
| 986 | struct sk_if_softc *sc_if = device_private(dv); |
| 987 | |
| 988 | msk_init_yukon(sc_if); |
| 989 | return true; |
| 990 | } |
| 991 | |
| 992 | /* |
| 993 | * Each XMAC chip is attached as a separate logical IP interface. |
| 994 | * Single port cards will have only one logical interface of course. |
| 995 | */ |
| 996 | void |
| 997 | msk_attach(device_t parent, device_t self, void *aux) |
| 998 | { |
| 999 | struct sk_if_softc *sc_if = device_private(self); |
| 1000 | struct sk_softc *sc = device_private(parent); |
| 1001 | struct skc_attach_args *sa = aux; |
| 1002 | struct ifnet *ifp; |
| 1003 | void *kva; |
| 1004 | bus_dma_segment_t seg; |
| 1005 | int i, rseg; |
| 1006 | u_int32_t chunk, val; |
| 1007 | |
| 1008 | sc_if->sk_dev = self; |
| 1009 | sc_if->sk_port = sa->skc_port; |
| 1010 | sc_if->sk_softc = sc; |
| 1011 | sc->sk_if[sa->skc_port] = sc_if; |
| 1012 | |
| 1013 | DPRINTFN(2, ("begin msk_attach: port=%d\n" , sc_if->sk_port)); |
| 1014 | |
| 1015 | /* |
| 1016 | * Get station address for this interface. Note that |
| 1017 | * dual port cards actually come with three station |
| 1018 | * addresses: one for each port, plus an extra. The |
| 1019 | * extra one is used by the SysKonnect driver software |
| 1020 | * as a 'virtual' station address for when both ports |
| 1021 | * are operating in failover mode. Currently we don't |
| 1022 | * use this extra address. |
| 1023 | */ |
| 1024 | for (i = 0; i < ETHER_ADDR_LEN; i++) |
| 1025 | sc_if->sk_enaddr[i] = |
| 1026 | sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); |
| 1027 | |
| 1028 | aprint_normal(": Ethernet address %s\n" , |
| 1029 | ether_sprintf(sc_if->sk_enaddr)); |
| 1030 | |
| 1031 | /* |
| 1032 | * Set up RAM buffer addresses. The NIC will have a certain |
| 1033 | * amount of SRAM on it, somewhere between 512K and 2MB. We |
| 1034 | * need to divide this up a) between the transmitter and |
| 1035 | * receiver and b) between the two XMACs, if this is a |
| 1036 | * dual port NIC. Our algorithm is to divide up the memory |
| 1037 | * evenly so that everyone gets a fair share. |
| 1038 | * |
| 1039 | * Just to be contrary, Yukon2 appears to have separate memory |
| 1040 | * for each MAC. |
| 1041 | */ |
| 1042 | chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; |
| 1043 | val = sc->sk_rboff / sizeof(u_int64_t); |
| 1044 | sc_if->sk_rx_ramstart = val; |
| 1045 | val += (chunk / sizeof(u_int64_t)); |
| 1046 | sc_if->sk_rx_ramend = val - 1; |
| 1047 | chunk = sc->sk_ramsize - chunk; |
| 1048 | sc_if->sk_tx_ramstart = val; |
| 1049 | val += (chunk / sizeof(u_int64_t)); |
| 1050 | sc_if->sk_tx_ramend = val - 1; |
| 1051 | |
| 1052 | DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" |
| 1053 | " tx_ramstart=%#x tx_ramend=%#x\n" , |
| 1054 | sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, |
| 1055 | sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); |
| 1056 | |
| 1057 | /* Allocate the descriptor queues. */ |
| 1058 | if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), |
| 1059 | PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { |
| 1060 | aprint_error(": can't alloc rx buffers\n" ); |
| 1061 | goto fail; |
| 1062 | } |
| 1063 | if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, |
| 1064 | sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { |
| 1065 | aprint_error(": can't map dma buffers (%zu bytes)\n" , |
| 1066 | sizeof(struct msk_ring_data)); |
| 1067 | goto fail_1; |
| 1068 | } |
| 1069 | if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, |
| 1070 | sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, |
| 1071 | &sc_if->sk_ring_map)) { |
| 1072 | aprint_error(": can't create dma map\n" ); |
| 1073 | goto fail_2; |
| 1074 | } |
| 1075 | if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, |
| 1076 | sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { |
| 1077 | aprint_error(": can't load dma map\n" ); |
| 1078 | goto fail_3; |
| 1079 | } |
| 1080 | sc_if->sk_rdata = (struct msk_ring_data *)kva; |
| 1081 | memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); |
| 1082 | |
| 1083 | ifp = &sc_if->sk_ethercom.ec_if; |
| 1084 | /* Try to allocate memory for jumbo buffers. */ |
| 1085 | if (msk_alloc_jumbo_mem(sc_if)) { |
| 1086 | aprint_error(": jumbo buffer allocation failed\n" ); |
| 1087 | goto fail_3; |
| 1088 | } |
| 1089 | sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; |
| 1090 | if (sc->sk_type != SK_YUKON_FE) |
| 1091 | sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
| 1092 | |
| 1093 | ifp->if_softc = sc_if; |
| 1094 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
| 1095 | ifp->if_ioctl = msk_ioctl; |
| 1096 | ifp->if_start = msk_start; |
| 1097 | ifp->if_stop = msk_stop; |
| 1098 | ifp->if_init = msk_init; |
| 1099 | ifp->if_watchdog = msk_watchdog; |
| 1100 | ifp->if_baudrate = 1000000000; |
| 1101 | IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); |
| 1102 | IFQ_SET_READY(&ifp->if_snd); |
| 1103 | strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); |
| 1104 | |
| 1105 | /* |
| 1106 | * Do miibus setup. |
| 1107 | */ |
| 1108 | msk_init_yukon(sc_if); |
| 1109 | |
| 1110 | DPRINTFN(2, ("msk_attach: 1\n" )); |
| 1111 | |
| 1112 | sc_if->sk_mii.mii_ifp = ifp; |
| 1113 | sc_if->sk_mii.mii_readreg = msk_miibus_readreg; |
| 1114 | sc_if->sk_mii.mii_writereg = msk_miibus_writereg; |
| 1115 | sc_if->sk_mii.mii_statchg = msk_miibus_statchg; |
| 1116 | |
| 1117 | sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; |
| 1118 | ifmedia_init(&sc_if->sk_mii.mii_media, 0, |
| 1119 | ether_mediachange, ether_mediastatus); |
| 1120 | mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, |
| 1121 | MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); |
| 1122 | if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { |
| 1123 | aprint_error_dev(sc_if->sk_dev, "no PHY found!\n" ); |
| 1124 | ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, |
| 1125 | 0, NULL); |
| 1126 | ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); |
| 1127 | } else |
| 1128 | ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); |
| 1129 | |
| 1130 | callout_init(&sc_if->sk_tick_ch, 0); |
| 1131 | callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); |
| 1132 | callout_schedule(&sc_if->sk_tick_ch, hz); |
| 1133 | |
| 1134 | /* |
| 1135 | * Call MI attach routines. |
| 1136 | */ |
| 1137 | if_attach(ifp); |
| 1138 | ether_ifattach(ifp, sc_if->sk_enaddr); |
| 1139 | |
| 1140 | if (pmf_device_register(self, NULL, msk_resume)) |
| 1141 | pmf_class_network_register(self, ifp); |
| 1142 | else |
| 1143 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 1144 | |
| 1145 | rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), |
| 1146 | RND_TYPE_NET, RND_FLAG_DEFAULT); |
| 1147 | |
| 1148 | DPRINTFN(2, ("msk_attach: end\n" )); |
| 1149 | return; |
| 1150 | |
| 1151 | fail_3: |
| 1152 | bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); |
| 1153 | fail_2: |
| 1154 | bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); |
| 1155 | fail_1: |
| 1156 | bus_dmamem_free(sc->sc_dmatag, &seg, rseg); |
| 1157 | fail: |
| 1158 | sc->sk_if[sa->skc_port] = NULL; |
| 1159 | } |
| 1160 | |
| 1161 | int |
| 1162 | mskcprint(void *aux, const char *pnp) |
| 1163 | { |
| 1164 | struct skc_attach_args *sa = aux; |
| 1165 | |
| 1166 | if (pnp) |
| 1167 | aprint_normal("sk port %c at %s" , |
| 1168 | (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); |
| 1169 | else |
| 1170 | aprint_normal(" port %c" , (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); |
| 1171 | return (UNCONF); |
| 1172 | } |
| 1173 | |
| 1174 | /* |
| 1175 | * Attach the interface. Allocate softc structures, do ifmedia |
| 1176 | * setup and ethernet/BPF attach. |
| 1177 | */ |
| 1178 | void |
| 1179 | mskc_attach(device_t parent, device_t self, void *aux) |
| 1180 | { |
| 1181 | struct sk_softc *sc = device_private(self); |
| 1182 | struct pci_attach_args *pa = aux; |
| 1183 | struct skc_attach_args skca; |
| 1184 | pci_chipset_tag_t pc = pa->pa_pc; |
| 1185 | pcireg_t command, memtype; |
| 1186 | pci_intr_handle_t ih; |
| 1187 | const char *intrstr = NULL; |
| 1188 | bus_size_t size; |
| 1189 | int rc, sk_nodenum; |
| 1190 | u_int8_t hw, skrs; |
| 1191 | const char *revstr = NULL; |
| 1192 | const struct sysctlnode *node; |
| 1193 | void *kva; |
| 1194 | bus_dma_segment_t seg; |
| 1195 | int rseg; |
| 1196 | char intrbuf[PCI_INTRSTR_LEN]; |
| 1197 | |
| 1198 | DPRINTFN(2, ("begin mskc_attach\n" )); |
| 1199 | |
| 1200 | sc->sk_dev = self; |
| 1201 | /* |
| 1202 | * Handle power management nonsense. |
| 1203 | */ |
| 1204 | command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; |
| 1205 | |
| 1206 | if (command == 0x01) { |
| 1207 | command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); |
| 1208 | if (command & SK_PSTATE_MASK) { |
| 1209 | u_int32_t iobase, membase, irq; |
| 1210 | |
| 1211 | /* Save important PCI config data. */ |
| 1212 | iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); |
| 1213 | membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); |
| 1214 | irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); |
| 1215 | |
| 1216 | /* Reset the power state. */ |
| 1217 | aprint_normal_dev(sc->sk_dev, "chip is in D%d power " |
| 1218 | "mode -- setting to D0\n" , |
| 1219 | command & SK_PSTATE_MASK); |
| 1220 | command &= 0xFFFFFFFC; |
| 1221 | pci_conf_write(pc, pa->pa_tag, |
| 1222 | SK_PCI_PWRMGMTCTRL, command); |
| 1223 | |
| 1224 | /* Restore PCI config data. */ |
| 1225 | pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); |
| 1226 | pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); |
| 1227 | pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | /* |
| 1232 | * Map control/status registers. |
| 1233 | */ |
| 1234 | |
| 1235 | memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); |
| 1236 | switch (memtype) { |
| 1237 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: |
| 1238 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: |
| 1239 | if (pci_mapreg_map(pa, SK_PCI_LOMEM, |
| 1240 | memtype, 0, &sc->sk_btag, &sc->sk_bhandle, |
| 1241 | NULL, &size) == 0) { |
| 1242 | break; |
| 1243 | } |
| 1244 | default: |
| 1245 | aprint_error(": can't map mem space\n" ); |
| 1246 | return; |
| 1247 | } |
| 1248 | |
| 1249 | sc->sc_dmatag = pa->pa_dmat; |
| 1250 | |
| 1251 | command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
| 1252 | command |= PCI_COMMAND_MASTER_ENABLE; |
| 1253 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); |
| 1254 | |
| 1255 | sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); |
| 1256 | sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); |
| 1257 | |
| 1258 | /* bail out here if chip is not recognized */ |
| 1259 | if (!(SK_IS_YUKON2(sc))) { |
| 1260 | aprint_error(": unknown chip type: %d\n" , sc->sk_type); |
| 1261 | goto fail_1; |
| 1262 | } |
| 1263 | DPRINTFN(2, ("mskc_attach: allocate interrupt\n" )); |
| 1264 | |
| 1265 | /* Allocate interrupt */ |
| 1266 | if (pci_intr_map(pa, &ih)) { |
| 1267 | aprint_error(": couldn't map interrupt\n" ); |
| 1268 | goto fail_1; |
| 1269 | } |
| 1270 | |
| 1271 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
| 1272 | sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); |
| 1273 | if (sc->sk_intrhand == NULL) { |
| 1274 | aprint_error(": couldn't establish interrupt" ); |
| 1275 | if (intrstr != NULL) |
| 1276 | aprint_error(" at %s" , intrstr); |
| 1277 | aprint_error("\n" ); |
| 1278 | goto fail_1; |
| 1279 | } |
| 1280 | |
| 1281 | if (bus_dmamem_alloc(sc->sc_dmatag, |
| 1282 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), |
| 1283 | PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { |
| 1284 | aprint_error(": can't alloc status buffers\n" ); |
| 1285 | goto fail_2; |
| 1286 | } |
| 1287 | |
| 1288 | if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, |
| 1289 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), |
| 1290 | &kva, BUS_DMA_NOWAIT)) { |
| 1291 | aprint_error(": can't map dma buffers (%zu bytes)\n" , |
| 1292 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); |
| 1293 | goto fail_3; |
| 1294 | } |
| 1295 | if (bus_dmamap_create(sc->sc_dmatag, |
| 1296 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, |
| 1297 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, |
| 1298 | BUS_DMA_NOWAIT, &sc->sk_status_map)) { |
| 1299 | aprint_error(": can't create dma map\n" ); |
| 1300 | goto fail_4; |
| 1301 | } |
| 1302 | if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, |
| 1303 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), |
| 1304 | NULL, BUS_DMA_NOWAIT)) { |
| 1305 | aprint_error(": can't load dma map\n" ); |
| 1306 | goto fail_5; |
| 1307 | } |
| 1308 | sc->sk_status_ring = (struct msk_status_desc *)kva; |
| 1309 | |
| 1310 | |
| 1311 | sc->sk_int_mod = SK_IM_DEFAULT; |
| 1312 | sc->sk_int_mod_pending = 0; |
| 1313 | |
| 1314 | /* Reset the adapter. */ |
| 1315 | msk_reset(sc); |
| 1316 | |
| 1317 | skrs = sk_win_read_1(sc, SK_EPROM0); |
| 1318 | if (skrs == 0x00) |
| 1319 | sc->sk_ramsize = 0x20000; |
| 1320 | else |
| 1321 | sc->sk_ramsize = skrs * (1<<12); |
| 1322 | sc->sk_rboff = SK_RBOFF_0; |
| 1323 | |
| 1324 | DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n" , |
| 1325 | sc->sk_ramsize, sc->sk_ramsize / 1024, |
| 1326 | sc->sk_rboff)); |
| 1327 | |
| 1328 | switch (sc->sk_type) { |
| 1329 | case SK_YUKON_XL: |
| 1330 | sc->sk_name = "Yukon-2 XL" ; |
| 1331 | break; |
| 1332 | case SK_YUKON_EC_U: |
| 1333 | sc->sk_name = "Yukon-2 EC Ultra" ; |
| 1334 | break; |
| 1335 | case SK_YUKON_EC: |
| 1336 | sc->sk_name = "Yukon-2 EC" ; |
| 1337 | break; |
| 1338 | case SK_YUKON_FE: |
| 1339 | sc->sk_name = "Yukon-2 FE" ; |
| 1340 | break; |
| 1341 | default: |
| 1342 | sc->sk_name = "Yukon (Unknown)" ; |
| 1343 | } |
| 1344 | |
| 1345 | if (sc->sk_type == SK_YUKON_XL) { |
| 1346 | switch (sc->sk_rev) { |
| 1347 | case SK_YUKON_XL_REV_A0: |
| 1348 | sc->sk_workaround = 0; |
| 1349 | revstr = "A0" ; |
| 1350 | break; |
| 1351 | case SK_YUKON_XL_REV_A1: |
| 1352 | sc->sk_workaround = SK_WA_4109; |
| 1353 | revstr = "A1" ; |
| 1354 | break; |
| 1355 | case SK_YUKON_XL_REV_A2: |
| 1356 | sc->sk_workaround = SK_WA_4109; |
| 1357 | revstr = "A2" ; |
| 1358 | break; |
| 1359 | case SK_YUKON_XL_REV_A3: |
| 1360 | sc->sk_workaround = SK_WA_4109; |
| 1361 | revstr = "A3" ; |
| 1362 | break; |
| 1363 | default: |
| 1364 | sc->sk_workaround = 0; |
| 1365 | break; |
| 1366 | } |
| 1367 | } |
| 1368 | |
| 1369 | if (sc->sk_type == SK_YUKON_EC) { |
| 1370 | switch (sc->sk_rev) { |
| 1371 | case SK_YUKON_EC_REV_A1: |
| 1372 | sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; |
| 1373 | revstr = "A1" ; |
| 1374 | break; |
| 1375 | case SK_YUKON_EC_REV_A2: |
| 1376 | sc->sk_workaround = SK_WA_4109; |
| 1377 | revstr = "A2" ; |
| 1378 | break; |
| 1379 | case SK_YUKON_EC_REV_A3: |
| 1380 | sc->sk_workaround = SK_WA_4109; |
| 1381 | revstr = "A3" ; |
| 1382 | break; |
| 1383 | default: |
| 1384 | sc->sk_workaround = 0; |
| 1385 | break; |
| 1386 | } |
| 1387 | } |
| 1388 | |
| 1389 | if (sc->sk_type == SK_YUKON_FE) { |
| 1390 | sc->sk_workaround = SK_WA_4109; |
| 1391 | switch (sc->sk_rev) { |
| 1392 | case SK_YUKON_FE_REV_A1: |
| 1393 | revstr = "A1" ; |
| 1394 | break; |
| 1395 | case SK_YUKON_FE_REV_A2: |
| 1396 | revstr = "A2" ; |
| 1397 | break; |
| 1398 | default: |
| 1399 | sc->sk_workaround = 0; |
| 1400 | break; |
| 1401 | } |
| 1402 | } |
| 1403 | |
| 1404 | if (sc->sk_type == SK_YUKON_EC_U) { |
| 1405 | sc->sk_workaround = SK_WA_4109; |
| 1406 | switch (sc->sk_rev) { |
| 1407 | case SK_YUKON_EC_U_REV_A0: |
| 1408 | revstr = "A0" ; |
| 1409 | break; |
| 1410 | case SK_YUKON_EC_U_REV_A1: |
| 1411 | revstr = "A1" ; |
| 1412 | break; |
| 1413 | case SK_YUKON_EC_U_REV_B0: |
| 1414 | revstr = "B0" ; |
| 1415 | break; |
| 1416 | default: |
| 1417 | sc->sk_workaround = 0; |
| 1418 | break; |
| 1419 | } |
| 1420 | } |
| 1421 | |
| 1422 | /* Announce the product name. */ |
| 1423 | aprint_normal(", %s" , sc->sk_name); |
| 1424 | if (revstr != NULL) |
| 1425 | aprint_normal(" rev. %s" , revstr); |
| 1426 | aprint_normal(" (0x%x): %s\n" , sc->sk_rev, intrstr); |
| 1427 | |
| 1428 | sc->sk_macs = 1; |
| 1429 | |
| 1430 | hw = sk_win_read_1(sc, SK_Y2_HWRES); |
| 1431 | if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { |
| 1432 | if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & |
| 1433 | SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) |
| 1434 | sc->sk_macs++; |
| 1435 | } |
| 1436 | |
| 1437 | skca.skc_port = SK_PORT_A; |
| 1438 | skca.skc_type = sc->sk_type; |
| 1439 | skca.skc_rev = sc->sk_rev; |
| 1440 | (void)config_found(sc->sk_dev, &skca, mskcprint); |
| 1441 | |
| 1442 | if (sc->sk_macs > 1) { |
| 1443 | skca.skc_port = SK_PORT_B; |
| 1444 | skca.skc_type = sc->sk_type; |
| 1445 | skca.skc_rev = sc->sk_rev; |
| 1446 | (void)config_found(sc->sk_dev, &skca, mskcprint); |
| 1447 | } |
| 1448 | |
| 1449 | /* Turn on the 'driver is loaded' LED. */ |
| 1450 | CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); |
| 1451 | |
| 1452 | /* skc sysctl setup */ |
| 1453 | |
| 1454 | if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, |
| 1455 | 0, CTLTYPE_NODE, device_xname(sc->sk_dev), |
| 1456 | SYSCTL_DESCR("mskc per-controller controls" ), |
| 1457 | NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, |
| 1458 | CTL_EOL)) != 0) { |
| 1459 | aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n" ); |
| 1460 | goto fail_6; |
| 1461 | } |
| 1462 | |
| 1463 | sk_nodenum = node->sysctl_num; |
| 1464 | |
| 1465 | /* interrupt moderation time in usecs */ |
| 1466 | if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, |
| 1467 | CTLFLAG_READWRITE, |
| 1468 | CTLTYPE_INT, "int_mod" , |
| 1469 | SYSCTL_DESCR("msk interrupt moderation timer" ), |
| 1470 | msk_sysctl_handler, 0, (void *)sc, |
| 1471 | 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, |
| 1472 | CTL_EOL)) != 0) { |
| 1473 | aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n" ); |
| 1474 | goto fail_6; |
| 1475 | } |
| 1476 | |
| 1477 | if (!pmf_device_register(self, mskc_suspend, mskc_resume)) |
| 1478 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 1479 | |
| 1480 | return; |
| 1481 | |
| 1482 | fail_6: |
| 1483 | bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); |
| 1484 | fail_5: |
| 1485 | bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); |
| 1486 | fail_4: |
| 1487 | bus_dmamem_unmap(sc->sc_dmatag, kva, |
| 1488 | MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); |
| 1489 | fail_3: |
| 1490 | bus_dmamem_free(sc->sc_dmatag, &seg, rseg); |
| 1491 | fail_2: |
| 1492 | pci_intr_disestablish(pc, sc->sk_intrhand); |
| 1493 | fail_1: |
| 1494 | bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); |
| 1495 | } |
| 1496 | |
| 1497 | int |
| 1498 | msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) |
| 1499 | { |
| 1500 | struct sk_softc *sc = sc_if->sk_softc; |
| 1501 | struct msk_tx_desc *f = NULL; |
| 1502 | u_int32_t frag, cur; |
| 1503 | int i; |
| 1504 | struct sk_txmap_entry *entry; |
| 1505 | bus_dmamap_t txmap; |
| 1506 | |
| 1507 | DPRINTFN(2, ("msk_encap\n" )); |
| 1508 | |
| 1509 | entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); |
| 1510 | if (entry == NULL) { |
| 1511 | DPRINTFN(2, ("msk_encap: no txmap available\n" )); |
| 1512 | return (ENOBUFS); |
| 1513 | } |
| 1514 | txmap = entry->dmamap; |
| 1515 | |
| 1516 | cur = frag = *txidx; |
| 1517 | |
| 1518 | #ifdef MSK_DEBUG |
| 1519 | if (mskdebug >= 2) |
| 1520 | msk_dump_mbuf(m_head); |
| 1521 | #endif |
| 1522 | |
| 1523 | /* |
| 1524 | * Start packing the mbufs in this chain into |
| 1525 | * the fragment pointers. Stop when we run out |
| 1526 | * of fragments or hit the end of the mbuf chain. |
| 1527 | */ |
| 1528 | if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, |
| 1529 | BUS_DMA_NOWAIT)) { |
| 1530 | DPRINTFN(2, ("msk_encap: dmamap failed\n" )); |
| 1531 | return (ENOBUFS); |
| 1532 | } |
| 1533 | |
| 1534 | if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { |
| 1535 | DPRINTFN(2, ("msk_encap: too few descriptors free\n" )); |
| 1536 | bus_dmamap_unload(sc->sc_dmatag, txmap); |
| 1537 | return (ENOBUFS); |
| 1538 | } |
| 1539 | |
| 1540 | DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n" , txmap->dm_nsegs)); |
| 1541 | |
| 1542 | /* Sync the DMA map. */ |
| 1543 | bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, |
| 1544 | BUS_DMASYNC_PREWRITE); |
| 1545 | |
| 1546 | for (i = 0; i < txmap->dm_nsegs; i++) { |
| 1547 | f = &sc_if->sk_rdata->sk_tx_ring[frag]; |
| 1548 | f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); |
| 1549 | f->sk_len = htole16(txmap->dm_segs[i].ds_len); |
| 1550 | f->sk_ctl = 0; |
| 1551 | if (i == 0) |
| 1552 | f->sk_opcode = SK_Y2_TXOPC_PACKET; |
| 1553 | else |
| 1554 | f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; |
| 1555 | cur = frag; |
| 1556 | SK_INC(frag, MSK_TX_RING_CNT); |
| 1557 | } |
| 1558 | |
| 1559 | sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; |
| 1560 | SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); |
| 1561 | |
| 1562 | sc_if->sk_cdata.sk_tx_map[cur] = entry; |
| 1563 | sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; |
| 1564 | |
| 1565 | /* Sync descriptors before handing to chip */ |
| 1566 | MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, |
| 1567 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 1568 | |
| 1569 | sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; |
| 1570 | |
| 1571 | /* Sync first descriptor to hand it off */ |
| 1572 | MSK_CDTXSYNC(sc_if, *txidx, 1, |
| 1573 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 1574 | |
| 1575 | sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; |
| 1576 | |
| 1577 | #ifdef MSK_DEBUG |
| 1578 | if (mskdebug >= 2) { |
| 1579 | struct msk_tx_desc *le; |
| 1580 | u_int32_t idx; |
| 1581 | for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { |
| 1582 | le = &sc_if->sk_rdata->sk_tx_ring[idx]; |
| 1583 | msk_dump_txdesc(le, idx); |
| 1584 | } |
| 1585 | } |
| 1586 | #endif |
| 1587 | |
| 1588 | *txidx = frag; |
| 1589 | |
| 1590 | DPRINTFN(2, ("msk_encap: completed successfully\n" )); |
| 1591 | |
| 1592 | return (0); |
| 1593 | } |
| 1594 | |
| 1595 | void |
| 1596 | msk_start(struct ifnet *ifp) |
| 1597 | { |
| 1598 | struct sk_if_softc *sc_if = ifp->if_softc; |
| 1599 | struct mbuf *m_head = NULL; |
| 1600 | u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; |
| 1601 | int pkts = 0; |
| 1602 | |
| 1603 | DPRINTFN(2, ("msk_start\n" )); |
| 1604 | |
| 1605 | while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { |
| 1606 | IFQ_POLL(&ifp->if_snd, m_head); |
| 1607 | if (m_head == NULL) |
| 1608 | break; |
| 1609 | |
| 1610 | /* |
| 1611 | * Pack the data into the transmit ring. If we |
| 1612 | * don't have room, set the OACTIVE flag and wait |
| 1613 | * for the NIC to drain the ring. |
| 1614 | */ |
| 1615 | if (msk_encap(sc_if, m_head, &idx)) { |
| 1616 | ifp->if_flags |= IFF_OACTIVE; |
| 1617 | break; |
| 1618 | } |
| 1619 | |
| 1620 | /* now we are committed to transmit the packet */ |
| 1621 | IFQ_DEQUEUE(&ifp->if_snd, m_head); |
| 1622 | pkts++; |
| 1623 | |
| 1624 | /* |
| 1625 | * If there's a BPF listener, bounce a copy of this frame |
| 1626 | * to him. |
| 1627 | */ |
| 1628 | bpf_mtap(ifp, m_head); |
| 1629 | } |
| 1630 | if (pkts == 0) |
| 1631 | return; |
| 1632 | |
| 1633 | /* Transmit */ |
| 1634 | if (idx != sc_if->sk_cdata.sk_tx_prod) { |
| 1635 | sc_if->sk_cdata.sk_tx_prod = idx; |
| 1636 | SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); |
| 1637 | |
| 1638 | /* Set a timeout in case the chip goes out to lunch. */ |
| 1639 | ifp->if_timer = 5; |
| 1640 | } |
| 1641 | } |
| 1642 | |
| 1643 | void |
| 1644 | msk_watchdog(struct ifnet *ifp) |
| 1645 | { |
| 1646 | struct sk_if_softc *sc_if = ifp->if_softc; |
| 1647 | u_int32_t reg; |
| 1648 | int idx; |
| 1649 | |
| 1650 | /* |
| 1651 | * Reclaim first as there is a possibility of losing Tx completion |
| 1652 | * interrupts. |
| 1653 | */ |
| 1654 | if (sc_if->sk_port == SK_PORT_A) |
| 1655 | reg = SK_STAT_BMU_TXA1_RIDX; |
| 1656 | else |
| 1657 | reg = SK_STAT_BMU_TXA2_RIDX; |
| 1658 | |
| 1659 | idx = sk_win_read_2(sc_if->sk_softc, reg); |
| 1660 | if (sc_if->sk_cdata.sk_tx_cons != idx) { |
| 1661 | msk_txeof(sc_if, idx); |
| 1662 | if (sc_if->sk_cdata.sk_tx_cnt != 0) { |
| 1663 | aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n" ); |
| 1664 | |
| 1665 | ifp->if_oerrors++; |
| 1666 | |
| 1667 | /* XXX Resets both ports; we shouldn't do that. */ |
| 1668 | msk_reset(sc_if->sk_softc); |
| 1669 | msk_init(ifp); |
| 1670 | } |
| 1671 | } |
| 1672 | } |
| 1673 | |
| 1674 | static bool |
| 1675 | mskc_suspend(device_t dv, const pmf_qual_t *qual) |
| 1676 | { |
| 1677 | struct sk_softc *sc = device_private(dv); |
| 1678 | |
| 1679 | DPRINTFN(2, ("mskc_suspend\n" )); |
| 1680 | |
| 1681 | /* Turn off the 'driver is loaded' LED. */ |
| 1682 | CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); |
| 1683 | |
| 1684 | return true; |
| 1685 | } |
| 1686 | |
| 1687 | static bool |
| 1688 | mskc_resume(device_t dv, const pmf_qual_t *qual) |
| 1689 | { |
| 1690 | struct sk_softc *sc = device_private(dv); |
| 1691 | |
| 1692 | DPRINTFN(2, ("mskc_resume\n" )); |
| 1693 | |
| 1694 | msk_reset(sc); |
| 1695 | CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); |
| 1696 | |
| 1697 | return true; |
| 1698 | } |
| 1699 | |
| 1700 | static __inline int |
| 1701 | msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) |
| 1702 | { |
| 1703 | if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | |
| 1704 | YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | |
| 1705 | YU_RXSTAT_JABBER)) != 0 || |
| 1706 | (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || |
| 1707 | YU_RXSTAT_BYTES(stat) != len) |
| 1708 | return (0); |
| 1709 | |
| 1710 | return (1); |
| 1711 | } |
| 1712 | |
| 1713 | void |
| 1714 | msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) |
| 1715 | { |
| 1716 | struct sk_softc *sc = sc_if->sk_softc; |
| 1717 | struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; |
| 1718 | struct mbuf *m; |
| 1719 | struct sk_chain *cur_rx; |
| 1720 | int cur, total_len = len; |
| 1721 | bus_dmamap_t dmamap; |
| 1722 | |
| 1723 | DPRINTFN(2, ("msk_rxeof\n" )); |
| 1724 | |
| 1725 | cur = sc_if->sk_cdata.sk_rx_cons; |
| 1726 | SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); |
| 1727 | SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); |
| 1728 | |
| 1729 | /* Sync the descriptor */ |
| 1730 | MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 1731 | |
| 1732 | cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; |
| 1733 | if (cur_rx->sk_mbuf == NULL) |
| 1734 | return; |
| 1735 | |
| 1736 | dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; |
| 1737 | bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, |
| 1738 | dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 1739 | |
| 1740 | m = cur_rx->sk_mbuf; |
| 1741 | cur_rx->sk_mbuf = NULL; |
| 1742 | |
| 1743 | if (total_len < SK_MIN_FRAMELEN || |
| 1744 | total_len > ETHER_MAX_LEN_JUMBO || |
| 1745 | msk_rxvalid(sc, rxstat, total_len) == 0) { |
| 1746 | ifp->if_ierrors++; |
| 1747 | msk_newbuf(sc_if, cur, m, dmamap); |
| 1748 | return; |
| 1749 | } |
| 1750 | |
| 1751 | /* |
| 1752 | * Try to allocate a new jumbo buffer. If that fails, copy the |
| 1753 | * packet to mbufs and put the jumbo buffer back in the ring |
| 1754 | * so it can be re-used. If allocating mbufs fails, then we |
| 1755 | * have to drop the packet. |
| 1756 | */ |
| 1757 | if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { |
| 1758 | struct mbuf *m0; |
| 1759 | m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, |
| 1760 | total_len + ETHER_ALIGN, 0, ifp, NULL); |
| 1761 | msk_newbuf(sc_if, cur, m, dmamap); |
| 1762 | if (m0 == NULL) { |
| 1763 | ifp->if_ierrors++; |
| 1764 | return; |
| 1765 | } |
| 1766 | m_adj(m0, ETHER_ALIGN); |
| 1767 | m = m0; |
| 1768 | } else { |
| 1769 | m_set_rcvif(m, ifp); |
| 1770 | m->m_pkthdr.len = m->m_len = total_len; |
| 1771 | } |
| 1772 | |
| 1773 | ifp->if_ipackets++; |
| 1774 | |
| 1775 | bpf_mtap(ifp, m); |
| 1776 | |
| 1777 | /* pass it on. */ |
| 1778 | if_percpuq_enqueue(ifp->if_percpuq, m); |
| 1779 | } |
| 1780 | |
| 1781 | void |
| 1782 | msk_txeof(struct sk_if_softc *sc_if, int idx) |
| 1783 | { |
| 1784 | struct sk_softc *sc = sc_if->sk_softc; |
| 1785 | struct msk_tx_desc *cur_tx; |
| 1786 | struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; |
| 1787 | u_int32_t sk_ctl; |
| 1788 | struct sk_txmap_entry *entry; |
| 1789 | int cons, prog; |
| 1790 | |
| 1791 | DPRINTFN(2, ("msk_txeof\n" )); |
| 1792 | |
| 1793 | /* |
| 1794 | * Go through our tx ring and free mbufs for those |
| 1795 | * frames that have been sent. |
| 1796 | */ |
| 1797 | cons = sc_if->sk_cdata.sk_tx_cons; |
| 1798 | prog = 0; |
| 1799 | while (cons != idx) { |
| 1800 | if (sc_if->sk_cdata.sk_tx_cnt <= 0) |
| 1801 | break; |
| 1802 | prog++; |
| 1803 | cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; |
| 1804 | |
| 1805 | MSK_CDTXSYNC(sc_if, cons, 1, |
| 1806 | BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 1807 | sk_ctl = cur_tx->sk_ctl; |
| 1808 | MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); |
| 1809 | #ifdef MSK_DEBUG |
| 1810 | if (mskdebug >= 2) |
| 1811 | msk_dump_txdesc(cur_tx, cons); |
| 1812 | #endif |
| 1813 | if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) |
| 1814 | ifp->if_opackets++; |
| 1815 | if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { |
| 1816 | entry = sc_if->sk_cdata.sk_tx_map[cons]; |
| 1817 | |
| 1818 | bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, |
| 1819 | entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); |
| 1820 | |
| 1821 | bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); |
| 1822 | SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, |
| 1823 | link); |
| 1824 | sc_if->sk_cdata.sk_tx_map[cons] = NULL; |
| 1825 | m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); |
| 1826 | sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; |
| 1827 | } |
| 1828 | sc_if->sk_cdata.sk_tx_cnt--; |
| 1829 | SK_INC(cons, MSK_TX_RING_CNT); |
| 1830 | } |
| 1831 | ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; |
| 1832 | |
| 1833 | if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) |
| 1834 | ifp->if_flags &= ~IFF_OACTIVE; |
| 1835 | |
| 1836 | if (prog > 0) |
| 1837 | sc_if->sk_cdata.sk_tx_cons = cons; |
| 1838 | } |
| 1839 | |
| 1840 | void |
| 1841 | msk_tick(void *xsc_if) |
| 1842 | { |
| 1843 | struct sk_if_softc *sc_if = xsc_if; |
| 1844 | struct mii_data *mii = &sc_if->sk_mii; |
| 1845 | uint16_t gpsr; |
| 1846 | int s; |
| 1847 | |
| 1848 | s = splnet(); |
| 1849 | gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); |
| 1850 | if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { |
| 1851 | SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); |
| 1852 | mii_tick(mii); |
| 1853 | } |
| 1854 | splx(s); |
| 1855 | |
| 1856 | callout_schedule(&sc_if->sk_tick_ch, hz); |
| 1857 | } |
| 1858 | |
| 1859 | void |
| 1860 | msk_intr_yukon(struct sk_if_softc *sc_if) |
| 1861 | { |
| 1862 | u_int8_t status; |
| 1863 | |
| 1864 | status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); |
| 1865 | /* RX overrun */ |
| 1866 | if ((status & SK_GMAC_INT_RX_OVER) != 0) { |
| 1867 | SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, |
| 1868 | SK_RFCTL_RX_FIFO_OVER); |
| 1869 | } |
| 1870 | /* TX underrun */ |
| 1871 | if ((status & SK_GMAC_INT_TX_UNDER) != 0) { |
| 1872 | SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, |
| 1873 | SK_TFCTL_TX_FIFO_UNDER); |
| 1874 | } |
| 1875 | |
| 1876 | DPRINTFN(2, ("msk_intr_yukon status=%#x\n" , status)); |
| 1877 | } |
| 1878 | |
| 1879 | int |
| 1880 | msk_intr(void *xsc) |
| 1881 | { |
| 1882 | struct sk_softc *sc = xsc; |
| 1883 | struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; |
| 1884 | struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; |
| 1885 | struct ifnet *ifp0 = NULL, *ifp1 = NULL; |
| 1886 | int claimed = 0; |
| 1887 | u_int32_t status; |
| 1888 | uint32_t st_status; |
| 1889 | uint16_t st_len; |
| 1890 | uint8_t st_opcode, st_link; |
| 1891 | struct msk_status_desc *cur_st; |
| 1892 | |
| 1893 | status = CSR_READ_4(sc, SK_Y2_ISSR2); |
| 1894 | if (status == 0) { |
| 1895 | CSR_WRITE_4(sc, SK_Y2_ICR, 2); |
| 1896 | return (0); |
| 1897 | } |
| 1898 | |
| 1899 | status = CSR_READ_4(sc, SK_ISR); |
| 1900 | |
| 1901 | if (sc_if0 != NULL) |
| 1902 | ifp0 = &sc_if0->sk_ethercom.ec_if; |
| 1903 | if (sc_if1 != NULL) |
| 1904 | ifp1 = &sc_if1->sk_ethercom.ec_if; |
| 1905 | |
| 1906 | if (sc_if0 && (status & SK_Y2_IMR_MAC1) && |
| 1907 | (ifp0->if_flags & IFF_RUNNING)) { |
| 1908 | msk_intr_yukon(sc_if0); |
| 1909 | } |
| 1910 | |
| 1911 | if (sc_if1 && (status & SK_Y2_IMR_MAC2) && |
| 1912 | (ifp1->if_flags & IFF_RUNNING)) { |
| 1913 | msk_intr_yukon(sc_if1); |
| 1914 | } |
| 1915 | |
| 1916 | for (;;) { |
| 1917 | cur_st = &sc->sk_status_ring[sc->sk_status_idx]; |
| 1918 | MSK_CDSTSYNC(sc, sc->sk_status_idx, |
| 1919 | BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 1920 | st_opcode = cur_st->sk_opcode; |
| 1921 | if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { |
| 1922 | MSK_CDSTSYNC(sc, sc->sk_status_idx, |
| 1923 | BUS_DMASYNC_PREREAD); |
| 1924 | break; |
| 1925 | } |
| 1926 | st_status = le32toh(cur_st->sk_status); |
| 1927 | st_len = le16toh(cur_st->sk_len); |
| 1928 | st_link = cur_st->sk_link; |
| 1929 | st_opcode &= ~SK_Y2_STOPC_OWN; |
| 1930 | |
| 1931 | switch (st_opcode) { |
| 1932 | case SK_Y2_STOPC_RXSTAT: |
| 1933 | msk_rxeof(sc->sk_if[st_link], st_len, st_status); |
| 1934 | SK_IF_WRITE_2(sc->sk_if[st_link], 0, |
| 1935 | SK_RXQ1_Y2_PREF_PUTIDX, |
| 1936 | sc->sk_if[st_link]->sk_cdata.sk_rx_prod); |
| 1937 | break; |
| 1938 | case SK_Y2_STOPC_TXSTAT: |
| 1939 | if (sc_if0) |
| 1940 | msk_txeof(sc_if0, st_status |
| 1941 | & SK_Y2_ST_TXA1_MSKL); |
| 1942 | if (sc_if1) |
| 1943 | msk_txeof(sc_if1, |
| 1944 | ((st_status & SK_Y2_ST_TXA2_MSKL) |
| 1945 | >> SK_Y2_ST_TXA2_SHIFTL) |
| 1946 | | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); |
| 1947 | break; |
| 1948 | default: |
| 1949 | aprint_error("opcode=0x%x\n" , st_opcode); |
| 1950 | break; |
| 1951 | } |
| 1952 | SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); |
| 1953 | } |
| 1954 | |
| 1955 | #define MSK_STATUS_RING_OWN_CNT(sc) \ |
| 1956 | (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ |
| 1957 | (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) |
| 1958 | |
| 1959 | while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { |
| 1960 | cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; |
| 1961 | cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; |
| 1962 | MSK_CDSTSYNC(sc, sc->sk_status_own_idx, |
| 1963 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 1964 | |
| 1965 | SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); |
| 1966 | } |
| 1967 | |
| 1968 | if (status & SK_Y2_IMR_BMU) { |
| 1969 | CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); |
| 1970 | claimed = 1; |
| 1971 | } |
| 1972 | |
| 1973 | CSR_WRITE_4(sc, SK_Y2_ICR, 2); |
| 1974 | |
| 1975 | if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) |
| 1976 | msk_start(ifp0); |
| 1977 | if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) |
| 1978 | msk_start(ifp1); |
| 1979 | |
| 1980 | rnd_add_uint32(&sc->rnd_source, status); |
| 1981 | |
| 1982 | if (sc->sk_int_mod_pending) |
| 1983 | msk_update_int_mod(sc, 1); |
| 1984 | |
| 1985 | return claimed; |
| 1986 | } |
| 1987 | |
| 1988 | void |
| 1989 | msk_init_yukon(struct sk_if_softc *sc_if) |
| 1990 | { |
| 1991 | u_int32_t v; |
| 1992 | u_int16_t reg; |
| 1993 | struct sk_softc *sc; |
| 1994 | int i; |
| 1995 | |
| 1996 | sc = sc_if->sk_softc; |
| 1997 | |
| 1998 | DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n" , |
| 1999 | CSR_READ_4(sc_if->sk_softc, SK_CSR))); |
| 2000 | |
| 2001 | DPRINTFN(6, ("msk_init_yukon: 1\n" )); |
| 2002 | |
| 2003 | /* GMAC and GPHY Reset */ |
| 2004 | SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); |
| 2005 | SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); |
| 2006 | DELAY(1000); |
| 2007 | |
| 2008 | DPRINTFN(6, ("msk_init_yukon: 2\n" )); |
| 2009 | |
| 2010 | SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); |
| 2011 | SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | |
| 2012 | SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); |
| 2013 | |
| 2014 | DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n" , |
| 2015 | SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); |
| 2016 | |
| 2017 | DPRINTFN(6, ("msk_init_yukon: 3\n" )); |
| 2018 | |
| 2019 | /* unused read of the interrupt source register */ |
| 2020 | DPRINTFN(6, ("msk_init_yukon: 4\n" )); |
| 2021 | SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); |
| 2022 | |
| 2023 | DPRINTFN(6, ("msk_init_yukon: 4a\n" )); |
| 2024 | reg = SK_YU_READ_2(sc_if, YUKON_PAR); |
| 2025 | DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n" , reg)); |
| 2026 | |
| 2027 | /* MIB Counter Clear Mode set */ |
| 2028 | reg |= YU_PAR_MIB_CLR; |
| 2029 | DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n" , reg)); |
| 2030 | DPRINTFN(6, ("msk_init_yukon: 4b\n" )); |
| 2031 | SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); |
| 2032 | |
| 2033 | /* MIB Counter Clear Mode clear */ |
| 2034 | DPRINTFN(6, ("msk_init_yukon: 5\n" )); |
| 2035 | reg &= ~YU_PAR_MIB_CLR; |
| 2036 | SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); |
| 2037 | |
| 2038 | /* receive control reg */ |
| 2039 | DPRINTFN(6, ("msk_init_yukon: 7\n" )); |
| 2040 | SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); |
| 2041 | |
| 2042 | /* transmit control register */ |
| 2043 | SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); |
| 2044 | |
| 2045 | /* transmit flow control register */ |
| 2046 | SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); |
| 2047 | |
| 2048 | /* transmit parameter register */ |
| 2049 | DPRINTFN(6, ("msk_init_yukon: 8\n" )); |
| 2050 | SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | |
| 2051 | YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); |
| 2052 | |
| 2053 | /* serial mode register */ |
| 2054 | DPRINTFN(6, ("msk_init_yukon: 9\n" )); |
| 2055 | reg = YU_SMR_DATA_BLIND(0x1c) | |
| 2056 | YU_SMR_MFL_VLAN | |
| 2057 | YU_SMR_IPG_DATA(0x1e); |
| 2058 | |
| 2059 | if (sc->sk_type != SK_YUKON_FE) |
| 2060 | reg |= YU_SMR_MFL_JUMBO; |
| 2061 | |
| 2062 | SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); |
| 2063 | |
| 2064 | DPRINTFN(6, ("msk_init_yukon: 10\n" )); |
| 2065 | struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; |
| 2066 | /* msk_attach calls me before ether_ifattach so check null */ |
| 2067 | if (ifp != NULL && ifp->if_sadl != NULL) |
| 2068 | memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), |
| 2069 | sizeof(sc_if->sk_enaddr)); |
| 2070 | /* Setup Yukon's address */ |
| 2071 | for (i = 0; i < 3; i++) { |
| 2072 | /* Write Source Address 1 (unicast filter) */ |
| 2073 | SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, |
| 2074 | sc_if->sk_enaddr[i * 2] | |
| 2075 | sc_if->sk_enaddr[i * 2 + 1] << 8); |
| 2076 | } |
| 2077 | |
| 2078 | for (i = 0; i < 3; i++) { |
| 2079 | reg = sk_win_read_2(sc_if->sk_softc, |
| 2080 | SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); |
| 2081 | SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); |
| 2082 | } |
| 2083 | |
| 2084 | /* Set promiscuous mode */ |
| 2085 | msk_setpromisc(sc_if); |
| 2086 | |
| 2087 | /* Set multicast filter */ |
| 2088 | DPRINTFN(6, ("msk_init_yukon: 11\n" )); |
| 2089 | msk_setmulti(sc_if); |
| 2090 | |
| 2091 | /* enable interrupt mask for counter overflows */ |
| 2092 | DPRINTFN(6, ("msk_init_yukon: 12\n" )); |
| 2093 | SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); |
| 2094 | SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); |
| 2095 | SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); |
| 2096 | |
| 2097 | /* Configure RX MAC FIFO Flush Mask */ |
| 2098 | v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | |
| 2099 | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | |
| 2100 | YU_RXSTAT_JABBER; |
| 2101 | SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); |
| 2102 | |
| 2103 | /* Configure RX MAC FIFO */ |
| 2104 | SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); |
| 2105 | SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | |
| 2106 | SK_RFCTL_FIFO_FLUSH_ON); |
| 2107 | |
| 2108 | /* Increase flush threshould to 64 bytes */ |
| 2109 | SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, |
| 2110 | SK_RFCTL_FIFO_THRESHOLD + 1); |
| 2111 | |
| 2112 | /* Configure TX MAC FIFO */ |
| 2113 | SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); |
| 2114 | SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); |
| 2115 | |
| 2116 | #if 1 |
| 2117 | SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); |
| 2118 | #endif |
| 2119 | DPRINTFN(6, ("msk_init_yukon: end\n" )); |
| 2120 | } |
| 2121 | |
| 2122 | /* |
| 2123 | * Note that to properly initialize any part of the GEnesis chip, |
| 2124 | * you first have to take it out of reset mode. |
| 2125 | */ |
| 2126 | int |
| 2127 | msk_init(struct ifnet *ifp) |
| 2128 | { |
| 2129 | struct sk_if_softc *sc_if = ifp->if_softc; |
| 2130 | struct sk_softc *sc = sc_if->sk_softc; |
| 2131 | int rc = 0, s; |
| 2132 | uint32_t imr, imtimer_ticks; |
| 2133 | |
| 2134 | |
| 2135 | DPRINTFN(2, ("msk_init\n" )); |
| 2136 | |
| 2137 | s = splnet(); |
| 2138 | |
| 2139 | /* Cancel pending I/O and free all RX/TX buffers. */ |
| 2140 | msk_stop(ifp,0); |
| 2141 | |
| 2142 | /* Configure I2C registers */ |
| 2143 | |
| 2144 | /* Configure XMAC(s) */ |
| 2145 | msk_init_yukon(sc_if); |
| 2146 | if ((rc = ether_mediachange(ifp)) != 0) |
| 2147 | goto out; |
| 2148 | |
| 2149 | /* Configure transmit arbiter(s) */ |
| 2150 | SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); |
| 2151 | #if 0 |
| 2152 | SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); |
| 2153 | #endif |
| 2154 | |
| 2155 | /* Configure RAMbuffers */ |
| 2156 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); |
| 2157 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); |
| 2158 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); |
| 2159 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); |
| 2160 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); |
| 2161 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); |
| 2162 | |
| 2163 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); |
| 2164 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); |
| 2165 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); |
| 2166 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); |
| 2167 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); |
| 2168 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); |
| 2169 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); |
| 2170 | |
| 2171 | /* Configure BMUs */ |
| 2172 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); |
| 2173 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); |
| 2174 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); |
| 2175 | SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ |
| 2176 | |
| 2177 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); |
| 2178 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); |
| 2179 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); |
| 2180 | SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ |
| 2181 | |
| 2182 | /* Make sure the sync transmit queue is disabled. */ |
| 2183 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); |
| 2184 | |
| 2185 | /* Init descriptors */ |
| 2186 | if (msk_init_rx_ring(sc_if) == ENOBUFS) { |
| 2187 | aprint_error_dev(sc_if->sk_dev, "initialization failed: no " |
| 2188 | "memory for rx buffers\n" ); |
| 2189 | msk_stop(ifp,0); |
| 2190 | splx(s); |
| 2191 | return ENOBUFS; |
| 2192 | } |
| 2193 | |
| 2194 | if (msk_init_tx_ring(sc_if) == ENOBUFS) { |
| 2195 | aprint_error_dev(sc_if->sk_dev, "initialization failed: no " |
| 2196 | "memory for tx buffers\n" ); |
| 2197 | msk_stop(ifp,0); |
| 2198 | splx(s); |
| 2199 | return ENOBUFS; |
| 2200 | } |
| 2201 | |
| 2202 | /* Set interrupt moderation if changed via sysctl. */ |
| 2203 | switch (sc->sk_type) { |
| 2204 | case SK_YUKON_EC: |
| 2205 | case SK_YUKON_EC_U: |
| 2206 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; |
| 2207 | break; |
| 2208 | case SK_YUKON_FE: |
| 2209 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; |
| 2210 | break; |
| 2211 | case SK_YUKON_XL: |
| 2212 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; |
| 2213 | break; |
| 2214 | default: |
| 2215 | imtimer_ticks = SK_IMTIMER_TICKS_YUKON; |
| 2216 | } |
| 2217 | imr = sk_win_read_4(sc, SK_IMTIMERINIT); |
| 2218 | if (imr != SK_IM_USECS(sc->sk_int_mod)) { |
| 2219 | sk_win_write_4(sc, SK_IMTIMERINIT, |
| 2220 | SK_IM_USECS(sc->sk_int_mod)); |
| 2221 | aprint_verbose_dev(sc->sk_dev, |
| 2222 | "interrupt moderation is %d us\n" , sc->sk_int_mod); |
| 2223 | } |
| 2224 | |
| 2225 | /* Initialize prefetch engine. */ |
| 2226 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); |
| 2227 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); |
| 2228 | SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); |
| 2229 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, |
| 2230 | MSK_RX_RING_ADDR(sc_if, 0)); |
| 2231 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, |
| 2232 | (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); |
| 2233 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); |
| 2234 | SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); |
| 2235 | |
| 2236 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); |
| 2237 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); |
| 2238 | SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); |
| 2239 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, |
| 2240 | MSK_TX_RING_ADDR(sc_if, 0)); |
| 2241 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, |
| 2242 | (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); |
| 2243 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); |
| 2244 | SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); |
| 2245 | |
| 2246 | SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, |
| 2247 | sc_if->sk_cdata.sk_rx_prod); |
| 2248 | |
| 2249 | /* Configure interrupt handling */ |
| 2250 | if (sc_if->sk_port == SK_PORT_A) |
| 2251 | sc->sk_intrmask |= SK_Y2_INTRS1; |
| 2252 | else |
| 2253 | sc->sk_intrmask |= SK_Y2_INTRS2; |
| 2254 | sc->sk_intrmask |= SK_Y2_IMR_BMU; |
| 2255 | CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); |
| 2256 | |
| 2257 | ifp->if_flags |= IFF_RUNNING; |
| 2258 | ifp->if_flags &= ~IFF_OACTIVE; |
| 2259 | |
| 2260 | callout_schedule(&sc_if->sk_tick_ch, hz); |
| 2261 | |
| 2262 | out: |
| 2263 | splx(s); |
| 2264 | return rc; |
| 2265 | } |
| 2266 | |
| 2267 | void |
| 2268 | msk_stop(struct ifnet *ifp, int disable) |
| 2269 | { |
| 2270 | struct sk_if_softc *sc_if = ifp->if_softc; |
| 2271 | struct sk_softc *sc = sc_if->sk_softc; |
| 2272 | struct sk_txmap_entry *dma; |
| 2273 | int i; |
| 2274 | |
| 2275 | DPRINTFN(2, ("msk_stop\n" )); |
| 2276 | |
| 2277 | callout_stop(&sc_if->sk_tick_ch); |
| 2278 | |
| 2279 | ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); |
| 2280 | |
| 2281 | /* Stop transfer of Tx descriptors */ |
| 2282 | |
| 2283 | /* Stop transfer of Rx descriptors */ |
| 2284 | |
| 2285 | /* Turn off various components of this interface. */ |
| 2286 | SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); |
| 2287 | SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); |
| 2288 | SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); |
| 2289 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); |
| 2290 | SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); |
| 2291 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); |
| 2292 | SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); |
| 2293 | SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); |
| 2294 | SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); |
| 2295 | SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); |
| 2296 | SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); |
| 2297 | SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); |
| 2298 | |
| 2299 | SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); |
| 2300 | SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); |
| 2301 | |
| 2302 | /* Disable interrupts */ |
| 2303 | if (sc_if->sk_port == SK_PORT_A) |
| 2304 | sc->sk_intrmask &= ~SK_Y2_INTRS1; |
| 2305 | else |
| 2306 | sc->sk_intrmask &= ~SK_Y2_INTRS2; |
| 2307 | CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); |
| 2308 | |
| 2309 | SK_XM_READ_2(sc_if, XM_ISR); |
| 2310 | SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); |
| 2311 | |
| 2312 | /* Free RX and TX mbufs still in the queues. */ |
| 2313 | for (i = 0; i < MSK_RX_RING_CNT; i++) { |
| 2314 | if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { |
| 2315 | m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); |
| 2316 | sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; |
| 2317 | } |
| 2318 | } |
| 2319 | |
| 2320 | for (i = 0; i < MSK_TX_RING_CNT; i++) { |
| 2321 | if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { |
| 2322 | m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); |
| 2323 | sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; |
| 2324 | #if 1 |
| 2325 | SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, |
| 2326 | sc_if->sk_cdata.sk_tx_map[i], link); |
| 2327 | sc_if->sk_cdata.sk_tx_map[i] = 0; |
| 2328 | #endif |
| 2329 | } |
| 2330 | } |
| 2331 | |
| 2332 | #if 1 |
| 2333 | while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { |
| 2334 | SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); |
| 2335 | bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); |
| 2336 | free(dma, M_DEVBUF); |
| 2337 | } |
| 2338 | #endif |
| 2339 | } |
| 2340 | |
| 2341 | CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, |
| 2342 | NULL, NULL); |
| 2343 | |
| 2344 | CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, |
| 2345 | NULL, NULL); |
| 2346 | |
| 2347 | #ifdef MSK_DEBUG |
| 2348 | void |
| 2349 | msk_dump_txdesc(struct msk_tx_desc *le, int idx) |
| 2350 | { |
| 2351 | #define DESC_PRINT(X) \ |
| 2352 | if (X) \ |
| 2353 | printf("txdesc[%d]." #X "=%#x\n", \ |
| 2354 | idx, X); |
| 2355 | |
| 2356 | DESC_PRINT(letoh32(le->sk_addr)); |
| 2357 | DESC_PRINT(letoh16(le->sk_len)); |
| 2358 | DESC_PRINT(le->sk_ctl); |
| 2359 | DESC_PRINT(le->sk_opcode); |
| 2360 | #undef DESC_PRINT |
| 2361 | } |
| 2362 | |
| 2363 | void |
| 2364 | msk_dump_bytes(const char *data, int len) |
| 2365 | { |
| 2366 | int c, i, j; |
| 2367 | |
| 2368 | for (i = 0; i < len; i += 16) { |
| 2369 | printf("%08x " , i); |
| 2370 | c = len - i; |
| 2371 | if (c > 16) c = 16; |
| 2372 | |
| 2373 | for (j = 0; j < c; j++) { |
| 2374 | printf("%02x " , data[i + j] & 0xff); |
| 2375 | if ((j & 0xf) == 7 && j > 0) |
| 2376 | printf(" " ); |
| 2377 | } |
| 2378 | |
| 2379 | for (; j < 16; j++) |
| 2380 | printf(" " ); |
| 2381 | printf(" " ); |
| 2382 | |
| 2383 | for (j = 0; j < c; j++) { |
| 2384 | int ch = data[i + j] & 0xff; |
| 2385 | printf("%c" , ' ' <= ch && ch <= '~' ? ch : ' '); |
| 2386 | } |
| 2387 | |
| 2388 | printf("\n" ); |
| 2389 | |
| 2390 | if (c < 16) |
| 2391 | break; |
| 2392 | } |
| 2393 | } |
| 2394 | |
| 2395 | void |
| 2396 | msk_dump_mbuf(struct mbuf *m) |
| 2397 | { |
| 2398 | int count = m->m_pkthdr.len; |
| 2399 | |
| 2400 | printf("m=%p, m->m_pkthdr.len=%d\n" , m, m->m_pkthdr.len); |
| 2401 | |
| 2402 | while (count > 0 && m) { |
| 2403 | printf("m=%p, m->m_data=%p, m->m_len=%d\n" , |
| 2404 | m, m->m_data, m->m_len); |
| 2405 | msk_dump_bytes(mtod(m, char *), m->m_len); |
| 2406 | |
| 2407 | count -= m->m_len; |
| 2408 | m = m->m_next; |
| 2409 | } |
| 2410 | } |
| 2411 | #endif |
| 2412 | |
| 2413 | static int |
| 2414 | msk_sysctl_handler(SYSCTLFN_ARGS) |
| 2415 | { |
| 2416 | int error, t; |
| 2417 | struct sysctlnode node; |
| 2418 | struct sk_softc *sc; |
| 2419 | |
| 2420 | node = *rnode; |
| 2421 | sc = node.sysctl_data; |
| 2422 | t = sc->sk_int_mod; |
| 2423 | node.sysctl_data = &t; |
| 2424 | error = sysctl_lookup(SYSCTLFN_CALL(&node)); |
| 2425 | if (error || newp == NULL) |
| 2426 | return error; |
| 2427 | |
| 2428 | if (t < SK_IM_MIN || t > SK_IM_MAX) |
| 2429 | return EINVAL; |
| 2430 | |
| 2431 | /* update the softc with sysctl-changed value, and mark |
| 2432 | for hardware update */ |
| 2433 | sc->sk_int_mod = t; |
| 2434 | sc->sk_int_mod_pending = 1; |
| 2435 | return 0; |
| 2436 | } |
| 2437 | |
| 2438 | /* |
| 2439 | * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be |
| 2440 | * set up in skc_attach() |
| 2441 | */ |
| 2442 | SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup" ) |
| 2443 | { |
| 2444 | int rc; |
| 2445 | const struct sysctlnode *node; |
| 2446 | |
| 2447 | if ((rc = sysctl_createv(clog, 0, NULL, &node, |
| 2448 | 0, CTLTYPE_NODE, "msk" , |
| 2449 | SYSCTL_DESCR("msk interface controls" ), |
| 2450 | NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { |
| 2451 | goto err; |
| 2452 | } |
| 2453 | |
| 2454 | msk_root_num = node->sysctl_num; |
| 2455 | return; |
| 2456 | |
| 2457 | err: |
| 2458 | aprint_error("%s: syctl_createv failed (rc = %d)\n" , __func__, rc); |
| 2459 | } |
| 2460 | |