| 1 | /* $NetBSD: nouveau_subdev_gpio_nve0.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2012 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_gpio_nve0.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $" ); |
| 29 | |
| 30 | #include "priv.h" |
| 31 | |
| 32 | struct nve0_gpio_priv { |
| 33 | struct nouveau_gpio base; |
| 34 | }; |
| 35 | |
| 36 | void |
| 37 | nve0_gpio_intr(struct nouveau_subdev *subdev) |
| 38 | { |
| 39 | struct nve0_gpio_priv *priv = (void *)subdev; |
| 40 | u32 intr0 = nv_rd32(priv, 0xdc00) & nv_rd32(priv, 0xdc08); |
| 41 | u32 intr1 = nv_rd32(priv, 0xdc80) & nv_rd32(priv, 0xdc88); |
| 42 | u32 hi = (intr0 & 0x0000ffff) | (intr1 << 16); |
| 43 | u32 lo = (intr0 >> 16) | (intr1 & 0xffff0000); |
| 44 | int i; |
| 45 | |
| 46 | for (i = 0; (hi | lo) && i < 32; i++) { |
| 47 | if ((hi | lo) & (1 << i)) |
| 48 | nouveau_event_trigger(priv->base.events, i); |
| 49 | } |
| 50 | |
| 51 | nv_wr32(priv, 0xdc00, intr0); |
| 52 | nv_wr32(priv, 0xdc88, intr1); |
| 53 | } |
| 54 | |
| 55 | void |
| 56 | nve0_gpio_intr_enable(struct nouveau_event *event, int line) |
| 57 | { |
| 58 | const u32 addr = line < 16 ? 0xdc00 : 0xdc80; |
| 59 | const u32 mask = 0x00010001 << (line & 0xf); |
| 60 | nv_wr32(event->priv, addr + 0x08, mask); |
| 61 | nv_mask(event->priv, addr + 0x00, mask, mask); |
| 62 | } |
| 63 | |
| 64 | void |
| 65 | nve0_gpio_intr_disable(struct nouveau_event *event, int line) |
| 66 | { |
| 67 | const u32 addr = line < 16 ? 0xdc00 : 0xdc80; |
| 68 | const u32 mask = 0x00010001 << (line & 0xf); |
| 69 | nv_wr32(event->priv, addr + 0x08, mask); |
| 70 | nv_mask(event->priv, addr + 0x00, mask, 0x00000000); |
| 71 | } |
| 72 | |
| 73 | int |
| 74 | nve0_gpio_fini(struct nouveau_object *object, bool suspend) |
| 75 | { |
| 76 | struct nve0_gpio_priv *priv = (void *)object; |
| 77 | nv_wr32(priv, 0xdc08, 0x00000000); |
| 78 | nv_wr32(priv, 0xdc88, 0x00000000); |
| 79 | return nouveau_gpio_fini(&priv->base, suspend); |
| 80 | } |
| 81 | |
| 82 | int |
| 83 | nve0_gpio_init(struct nouveau_object *object) |
| 84 | { |
| 85 | struct nve0_gpio_priv *priv = (void *)object; |
| 86 | int ret; |
| 87 | |
| 88 | ret = nouveau_gpio_init(&priv->base); |
| 89 | if (ret) |
| 90 | return ret; |
| 91 | |
| 92 | nv_wr32(priv, 0xdc00, 0xffffffff); |
| 93 | nv_wr32(priv, 0xdc80, 0xffffffff); |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | void |
| 98 | nve0_gpio_dtor(struct nouveau_object *object) |
| 99 | { |
| 100 | struct nve0_gpio_priv *priv = (void *)object; |
| 101 | nouveau_gpio_destroy(&priv->base); |
| 102 | } |
| 103 | |
| 104 | static int |
| 105 | nve0_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 106 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 107 | struct nouveau_object **pobject) |
| 108 | { |
| 109 | struct nve0_gpio_priv *priv; |
| 110 | int ret; |
| 111 | |
| 112 | ret = nouveau_gpio_create(parent, engine, oclass, 32, &priv); |
| 113 | *pobject = nv_object(priv); |
| 114 | if (ret) |
| 115 | return ret; |
| 116 | |
| 117 | priv->base.reset = nvd0_gpio_reset; |
| 118 | priv->base.drive = nvd0_gpio_drive; |
| 119 | priv->base.sense = nvd0_gpio_sense; |
| 120 | priv->base.events->priv = priv; |
| 121 | priv->base.events->enable = nve0_gpio_intr_enable; |
| 122 | priv->base.events->disable = nve0_gpio_intr_disable; |
| 123 | nv_subdev(priv)->intr = nve0_gpio_intr; |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | struct nouveau_oclass |
| 128 | nve0_gpio_oclass = { |
| 129 | .handle = NV_SUBDEV(GPIO, 0xe0), |
| 130 | .ofuncs = &(struct nouveau_ofuncs) { |
| 131 | .ctor = nve0_gpio_ctor, |
| 132 | .dtor = nv50_gpio_dtor, |
| 133 | .init = nve0_gpio_init, |
| 134 | .fini = nve0_gpio_fini, |
| 135 | }, |
| 136 | }; |
| 137 | |