| 1 | /* |
| 2 | * Product specific probe and attach routines for: |
| 3 | * 3940, 2940, aic7895, aic7890, aic7880, |
| 4 | * aic7870, aic7860 and aic7850 SCSI controllers |
| 5 | * |
| 6 | * Copyright (c) 1994-2001 Justin T. Gibbs. |
| 7 | * Copyright (c) 2000-2001 Adaptec Inc. |
| 8 | * All rights reserved. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions, and the following disclaimer, |
| 15 | * without modification. |
| 16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 17 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 18 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 19 | * including a substantially similar Disclaimer requirement for further |
| 20 | * binary redistribution. |
| 21 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 22 | * of any contributors may be used to endorse or promote products derived |
| 23 | * from this software without specific prior written permission. |
| 24 | * |
| 25 | * Alternatively, this software may be distributed under the terms of the |
| 26 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 27 | * Software Foundation. |
| 28 | * |
| 29 | * NO WARRANTY |
| 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 31 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 32 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 33 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 34 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 36 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 37 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 38 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 39 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 40 | * POSSIBILITY OF SUCH DAMAGES. |
| 41 | * |
| 42 | * $Id: ahc_pci.c,v 1.71 2016/07/14 04:00:46 msaitoh Exp $ |
| 43 | * |
| 44 | * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ |
| 45 | * |
| 46 | * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ |
| 47 | */ |
| 48 | /* |
| 49 | * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 |
| 50 | */ |
| 51 | |
| 52 | #include <sys/cdefs.h> |
| 53 | __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.71 2016/07/14 04:00:46 msaitoh Exp $" ); |
| 54 | |
| 55 | #include <sys/param.h> |
| 56 | #include <sys/systm.h> |
| 57 | #include <sys/malloc.h> |
| 58 | #include <sys/kernel.h> |
| 59 | #include <sys/queue.h> |
| 60 | #include <sys/device.h> |
| 61 | #include <sys/reboot.h> |
| 62 | |
| 63 | #include <sys/bus.h> |
| 64 | #include <sys/intr.h> |
| 65 | |
| 66 | #include <dev/pci/pcireg.h> |
| 67 | #include <dev/pci/pcivar.h> |
| 68 | |
| 69 | |
| 70 | /* XXXX some i386 on-board chips act weird when memory-mapped */ |
| 71 | #ifndef __i386__ |
| 72 | #define AHC_ALLOW_MEMIO |
| 73 | #endif |
| 74 | |
| 75 | #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ |
| 76 | #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ |
| 77 | |
| 78 | #include <dev/ic/aic7xxx_osm.h> |
| 79 | #include <dev/ic/aic7xxx_inline.h> |
| 80 | |
| 81 | #include <dev/ic/smc93cx6var.h> |
| 82 | |
| 83 | |
| 84 | static inline uint64_t |
| 85 | ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) |
| 86 | { |
| 87 | uint64_t id; |
| 88 | |
| 89 | id = subvendor |
| 90 | | (subdevice << 16) |
| 91 | | ((uint64_t)vendor << 32) |
| 92 | | ((uint64_t)device << 48); |
| 93 | |
| 94 | return (id); |
| 95 | } |
| 96 | |
| 97 | #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull |
| 98 | #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull |
| 99 | #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull |
| 100 | #define ID_9005_SISL_MASK 0x000FFFFF00000000ull |
| 101 | #define ID_9005_SISL_ID 0x0005900500000000ull |
| 102 | #define ID_AIC7850 0x5078900400000000ull |
| 103 | #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull |
| 104 | #define ID_AIC7855 0x5578900400000000ull |
| 105 | #define ID_AIC7859 0x3860900400000000ull |
| 106 | #define ID_AHA_2930CU 0x3860900438699004ull |
| 107 | #define ID_AIC7860 0x6078900400000000ull |
| 108 | #define ID_AIC7860C 0x6078900478609004ull |
| 109 | #define ID_AHA_1480A 0x6075900400000000ull |
| 110 | #define ID_AHA_2940AU_0 0x6178900400000000ull |
| 111 | #define ID_AHA_2940AU_1 0x6178900478619004ull |
| 112 | #define ID_AHA_2940AU_CN 0x2178900478219004ull |
| 113 | #define ID_AHA_2930C_VAR 0x6038900438689004ull |
| 114 | |
| 115 | #define ID_AIC7870 0x7078900400000000ull |
| 116 | #define ID_AHA_2940 0x7178900400000000ull |
| 117 | #define ID_AHA_3940 0x7278900400000000ull |
| 118 | #define ID_AHA_398X 0x7378900400000000ull |
| 119 | #define ID_AHA_2944 0x7478900400000000ull |
| 120 | #define ID_AHA_3944 0x7578900400000000ull |
| 121 | #define ID_AHA_4944 0x7678900400000000ull |
| 122 | |
| 123 | #define ID_AIC7880 0x8078900400000000ull |
| 124 | #define ID_AIC7880_B 0x8078900478809004ull |
| 125 | #define ID_AHA_2940U 0x8178900400000000ull |
| 126 | #define ID_AHA_3940U 0x8278900400000000ull |
| 127 | #define ID_AHA_2944U 0x8478900400000000ull |
| 128 | #define ID_AHA_3944U 0x8578900400000000ull |
| 129 | #define ID_AHA_398XU 0x8378900400000000ull |
| 130 | #define ID_AHA_4944U 0x8678900400000000ull |
| 131 | #define ID_AHA_2940UB 0x8178900478819004ull |
| 132 | #define ID_AHA_2930U 0x8878900478889004ull |
| 133 | #define ID_AHA_2940U_PRO 0x8778900478879004ull |
| 134 | #define ID_AHA_2940U_CN 0x0078900478009004ull |
| 135 | |
| 136 | #define ID_AIC7895 0x7895900478959004ull |
| 137 | #define ID_AIC7895_ARO 0x7890900478939004ull |
| 138 | #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull |
| 139 | #define ID_AHA_2940U_DUAL 0x7895900478919004ull |
| 140 | #define ID_AHA_3940AU 0x7895900478929004ull |
| 141 | #define ID_AHA_3944AU 0x7895900478949004ull |
| 142 | |
| 143 | #define ID_AIC7890 0x001F9005000F9005ull |
| 144 | #define ID_AIC7890_ARO 0x00139005000F9005ull |
| 145 | #define ID_AAA_131U2 0x0013900500039005ull |
| 146 | #define ID_AHA_2930U2 0x0011900501819005ull |
| 147 | #define ID_AHA_2940U2B 0x00109005A1009005ull |
| 148 | #define ID_AHA_2940U2_OEM 0x0010900521809005ull |
| 149 | #define ID_AHA_2940U2 0x00109005A1809005ull |
| 150 | #define ID_AHA_2950U2B 0x00109005E1009005ull |
| 151 | |
| 152 | #define ID_AIC7892 0x008F9005FFFF9005ull |
| 153 | #define ID_AIC7892_ARO 0x00839005FFFF9005ull |
| 154 | #define ID_AHA_2915LP 0x0082900502109005ull |
| 155 | #define ID_AHA_29160 0x00809005E2A09005ull |
| 156 | #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull |
| 157 | #define ID_AHA_29160N 0x0080900562A09005ull |
| 158 | #define ID_AHA_29160C 0x0080900562209005ull |
| 159 | #define ID_AHA_29160B 0x00809005E2209005ull |
| 160 | #define ID_AHA_19160B 0x0081900562A19005ull |
| 161 | |
| 162 | #define ID_AIC7896 0x005F9005FFFF9005ull |
| 163 | #define ID_AIC7896_ARO 0x00539005FFFF9005ull |
| 164 | #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull |
| 165 | #define ID_AHA_3950U2B_1 0x00509005F5009005ull |
| 166 | #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull |
| 167 | #define ID_AHA_3950U2D_1 0x00519005B5009005ull |
| 168 | |
| 169 | #define ID_AIC7899 0x00CF9005FFFF9005ull |
| 170 | #define ID_AIC7899_ARO 0x00C39005FFFF9005ull |
| 171 | #define ID_AHA_3960D 0x00C09005F6209005ull |
| 172 | #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull |
| 173 | |
| 174 | #define ID_AIC7810 0x1078900400000000ull |
| 175 | #define ID_AIC7815 0x7815900400000000ull |
| 176 | |
| 177 | #define DEVID_9005_TYPE(id) ((id) & 0xF) |
| 178 | #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ |
| 179 | #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ |
| 180 | #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ |
| 181 | #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ |
| 182 | |
| 183 | #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) |
| 184 | #define DEVID_9005_MAXRATE_U160 0x0 |
| 185 | #define DEVID_9005_MAXRATE_ULTRA2 0x1 |
| 186 | #define DEVID_9005_MAXRATE_ULTRA 0x2 |
| 187 | #define DEVID_9005_MAXRATE_FAST 0x3 |
| 188 | |
| 189 | #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) |
| 190 | |
| 191 | #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) |
| 192 | #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ |
| 193 | |
| 194 | #define SUBID_9005_TYPE(id) ((id) & 0xF) |
| 195 | #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ |
| 196 | #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ |
| 197 | #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ |
| 198 | #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ |
| 199 | |
| 200 | #define SUBID_9005_TYPE_KNOWN(id) \ |
| 201 | ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ |
| 202 | || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ |
| 203 | || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ |
| 204 | || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) |
| 205 | |
| 206 | #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) |
| 207 | #define SUBID_9005_MAXRATE_ULTRA2 0x0 |
| 208 | #define SUBID_9005_MAXRATE_ULTRA 0x1 |
| 209 | #define SUBID_9005_MAXRATE_U160 0x2 |
| 210 | #define SUBID_9005_MAXRATE_RESERVED 0x3 |
| 211 | |
| 212 | #define SUBID_9005_SEEPTYPE(id) \ |
| 213 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 214 | ? ((id) & 0xC0) >> 6 \ |
| 215 | : ((id) & 0x300) >> 8) |
| 216 | #define SUBID_9005_SEEPTYPE_NONE 0x0 |
| 217 | #define SUBID_9005_SEEPTYPE_1K 0x1 |
| 218 | #define SUBID_9005_SEEPTYPE_2K_4K 0x2 |
| 219 | #define SUBID_9005_SEEPTYPE_RESERVED 0x3 |
| 220 | #define SUBID_9005_AUTOTERM(id) \ |
| 221 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 222 | ? (((id) & 0x400) >> 10) == 0 \ |
| 223 | : (((id) & 0x40) >> 6) == 0) |
| 224 | |
| 225 | #define SUBID_9005_NUMCHAN(id) \ |
| 226 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 227 | ? ((id) & 0x300) >> 8 \ |
| 228 | : ((id) & 0xC00) >> 10) |
| 229 | |
| 230 | #define SUBID_9005_LEGACYCONN(id) \ |
| 231 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 232 | ? 0 \ |
| 233 | : ((id) & 0x80) >> 7) |
| 234 | |
| 235 | #define SUBID_9005_MFUNCENB(id) \ |
| 236 | ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ |
| 237 | ? ((id) & 0x800) >> 11 \ |
| 238 | : ((id) & 0x1000) >> 12) |
| 239 | /* |
| 240 | * Informational only. Should use chip register to be |
| 241 | * certain, but may be use in identification strings. |
| 242 | */ |
| 243 | #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 |
| 244 | #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 |
| 245 | #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 |
| 246 | |
| 247 | static ahc_device_setup_t ahc_aic785X_setup; |
| 248 | static ahc_device_setup_t ahc_aic7860_setup; |
| 249 | static ahc_device_setup_t ahc_apa1480_setup; |
| 250 | static ahc_device_setup_t ahc_aic7870_setup; |
| 251 | static ahc_device_setup_t ahc_aha394X_setup; |
| 252 | static ahc_device_setup_t ahc_aha494X_setup; |
| 253 | static ahc_device_setup_t ahc_aha398X_setup; |
| 254 | static ahc_device_setup_t ahc_aic7880_setup; |
| 255 | static ahc_device_setup_t ahc_aha2940Pro_setup; |
| 256 | static ahc_device_setup_t ahc_aha394XU_setup; |
| 257 | static ahc_device_setup_t ahc_aha398XU_setup; |
| 258 | static ahc_device_setup_t ahc_aic7890_setup; |
| 259 | static ahc_device_setup_t ahc_aic7892_setup; |
| 260 | static ahc_device_setup_t ahc_aic7895_setup; |
| 261 | static ahc_device_setup_t ahc_aic7896_setup; |
| 262 | static ahc_device_setup_t ahc_aic7899_setup; |
| 263 | static ahc_device_setup_t ahc_aha29160C_setup; |
| 264 | static ahc_device_setup_t ahc_raid_setup; |
| 265 | static ahc_device_setup_t ahc_aha394XX_setup; |
| 266 | static ahc_device_setup_t ahc_aha494XX_setup; |
| 267 | static ahc_device_setup_t ahc_aha398XX_setup; |
| 268 | |
| 269 | static struct ahc_pci_identity ahc_pci_ident_table [] = |
| 270 | { |
| 271 | /* aic7850 based controllers */ |
| 272 | { |
| 273 | ID_AHA_2902_04_10_15_20_30C, |
| 274 | ID_ALL_MASK, |
| 275 | "Adaptec 2902/04/10/15/20/30C SCSI adapter" , |
| 276 | ahc_aic785X_setup |
| 277 | }, |
| 278 | /* aic7860 based controllers */ |
| 279 | { |
| 280 | ID_AHA_2930CU, |
| 281 | ID_ALL_MASK, |
| 282 | "Adaptec 2930CU SCSI adapter" , |
| 283 | ahc_aic7860_setup |
| 284 | }, |
| 285 | { |
| 286 | ID_AHA_1480A & ID_DEV_VENDOR_MASK, |
| 287 | ID_DEV_VENDOR_MASK, |
| 288 | "Adaptec 1480A Ultra SCSI adapter" , |
| 289 | ahc_apa1480_setup |
| 290 | }, |
| 291 | { |
| 292 | ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, |
| 293 | ID_DEV_VENDOR_MASK, |
| 294 | "Adaptec 2940A Ultra SCSI adapter" , |
| 295 | ahc_aic7860_setup |
| 296 | }, |
| 297 | { |
| 298 | ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, |
| 299 | ID_DEV_VENDOR_MASK, |
| 300 | "Adaptec 2940A/CN Ultra SCSI adapter" , |
| 301 | ahc_aic7860_setup |
| 302 | }, |
| 303 | { |
| 304 | ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, |
| 305 | ID_DEV_VENDOR_MASK, |
| 306 | "Adaptec 2930C Ultra SCSI adapter (VAR)" , |
| 307 | ahc_aic7860_setup |
| 308 | }, |
| 309 | /* aic7870 based controllers */ |
| 310 | { |
| 311 | ID_AHA_2940, |
| 312 | ID_ALL_MASK, |
| 313 | "Adaptec 2940 SCSI adapter" , |
| 314 | ahc_aic7870_setup |
| 315 | }, |
| 316 | { |
| 317 | ID_AHA_3940, |
| 318 | ID_ALL_MASK, |
| 319 | "Adaptec 3940 SCSI adapter" , |
| 320 | ahc_aha394X_setup |
| 321 | }, |
| 322 | { |
| 323 | ID_AHA_398X, |
| 324 | ID_ALL_MASK, |
| 325 | "Adaptec 398X SCSI RAID adapter" , |
| 326 | ahc_aha398X_setup |
| 327 | }, |
| 328 | { |
| 329 | ID_AHA_2944, |
| 330 | ID_ALL_MASK, |
| 331 | "Adaptec 2944 SCSI adapter" , |
| 332 | ahc_aic7870_setup |
| 333 | }, |
| 334 | { |
| 335 | ID_AHA_3944, |
| 336 | ID_ALL_MASK, |
| 337 | "Adaptec 3944 SCSI adapter" , |
| 338 | ahc_aha394X_setup |
| 339 | }, |
| 340 | { |
| 341 | ID_AHA_4944, |
| 342 | ID_ALL_MASK, |
| 343 | "Adaptec 4944 SCSI adapter" , |
| 344 | ahc_aha494X_setup |
| 345 | }, |
| 346 | /* aic7880 based controllers */ |
| 347 | { |
| 348 | ID_AHA_2940U & ID_DEV_VENDOR_MASK, |
| 349 | ID_DEV_VENDOR_MASK, |
| 350 | "Adaptec 2940 Ultra SCSI adapter" , |
| 351 | ahc_aic7880_setup |
| 352 | }, |
| 353 | { |
| 354 | ID_AHA_3940U & ID_DEV_VENDOR_MASK, |
| 355 | ID_DEV_VENDOR_MASK, |
| 356 | "Adaptec 3940 Ultra SCSI adapter" , |
| 357 | ahc_aha394XU_setup |
| 358 | }, |
| 359 | { |
| 360 | ID_AHA_2944U & ID_DEV_VENDOR_MASK, |
| 361 | ID_DEV_VENDOR_MASK, |
| 362 | "Adaptec 2944 Ultra SCSI adapter" , |
| 363 | ahc_aic7880_setup |
| 364 | }, |
| 365 | { |
| 366 | ID_AHA_3944U & ID_DEV_VENDOR_MASK, |
| 367 | ID_DEV_VENDOR_MASK, |
| 368 | "Adaptec 3944 Ultra SCSI adapter" , |
| 369 | ahc_aha394XU_setup |
| 370 | }, |
| 371 | { |
| 372 | ID_AHA_398XU & ID_DEV_VENDOR_MASK, |
| 373 | ID_DEV_VENDOR_MASK, |
| 374 | "Adaptec 398X Ultra SCSI RAID adapter" , |
| 375 | ahc_aha398XU_setup |
| 376 | }, |
| 377 | { |
| 378 | /* |
| 379 | * XXX Don't know the slot numbers |
| 380 | * so we can't identify channels |
| 381 | */ |
| 382 | ID_AHA_4944U & ID_DEV_VENDOR_MASK, |
| 383 | ID_DEV_VENDOR_MASK, |
| 384 | "Adaptec 4944 Ultra SCSI adapter" , |
| 385 | ahc_aic7880_setup |
| 386 | }, |
| 387 | { |
| 388 | ID_AHA_2930U & ID_DEV_VENDOR_MASK, |
| 389 | ID_DEV_VENDOR_MASK, |
| 390 | "Adaptec 2930 Ultra SCSI adapter" , |
| 391 | ahc_aic7880_setup |
| 392 | }, |
| 393 | { |
| 394 | ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, |
| 395 | ID_DEV_VENDOR_MASK, |
| 396 | "Adaptec 2940 Pro Ultra SCSI adapter" , |
| 397 | ahc_aha2940Pro_setup |
| 398 | }, |
| 399 | { |
| 400 | ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, |
| 401 | ID_DEV_VENDOR_MASK, |
| 402 | "Adaptec 2940/CN Ultra SCSI adapter" , |
| 403 | ahc_aic7880_setup |
| 404 | }, |
| 405 | /* Ignore all SISL (AAC on MB) based controllers. */ |
| 406 | { |
| 407 | ID_9005_SISL_ID, |
| 408 | ID_9005_SISL_MASK, |
| 409 | NULL, |
| 410 | NULL |
| 411 | }, |
| 412 | /* aic7890 based controllers */ |
| 413 | { |
| 414 | ID_AHA_2930U2, |
| 415 | ID_ALL_MASK, |
| 416 | "Adaptec 2930 Ultra2 SCSI adapter" , |
| 417 | ahc_aic7890_setup |
| 418 | }, |
| 419 | { |
| 420 | ID_AHA_2940U2B, |
| 421 | ID_ALL_MASK, |
| 422 | "Adaptec 2940B Ultra2 SCSI adapter" , |
| 423 | ahc_aic7890_setup |
| 424 | }, |
| 425 | { |
| 426 | ID_AHA_2940U2_OEM, |
| 427 | ID_ALL_MASK, |
| 428 | "Adaptec 2940 Ultra2 SCSI adapter (OEM)" , |
| 429 | ahc_aic7890_setup |
| 430 | }, |
| 431 | { |
| 432 | ID_AHA_2940U2, |
| 433 | ID_ALL_MASK, |
| 434 | "Adaptec 2940 Ultra2 SCSI adapter" , |
| 435 | ahc_aic7890_setup |
| 436 | }, |
| 437 | { |
| 438 | ID_AHA_2950U2B, |
| 439 | ID_ALL_MASK, |
| 440 | "Adaptec 2950 Ultra2 SCSI adapter" , |
| 441 | ahc_aic7890_setup |
| 442 | }, |
| 443 | { |
| 444 | ID_AIC7890_ARO, |
| 445 | ID_ALL_MASK, |
| 446 | "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)" , |
| 447 | ahc_aic7890_setup |
| 448 | }, |
| 449 | { |
| 450 | ID_AAA_131U2, |
| 451 | ID_ALL_MASK, |
| 452 | "Adaptec AAA-131 Ultra2 RAID adapter" , |
| 453 | ahc_aic7890_setup |
| 454 | }, |
| 455 | /* aic7892 based controllers */ |
| 456 | { |
| 457 | ID_AHA_29160, |
| 458 | ID_ALL_MASK, |
| 459 | "Adaptec 29160 Ultra160 SCSI adapter" , |
| 460 | ahc_aic7892_setup |
| 461 | }, |
| 462 | { |
| 463 | ID_AHA_29160_CPQ, |
| 464 | ID_ALL_MASK, |
| 465 | "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter" , |
| 466 | ahc_aic7892_setup |
| 467 | }, |
| 468 | { |
| 469 | ID_AHA_29160N, |
| 470 | ID_ALL_MASK, |
| 471 | "Adaptec 29160N Ultra160 SCSI adapter" , |
| 472 | ahc_aic7892_setup |
| 473 | }, |
| 474 | { |
| 475 | ID_AHA_29160C, |
| 476 | ID_ALL_MASK, |
| 477 | "Adaptec 29160C Ultra160 SCSI adapter" , |
| 478 | ahc_aha29160C_setup |
| 479 | }, |
| 480 | { |
| 481 | ID_AHA_29160B, |
| 482 | ID_ALL_MASK, |
| 483 | "Adaptec 29160B Ultra160 SCSI adapter" , |
| 484 | ahc_aic7892_setup |
| 485 | }, |
| 486 | { |
| 487 | ID_AHA_19160B, |
| 488 | ID_ALL_MASK, |
| 489 | "Adaptec 19160B Ultra160 SCSI adapter" , |
| 490 | ahc_aic7892_setup |
| 491 | }, |
| 492 | { |
| 493 | ID_AIC7892_ARO, |
| 494 | ID_ALL_MASK, |
| 495 | "Adaptec aic7892 Ultra160 SCSI adapter (ARO)" , |
| 496 | ahc_aic7892_setup |
| 497 | }, |
| 498 | { |
| 499 | ID_AHA_2915LP, |
| 500 | ID_ALL_MASK, |
| 501 | "Adaptec 2915LP Ultra160 SCSI adapter" , |
| 502 | ahc_aic7892_setup |
| 503 | }, |
| 504 | /* aic7895 based controllers */ |
| 505 | { |
| 506 | ID_AHA_2940U_DUAL, |
| 507 | ID_ALL_MASK, |
| 508 | "Adaptec 2940/DUAL Ultra SCSI adapter" , |
| 509 | ahc_aic7895_setup |
| 510 | }, |
| 511 | { |
| 512 | ID_AHA_3940AU, |
| 513 | ID_ALL_MASK, |
| 514 | "Adaptec 3940A Ultra SCSI adapter" , |
| 515 | ahc_aic7895_setup |
| 516 | }, |
| 517 | { |
| 518 | ID_AHA_3944AU, |
| 519 | ID_ALL_MASK, |
| 520 | "Adaptec 3944A Ultra SCSI adapter" , |
| 521 | ahc_aic7895_setup |
| 522 | }, |
| 523 | { |
| 524 | ID_AIC7895_ARO, |
| 525 | ID_AIC7895_ARO_MASK, |
| 526 | "Adaptec aic7895 Ultra SCSI adapter (ARO)" , |
| 527 | ahc_aic7895_setup |
| 528 | }, |
| 529 | /* aic7896/97 based controllers */ |
| 530 | { |
| 531 | ID_AHA_3950U2B_0, |
| 532 | ID_ALL_MASK, |
| 533 | "Adaptec 3950B Ultra2 SCSI adapter" , |
| 534 | ahc_aic7896_setup |
| 535 | }, |
| 536 | { |
| 537 | ID_AHA_3950U2B_1, |
| 538 | ID_ALL_MASK, |
| 539 | "Adaptec 3950B Ultra2 SCSI adapter" , |
| 540 | ahc_aic7896_setup |
| 541 | }, |
| 542 | { |
| 543 | ID_AHA_3950U2D_0, |
| 544 | ID_ALL_MASK, |
| 545 | "Adaptec 3950D Ultra2 SCSI adapter" , |
| 546 | ahc_aic7896_setup |
| 547 | }, |
| 548 | { |
| 549 | ID_AHA_3950U2D_1, |
| 550 | ID_ALL_MASK, |
| 551 | "Adaptec 3950D Ultra2 SCSI adapter" , |
| 552 | ahc_aic7896_setup |
| 553 | }, |
| 554 | { |
| 555 | ID_AIC7896_ARO, |
| 556 | ID_ALL_MASK, |
| 557 | "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)" , |
| 558 | ahc_aic7896_setup |
| 559 | }, |
| 560 | /* aic7899 based controllers */ |
| 561 | { |
| 562 | ID_AHA_3960D, |
| 563 | ID_ALL_MASK, |
| 564 | "Adaptec 3960D Ultra160 SCSI adapter" , |
| 565 | ahc_aic7899_setup |
| 566 | }, |
| 567 | { |
| 568 | ID_AHA_3960D_CPQ, |
| 569 | ID_ALL_MASK, |
| 570 | "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter" , |
| 571 | ahc_aic7899_setup |
| 572 | }, |
| 573 | { |
| 574 | ID_AIC7899_ARO, |
| 575 | ID_ALL_MASK, |
| 576 | "Adaptec aic7899 Ultra160 SCSI adapter (ARO)" , |
| 577 | ahc_aic7899_setup |
| 578 | }, |
| 579 | /* Generic chip probes for devices we don't know 'exactly' */ |
| 580 | { |
| 581 | ID_AIC7850 & ID_DEV_VENDOR_MASK, |
| 582 | ID_DEV_VENDOR_MASK, |
| 583 | "Adaptec aic7850 SCSI adapter" , |
| 584 | ahc_aic785X_setup |
| 585 | }, |
| 586 | { |
| 587 | ID_AIC7855 & ID_DEV_VENDOR_MASK, |
| 588 | ID_DEV_VENDOR_MASK, |
| 589 | "Adaptec aic7855 SCSI adapter" , |
| 590 | ahc_aic785X_setup |
| 591 | }, |
| 592 | { |
| 593 | ID_AIC7859 & ID_DEV_VENDOR_MASK, |
| 594 | ID_DEV_VENDOR_MASK, |
| 595 | "Adaptec aic7859 SCSI adapter" , |
| 596 | ahc_aic7860_setup |
| 597 | }, |
| 598 | { |
| 599 | ID_AIC7860 & ID_DEV_VENDOR_MASK, |
| 600 | ID_DEV_VENDOR_MASK, |
| 601 | "Adaptec aic7860 Ultra SCSI adapter" , |
| 602 | ahc_aic7860_setup |
| 603 | }, |
| 604 | { |
| 605 | ID_AIC7870 & ID_DEV_VENDOR_MASK, |
| 606 | ID_DEV_VENDOR_MASK, |
| 607 | "Adaptec aic7870 SCSI adapter" , |
| 608 | ahc_aic7870_setup |
| 609 | }, |
| 610 | { |
| 611 | ID_AIC7880 & ID_DEV_VENDOR_MASK, |
| 612 | ID_DEV_VENDOR_MASK, |
| 613 | "Adaptec aic7880 Ultra SCSI adapter" , |
| 614 | ahc_aic7880_setup |
| 615 | }, |
| 616 | { |
| 617 | ID_AIC7890 & ID_9005_GENERIC_MASK, |
| 618 | ID_9005_GENERIC_MASK, |
| 619 | "Adaptec aic7890/91 Ultra2 SCSI adapter" , |
| 620 | ahc_aic7890_setup |
| 621 | }, |
| 622 | { |
| 623 | ID_AIC7892 & ID_9005_GENERIC_MASK, |
| 624 | ID_9005_GENERIC_MASK, |
| 625 | "Adaptec aic7892 Ultra160 SCSI adapter" , |
| 626 | ahc_aic7892_setup |
| 627 | }, |
| 628 | { |
| 629 | ID_AIC7895 & ID_DEV_VENDOR_MASK, |
| 630 | ID_DEV_VENDOR_MASK, |
| 631 | "Adaptec aic7895 Ultra SCSI adapter" , |
| 632 | ahc_aic7895_setup |
| 633 | }, |
| 634 | { |
| 635 | ID_AIC7896 & ID_9005_GENERIC_MASK, |
| 636 | ID_9005_GENERIC_MASK, |
| 637 | "Adaptec aic7896/97 Ultra2 SCSI adapter" , |
| 638 | ahc_aic7896_setup |
| 639 | }, |
| 640 | { |
| 641 | ID_AIC7899 & ID_9005_GENERIC_MASK, |
| 642 | ID_9005_GENERIC_MASK, |
| 643 | "Adaptec aic7899 Ultra160 SCSI adapter" , |
| 644 | ahc_aic7899_setup |
| 645 | }, |
| 646 | { |
| 647 | ID_AIC7810 & ID_DEV_VENDOR_MASK, |
| 648 | ID_DEV_VENDOR_MASK, |
| 649 | "Adaptec aic7810 RAID memory controller" , |
| 650 | ahc_raid_setup |
| 651 | }, |
| 652 | { |
| 653 | ID_AIC7815 & ID_DEV_VENDOR_MASK, |
| 654 | ID_DEV_VENDOR_MASK, |
| 655 | "Adaptec aic7815 RAID memory controller" , |
| 656 | ahc_raid_setup |
| 657 | } |
| 658 | }; |
| 659 | |
| 660 | static const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); |
| 661 | |
| 662 | #define AHC_394X_SLOT_CHANNEL_A 4 |
| 663 | #define AHC_394X_SLOT_CHANNEL_B 5 |
| 664 | |
| 665 | #define AHC_398X_SLOT_CHANNEL_A 4 |
| 666 | #define AHC_398X_SLOT_CHANNEL_B 8 |
| 667 | #define AHC_398X_SLOT_CHANNEL_C 12 |
| 668 | |
| 669 | #define AHC_494X_SLOT_CHANNEL_A 4 |
| 670 | #define AHC_494X_SLOT_CHANNEL_B 5 |
| 671 | #define AHC_494X_SLOT_CHANNEL_C 6 |
| 672 | #define AHC_494X_SLOT_CHANNEL_D 7 |
| 673 | |
| 674 | #define DEVCONFIG 0x40 |
| 675 | #define PCIERRGENDIS 0x80000000ul |
| 676 | #define SCBSIZE32 0x00010000ul /* aic789X only */ |
| 677 | #define REXTVALID 0x00001000ul /* ultra cards only */ |
| 678 | #define MPORTMODE 0x00000400ul /* aic7870+ only */ |
| 679 | #define RAMPSM 0x00000200ul /* aic7870+ only */ |
| 680 | #define VOLSENSE 0x00000100ul |
| 681 | #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ |
| 682 | #define SCBRAMSEL 0x00000080ul |
| 683 | #define MRDCEN 0x00000040ul |
| 684 | #define EXTSCBTIME 0x00000020ul /* aic7870 only */ |
| 685 | #define EXTSCBPEN 0x00000010ul /* aic7870 only */ |
| 686 | #define BERREN 0x00000008ul |
| 687 | #define DACEN 0x00000004ul |
| 688 | #define STPWLEVEL 0x00000002ul |
| 689 | #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ |
| 690 | |
| 691 | #define CSIZE_LATTIME 0x0c |
| 692 | #define CACHESIZE 0x0000003ful /* only 5 bits */ |
| 693 | #define LATTIME 0x0000ff00ul |
| 694 | |
| 695 | /* PCI STATUS definitions */ |
| 696 | #define DPE 0x80 |
| 697 | #define SSE 0x40 |
| 698 | #define RMA 0x20 |
| 699 | #define RTA 0x10 |
| 700 | #define STA 0x08 |
| 701 | #define DPR 0x01 |
| 702 | |
| 703 | static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, |
| 704 | uint16_t subvendor, uint16_t subdevice); |
| 705 | static int ahc_ext_scbram_present(struct ahc_softc *ahc); |
| 706 | static void ahc_scbram_config(struct ahc_softc *ahc, int enable, |
| 707 | int pcheck, int fast, int large); |
| 708 | static void ahc_probe_ext_scbram(struct ahc_softc *ahc); |
| 709 | |
| 710 | static void ahc_pci_intr(struct ahc_softc *); |
| 711 | |
| 712 | static const struct ahc_pci_identity * |
| 713 | ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) |
| 714 | { |
| 715 | u_int64_t full_id; |
| 716 | const struct ahc_pci_identity *entry; |
| 717 | u_int i; |
| 718 | |
| 719 | full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), |
| 720 | PCI_PRODUCT(subid), PCI_VENDOR(subid)); |
| 721 | |
| 722 | /* |
| 723 | * If the second function is not hooked up, ignore it. |
| 724 | * Unfortunately, not all MB vendors implement the |
| 725 | * subdevice ID as per the Adaptec spec, so do our best |
| 726 | * to sanity check it prior to accepting the subdevice |
| 727 | * ID as valid. |
| 728 | */ |
| 729 | if (func > 0 |
| 730 | && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), |
| 731 | PCI_VENDOR(subid), PCI_PRODUCT(subid)) |
| 732 | && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) |
| 733 | return (NULL); |
| 734 | |
| 735 | for (i = 0; i < ahc_num_pci_devs; i++) { |
| 736 | entry = &ahc_pci_ident_table[i]; |
| 737 | if (entry->full_id == (full_id & entry->id_mask)) |
| 738 | return (entry); |
| 739 | } |
| 740 | return (NULL); |
| 741 | } |
| 742 | |
| 743 | static int |
| 744 | ahc_pci_probe(device_t parent, cfdata_t match, void *aux) |
| 745 | { |
| 746 | struct pci_attach_args *pa = aux; |
| 747 | const struct ahc_pci_identity *entry; |
| 748 | pcireg_t subid; |
| 749 | |
| 750 | subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); |
| 751 | entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); |
| 752 | return (entry != NULL && entry->setup != NULL) ? 1 : 0; |
| 753 | } |
| 754 | |
| 755 | static void |
| 756 | ahc_pci_attach(device_t parent, device_t self, void *aux) |
| 757 | { |
| 758 | struct pci_attach_args *pa = aux; |
| 759 | const struct ahc_pci_identity *entry; |
| 760 | struct ahc_softc *ahc = device_private(self); |
| 761 | pcireg_t command; |
| 762 | u_int our_id = 0; |
| 763 | u_int sxfrctl1; |
| 764 | u_int scsiseq; |
| 765 | u_int sblkctl; |
| 766 | uint8_t dscommand0; |
| 767 | uint32_t devconfig; |
| 768 | int error; |
| 769 | pcireg_t subid; |
| 770 | int ioh_valid; |
| 771 | bus_space_tag_t st, iot; |
| 772 | bus_space_handle_t sh, ioh; |
| 773 | #ifdef AHC_ALLOW_MEMIO |
| 774 | int memh_valid; |
| 775 | bus_space_tag_t memt; |
| 776 | bus_space_handle_t memh; |
| 777 | pcireg_t memtype; |
| 778 | #endif |
| 779 | pci_intr_handle_t ih; |
| 780 | const char *intrstr; |
| 781 | struct ahc_pci_busdata *bd; |
| 782 | bool override_ultra; |
| 783 | char intrbuf[PCI_INTRSTR_LEN]; |
| 784 | |
| 785 | ahc->sc_dev = self; |
| 786 | ahc_set_name(ahc, device_xname(ahc->sc_dev)); |
| 787 | ahc->parent_dmat = pa->pa_dmat; |
| 788 | |
| 789 | command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
| 790 | subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); |
| 791 | entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); |
| 792 | if (entry == NULL) |
| 793 | return; |
| 794 | aprint_naive("\n" ); |
| 795 | aprint_normal(": %s\n" , entry->name); |
| 796 | |
| 797 | /* Keep information about the PCI bus */ |
| 798 | bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); |
| 799 | if (bd == NULL) { |
| 800 | aprint_error("%s: unable to allocate bus-specific data\n" , |
| 801 | ahc_name(ahc)); |
| 802 | return; |
| 803 | } |
| 804 | memset(bd, 0, sizeof(struct ahc_pci_busdata)); |
| 805 | |
| 806 | bd->pc = pa->pa_pc; |
| 807 | bd->tag = pa->pa_tag; |
| 808 | bd->func = pa->pa_function; |
| 809 | bd->dev = pa->pa_device; |
| 810 | bd->class = pa->pa_class; |
| 811 | |
| 812 | ahc->bd = bd; |
| 813 | |
| 814 | ahc->description = entry->name; |
| 815 | |
| 816 | error = entry->setup(ahc); |
| 817 | if (error != 0) |
| 818 | return; |
| 819 | |
| 820 | ioh_valid = 0; |
| 821 | |
| 822 | #ifdef AHC_ALLOW_MEMIO |
| 823 | memh_valid = 0; |
| 824 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); |
| 825 | switch (memtype) { |
| 826 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: |
| 827 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: |
| 828 | memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, |
| 829 | memtype, 0, &memt, &memh, NULL, NULL) == 0); |
| 830 | break; |
| 831 | default: |
| 832 | memh_valid = 0; |
| 833 | } |
| 834 | #endif |
| 835 | ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, |
| 836 | PCI_MAPREG_TYPE_IO, 0, &iot, |
| 837 | &ioh, NULL, NULL) == 0); |
| 838 | |
| 839 | #if 0 |
| 840 | printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n" , |
| 841 | ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, |
| 842 | (u_long)ioh); |
| 843 | #endif |
| 844 | |
| 845 | #ifdef AHC_ALLOW_MEMIO |
| 846 | if (memh_valid) { |
| 847 | st = memt; |
| 848 | sh = memh; |
| 849 | } else |
| 850 | #endif |
| 851 | if (ioh_valid) { |
| 852 | st = iot; |
| 853 | sh = ioh; |
| 854 | } else { |
| 855 | aprint_error(": unable to map registers\n" ); |
| 856 | return; |
| 857 | } |
| 858 | ahc->tag = st; |
| 859 | ahc->bsh = sh; |
| 860 | |
| 861 | ahc->chip |= AHC_PCI; |
| 862 | /* |
| 863 | * Before we continue probing the card, ensure that |
| 864 | * its interrupts are *disabled*. We don't want |
| 865 | * a misstep to hang the machine in an interrupt |
| 866 | * storm. |
| 867 | */ |
| 868 | ahc_intr_enable(ahc, FALSE); |
| 869 | |
| 870 | /* |
| 871 | * XXX somehow reading this once fails on some sparc64 systems. |
| 872 | * This may be a problem in the sparc64 PCI code. Doing it |
| 873 | * twice works around it. |
| 874 | */ |
| 875 | devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); |
| 876 | devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); |
| 877 | |
| 878 | /* |
| 879 | * If we need to support high memory, enable dual |
| 880 | * address cycles. This bit must be set to enable |
| 881 | * high address bit generation even if we are on a |
| 882 | * 64bit bus (PCI64BIT set in devconfig). |
| 883 | */ |
| 884 | if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { |
| 885 | |
| 886 | if (1/*bootverbose*/) |
| 887 | aprint_normal("%s: Enabling 39Bit Addressing\n" , |
| 888 | ahc_name(ahc)); |
| 889 | devconfig |= DACEN; |
| 890 | } |
| 891 | |
| 892 | /* Ensure that pci error generation, a test feature, is disabled. */ |
| 893 | devconfig |= PCIERRGENDIS; |
| 894 | |
| 895 | pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); |
| 896 | |
| 897 | /* Ensure busmastering is enabled */ |
| 898 | command |= PCI_COMMAND_MASTER_ENABLE; |
| 899 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); |
| 900 | |
| 901 | /* |
| 902 | * Disable PCI parity error reporting. Users typically |
| 903 | * do this to work around broken PCI chipsets that get |
| 904 | * the parity timing wrong and thus generate lots of spurious |
| 905 | * errors. |
| 906 | */ |
| 907 | if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) |
| 908 | command &= ~PCI_COMMAND_PARITY_ENABLE; |
| 909 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); |
| 910 | |
| 911 | /* On all PCI adapters, we allow SCB paging */ |
| 912 | ahc->flags |= AHC_PAGESCBS; |
| 913 | error = ahc_softc_init(ahc); |
| 914 | if (error != 0) |
| 915 | goto error_out; |
| 916 | |
| 917 | ahc->bus_intr = ahc_pci_intr; |
| 918 | |
| 919 | /* Remember how the card was setup in case there is no SEEPROM */ |
| 920 | if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { |
| 921 | ahc_pause(ahc); |
| 922 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 923 | our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; |
| 924 | else |
| 925 | our_id = ahc_inb(ahc, SCSIID) & OID; |
| 926 | sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; |
| 927 | scsiseq = ahc_inb(ahc, SCSISEQ); |
| 928 | } else { |
| 929 | sxfrctl1 = STPWEN; |
| 930 | our_id = 7; |
| 931 | scsiseq = 0; |
| 932 | } |
| 933 | |
| 934 | error = ahc_reset(ahc); |
| 935 | if (error != 0) |
| 936 | goto error_out; |
| 937 | |
| 938 | if ((ahc->features & AHC_DT) != 0) { |
| 939 | u_int sfunct; |
| 940 | |
| 941 | /* Perform ALT-Mode Setup */ |
| 942 | sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; |
| 943 | ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); |
| 944 | ahc_outb(ahc, OPTIONMODE, |
| 945 | OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); |
| 946 | ahc_outb(ahc, SFUNCT, sfunct); |
| 947 | |
| 948 | /* Normal mode setup */ |
| 949 | ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN |
| 950 | |TARGCRCENDEN); |
| 951 | } |
| 952 | |
| 953 | if (pci_intr_map(pa, &ih)) { |
| 954 | aprint_error("%s: couldn't map interrupt\n" , ahc_name(ahc)); |
| 955 | ahc_free(ahc); |
| 956 | return; |
| 957 | } |
| 958 | intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); |
| 959 | ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); |
| 960 | if (ahc->ih == NULL) { |
| 961 | aprint_error_dev(ahc->sc_dev, |
| 962 | "couldn't establish interrupt\n" ); |
| 963 | if (intrstr != NULL) |
| 964 | aprint_error(" at %s" , intrstr); |
| 965 | aprint_error("\n" ); |
| 966 | ahc_free(ahc); |
| 967 | return; |
| 968 | } |
| 969 | if (intrstr != NULL) |
| 970 | aprint_normal("%s: interrupting at %s\n" , ahc_name(ahc), |
| 971 | intrstr); |
| 972 | |
| 973 | dscommand0 = ahc_inb(ahc, DSCOMMAND0); |
| 974 | dscommand0 |= MPARCKEN|CACHETHEN; |
| 975 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 976 | |
| 977 | /* |
| 978 | * DPARCKEN doesn't work correctly on |
| 979 | * some MBs so don't use it. |
| 980 | */ |
| 981 | dscommand0 &= ~DPARCKEN; |
| 982 | } |
| 983 | |
| 984 | /* |
| 985 | * Handle chips that must have cache line |
| 986 | * streaming (dis/en)abled. |
| 987 | */ |
| 988 | if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) |
| 989 | dscommand0 |= CACHETHEN; |
| 990 | |
| 991 | if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) |
| 992 | dscommand0 &= ~CACHETHEN; |
| 993 | |
| 994 | ahc_outb(ahc, DSCOMMAND0, dscommand0); |
| 995 | |
| 996 | ahc->pci_cachesize = |
| 997 | pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; |
| 998 | ahc->pci_cachesize *= 4; |
| 999 | |
| 1000 | if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 |
| 1001 | && ahc->pci_cachesize == 4) { |
| 1002 | pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); |
| 1003 | ahc->pci_cachesize = 0; |
| 1004 | } |
| 1005 | |
| 1006 | /* |
| 1007 | * We cannot perform ULTRA speeds without the presence |
| 1008 | * of the external precision resistor. |
| 1009 | * Allow override for the SGI O2 though, which has two onboard ahc |
| 1010 | * that fail here but are perfectly capable of ultra speeds. |
| 1011 | */ |
| 1012 | override_ultra = FALSE; |
| 1013 | prop_dictionary_get_bool(device_properties(self), |
| 1014 | "aic7xxx-override-ultra" , &override_ultra); |
| 1015 | |
| 1016 | if (((ahc->features & AHC_ULTRA) != 0) && (!override_ultra)) { |
| 1017 | uint32_t dvconfig; |
| 1018 | |
| 1019 | dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); |
| 1020 | if ((dvconfig & REXTVALID) == 0) |
| 1021 | ahc->features &= ~AHC_ULTRA; |
| 1022 | } |
| 1023 | |
| 1024 | ahc->seep_config = malloc(sizeof(*ahc->seep_config), |
| 1025 | M_DEVBUF, M_NOWAIT); |
| 1026 | if (ahc->seep_config == NULL) |
| 1027 | goto error_out; |
| 1028 | |
| 1029 | memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); |
| 1030 | |
| 1031 | /* See if we have a SEEPROM and perform auto-term */ |
| 1032 | ahc_check_extport(ahc, &sxfrctl1); |
| 1033 | |
| 1034 | /* |
| 1035 | * Take the LED out of diagnostic mode |
| 1036 | */ |
| 1037 | sblkctl = ahc_inb(ahc, SBLKCTL); |
| 1038 | ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); |
| 1039 | |
| 1040 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1041 | ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); |
| 1042 | } else { |
| 1043 | ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); |
| 1044 | } |
| 1045 | |
| 1046 | if (ahc->flags & AHC_USEDEFAULTS) { |
| 1047 | /* |
| 1048 | * PCI Adapter default setup |
| 1049 | * Should only be used if the adapter does not have |
| 1050 | * a SEEPROM. |
| 1051 | */ |
| 1052 | /* See if someone else set us up already */ |
| 1053 | if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 |
| 1054 | && scsiseq != 0) { |
| 1055 | prop_bool_t usetd; |
| 1056 | |
| 1057 | printf("%s: Using left over BIOS settings\n" , |
| 1058 | ahc_name(ahc)); |
| 1059 | ahc->flags &= ~AHC_USEDEFAULTS; |
| 1060 | /* |
| 1061 | * Ignore target device settings and use default |
| 1062 | * if BIOS initializes chip's SRAM with some |
| 1063 | * conservative settings (async, no tagged |
| 1064 | * queuing etc.) and machine dependent device |
| 1065 | * property is set. |
| 1066 | */ |
| 1067 | usetd = prop_dictionary_get( |
| 1068 | device_properties(ahc->sc_dev), |
| 1069 | "aic7xxx-use-target-defaults" ); |
| 1070 | if (usetd != NULL) { |
| 1071 | KASSERT(prop_object_type(usetd) == |
| 1072 | PROP_TYPE_BOOL); |
| 1073 | if (prop_bool_true(usetd)) |
| 1074 | ahc->flags |= AHC_USETARGETDEFAULTS; |
| 1075 | } |
| 1076 | ahc->flags |= AHC_BIOS_ENABLED; |
| 1077 | } else { |
| 1078 | /* |
| 1079 | * Assume only one connector and always turn |
| 1080 | * on termination. |
| 1081 | */ |
| 1082 | our_id = 0x07; |
| 1083 | sxfrctl1 = STPWEN; |
| 1084 | } |
| 1085 | ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); |
| 1086 | |
| 1087 | ahc->our_id = our_id; |
| 1088 | } |
| 1089 | |
| 1090 | /* |
| 1091 | * Take a look to see if we have external SRAM. |
| 1092 | * We currently do not attempt to use SRAM that is |
| 1093 | * shared among multiple controllers. |
| 1094 | */ |
| 1095 | ahc_probe_ext_scbram(ahc); |
| 1096 | |
| 1097 | /* |
| 1098 | * Record our termination setting for the |
| 1099 | * generic initialization routine. |
| 1100 | */ |
| 1101 | if ((sxfrctl1 & STPWEN) != 0) |
| 1102 | ahc->flags |= AHC_TERM_ENB_A; |
| 1103 | |
| 1104 | if (ahc_init(ahc)) |
| 1105 | goto error_out; |
| 1106 | |
| 1107 | ahc_attach(ahc); |
| 1108 | |
| 1109 | return; |
| 1110 | |
| 1111 | error_out: |
| 1112 | ahc_free(ahc); |
| 1113 | return; |
| 1114 | } |
| 1115 | |
| 1116 | CFATTACH_DECL_NEW(ahc_pci, sizeof(struct ahc_softc), |
| 1117 | ahc_pci_probe, ahc_pci_attach, NULL, NULL); |
| 1118 | |
| 1119 | static int |
| 1120 | ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, |
| 1121 | uint16_t subdevice, uint16_t subvendor) |
| 1122 | { |
| 1123 | int result; |
| 1124 | |
| 1125 | /* Default to invalid. */ |
| 1126 | result = 0; |
| 1127 | if (vendor == 0x9005 |
| 1128 | && subvendor == 0x9005 |
| 1129 | && subdevice != device |
| 1130 | && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { |
| 1131 | |
| 1132 | switch (SUBID_9005_TYPE(subdevice)) { |
| 1133 | case SUBID_9005_TYPE_MB: |
| 1134 | break; |
| 1135 | case SUBID_9005_TYPE_CARD: |
| 1136 | case SUBID_9005_TYPE_LCCARD: |
| 1137 | /* |
| 1138 | * Currently only trust Adaptec cards to |
| 1139 | * get the sub device info correct. |
| 1140 | */ |
| 1141 | if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) |
| 1142 | result = 1; |
| 1143 | break; |
| 1144 | case SUBID_9005_TYPE_RAID: |
| 1145 | break; |
| 1146 | default: |
| 1147 | break; |
| 1148 | } |
| 1149 | } |
| 1150 | return (result); |
| 1151 | } |
| 1152 | |
| 1153 | |
| 1154 | /* |
| 1155 | * Test for the presense of external sram in an |
| 1156 | * "unshared" configuration. |
| 1157 | */ |
| 1158 | static int |
| 1159 | ahc_ext_scbram_present(struct ahc_softc *ahc) |
| 1160 | { |
| 1161 | u_int chip; |
| 1162 | int ramps; |
| 1163 | int single_user; |
| 1164 | uint32_t devconfig; |
| 1165 | |
| 1166 | chip = ahc->chip & AHC_CHIPID_MASK; |
| 1167 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); |
| 1168 | single_user = (devconfig & MPORTMODE) != 0; |
| 1169 | |
| 1170 | if ((ahc->features & AHC_ULTRA2) != 0) |
| 1171 | ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; |
| 1172 | else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) |
| 1173 | /* |
| 1174 | * External SCBRAM arbitration is flakey |
| 1175 | * on these chips. Unfortunately this means |
| 1176 | * we don't use the extra SCB ram space on the |
| 1177 | * 3940AUW. |
| 1178 | */ |
| 1179 | ramps = 0; |
| 1180 | else if (chip >= AHC_AIC7870) |
| 1181 | ramps = (devconfig & RAMPSM) != 0; |
| 1182 | else |
| 1183 | ramps = 0; |
| 1184 | |
| 1185 | if (ramps && single_user) |
| 1186 | return (1); |
| 1187 | return (0); |
| 1188 | } |
| 1189 | |
| 1190 | /* |
| 1191 | * Enable external scbram. |
| 1192 | */ |
| 1193 | static void |
| 1194 | ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, |
| 1195 | int fast, int large) |
| 1196 | { |
| 1197 | uint32_t devconfig; |
| 1198 | |
| 1199 | if (ahc->features & AHC_MULTI_FUNC) { |
| 1200 | /* |
| 1201 | * Set the SCB Base addr (highest address bit) |
| 1202 | * depending on which channel we are. |
| 1203 | */ |
| 1204 | ahc_outb(ahc, SCBBADDR, ahc->bd->func); |
| 1205 | } |
| 1206 | |
| 1207 | ahc->flags &= ~AHC_LSCBS_ENABLED; |
| 1208 | if (large) |
| 1209 | ahc->flags |= AHC_LSCBS_ENABLED; |
| 1210 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); |
| 1211 | if ((ahc->features & AHC_ULTRA2) != 0) { |
| 1212 | u_int dscommand0; |
| 1213 | |
| 1214 | dscommand0 = ahc_inb(ahc, DSCOMMAND0); |
| 1215 | if (enable) |
| 1216 | dscommand0 &= ~INTSCBRAMSEL; |
| 1217 | else |
| 1218 | dscommand0 |= INTSCBRAMSEL; |
| 1219 | if (large) |
| 1220 | dscommand0 &= ~USCBSIZE32; |
| 1221 | else |
| 1222 | dscommand0 |= USCBSIZE32; |
| 1223 | ahc_outb(ahc, DSCOMMAND0, dscommand0); |
| 1224 | } else { |
| 1225 | if (fast) |
| 1226 | devconfig &= ~EXTSCBTIME; |
| 1227 | else |
| 1228 | devconfig |= EXTSCBTIME; |
| 1229 | if (enable) |
| 1230 | devconfig &= ~SCBRAMSEL; |
| 1231 | else |
| 1232 | devconfig |= SCBRAMSEL; |
| 1233 | if (large) |
| 1234 | devconfig &= ~SCBSIZE32; |
| 1235 | else |
| 1236 | devconfig |= SCBSIZE32; |
| 1237 | } |
| 1238 | if (pcheck) |
| 1239 | devconfig |= EXTSCBPEN; |
| 1240 | else |
| 1241 | devconfig &= ~EXTSCBPEN; |
| 1242 | |
| 1243 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); |
| 1244 | } |
| 1245 | |
| 1246 | /* |
| 1247 | * Take a look to see if we have external SRAM. |
| 1248 | * We currently do not attempt to use SRAM that is |
| 1249 | * shared among multiple controllers. |
| 1250 | */ |
| 1251 | static void |
| 1252 | ahc_probe_ext_scbram(struct ahc_softc *ahc) |
| 1253 | { |
| 1254 | int num_scbs; |
| 1255 | int test_num_scbs; |
| 1256 | int enable; |
| 1257 | int pcheck; |
| 1258 | int fast; |
| 1259 | int large; |
| 1260 | |
| 1261 | enable = FALSE; |
| 1262 | pcheck = FALSE; |
| 1263 | fast = FALSE; |
| 1264 | large = FALSE; |
| 1265 | num_scbs = 0; |
| 1266 | |
| 1267 | if (ahc_ext_scbram_present(ahc) == 0) |
| 1268 | goto done; |
| 1269 | |
| 1270 | /* |
| 1271 | * Probe for the best parameters to use. |
| 1272 | */ |
| 1273 | ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); |
| 1274 | num_scbs = ahc_probe_scbs(ahc); |
| 1275 | if (num_scbs == 0) { |
| 1276 | /* The SRAM wasn't really present. */ |
| 1277 | goto done; |
| 1278 | } |
| 1279 | enable = TRUE; |
| 1280 | |
| 1281 | /* |
| 1282 | * Clear any outstanding parity error |
| 1283 | * and ensure that parity error reporting |
| 1284 | * is enabled. |
| 1285 | */ |
| 1286 | ahc_outb(ahc, SEQCTL, 0); |
| 1287 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1288 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1289 | |
| 1290 | /* Now see if we can do parity */ |
| 1291 | ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); |
| 1292 | num_scbs = ahc_probe_scbs(ahc); |
| 1293 | if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 |
| 1294 | || (ahc_inb(ahc, ERROR) & MPARERR) == 0) |
| 1295 | pcheck = TRUE; |
| 1296 | |
| 1297 | /* Clear any resulting parity error */ |
| 1298 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1299 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1300 | |
| 1301 | /* Now see if we can do fast timing */ |
| 1302 | ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); |
| 1303 | test_num_scbs = ahc_probe_scbs(ahc); |
| 1304 | if (test_num_scbs == num_scbs |
| 1305 | && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 |
| 1306 | || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) |
| 1307 | fast = TRUE; |
| 1308 | |
| 1309 | /* |
| 1310 | * See if we can use large SCBs and still maintain |
| 1311 | * the same overall count of SCBs. |
| 1312 | */ |
| 1313 | if ((ahc->features & AHC_LARGE_SCBS) != 0) { |
| 1314 | ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); |
| 1315 | test_num_scbs = ahc_probe_scbs(ahc); |
| 1316 | if (test_num_scbs >= num_scbs) { |
| 1317 | large = TRUE; |
| 1318 | num_scbs = test_num_scbs; |
| 1319 | if (num_scbs >= 64) { |
| 1320 | /* |
| 1321 | * We have enough space to move the |
| 1322 | * "busy targets table" into SCB space |
| 1323 | * and make it qualify all the way to the |
| 1324 | * lun level. |
| 1325 | */ |
| 1326 | ahc->flags |= AHC_SCB_BTT; |
| 1327 | } |
| 1328 | } |
| 1329 | } |
| 1330 | done: |
| 1331 | /* |
| 1332 | * Disable parity error reporting until we |
| 1333 | * can load instruction ram. |
| 1334 | */ |
| 1335 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); |
| 1336 | /* Clear any latched parity error */ |
| 1337 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1338 | ahc_outb(ahc, CLRINT, CLRBRKADRINT); |
| 1339 | if (1/*bootverbose*/ && enable) { |
| 1340 | printf("%s: External SRAM, %s access%s, %dbytes/SCB\n" , |
| 1341 | ahc_name(ahc), fast ? "fast" : "slow" , |
| 1342 | pcheck ? ", parity checking enabled" : "" , |
| 1343 | large ? 64 : 32); |
| 1344 | } |
| 1345 | ahc_scbram_config(ahc, enable, pcheck, fast, large); |
| 1346 | } |
| 1347 | |
| 1348 | #if 0 |
| 1349 | /* |
| 1350 | * Perform some simple tests that should catch situations where |
| 1351 | * our registers are invalidly mapped. |
| 1352 | */ |
| 1353 | static int |
| 1354 | ahc_pci_test_register_access(struct ahc_softc *ahc) |
| 1355 | { |
| 1356 | int error; |
| 1357 | u_int status1; |
| 1358 | uint32_t cmd; |
| 1359 | uint8_t hcntrl; |
| 1360 | |
| 1361 | error = EIO; |
| 1362 | |
| 1363 | /* |
| 1364 | * Enable PCI error interrupt status, but suppress NMIs |
| 1365 | * generated by SERR raised due to target aborts. |
| 1366 | */ |
| 1367 | cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); |
| 1368 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, |
| 1369 | cmd & ~PCIM_CMD_SERRESPEN); |
| 1370 | |
| 1371 | /* |
| 1372 | * First a simple test to see if any |
| 1373 | * registers can be read. Reading |
| 1374 | * HCNTRL has no side effects and has |
| 1375 | * at least one bit that is guaranteed to |
| 1376 | * be zero so it is a good register to |
| 1377 | * use for this test. |
| 1378 | */ |
| 1379 | hcntrl = ahc_inb(ahc, HCNTRL); |
| 1380 | if (hcntrl == 0xFF) |
| 1381 | goto fail; |
| 1382 | |
| 1383 | /* |
| 1384 | * Next create a situation where write combining |
| 1385 | * or read prefetching could be initiated by the |
| 1386 | * CPU or host bridge. Our device does not support |
| 1387 | * either, so look for data corruption and/or flagged |
| 1388 | * PCI errors. |
| 1389 | */ |
| 1390 | ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); |
| 1391 | while (ahc_is_paused(ahc) == 0) |
| 1392 | ; |
| 1393 | ahc_outb(ahc, SEQCTL, PERRORDIS); |
| 1394 | ahc_outb(ahc, SCBPTR, 0); |
| 1395 | ahc_outl(ahc, SCB_BASE, 0x5aa555aa); |
| 1396 | if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) |
| 1397 | goto fail; |
| 1398 | |
| 1399 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, |
| 1400 | PCI_COMMAND_STATUS_REG + 1); |
| 1401 | if ((status1 & STA) != 0) |
| 1402 | goto fail; |
| 1403 | |
| 1404 | error = 0; |
| 1405 | |
| 1406 | fail: |
| 1407 | /* Silently clear any latched errors. */ |
| 1408 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, |
| 1409 | PCI_COMMAND_STATUS_REG + 1); |
| 1410 | ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, |
| 1411 | status1, /*bytes*/1); |
| 1412 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1413 | ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); |
| 1414 | ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); |
| 1415 | return (error); |
| 1416 | } |
| 1417 | #endif |
| 1418 | |
| 1419 | static void |
| 1420 | ahc_pci_intr(struct ahc_softc *ahc) |
| 1421 | { |
| 1422 | u_int error; |
| 1423 | u_int status1; |
| 1424 | |
| 1425 | error = ahc_inb(ahc, ERROR); |
| 1426 | if ((error & PCIERRSTAT) == 0) |
| 1427 | return; |
| 1428 | |
| 1429 | status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, |
| 1430 | PCI_COMMAND_STATUS_REG); |
| 1431 | |
| 1432 | printf("%s: PCI error Interrupt at seqaddr = 0x%x\n" , |
| 1433 | ahc_name(ahc), |
| 1434 | ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); |
| 1435 | |
| 1436 | if (status1 & DPE) { |
| 1437 | printf("%s: Data Parity Error Detected during address " |
| 1438 | "or write data phase\n" , ahc_name(ahc)); |
| 1439 | } |
| 1440 | if (status1 & SSE) { |
| 1441 | printf("%s: Signal System Error Detected\n" , ahc_name(ahc)); |
| 1442 | } |
| 1443 | if (status1 & RMA) { |
| 1444 | printf("%s: Received a Master Abort\n" , ahc_name(ahc)); |
| 1445 | } |
| 1446 | if (status1 & RTA) { |
| 1447 | printf("%s: Received a Target Abort\n" , ahc_name(ahc)); |
| 1448 | } |
| 1449 | if (status1 & STA) { |
| 1450 | printf("%s: Signaled a Target Abort\n" , ahc_name(ahc)); |
| 1451 | } |
| 1452 | if (status1 & DPR) { |
| 1453 | printf("%s: Data Parity Error has been reported via PERR#\n" , |
| 1454 | ahc_name(ahc)); |
| 1455 | } |
| 1456 | |
| 1457 | /* Clear latched errors. */ |
| 1458 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, |
| 1459 | status1); |
| 1460 | |
| 1461 | if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { |
| 1462 | printf("%s: Latched PCIERR interrupt with " |
| 1463 | "no status bits set\n" , ahc_name(ahc)); |
| 1464 | } else { |
| 1465 | ahc_outb(ahc, CLRINT, CLRPARERR); |
| 1466 | } |
| 1467 | |
| 1468 | ahc_unpause(ahc); |
| 1469 | } |
| 1470 | |
| 1471 | static int |
| 1472 | ahc_aic785X_setup(struct ahc_softc *ahc) |
| 1473 | { |
| 1474 | uint8_t rev; |
| 1475 | |
| 1476 | ahc->channel = 'A'; |
| 1477 | ahc->chip = AHC_AIC7850; |
| 1478 | ahc->features = AHC_AIC7850_FE; |
| 1479 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 1480 | rev = PCI_REVISION(ahc->bd->class); |
| 1481 | if (rev >= 1) |
| 1482 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 1483 | return (0); |
| 1484 | } |
| 1485 | |
| 1486 | static int |
| 1487 | ahc_aic7860_setup(struct ahc_softc *ahc) |
| 1488 | { |
| 1489 | uint8_t rev; |
| 1490 | |
| 1491 | ahc->channel = 'A'; |
| 1492 | ahc->chip = AHC_AIC7860; |
| 1493 | ahc->features = AHC_AIC7860_FE; |
| 1494 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 1495 | rev = PCI_REVISION(ahc->bd->class); |
| 1496 | if (rev >= 1) |
| 1497 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 1498 | return (0); |
| 1499 | } |
| 1500 | |
| 1501 | static int |
| 1502 | ahc_apa1480_setup(struct ahc_softc *ahc) |
| 1503 | { |
| 1504 | int error; |
| 1505 | |
| 1506 | error = ahc_aic7860_setup(ahc); |
| 1507 | if (error != 0) |
| 1508 | return (error); |
| 1509 | ahc->features |= AHC_REMOVABLE; |
| 1510 | return (0); |
| 1511 | } |
| 1512 | |
| 1513 | static int |
| 1514 | ahc_aic7870_setup(struct ahc_softc *ahc) |
| 1515 | { |
| 1516 | |
| 1517 | ahc->channel = 'A'; |
| 1518 | ahc->chip = AHC_AIC7870; |
| 1519 | ahc->features = AHC_AIC7870_FE; |
| 1520 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 1521 | return (0); |
| 1522 | } |
| 1523 | |
| 1524 | static int |
| 1525 | ahc_aha394X_setup(struct ahc_softc *ahc) |
| 1526 | { |
| 1527 | int error; |
| 1528 | |
| 1529 | error = ahc_aic7870_setup(ahc); |
| 1530 | if (error == 0) |
| 1531 | error = ahc_aha394XX_setup(ahc); |
| 1532 | return (error); |
| 1533 | } |
| 1534 | |
| 1535 | static int |
| 1536 | ahc_aha398X_setup(struct ahc_softc *ahc) |
| 1537 | { |
| 1538 | int error; |
| 1539 | |
| 1540 | error = ahc_aic7870_setup(ahc); |
| 1541 | if (error == 0) |
| 1542 | error = ahc_aha398XX_setup(ahc); |
| 1543 | return (error); |
| 1544 | } |
| 1545 | |
| 1546 | static int |
| 1547 | ahc_aha494X_setup(struct ahc_softc *ahc) |
| 1548 | { |
| 1549 | int error; |
| 1550 | |
| 1551 | error = ahc_aic7870_setup(ahc); |
| 1552 | if (error == 0) |
| 1553 | error = ahc_aha494XX_setup(ahc); |
| 1554 | return (error); |
| 1555 | } |
| 1556 | |
| 1557 | static int |
| 1558 | ahc_aic7880_setup(struct ahc_softc *ahc) |
| 1559 | { |
| 1560 | uint8_t rev; |
| 1561 | |
| 1562 | ahc->channel = 'A'; |
| 1563 | ahc->chip = AHC_AIC7880; |
| 1564 | ahc->features = AHC_AIC7880_FE; |
| 1565 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG; |
| 1566 | rev = PCI_REVISION(ahc->bd->class); |
| 1567 | if (rev >= 1) { |
| 1568 | ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; |
| 1569 | } else { |
| 1570 | ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; |
| 1571 | } |
| 1572 | return (0); |
| 1573 | } |
| 1574 | |
| 1575 | static int |
| 1576 | ahc_aha2940Pro_setup(struct ahc_softc *ahc) |
| 1577 | { |
| 1578 | |
| 1579 | ahc->flags |= AHC_INT50_SPEEDFLEX; |
| 1580 | return (ahc_aic7880_setup(ahc)); |
| 1581 | } |
| 1582 | |
| 1583 | static int |
| 1584 | ahc_aha394XU_setup(struct ahc_softc *ahc) |
| 1585 | { |
| 1586 | int error; |
| 1587 | |
| 1588 | error = ahc_aic7880_setup(ahc); |
| 1589 | if (error == 0) |
| 1590 | error = ahc_aha394XX_setup(ahc); |
| 1591 | return (error); |
| 1592 | } |
| 1593 | |
| 1594 | static int |
| 1595 | ahc_aha398XU_setup(struct ahc_softc *ahc) |
| 1596 | { |
| 1597 | int error; |
| 1598 | |
| 1599 | error = ahc_aic7880_setup(ahc); |
| 1600 | if (error == 0) |
| 1601 | error = ahc_aha398XX_setup(ahc); |
| 1602 | return (error); |
| 1603 | } |
| 1604 | |
| 1605 | static int |
| 1606 | ahc_aic7890_setup(struct ahc_softc *ahc) |
| 1607 | { |
| 1608 | uint8_t rev; |
| 1609 | |
| 1610 | ahc->channel = 'A'; |
| 1611 | ahc->chip = AHC_AIC7890; |
| 1612 | ahc->features = AHC_AIC7890_FE; |
| 1613 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1614 | rev = PCI_REVISION(ahc->bd->class); |
| 1615 | if (rev == 0) |
| 1616 | ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; |
| 1617 | return (0); |
| 1618 | } |
| 1619 | |
| 1620 | static int |
| 1621 | ahc_aic7892_setup(struct ahc_softc *ahc) |
| 1622 | { |
| 1623 | |
| 1624 | ahc->channel = 'A'; |
| 1625 | ahc->chip = AHC_AIC7892; |
| 1626 | ahc->features = AHC_AIC7892_FE; |
| 1627 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1628 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
| 1629 | return (0); |
| 1630 | } |
| 1631 | |
| 1632 | static int |
| 1633 | ahc_aic7895_setup(struct ahc_softc *ahc) |
| 1634 | { |
| 1635 | uint8_t rev; |
| 1636 | |
| 1637 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
| 1638 | /* |
| 1639 | * The 'C' revision of the aic7895 has a few additional features. |
| 1640 | */ |
| 1641 | rev = PCI_REVISION(ahc->bd->class); |
| 1642 | if (rev >= 4) { |
| 1643 | ahc->chip = AHC_AIC7895C; |
| 1644 | ahc->features = AHC_AIC7895C_FE; |
| 1645 | } else { |
| 1646 | u_int command; |
| 1647 | |
| 1648 | ahc->chip = AHC_AIC7895; |
| 1649 | ahc->features = AHC_AIC7895_FE; |
| 1650 | |
| 1651 | /* |
| 1652 | * The BIOS disables the use of MWI transactions |
| 1653 | * since it does not have the MWI bug work around |
| 1654 | * we have. Disabling MWI reduces performance, so |
| 1655 | * turn it on again. |
| 1656 | */ |
| 1657 | command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, |
| 1658 | PCI_COMMAND_STATUS_REG); |
| 1659 | command |= PCI_COMMAND_INVALIDATE_ENABLE; |
| 1660 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, |
| 1661 | PCI_COMMAND_STATUS_REG, command); |
| 1662 | ahc->bugs |= AHC_PCI_MWI_BUG; |
| 1663 | } |
| 1664 | /* |
| 1665 | * XXX Does CACHETHEN really not work??? What about PCI retry? |
| 1666 | * on C level chips. Need to test, but for now, play it safe. |
| 1667 | */ |
| 1668 | ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG |
| 1669 | | AHC_CACHETHEN_BUG; |
| 1670 | |
| 1671 | #if 0 |
| 1672 | uint32_t devconfig; |
| 1673 | |
| 1674 | /* |
| 1675 | * Cachesize must also be zero due to stray DAC |
| 1676 | * problem when sitting behind some bridges. |
| 1677 | */ |
| 1678 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); |
| 1679 | devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); |
| 1680 | devconfig |= MRDCEN; |
| 1681 | pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); |
| 1682 | #endif |
| 1683 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1684 | return (0); |
| 1685 | } |
| 1686 | |
| 1687 | static int |
| 1688 | ahc_aic7896_setup(struct ahc_softc *ahc) |
| 1689 | { |
| 1690 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
| 1691 | ahc->chip = AHC_AIC7896; |
| 1692 | ahc->features = AHC_AIC7896_FE; |
| 1693 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1694 | ahc->bugs |= AHC_CACHETHEN_DIS_BUG; |
| 1695 | return (0); |
| 1696 | } |
| 1697 | |
| 1698 | static int |
| 1699 | ahc_aic7899_setup(struct ahc_softc *ahc) |
| 1700 | { |
| 1701 | ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; |
| 1702 | ahc->chip = AHC_AIC7899; |
| 1703 | ahc->features = AHC_AIC7899_FE; |
| 1704 | ahc->flags |= AHC_NEWEEPROM_FMT; |
| 1705 | ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; |
| 1706 | return (0); |
| 1707 | } |
| 1708 | |
| 1709 | static int |
| 1710 | ahc_aha29160C_setup(struct ahc_softc *ahc) |
| 1711 | { |
| 1712 | int error; |
| 1713 | |
| 1714 | error = ahc_aic7899_setup(ahc); |
| 1715 | if (error != 0) |
| 1716 | return (error); |
| 1717 | ahc->features |= AHC_REMOVABLE; |
| 1718 | return (0); |
| 1719 | } |
| 1720 | |
| 1721 | static int |
| 1722 | ahc_raid_setup(struct ahc_softc *ahc) |
| 1723 | { |
| 1724 | aprint_normal_dev(ahc->sc_dev, "RAID functionality unsupported\n" ); |
| 1725 | return (ENXIO); |
| 1726 | } |
| 1727 | |
| 1728 | static int |
| 1729 | ahc_aha394XX_setup(struct ahc_softc *ahc) |
| 1730 | { |
| 1731 | |
| 1732 | switch (ahc->bd->dev) { |
| 1733 | case AHC_394X_SLOT_CHANNEL_A: |
| 1734 | ahc->channel = 'A'; |
| 1735 | break; |
| 1736 | case AHC_394X_SLOT_CHANNEL_B: |
| 1737 | ahc->channel = 'B'; |
| 1738 | break; |
| 1739 | default: |
| 1740 | printf("adapter at unexpected slot %d\n" |
| 1741 | "unable to map to a channel\n" , |
| 1742 | ahc->bd->dev); |
| 1743 | ahc->channel = 'A'; |
| 1744 | } |
| 1745 | return (0); |
| 1746 | } |
| 1747 | |
| 1748 | static int |
| 1749 | ahc_aha398XX_setup(struct ahc_softc *ahc) |
| 1750 | { |
| 1751 | |
| 1752 | switch (ahc->bd->dev) { |
| 1753 | case AHC_398X_SLOT_CHANNEL_A: |
| 1754 | ahc->channel = 'A'; |
| 1755 | break; |
| 1756 | case AHC_398X_SLOT_CHANNEL_B: |
| 1757 | ahc->channel = 'B'; |
| 1758 | break; |
| 1759 | case AHC_398X_SLOT_CHANNEL_C: |
| 1760 | ahc->channel = 'C'; |
| 1761 | break; |
| 1762 | default: |
| 1763 | printf("adapter at unexpected slot %d\n" |
| 1764 | "unable to map to a channel\n" , |
| 1765 | ahc->bd->dev); |
| 1766 | ahc->channel = 'A'; |
| 1767 | break; |
| 1768 | } |
| 1769 | ahc->flags |= AHC_LARGE_SEEPROM; |
| 1770 | return (0); |
| 1771 | } |
| 1772 | |
| 1773 | static int |
| 1774 | ahc_aha494XX_setup(struct ahc_softc *ahc) |
| 1775 | { |
| 1776 | |
| 1777 | switch (ahc->bd->dev) { |
| 1778 | case AHC_494X_SLOT_CHANNEL_A: |
| 1779 | ahc->channel = 'A'; |
| 1780 | break; |
| 1781 | case AHC_494X_SLOT_CHANNEL_B: |
| 1782 | ahc->channel = 'B'; |
| 1783 | break; |
| 1784 | case AHC_494X_SLOT_CHANNEL_C: |
| 1785 | ahc->channel = 'C'; |
| 1786 | break; |
| 1787 | case AHC_494X_SLOT_CHANNEL_D: |
| 1788 | ahc->channel = 'D'; |
| 1789 | break; |
| 1790 | default: |
| 1791 | printf("adapter at unexpected slot %d\n" |
| 1792 | "unable to map to a channel\n" , |
| 1793 | ahc->bd->dev); |
| 1794 | ahc->channel = 'A'; |
| 1795 | } |
| 1796 | ahc->flags |= AHC_LARGE_SEEPROM; |
| 1797 | return (0); |
| 1798 | } |
| 1799 | |