| 1 | /* $NetBSD: if_bgereg.h,v 1.91 2015/05/17 12:06:26 msaitoh Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 2001 Wind River Systems |
| 4 | * Copyright (c) 1997, 1998, 1999, 2001 |
| 5 | * Bill Paul <wpaul@windriver.com>. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. All advertising materials mentioning features or use of this software |
| 16 | * must display the following acknowledgement: |
| 17 | * This product includes software developed by Bill Paul. |
| 18 | * 4. Neither the name of the author nor the names of any co-contributors |
| 19 | * may be used to endorse or promote products derived from this software |
| 20 | * without specific prior written permission. |
| 21 | * |
| 22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 32 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | * |
| 34 | * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * BCM570x memory map. The internal memory layout varies somewhat |
| 39 | * depending on whether or not we have external SSRAM attached. |
| 40 | * The BCM5700 can have up to 16MB of external memory. The BCM5701 |
| 41 | * is apparently not designed to use external SSRAM. The mappings |
| 42 | * up to the first 4 send rings are the same for both internal and |
| 43 | * external memory configurations. Note that mini RX ring space is |
| 44 | * only available with external SSRAM configurations, which means |
| 45 | * the mini RX ring is not supported on the BCM5701. |
| 46 | * |
| 47 | * The NIC's memory can be accessed by the host in one of 3 ways: |
| 48 | * |
| 49 | * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA |
| 50 | * registers in PCI config space can be used to read any 32-bit |
| 51 | * address within the NIC's memory. |
| 52 | * |
| 53 | * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config |
| 54 | * space can be used in conjunction with the memory window in the |
| 55 | * device register space at offset 0x8000 to read any 32K chunk |
| 56 | * of NIC memory. |
| 57 | * |
| 58 | * 3) Flat mode. If the 'flat mode' bit in the PCI state register is |
| 59 | * set, the device I/O mapping consumes 32MB of host address space, |
| 60 | * allowing all of the registers and internal NIC memory to be |
| 61 | * accessed directly. NIC memory addresses are offset by 0x01000000. |
| 62 | * Flat mode consumes so much host address space that it is not |
| 63 | * recommended. |
| 64 | */ |
| 65 | #define BGE_PAGE_ZERO 0x00000000 |
| 66 | #define BGE_PAGE_ZERO_END 0x000000FF |
| 67 | #define BGE_SEND_RING_RCB 0x00000100 |
| 68 | #define BGE_SEND_RING_RCB_END 0x000001FF |
| 69 | #define BGE_RX_RETURN_RING_RCB 0x00000200 |
| 70 | #define BGE_RX_RETURN_RING_RCB_END 0x000002FF |
| 71 | #define BGE_STATS_BLOCK 0x00000300 |
| 72 | #define BGE_STATS_BLOCK_END 0x00000AFF |
| 73 | #define BGE_STATUS_BLOCK 0x00000B00 |
| 74 | #define BGE_STATUS_BLOCK_END 0x00000B4F |
| 75 | #define BGE_SRAM_FW_MB 0x00000B50 |
| 76 | #define BGE_SRAM_DATA_SIG 0x00000B54 |
| 77 | #define BGE_SRAM_DATA_CFG 0x00000B58 |
| 78 | #define BGE_SRAM_DATA_VER 0x00000B5C |
| 79 | #define BGE_SRAM_FW_CMD_MB 0x00000B78 |
| 80 | #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C |
| 81 | #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 |
| 82 | #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 |
| 83 | #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 |
| 84 | #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 |
| 85 | #define BGE_SRAM_DATA_CFG_2 0x00000D38 |
| 86 | #define BGE_SRAM_DATA_CFG_3 0x00000D3C |
| 87 | #define BGE_SRAM_DATA_CFG_4 0x00000D60 |
| 88 | #define BGE_SRAM_DATA_CFG_5 0x00000E0C |
| 89 | #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF |
| 90 | #define BGE_UNMAPPED 0x00001000 |
| 91 | #define BGE_UNMAPPED_END 0x00001FFF |
| 92 | #define BGE_DMA_DESCRIPTORS 0x00002000 |
| 93 | #define BGE_DMA_DESCRIPTORS_END 0x00003FFF |
| 94 | #define BGE_SEND_RING_5717 0x00004000 |
| 95 | #define BGE_SEND_RING_1_TO_4 0x00004000 |
| 96 | #define BGE_SEND_RING_1_TO_4_END 0x00005FFF |
| 97 | |
| 98 | /* Firmware interface */ |
| 99 | #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ |
| 100 | |
| 101 | #define BGE_FW_CMD_DRV_ALIVE 0x00000001 |
| 102 | #define BGE_FW_CMD_PAUSE 0x00000002 |
| 103 | #define BGE_FW_CMD_DRV_ALIVE3 0x0000000e |
| 104 | |
| 105 | #define BGE_FW_HB_TIMEOUT_SEC 3 |
| 106 | |
| 107 | #define BGE_FW_DRV_STATE_START 0x00000001 |
| 108 | #define BGE_FW_DRV_STATE_START_DONE 0x80000001 |
| 109 | #define BGE_FW_DRV_STATE_UNLOAD 0x00000002 |
| 110 | #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 |
| 111 | #define BGE_FW_DRV_STATE_SUSPEND 0x00000004 |
| 112 | |
| 113 | /* SRAM data version */ |
| 114 | #define BGE_SRAM_DATA_VER_SHIFT 16 |
| 115 | |
| 116 | /* Mappings for internal memory configuration */ |
| 117 | #define BGE_STD_RX_RINGS 0x00006000 |
| 118 | #define BGE_STD_RX_RINGS_END 0x00006FFF |
| 119 | #define BGE_JUMBO_RX_RINGS 0x00007000 |
| 120 | #define BGE_JUMBO_RX_RINGS_END 0x00007FFF |
| 121 | #define BGE_BUFFPOOL_1 0x00008000 |
| 122 | #define BGE_BUFFPOOL_1_END 0x0000FFFF |
| 123 | #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ |
| 124 | #define BGE_BUFFPOOL_2_END 0x00017FFF |
| 125 | #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ |
| 126 | #define BGE_BUFFPOOL_3_END 0x0001FFFF |
| 127 | #define BGE_STD_RX_RINGS_5717 0x00040000 |
| 128 | #define BGE_JUMBO_RX_RINGS_5717 0x00044400 |
| 129 | |
| 130 | /* Mappings for external SSRAM configurations */ |
| 131 | #define BGE_SEND_RING_5_TO_6 0x00006000 |
| 132 | #define BGE_SEND_RING_5_TO_6_END 0x00006FFF |
| 133 | #define BGE_SEND_RING_7_TO_8 0x00007000 |
| 134 | #define BGE_SEND_RING_7_TO_8_END 0x00007FFF |
| 135 | #define BGE_SEND_RING_9_TO_16 0x00008000 |
| 136 | #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF |
| 137 | #define BGE_EXT_STD_RX_RINGS 0x0000C000 |
| 138 | #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF |
| 139 | #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 |
| 140 | #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF |
| 141 | #define BGE_MINI_RX_RINGS 0x0000E000 |
| 142 | #define BGE_MINI_RX_RINGS_END 0x0000FFFF |
| 143 | #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ |
| 144 | #define BGE_AVAIL_REGION1_END 0x00017FFF |
| 145 | #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ |
| 146 | #define BGE_AVAIL_REGION2_END 0x0001FFFF |
| 147 | #define BGE_EXT_SSRAM 0x00020000 |
| 148 | #define BGE_EXT_SSRAM_END 0x000FFFFF |
| 149 | |
| 150 | |
| 151 | /* |
| 152 | * BCM570x register offsets. These are memory mapped registers |
| 153 | * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. |
| 154 | * Each register must be accessed using 32 bit operations. |
| 155 | * |
| 156 | * All registers are accessed through a 32K shared memory block. |
| 157 | * The first group of registers are actually copies of the PCI |
| 158 | * configuration space registers. |
| 159 | */ |
| 160 | |
| 161 | /* |
| 162 | * PCI registers defined in the PCI 2.2 spec. |
| 163 | */ |
| 164 | #define BGE_PCI_VID 0x00 |
| 165 | #define BGE_PCI_DID 0x02 |
| 166 | #define BGE_PCI_CMD 0x04 |
| 167 | #define BGE_PCI_STS 0x06 |
| 168 | #define BGE_PCI_REV 0x08 |
| 169 | #define BGE_PCI_CLASS 0x09 |
| 170 | #define BGE_PCI_CACHESZ 0x0C |
| 171 | #define BGE_PCI_LATTIMER 0x0D |
| 172 | #define BGE_PCI_HDRTYPE 0x0E |
| 173 | #define BGE_PCI_BIST 0x0F |
| 174 | #define BGE_PCI_BAR0 0x10 |
| 175 | #define BGE_PCI_BAR1 0x14 |
| 176 | #define BGE_PCI_BAR2 0x18 |
| 177 | #define BGE_PCI_SUBSYS 0x2C |
| 178 | #define BGE_PCI_SUBVID 0x2E |
| 179 | #define BGE_PCI_ROMBASE 0x30 |
| 180 | #define BGE_PCI_CAPPTR 0x34 |
| 181 | #define BGE_PCI_INTLINE 0x3C |
| 182 | #define BGE_PCI_INTPIN 0x3D |
| 183 | #define BGE_PCI_MINGNT 0x3E |
| 184 | #define BGE_PCI_MAXLAT 0x3F |
| 185 | #define BGE_PCI_PCIXCAP 0x40 |
| 186 | #define BGE_PCI_NEXTPTR_PM 0x41 |
| 187 | #define BGE_PCIX_CMD 0x42 |
| 188 | #define BGE_PCIX_STS 0x44 |
| 189 | #define BGE_PCI_PWRMGMT_CAPID 0x48 |
| 190 | #define BGE_PCI_NEXTPTR_VPD 0x49 |
| 191 | #define BGE_PCI_PWRMGMT_CAPS 0x4A |
| 192 | #define BGE_PCI_PWRMGMT_CMD 0x4C |
| 193 | #define BGE_PCI_PWRMGMT_STS 0x4D |
| 194 | #define BGE_PCI_PWRMGMT_DATA 0x4F |
| 195 | #define BGE_PCI_VPD_CAPID 0x50 |
| 196 | #define BGE_PCI_NEXTPTR_MSI 0x51 |
| 197 | #define BGE_PCI_VPD_ADDR 0x52 |
| 198 | #define BGE_PCI_VPD_DATA 0x54 |
| 199 | #define BGE_PCI_MSI_CAPID 0x58 |
| 200 | #define BGE_PCI_NEXTPTR_NONE 0x59 |
| 201 | #define BGE_PCI_MSI_CTL 0x5A |
| 202 | #define BGE_PCI_MSI_ADDR_HI 0x5C |
| 203 | #define BGE_PCI_MSI_ADDR_LO 0x60 |
| 204 | #define BGE_PCI_MSI_DATA 0x64 |
| 205 | |
| 206 | /* |
| 207 | * PCI Express definitions |
| 208 | * According to |
| 209 | * PCI Express base specification, REV. 1.0a |
| 210 | */ |
| 211 | |
| 212 | /* PCI Express device control, 16bits */ |
| 213 | #define BGE_PCIE_DEVCTL 0x08 |
| 214 | #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 |
| 215 | #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 |
| 216 | #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 |
| 217 | #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 |
| 218 | #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 |
| 219 | #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 |
| 220 | #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 |
| 221 | |
| 222 | /* PCI MSI. ??? */ |
| 223 | #define BGE_PCIE_CAPID_REG 0xD0 |
| 224 | #define BGE_PCIE_CAPID 0x10 |
| 225 | |
| 226 | /* |
| 227 | * PCI registers specific to the BCM570x family. |
| 228 | */ |
| 229 | #define BGE_PCI_MISC_CTL 0x68 |
| 230 | #define BGE_PCI_DMA_RW_CTL 0x6C |
| 231 | #define BGE_PCI_PCISTATE 0x70 |
| 232 | #define BGE_PCI_CLKCTL 0x74 |
| 233 | #define BGE_PCI_REG_BASEADDR 0x78 |
| 234 | #define BGE_PCI_MEMWIN_BASEADDR 0x7C |
| 235 | #define BGE_PCI_REG_DATA 0x80 |
| 236 | #define BGE_PCI_MEMWIN_DATA 0x84 |
| 237 | #define BGE_PCI_MODECTL 0x88 |
| 238 | #define BGE_PCI_MISC_CFG 0x8C |
| 239 | #define BGE_PCI_MISC_LOCALCTL 0x90 |
| 240 | #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 |
| 241 | #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C |
| 242 | #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 |
| 243 | #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 |
| 244 | #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 |
| 245 | #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC |
| 246 | #define BGE_PCI_ISR_MBX_HI 0xB0 |
| 247 | #define BGE_PCI_ISR_MBX_LO 0xB4 |
| 248 | #define BGE_PCI_PRODID_ASICREV 0xBC |
| 249 | #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 |
| 250 | #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC |
| 251 | |
| 252 | #define BGE_PCI_UNKNOWN0 0xC4 |
| 253 | |
| 254 | /* PCI Misc. Host control register */ |
| 255 | #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 |
| 256 | #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 |
| 257 | #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 |
| 258 | #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 |
| 259 | #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 |
| 260 | #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 |
| 261 | #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 |
| 262 | #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 |
| 263 | #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 |
| 264 | #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 |
| 265 | #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 |
| 266 | |
| 267 | #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) |
| 268 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 269 | #define BGE_DMA_SWAP_OPTIONS \ |
| 270 | BGE_MODECTL_WORDSWAP_NONFRAME| \ |
| 271 | BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA |
| 272 | #else |
| 273 | #define BGE_DMA_SWAP_OPTIONS \ |
| 274 | BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ |
| 275 | BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA |
| 276 | #endif |
| 277 | |
| 278 | #define BGE_INIT \ |
| 279 | (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ |
| 280 | BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS| \ |
| 281 | BGE_PCIMISCCTL_PCISTATE_RW) |
| 282 | |
| 283 | #define BGE_CHIPID_TIGON_I 0x4000 |
| 284 | #define BGE_CHIPID_TIGON_II 0x6000 |
| 285 | #define BGE_CHIPID_BCM5700_A0 0x7000 |
| 286 | #define BGE_CHIPID_BCM5700_A1 0x7001 |
| 287 | #define BGE_CHIPID_BCM5700_B0 0x7100 |
| 288 | #define BGE_CHIPID_BCM5700_B1 0x7101 |
| 289 | #define BGE_CHIPID_BCM5700_B2 0x7102 |
| 290 | #define BGE_CHIPID_BCM5700_B3 0x7103 |
| 291 | #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 |
| 292 | #define BGE_CHIPID_BCM5700_C0 0x7200 |
| 293 | #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ |
| 294 | #define BGE_CHIPID_BCM5701_B0 0x0100 |
| 295 | #define BGE_CHIPID_BCM5701_B2 0x0102 |
| 296 | #define BGE_CHIPID_BCM5701_B5 0x0105 |
| 297 | #define BGE_CHIPID_BCM5703_A0 0x1000 |
| 298 | #define BGE_CHIPID_BCM5703_A1 0x1001 |
| 299 | #define BGE_CHIPID_BCM5703_A2 0x1002 |
| 300 | #define BGE_CHIPID_BCM5703_A3 0x1003 |
| 301 | #define BGE_CHIPID_BCM5703_B0 0x1100 |
| 302 | #define BGE_CHIPID_BCM5704_A0 0x2000 |
| 303 | #define BGE_CHIPID_BCM5704_A1 0x2001 |
| 304 | #define BGE_CHIPID_BCM5704_A2 0x2002 |
| 305 | #define BGE_CHIPID_BCM5704_A3 0x2003 |
| 306 | #define BGE_CHIPID_BCM5704_B0 0x2100 |
| 307 | #define BGE_CHIPID_BCM5705_A0 0x3000 |
| 308 | #define BGE_CHIPID_BCM5705_A1 0x3001 |
| 309 | #define BGE_CHIPID_BCM5705_A2 0x3002 |
| 310 | #define BGE_CHIPID_BCM5705_A3 0x3003 |
| 311 | #define BGE_CHIPID_BCM5750_A0 0x4000 |
| 312 | #define BGE_CHIPID_BCM5750_A1 0x4001 |
| 313 | #define BGE_CHIPID_BCM5750_A3 0x4003 |
| 314 | #define BGE_CHIPID_BCM5750_B0 0x4010 |
| 315 | #define BGE_CHIPID_BCM5750_B1 0x4101 |
| 316 | #define BGE_CHIPID_BCM5750_C0 0x4200 |
| 317 | #define BGE_CHIPID_BCM5750_C1 0x4201 |
| 318 | #define BGE_CHIPID_BCM5750_C2 0x4202 |
| 319 | #define BGE_CHIPID_BCM5714_A0 0x5000 |
| 320 | #define BGE_CHIPID_BCM5761_A0 0x5761000 |
| 321 | #define BGE_CHIPID_BCM5761_A1 0x5761100 |
| 322 | #define BGE_CHIPID_BCM5784_A0 0x5784000 |
| 323 | #define BGE_CHIPID_BCM5784_A1 0x5784001 |
| 324 | #define BGE_CHIPID_BCM5784_B0 0x5784100 |
| 325 | #define BGE_CHIPID_BCM5752_A0 0x6000 |
| 326 | #define BGE_CHIPID_BCM5752_A1 0x6001 |
| 327 | #define BGE_CHIPID_BCM5752_A2 0x6002 |
| 328 | #define BGE_CHIPID_BCM5714_B0 0x8000 |
| 329 | #define BGE_CHIPID_BCM5714_B3 0x8003 |
| 330 | #define BGE_CHIPID_BCM5715_A0 0x9000 |
| 331 | #define BGE_CHIPID_BCM5715_A1 0x9001 |
| 332 | #define BGE_CHIPID_BCM5715_A3 0x9003 |
| 333 | #define BGE_CHIPID_BCM5755_A0 0xa000 |
| 334 | #define BGE_CHIPID_BCM5755_A1 0xa001 |
| 335 | #define BGE_CHIPID_BCM5755_A2 0xa002 |
| 336 | #define BGE_CHIPID_BCM5755_C0 0xa200 |
| 337 | #define BGE_CHIPID_BCM5787_A0 0xb000 |
| 338 | #define BGE_CHIPID_BCM5787_A1 0xb001 |
| 339 | #define BGE_CHIPID_BCM5787_A2 0xb002 |
| 340 | #define BGE_CHIPID_BCM5906_A0 0xc000 |
| 341 | #define BGE_CHIPID_BCM5906_A1 0xc001 |
| 342 | #define BGE_CHIPID_BCM5906_A2 0xc002 |
| 343 | #define BGE_CHIPID_BCM57762 0x57766000 |
| 344 | #define BGE_CHIPID_BCM57780_A0 0x57780000 |
| 345 | #define BGE_CHIPID_BCM57780_A1 0x57780001 |
| 346 | #define BGE_CHIPID_BCM5717_A0 0x05717000 |
| 347 | #define BGE_CHIPID_BCM5717_B0 0x05717100 |
| 348 | #define BGE_CHIPID_BCM5719_A0 0x05719000 |
| 349 | #define BGE_CHIPID_BCM5720_A0 0x05720000 |
| 350 | #define BGE_CHIPID_BCM57765_A0 0x57785000 |
| 351 | #define BGE_CHIPID_BCM57765_B0 0x57785100 |
| 352 | |
| 353 | /* shorthand one */ |
| 354 | #define BGE_ASICREV(x) ((x) >> 12) |
| 355 | #define BGE_ASICREV_BCM5700 0x07 |
| 356 | #define BGE_ASICREV_BCM5701 0x00 |
| 357 | #define BGE_ASICREV_BCM5703 0x01 |
| 358 | #define BGE_ASICREV_BCM5704 0x02 |
| 359 | #define BGE_ASICREV_BCM5705 0x03 |
| 360 | #define BGE_ASICREV_BCM5750 0x04 |
| 361 | #define BGE_ASICREV_BCM5714_A0 0x05 |
| 362 | #define BGE_ASICREV_BCM5752 0x06 |
| 363 | /* ASIC revision 0x07 is the original bcm5700 */ |
| 364 | #define BGE_ASICREV_BCM5780 0x08 |
| 365 | #define BGE_ASICREV_BCM5714 0x09 |
| 366 | #define BGE_ASICREV_BCM5755 0x0a |
| 367 | #define BGE_ASICREV_BCM5787 0x0b |
| 368 | #define BGE_ASICREV_BCM5906 0x0c |
| 369 | #define BGE_ASICREV_USE_PRODID_REG 0x0f |
| 370 | #define BGE_ASICREV_BCM5761 0x5761 |
| 371 | #define BGE_ASICREV_BCM5784 0x5784 |
| 372 | #define BGE_ASICREV_BCM5785 0x5785 |
| 373 | #define BGE_ASICREV_BCM57780 0x57780 |
| 374 | #define BGE_ASICREV_BCM5717 0x5717 |
| 375 | #define BGE_ASICREV_BCM5719 0x5719 |
| 376 | #define BGE_ASICREV_BCM5720 0x5720 |
| 377 | #define BGE_ASICREV_BCM57765 0x57785 |
| 378 | #define BGE_ASICREV_BCM57766 0x57766 |
| 379 | |
| 380 | /* chip revisions */ |
| 381 | #define BGE_CHIPREV(x) ((x) >> 8) |
| 382 | #define BGE_CHIPREV_5700_AX 0x70 |
| 383 | #define BGE_CHIPREV_5700_BX 0x71 |
| 384 | #define BGE_CHIPREV_5700_CX 0x72 |
| 385 | #define BGE_CHIPREV_5701_AX 0x00 |
| 386 | #define BGE_CHIPREV_5703_AX 0x10 |
| 387 | #define BGE_CHIPREV_5704_AX 0x20 |
| 388 | #define BGE_CHIPREV_5704_BX 0x21 |
| 389 | #define BGE_CHIPREV_5750_AX 0x40 |
| 390 | #define BGE_CHIPREV_5750_BX 0x41 |
| 391 | #define BGE_CHIPREV_5784_AX 0x57840 |
| 392 | #define BGE_CHIPREV_57765_AX 0x577850 |
| 393 | |
| 394 | /* PCI DMA Read/Write Control register */ |
| 395 | #define BGE_PCIDMARWCTL_MINDMA 0x000000FF |
| 396 | #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 |
| 397 | #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 |
| 398 | #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 |
| 399 | #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 |
| 400 | #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 |
| 401 | #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 |
| 402 | #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 |
| 403 | #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 |
| 404 | #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 |
| 405 | #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 |
| 406 | #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 |
| 407 | #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 |
| 408 | |
| 409 | #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) |
| 410 | #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) |
| 411 | #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) |
| 412 | #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) |
| 413 | |
| 414 | #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 |
| 415 | #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 |
| 416 | |
| 417 | #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 |
| 418 | #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 |
| 419 | #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 |
| 420 | #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 |
| 421 | #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 |
| 422 | #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 |
| 423 | #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 |
| 424 | #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 |
| 425 | |
| 426 | #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 |
| 427 | #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 |
| 428 | #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 |
| 429 | #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 |
| 430 | #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 |
| 431 | #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 |
| 432 | #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 |
| 433 | #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 |
| 434 | |
| 435 | /* |
| 436 | * PCI state register -- note, this register is read only |
| 437 | * unless the PCISTATE_RW bit of the PCI Misc. Host Control |
| 438 | * register is set. |
| 439 | */ |
| 440 | #define BGE_PCISTATE_FORCE_RESET 0x00000001 |
| 441 | #define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 |
| 442 | #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ |
| 443 | #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ |
| 444 | #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ |
| 445 | #define BGE_PCISTATE_ROM_ENABLE 0x00000020 |
| 446 | #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 |
| 447 | #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 |
| 448 | #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 |
| 449 | #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 |
| 450 | #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 |
| 451 | #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 |
| 452 | #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 |
| 453 | |
| 454 | /* |
| 455 | * The following bits in PCI state register are reserved. |
| 456 | * If we check that the register values reverts on reset, |
| 457 | * do not check these bits. On some 5704C (rev A3) and some |
| 458 | * Altima chips, these bits do not revert until much later |
| 459 | * in the bge driver's bge_reset() chip-reset state machine. |
| 460 | */ |
| 461 | #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) |
| 462 | |
| 463 | /* |
| 464 | * PCI Clock Control register -- note, this register is read only |
| 465 | * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control |
| 466 | * register is set. |
| 467 | */ |
| 468 | #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F |
| 469 | #define BGE_PCICLOCKCTL_M66EN 0x00000080 |
| 470 | #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 |
| 471 | #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 |
| 472 | #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 |
| 473 | #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 |
| 474 | #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 |
| 475 | #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 |
| 476 | #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 |
| 477 | #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 |
| 478 | |
| 479 | /* |
| 480 | * High priority mailbox registers |
| 481 | * Each mailbox is 64-bits wide, though we only use the |
| 482 | * lower 32 bits. To write a 64-bit value, write the upper 32 bits |
| 483 | * first. The NIC will load the mailbox after the lower 32 bit word |
| 484 | * has been updated. |
| 485 | */ |
| 486 | #define BGE_MBX_IRQ0_HI 0x0200 |
| 487 | #define BGE_MBX_IRQ0_LO 0x0204 |
| 488 | #define BGE_MBX_IRQ1_HI 0x0208 |
| 489 | #define BGE_MBX_IRQ1_LO 0x020C |
| 490 | #define BGE_MBX_IRQ2_HI 0x0210 |
| 491 | #define BGE_MBX_IRQ2_LO 0x0214 |
| 492 | #define BGE_MBX_IRQ3_HI 0x0218 |
| 493 | #define BGE_MBX_IRQ3_LO 0x021C |
| 494 | #define BGE_MBX_GEN0_HI 0x0220 |
| 495 | #define BGE_MBX_GEN0_LO 0x0224 |
| 496 | #define BGE_MBX_GEN1_HI 0x0228 |
| 497 | #define BGE_MBX_GEN1_LO 0x022C |
| 498 | #define BGE_MBX_GEN2_HI 0x0230 |
| 499 | #define BGE_MBX_GEN2_LO 0x0234 |
| 500 | #define BGE_MBX_GEN3_HI 0x0228 |
| 501 | #define BGE_MBX_GEN3_LO 0x022C |
| 502 | #define BGE_MBX_GEN4_HI 0x0240 |
| 503 | #define BGE_MBX_GEN4_LO 0x0244 |
| 504 | #define BGE_MBX_GEN5_HI 0x0248 |
| 505 | #define BGE_MBX_GEN5_LO 0x024C |
| 506 | #define BGE_MBX_GEN6_HI 0x0250 |
| 507 | #define BGE_MBX_GEN6_LO 0x0254 |
| 508 | #define BGE_MBX_GEN7_HI 0x0258 |
| 509 | #define BGE_MBX_GEN7_LO 0x025C |
| 510 | #define BGE_MBX_RELOAD_STATS_HI 0x0260 |
| 511 | #define BGE_MBX_RELOAD_STATS_LO 0x0264 |
| 512 | #define BGE_MBX_RX_STD_PROD_HI 0x0268 |
| 513 | #define BGE_MBX_RX_STD_PROD_LO 0x026C |
| 514 | #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 |
| 515 | #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 |
| 516 | #define BGE_MBX_RX_MINI_PROD_HI 0x0278 |
| 517 | #define BGE_MBX_RX_MINI_PROD_LO 0x027C |
| 518 | #define BGE_MBX_RX_CONS0_HI 0x0280 |
| 519 | #define BGE_MBX_RX_CONS0_LO 0x0284 |
| 520 | #define BGE_MBX_RX_CONS1_HI 0x0288 |
| 521 | #define BGE_MBX_RX_CONS1_LO 0x028C |
| 522 | #define BGE_MBX_RX_CONS2_HI 0x0290 |
| 523 | #define BGE_MBX_RX_CONS2_LO 0x0294 |
| 524 | #define BGE_MBX_RX_CONS3_HI 0x0298 |
| 525 | #define BGE_MBX_RX_CONS3_LO 0x029C |
| 526 | #define BGE_MBX_RX_CONS4_HI 0x02A0 |
| 527 | #define BGE_MBX_RX_CONS4_LO 0x02A4 |
| 528 | #define BGE_MBX_RX_CONS5_HI 0x02A8 |
| 529 | #define BGE_MBX_RX_CONS5_LO 0x02AC |
| 530 | #define BGE_MBX_RX_CONS6_HI 0x02B0 |
| 531 | #define BGE_MBX_RX_CONS6_LO 0x02B4 |
| 532 | #define BGE_MBX_RX_CONS7_HI 0x02B8 |
| 533 | #define BGE_MBX_RX_CONS7_LO 0x02BC |
| 534 | #define BGE_MBX_RX_CONS8_HI 0x02C0 |
| 535 | #define BGE_MBX_RX_CONS8_LO 0x02C4 |
| 536 | #define BGE_MBX_RX_CONS9_HI 0x02C8 |
| 537 | #define BGE_MBX_RX_CONS9_LO 0x02CC |
| 538 | #define BGE_MBX_RX_CONS10_HI 0x02D0 |
| 539 | #define BGE_MBX_RX_CONS10_LO 0x02D4 |
| 540 | #define BGE_MBX_RX_CONS11_HI 0x02D8 |
| 541 | #define BGE_MBX_RX_CONS11_LO 0x02DC |
| 542 | #define BGE_MBX_RX_CONS12_HI 0x02E0 |
| 543 | #define BGE_MBX_RX_CONS12_LO 0x02E4 |
| 544 | #define BGE_MBX_RX_CONS13_HI 0x02E8 |
| 545 | #define BGE_MBX_RX_CONS13_LO 0x02EC |
| 546 | #define BGE_MBX_RX_CONS14_HI 0x02F0 |
| 547 | #define BGE_MBX_RX_CONS14_LO 0x02F4 |
| 548 | #define BGE_MBX_RX_CONS15_HI 0x02F8 |
| 549 | #define BGE_MBX_RX_CONS15_LO 0x02FC |
| 550 | #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 |
| 551 | #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 |
| 552 | #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 |
| 553 | #define BGE_MBX_TX_HOST_PROD1_LO 0x030C |
| 554 | #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 |
| 555 | #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 |
| 556 | #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 |
| 557 | #define BGE_MBX_TX_HOST_PROD3_LO 0x031C |
| 558 | #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 |
| 559 | #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 |
| 560 | #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 |
| 561 | #define BGE_MBX_TX_HOST_PROD5_LO 0x032C |
| 562 | #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 |
| 563 | #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 |
| 564 | #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 |
| 565 | #define BGE_MBX_TX_HOST_PROD7_LO 0x033C |
| 566 | #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 |
| 567 | #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 |
| 568 | #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 |
| 569 | #define BGE_MBX_TX_HOST_PROD9_LO 0x034C |
| 570 | #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 |
| 571 | #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 |
| 572 | #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 |
| 573 | #define BGE_MBX_TX_HOST_PROD11_LO 0x035C |
| 574 | #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 |
| 575 | #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 |
| 576 | #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 |
| 577 | #define BGE_MBX_TX_HOST_PROD13_LO 0x036C |
| 578 | #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 |
| 579 | #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 |
| 580 | #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 |
| 581 | #define BGE_MBX_TX_HOST_PROD15_LO 0x037C |
| 582 | #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 |
| 583 | #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 |
| 584 | #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 |
| 585 | #define BGE_MBX_TX_NIC_PROD1_LO 0x038C |
| 586 | #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 |
| 587 | #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 |
| 588 | #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 |
| 589 | #define BGE_MBX_TX_NIC_PROD3_LO 0x039C |
| 590 | #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 |
| 591 | #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 |
| 592 | #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 |
| 593 | #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC |
| 594 | #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 |
| 595 | #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 |
| 596 | #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 |
| 597 | #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC |
| 598 | #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 |
| 599 | #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 |
| 600 | #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 |
| 601 | #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC |
| 602 | #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 |
| 603 | #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 |
| 604 | #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 |
| 605 | #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC |
| 606 | #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 |
| 607 | #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 |
| 608 | #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 |
| 609 | #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC |
| 610 | #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 |
| 611 | #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 |
| 612 | #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 |
| 613 | #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC |
| 614 | |
| 615 | #define BGE_TX_RINGS_MAX 1 |
| 616 | #define BGE_TX_RINGS_57765_MAX 2 |
| 617 | #define BGE_TX_RINGS_5717_MAX 4 |
| 618 | #define BGE_TX_RINGS_EXTSSRAM_MAX 16 |
| 619 | #define BGE_RX_RINGS_MAX 16 |
| 620 | |
| 621 | /* Ethernet MAC control registers */ |
| 622 | #define BGE_MAC_MODE 0x0400 |
| 623 | #define BGE_MAC_STS 0x0404 |
| 624 | #define BGE_MAC_EVT_ENB 0x0408 |
| 625 | #define BGE_MAC_LED_CTL 0x040C |
| 626 | #define BGE_MAC_ADDR1_LO 0x0410 |
| 627 | #define BGE_MAC_ADDR1_HI 0x0414 |
| 628 | #define BGE_MAC_ADDR2_LO 0x0418 |
| 629 | #define BGE_MAC_ADDR2_HI 0x041C |
| 630 | #define BGE_MAC_ADDR3_LO 0x0420 |
| 631 | #define BGE_MAC_ADDR3_HI 0x0424 |
| 632 | #define BGE_MAC_ADDR4_LO 0x0428 |
| 633 | #define BGE_MAC_ADDR4_HI 0x042C |
| 634 | #define BGE_WOL_PATPTR 0x0430 |
| 635 | #define BGE_WOL_PATCFG 0x0434 |
| 636 | #define BGE_TX_RANDOM_BACKOFF 0x0438 |
| 637 | #define BGE_RX_MTU 0x043C |
| 638 | #define BGE_GBIT_PCS_TEST 0x0440 |
| 639 | #define BGE_TX_TBI_AUTONEG 0x0444 |
| 640 | #define BGE_RX_TBI_AUTONEG 0x0448 |
| 641 | #define BGE_MI_COMM 0x044C |
| 642 | #define BGE_MI_STS 0x0450 |
| 643 | #define BGE_MI_MODE 0x0454 |
| 644 | #define BGE_AUTOPOLL_STS 0x0458 |
| 645 | #define BGE_TX_MODE 0x045C |
| 646 | #define BGE_TX_STS 0x0460 |
| 647 | #define BGE_TX_LENGTHS 0x0464 |
| 648 | #define BGE_RX_MODE 0x0468 |
| 649 | #define BGE_RX_STS 0x046C |
| 650 | #define BGE_MAR0 0x0470 |
| 651 | #define BGE_MAR1 0x0474 |
| 652 | #define BGE_MAR2 0x0478 |
| 653 | #define BGE_MAR3 0x047C |
| 654 | #define BGE_RX_BD_RULES_CTL0 0x0480 |
| 655 | #define BGE_RX_BD_RULES_MASKVAL0 0x0484 |
| 656 | #define BGE_RX_BD_RULES_CTL1 0x0488 |
| 657 | #define BGE_RX_BD_RULES_MASKVAL1 0x048C |
| 658 | #define BGE_RX_BD_RULES_CTL2 0x0490 |
| 659 | #define BGE_RX_BD_RULES_MASKVAL2 0x0494 |
| 660 | #define BGE_RX_BD_RULES_CTL3 0x0498 |
| 661 | #define BGE_RX_BD_RULES_MASKVAL3 0x049C |
| 662 | #define BGE_RX_BD_RULES_CTL4 0x04A0 |
| 663 | #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 |
| 664 | #define BGE_RX_BD_RULES_CTL5 0x04A8 |
| 665 | #define BGE_RX_BD_RULES_MASKVAL5 0x04AC |
| 666 | #define BGE_RX_BD_RULES_CTL6 0x04B0 |
| 667 | #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 |
| 668 | #define BGE_RX_BD_RULES_CTL7 0x04B8 |
| 669 | #define BGE_RX_BD_RULES_MASKVAL7 0x04BC |
| 670 | #define BGE_RX_BD_RULES_CTL8 0x04C0 |
| 671 | #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 |
| 672 | #define BGE_RX_BD_RULES_CTL9 0x04C8 |
| 673 | #define BGE_RX_BD_RULES_MASKVAL9 0x04CC |
| 674 | #define BGE_RX_BD_RULES_CTL10 0x04D0 |
| 675 | #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 |
| 676 | #define BGE_RX_BD_RULES_CTL11 0x04D8 |
| 677 | #define BGE_RX_BD_RULES_MASKVAL11 0x04DC |
| 678 | #define BGE_RX_BD_RULES_CTL12 0x04E0 |
| 679 | #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 |
| 680 | #define BGE_RX_BD_RULES_CTL13 0x04E8 |
| 681 | #define BGE_RX_BD_RULES_MASKVAL13 0x04EC |
| 682 | #define BGE_RX_BD_RULES_CTL14 0x04F0 |
| 683 | #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 |
| 684 | #define BGE_RX_BD_RULES_CTL15 0x04F8 |
| 685 | #define BGE_RX_BD_RULES_MASKVAL15 0x04FC |
| 686 | #define BGE_RX_RULES_CFG 0x0500 |
| 687 | #define BGE_MAX_RX_FRAME_LOWAT 0x0504 |
| 688 | #define BGE_SERDES_CFG 0x0590 |
| 689 | #define BGE_SGDIG_CFG 0x05B0 |
| 690 | #define BGE_SGDIG_STS 0x05B4 |
| 691 | #define BGE_MAC_STATS 0x0800 |
| 692 | |
| 693 | /* Ethernet MAC Mode register */ |
| 694 | #define BGE_MACMODE_RESET 0x00000001 |
| 695 | #define BGE_MACMODE_HALF_DUPLEX 0x00000002 |
| 696 | #define BGE_MACMODE_PORTMODE 0x0000000C |
| 697 | #define BGE_MACMODE_LOOPBACK 0x00000010 |
| 698 | #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 |
| 699 | #define BGE_MACMODE_TX_BURST_ENB 0x00000100 |
| 700 | #define BGE_MACMODE_MAX_DEFER 0x00000200 |
| 701 | #define BGE_MACMODE_LINK_POLARITY 0x00000400 |
| 702 | #define BGE_MACMODE_RX_STATS_ENB 0x00000800 |
| 703 | #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 |
| 704 | #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 |
| 705 | #define BGE_MACMODE_TX_STATS_ENB 0x00004000 |
| 706 | #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 |
| 707 | #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 |
| 708 | #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 |
| 709 | #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 |
| 710 | #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 |
| 711 | #define BGE_MACMODE_MIP_ENB 0x00100000 |
| 712 | #define BGE_MACMODE_TXDMA_ENB 0x00200000 |
| 713 | #define BGE_MACMODE_RXDMA_ENB 0x00400000 |
| 714 | #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 |
| 715 | #define BGE_MACMODE_APE_RX_EN 0x08000000 |
| 716 | #define BGE_MACMODE_APE_TX_EN 0x10000000 |
| 717 | |
| 718 | #define BGE_PORTMODE_NONE 0x00000000 |
| 719 | #define BGE_PORTMODE_MII 0x00000004 |
| 720 | #define BGE_PORTMODE_GMII 0x00000008 |
| 721 | #define BGE_PORTMODE_TBI 0x0000000C |
| 722 | |
| 723 | /* MAC Status register */ |
| 724 | #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 |
| 725 | #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 |
| 726 | #define BGE_MACSTAT_RX_CFG 0x00000004 |
| 727 | #define BGE_MACSTAT_CFG_CHANGED 0x00000008 |
| 728 | #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 |
| 729 | #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 |
| 730 | #define BGE_MACSTAT_LINK_CHANGED 0x00001000 |
| 731 | #define BGE_MACSTAT_MI_COMPLETE 0x00400000 |
| 732 | #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 |
| 733 | #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 |
| 734 | #define BGE_MACSTAT_ODI_ERROR 0x02000000 |
| 735 | #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 |
| 736 | #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 |
| 737 | |
| 738 | /* MAC Event Enable Register */ |
| 739 | #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 |
| 740 | #define BGE_EVTENB_LINK_CHANGED 0x00001000 |
| 741 | #define BGE_EVTENB_MI_COMPLETE 0x00400000 |
| 742 | #define BGE_EVTENB_MI_INTERRUPT 0x00800000 |
| 743 | #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 |
| 744 | #define BGE_EVTENB_ODI_ERROR 0x02000000 |
| 745 | #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 |
| 746 | #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 |
| 747 | |
| 748 | /* LED Control Register */ |
| 749 | #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 |
| 750 | #define BGE_LEDCTL_1000MBPS_LED 0x00000002 |
| 751 | #define BGE_LEDCTL_100MBPS_LED 0x00000004 |
| 752 | #define BGE_LEDCTL_10MBPS_LED 0x00000008 |
| 753 | #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 |
| 754 | #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 |
| 755 | #define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 |
| 756 | #define BGE_LEDCTL_1000MBPS_STS 0x00000080 |
| 757 | #define BGE_LEDCTL_100MBPS_STS 0x00000100 |
| 758 | #define BGE_LEDCTL_10MBPS_STS 0x00000200 |
| 759 | #define BGE_LEDCTL_TRAFLED_STS 0x00000400 |
| 760 | #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 |
| 761 | #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 |
| 762 | |
| 763 | /* TX backoff seed register */ |
| 764 | #define BGE_TX_BACKOFF_SEED_MASK 0x3FF |
| 765 | |
| 766 | /* Autopoll status register */ |
| 767 | #define BGE_AUTOPOLLSTS_ERROR 0x00000001 |
| 768 | |
| 769 | /* Transmit MAC mode register */ |
| 770 | #define BGE_TXMODE_RESET 0x00000001 |
| 771 | #define BGE_TXMODE_ENABLE 0x00000002 |
| 772 | #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 |
| 773 | #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 |
| 774 | #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 |
| 775 | #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 |
| 776 | #define BGE_TXMODE_JMB_FRM_LEN 0x00400000 |
| 777 | #define BGE_TXMODE_CNT_DN_MODE 0x00800000 |
| 778 | |
| 779 | /* Transmit MAC status register */ |
| 780 | #define BGE_TXSTAT_RX_XOFFED 0x00000001 |
| 781 | #define BGE_TXSTAT_SENT_XOFF 0x00000002 |
| 782 | #define BGE_TXSTAT_SENT_XON 0x00000004 |
| 783 | #define BGE_TXSTAT_LINK_UP 0x00000008 |
| 784 | #define BGE_TXSTAT_ODI_UFLOW 0x00000010 |
| 785 | #define BGE_TXSTAT_ODI_OFLOW 0x00000020 |
| 786 | |
| 787 | /* Transmit MAC lengths register */ |
| 788 | #define BGE_TXLEN_SLOTTIME 0x000000FF |
| 789 | #define BGE_TXLEN_IPG 0x00000F00 |
| 790 | #define BGE_TXLEN_CRS 0x00003000 |
| 791 | #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 |
| 792 | #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 |
| 793 | |
| 794 | /* Receive MAC mode register */ |
| 795 | #define BGE_RXMODE_RESET 0x00000001 |
| 796 | #define BGE_RXMODE_ENABLE 0x00000002 |
| 797 | #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 |
| 798 | #define BGE_RXMODE_RX_GIANTS 0x00000020 |
| 799 | #define BGE_RXMODE_RX_RUNTS 0x00000040 |
| 800 | #define BGE_RXMODE_8022_LENCHECK 0x00000080 |
| 801 | #define BGE_RXMODE_RX_PROMISC 0x00000100 |
| 802 | #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 |
| 803 | #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 |
| 804 | #define BGE_RXMODE_IPV6_ENABLE 0x01000000 |
| 805 | |
| 806 | /* Receive MAC status register */ |
| 807 | #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 |
| 808 | #define BGE_RXSTAT_RCVD_XOFF 0x00000002 |
| 809 | #define BGE_RXSTAT_RCVD_XON 0x00000004 |
| 810 | |
| 811 | /* Receive Rules Control register */ |
| 812 | #define BGE_RXRULECTL_OFFSET 0x000000FF |
| 813 | #define BGE_RXRULECTL_CLASS 0x00001F00 |
| 814 | #define BGE_RXRULECTL_HDRTYPE 0x0000E000 |
| 815 | #define BGE_RXRULECTL_COMPARE_OP 0x00030000 |
| 816 | #define BGE_RXRULECTL_MAP 0x01000000 |
| 817 | #define BGE_RXRULECTL_DISCARD 0x02000000 |
| 818 | #define BGE_RXRULECTL_MASK 0x04000000 |
| 819 | #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 |
| 820 | #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 |
| 821 | #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 |
| 822 | #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 |
| 823 | |
| 824 | /* Receive Rules Mask register */ |
| 825 | #define BGE_RXRULEMASK_VALUE 0x0000FFFF |
| 826 | #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 |
| 827 | |
| 828 | /* SGDIG config (not documented) */ |
| 829 | #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 |
| 830 | #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 |
| 831 | #define BGE_SGDIGCFG_SEND 0x40000000 |
| 832 | #define BGE_SGDIGCFG_AUTO 0x80000000 |
| 833 | |
| 834 | /* SGDIG status (not documented) */ |
| 835 | #define BGE_SGDIGSTS_DONE 0x00000002 |
| 836 | #define BGE_SGDIGSTS_IS_SERDES 0x00000100 |
| 837 | |
| 838 | /* MI communication register */ |
| 839 | #define BGE_MICOMM_DATA 0x0000FFFF |
| 840 | #define BGE_MICOMM_REG 0x001F0000 |
| 841 | #define BGE_MICOMM_PHY 0x03E00000 |
| 842 | #define BGE_MICOMM_CMD 0x0C000000 |
| 843 | #define BGE_MICOMM_READFAIL 0x10000000 |
| 844 | #define BGE_MICOMM_BUSY 0x20000000 |
| 845 | |
| 846 | #define BGE_MIREG(x) ((x & 0x1F) << 16) |
| 847 | #define BGE_MIPHY(x) ((x & 0x1F) << 21) |
| 848 | #define BGE_MICMD_WRITE 0x04000000 |
| 849 | #define BGE_MICMD_READ 0x08000000 |
| 850 | |
| 851 | /* MI status register */ |
| 852 | #define BGE_MISTS_LINK 0x00000001 |
| 853 | #define BGE_MISTS_10MBPS 0x00000002 |
| 854 | |
| 855 | #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 |
| 856 | #define BGE_MIMODE_AUTOPOLL 0x00000010 |
| 857 | #define BGE_MIMODE_PHYADDR_SHIFT 5 |
| 858 | #define BGE_MIMODE_PHYADDR_MASK 0x000003E0 |
| 859 | #define BGE_MIMODE_CLKCNT 0x001F0000 |
| 860 | #define BGE_MIMODE_500KHZ_CONST 0x00008000 |
| 861 | #define BGE_MIMODE_BASE 0x000C0000 |
| 862 | |
| 863 | #define BGE_MIMODE_PHYADDR(x) ((x) << BGE_MIMODE_PHYADDR_SHIFT) |
| 864 | |
| 865 | /* |
| 866 | * Send data initiator control registers. |
| 867 | */ |
| 868 | #define BGE_SDI_MODE 0x0C00 |
| 869 | #define BGE_SDI_STATUS 0x0C04 |
| 870 | #define BGE_SDI_STATS_CTL 0x0C08 |
| 871 | #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C |
| 872 | #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 |
| 873 | #define BGE_ISO_PKT_TX 0x0C20 |
| 874 | #define BGE_LOCSTATS_COS0 0x0C80 |
| 875 | #define BGE_LOCSTATS_COS1 0x0C84 |
| 876 | #define BGE_LOCSTATS_COS2 0x0C88 |
| 877 | #define BGE_LOCSTATS_COS3 0x0C8C |
| 878 | #define BGE_LOCSTATS_COS4 0x0C90 |
| 879 | #define BGE_LOCSTATS_COS5 0x0C84 |
| 880 | #define BGE_LOCSTATS_COS6 0x0C98 |
| 881 | #define BGE_LOCSTATS_COS7 0x0C9C |
| 882 | #define BGE_LOCSTATS_COS8 0x0CA0 |
| 883 | #define BGE_LOCSTATS_COS9 0x0CA4 |
| 884 | #define BGE_LOCSTATS_COS10 0x0CA8 |
| 885 | #define BGE_LOCSTATS_COS11 0x0CAC |
| 886 | #define BGE_LOCSTATS_COS12 0x0CB0 |
| 887 | #define BGE_LOCSTATS_COS13 0x0CB4 |
| 888 | #define BGE_LOCSTATS_COS14 0x0CB8 |
| 889 | #define BGE_LOCSTATS_COS15 0x0CBC |
| 890 | #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 |
| 891 | #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 |
| 892 | #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 |
| 893 | #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC |
| 894 | #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 |
| 895 | #define BGE_LOCSTATS_IRQS 0x0CD4 |
| 896 | #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 |
| 897 | #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC |
| 898 | |
| 899 | /* Send Data Initiator mode register */ |
| 900 | #define BGE_SDIMODE_RESET 0x00000001 |
| 901 | #define BGE_SDIMODE_ENABLE 0x00000002 |
| 902 | #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 |
| 903 | #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 |
| 904 | |
| 905 | /* Send Data Initiator stats register */ |
| 906 | #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 |
| 907 | |
| 908 | /* Send Data Initiator stats control register */ |
| 909 | #define BGE_SDISTATSCTL_ENABLE 0x00000001 |
| 910 | #define BGE_SDISTATSCTL_FASTER 0x00000002 |
| 911 | #define BGE_SDISTATSCTL_CLEAR 0x00000004 |
| 912 | #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 |
| 913 | #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 |
| 914 | |
| 915 | /* |
| 916 | * Send Data Completion Control registers |
| 917 | */ |
| 918 | #define BGE_SDC_MODE 0x1000 |
| 919 | #define BGE_SDC_STATUS 0x1004 |
| 920 | |
| 921 | /* Send Data completion mode register */ |
| 922 | #define BGE_SDCMODE_RESET 0x00000001 |
| 923 | #define BGE_SDCMODE_ENABLE 0x00000002 |
| 924 | #define BGE_SDCMODE_ATTN 0x00000004 |
| 925 | #define BGE_SDCMODE_CDELAY 0x00000010 |
| 926 | |
| 927 | /* Send Data completion status register */ |
| 928 | #define BGE_SDCSTAT_ATTN 0x00000004 |
| 929 | |
| 930 | /* |
| 931 | * Send BD Ring Selector Control registers |
| 932 | */ |
| 933 | #define BGE_SRS_MODE 0x1400 |
| 934 | #define BGE_SRS_STATUS 0x1404 |
| 935 | #define BGE_SRS_HWDIAG 0x1408 |
| 936 | #define BGE_SRS_LOC_NIC_CONS0 0x1440 |
| 937 | #define BGE_SRS_LOC_NIC_CONS1 0x1444 |
| 938 | #define BGE_SRS_LOC_NIC_CONS2 0x1448 |
| 939 | #define BGE_SRS_LOC_NIC_CONS3 0x144C |
| 940 | #define BGE_SRS_LOC_NIC_CONS4 0x1450 |
| 941 | #define BGE_SRS_LOC_NIC_CONS5 0x1454 |
| 942 | #define BGE_SRS_LOC_NIC_CONS6 0x1458 |
| 943 | #define BGE_SRS_LOC_NIC_CONS7 0x145C |
| 944 | #define BGE_SRS_LOC_NIC_CONS8 0x1460 |
| 945 | #define BGE_SRS_LOC_NIC_CONS9 0x1464 |
| 946 | #define BGE_SRS_LOC_NIC_CONS10 0x1468 |
| 947 | #define BGE_SRS_LOC_NIC_CONS11 0x146C |
| 948 | #define BGE_SRS_LOC_NIC_CONS12 0x1470 |
| 949 | #define BGE_SRS_LOC_NIC_CONS13 0x1474 |
| 950 | #define BGE_SRS_LOC_NIC_CONS14 0x1478 |
| 951 | #define BGE_SRS_LOC_NIC_CONS15 0x147C |
| 952 | |
| 953 | /* Send BD Ring Selector Mode register */ |
| 954 | #define BGE_SRSMODE_RESET 0x00000001 |
| 955 | #define BGE_SRSMODE_ENABLE 0x00000002 |
| 956 | #define BGE_SRSMODE_ATTN 0x00000004 |
| 957 | |
| 958 | /* Send BD Ring Selector Status register */ |
| 959 | #define 0x00000004 |
| 960 | |
| 961 | /* Send BD Ring Selector HW Diagnostics register */ |
| 962 | #define BGE_SRSHWDIAG_STATE 0x0000000F |
| 963 | #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 |
| 964 | #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 |
| 965 | #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 |
| 966 | |
| 967 | /* |
| 968 | * Send BD Initiator Selector Control registers |
| 969 | */ |
| 970 | #define BGE_SBDI_MODE 0x1800 |
| 971 | #define BGE_SBDI_STATUS 0x1804 |
| 972 | #define BGE_SBDI_LOC_NIC_PROD0 0x1808 |
| 973 | #define BGE_SBDI_LOC_NIC_PROD1 0x180C |
| 974 | #define BGE_SBDI_LOC_NIC_PROD2 0x1810 |
| 975 | #define BGE_SBDI_LOC_NIC_PROD3 0x1814 |
| 976 | #define BGE_SBDI_LOC_NIC_PROD4 0x1818 |
| 977 | #define BGE_SBDI_LOC_NIC_PROD5 0x181C |
| 978 | #define BGE_SBDI_LOC_NIC_PROD6 0x1820 |
| 979 | #define BGE_SBDI_LOC_NIC_PROD7 0x1824 |
| 980 | #define BGE_SBDI_LOC_NIC_PROD8 0x1828 |
| 981 | #define BGE_SBDI_LOC_NIC_PROD9 0x182C |
| 982 | #define BGE_SBDI_LOC_NIC_PROD10 0x1830 |
| 983 | #define BGE_SBDI_LOC_NIC_PROD11 0x1834 |
| 984 | #define BGE_SBDI_LOC_NIC_PROD12 0x1838 |
| 985 | #define BGE_SBDI_LOC_NIC_PROD13 0x183C |
| 986 | #define BGE_SBDI_LOC_NIC_PROD14 0x1840 |
| 987 | #define BGE_SBDI_LOC_NIC_PROD15 0x1844 |
| 988 | |
| 989 | /* Send BD Initiator Mode register */ |
| 990 | #define BGE_SBDIMODE_RESET 0x00000001 |
| 991 | #define BGE_SBDIMODE_ENABLE 0x00000002 |
| 992 | #define BGE_SBDIMODE_ATTN 0x00000004 |
| 993 | |
| 994 | /* Send BD Initiator Status register */ |
| 995 | #define BGE_SBDISTAT_ERROR 0x00000004 |
| 996 | |
| 997 | /* |
| 998 | * Send BD Completion Control registers |
| 999 | */ |
| 1000 | #define BGE_SBDC_MODE 0x1C00 |
| 1001 | #define BGE_SBDC_STATUS 0x1C04 |
| 1002 | |
| 1003 | /* Send BD Completion Control Mode register */ |
| 1004 | #define BGE_SBDCMODE_RESET 0x00000001 |
| 1005 | #define BGE_SBDCMODE_ENABLE 0x00000002 |
| 1006 | #define BGE_SBDCMODE_ATTN 0x00000004 |
| 1007 | |
| 1008 | /* Send BD Completion Control Status register */ |
| 1009 | #define BGE_SBDCSTAT_ATTN 0x00000004 |
| 1010 | |
| 1011 | /* |
| 1012 | * Receive List Placement Control registers |
| 1013 | */ |
| 1014 | #define BGE_RXLP_MODE 0x2000 |
| 1015 | #define BGE_RXLP_STATUS 0x2004 |
| 1016 | #define BGE_RXLP_SEL_LIST_LOCK 0x2008 |
| 1017 | #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C |
| 1018 | #define BGE_RXLP_CFG 0x2010 |
| 1019 | #define BGE_RXLP_STATS_CTL 0x2014 |
| 1020 | #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 |
| 1021 | #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C |
| 1022 | #define BGE_RXLP_HEAD0 0x2100 |
| 1023 | #define BGE_RXLP_TAIL0 0x2104 |
| 1024 | #define BGE_RXLP_COUNT0 0x2108 |
| 1025 | #define BGE_RXLP_HEAD1 0x2110 |
| 1026 | #define BGE_RXLP_TAIL1 0x2114 |
| 1027 | #define BGE_RXLP_COUNT1 0x2118 |
| 1028 | #define BGE_RXLP_HEAD2 0x2120 |
| 1029 | #define BGE_RXLP_TAIL2 0x2124 |
| 1030 | #define BGE_RXLP_COUNT2 0x2128 |
| 1031 | #define BGE_RXLP_HEAD3 0x2130 |
| 1032 | #define BGE_RXLP_TAIL3 0x2134 |
| 1033 | #define BGE_RXLP_COUNT3 0x2138 |
| 1034 | #define BGE_RXLP_HEAD4 0x2140 |
| 1035 | #define BGE_RXLP_TAIL4 0x2144 |
| 1036 | #define BGE_RXLP_COUNT4 0x2148 |
| 1037 | #define BGE_RXLP_HEAD5 0x2150 |
| 1038 | #define BGE_RXLP_TAIL5 0x2154 |
| 1039 | #define BGE_RXLP_COUNT5 0x2158 |
| 1040 | #define BGE_RXLP_HEAD6 0x2160 |
| 1041 | #define BGE_RXLP_TAIL6 0x2164 |
| 1042 | #define BGE_RXLP_COUNT6 0x2168 |
| 1043 | #define BGE_RXLP_HEAD7 0x2170 |
| 1044 | #define BGE_RXLP_TAIL7 0x2174 |
| 1045 | #define BGE_RXLP_COUNT7 0x2178 |
| 1046 | #define BGE_RXLP_HEAD8 0x2180 |
| 1047 | #define BGE_RXLP_TAIL8 0x2184 |
| 1048 | #define BGE_RXLP_COUNT8 0x2188 |
| 1049 | #define BGE_RXLP_HEAD9 0x2190 |
| 1050 | #define BGE_RXLP_TAIL9 0x2194 |
| 1051 | #define BGE_RXLP_COUNT9 0x2198 |
| 1052 | #define BGE_RXLP_HEAD10 0x21A0 |
| 1053 | #define BGE_RXLP_TAIL10 0x21A4 |
| 1054 | #define BGE_RXLP_COUNT10 0x21A8 |
| 1055 | #define BGE_RXLP_HEAD11 0x21B0 |
| 1056 | #define BGE_RXLP_TAIL11 0x21B4 |
| 1057 | #define BGE_RXLP_COUNT11 0x21B8 |
| 1058 | #define BGE_RXLP_HEAD12 0x21C0 |
| 1059 | #define BGE_RXLP_TAIL12 0x21C4 |
| 1060 | #define BGE_RXLP_COUNT12 0x21C8 |
| 1061 | #define BGE_RXLP_HEAD13 0x21D0 |
| 1062 | #define BGE_RXLP_TAIL13 0x21D4 |
| 1063 | #define BGE_RXLP_COUNT13 0x21D8 |
| 1064 | #define BGE_RXLP_HEAD14 0x21E0 |
| 1065 | #define BGE_RXLP_TAIL14 0x21E4 |
| 1066 | #define BGE_RXLP_COUNT14 0x21E8 |
| 1067 | #define BGE_RXLP_HEAD15 0x21F0 |
| 1068 | #define BGE_RXLP_TAIL15 0x21F4 |
| 1069 | #define BGE_RXLP_COUNT15 0x21F8 |
| 1070 | #define BGE_RXLP_LOCSTAT_COS0 0x2200 |
| 1071 | #define BGE_RXLP_LOCSTAT_COS1 0x2204 |
| 1072 | #define BGE_RXLP_LOCSTAT_COS2 0x2208 |
| 1073 | #define BGE_RXLP_LOCSTAT_COS3 0x220C |
| 1074 | #define BGE_RXLP_LOCSTAT_COS4 0x2210 |
| 1075 | #define BGE_RXLP_LOCSTAT_COS5 0x2214 |
| 1076 | #define BGE_RXLP_LOCSTAT_COS6 0x2218 |
| 1077 | #define BGE_RXLP_LOCSTAT_COS7 0x221C |
| 1078 | #define BGE_RXLP_LOCSTAT_COS8 0x2220 |
| 1079 | #define BGE_RXLP_LOCSTAT_COS9 0x2224 |
| 1080 | #define BGE_RXLP_LOCSTAT_COS10 0x2228 |
| 1081 | #define BGE_RXLP_LOCSTAT_COS11 0x222C |
| 1082 | #define BGE_RXLP_LOCSTAT_COS12 0x2230 |
| 1083 | #define BGE_RXLP_LOCSTAT_COS13 0x2234 |
| 1084 | #define BGE_RXLP_LOCSTAT_COS14 0x2238 |
| 1085 | #define BGE_RXLP_LOCSTAT_COS15 0x223C |
| 1086 | #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 |
| 1087 | #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 |
| 1088 | #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 |
| 1089 | #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C |
| 1090 | #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 |
| 1091 | #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 |
| 1092 | #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 |
| 1093 | |
| 1094 | |
| 1095 | /* Receive List Placement mode register */ |
| 1096 | #define BGE_RXLPMODE_RESET 0x00000001 |
| 1097 | #define BGE_RXLPMODE_ENABLE 0x00000002 |
| 1098 | #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 |
| 1099 | #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 |
| 1100 | #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 |
| 1101 | |
| 1102 | /* Receive List Placement Status register */ |
| 1103 | #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 |
| 1104 | #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 |
| 1105 | #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 |
| 1106 | |
| 1107 | /* Receive List Placement Statistics Enable Mask register */ |
| 1108 | #define BGE_RXLPSTATCONTROL_DACK_FIX 0x00040000 |
| 1109 | #define BGE_RXLPSTATCONTROL_LBIRST_FIX 0x00400000 |
| 1110 | |
| 1111 | /* |
| 1112 | * Receive Data and Receive BD Initiator Control Registers |
| 1113 | */ |
| 1114 | #define BGE_RDBDI_MODE 0x2400 |
| 1115 | #define BGE_RDBDI_STATUS 0x2404 |
| 1116 | #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 |
| 1117 | #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 |
| 1118 | #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 |
| 1119 | #define BGE_RX_JUMBO_RCB_NICADDR 0x244C |
| 1120 | #define BGE_RX_STD_RCB_HADDR_HI 0x2450 |
| 1121 | #define BGE_RX_STD_RCB_HADDR_LO 0x2454 |
| 1122 | #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 |
| 1123 | #define BGE_RX_STD_RCB_NICADDR 0x245C |
| 1124 | #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 |
| 1125 | #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 |
| 1126 | #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 |
| 1127 | #define BGE_RX_MINI_RCB_NICADDR 0x246C |
| 1128 | #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 |
| 1129 | #define BGE_RDBDI_STD_RX_CONS 0x2474 |
| 1130 | #define BGE_RDBDI_MINI_RX_CONS 0x2478 |
| 1131 | #define BGE_RDBDI_RETURN_PROD0 0x2480 |
| 1132 | #define BGE_RDBDI_RETURN_PROD1 0x2484 |
| 1133 | #define BGE_RDBDI_RETURN_PROD2 0x2488 |
| 1134 | #define BGE_RDBDI_RETURN_PROD3 0x248C |
| 1135 | #define BGE_RDBDI_RETURN_PROD4 0x2490 |
| 1136 | #define BGE_RDBDI_RETURN_PROD5 0x2494 |
| 1137 | #define BGE_RDBDI_RETURN_PROD6 0x2498 |
| 1138 | #define BGE_RDBDI_RETURN_PROD7 0x249C |
| 1139 | #define BGE_RDBDI_RETURN_PROD8 0x24A0 |
| 1140 | #define BGE_RDBDI_RETURN_PROD9 0x24A4 |
| 1141 | #define BGE_RDBDI_RETURN_PROD10 0x24A8 |
| 1142 | #define BGE_RDBDI_RETURN_PROD11 0x24AC |
| 1143 | #define BGE_RDBDI_RETURN_PROD12 0x24B0 |
| 1144 | #define BGE_RDBDI_RETURN_PROD13 0x24B4 |
| 1145 | #define BGE_RDBDI_RETURN_PROD14 0x24B8 |
| 1146 | #define BGE_RDBDI_RETURN_PROD15 0x24BC |
| 1147 | #define BGE_RDBDI_HWDIAG 0x24C0 |
| 1148 | |
| 1149 | |
| 1150 | /* Receive Data and Receive BD Initiator Mode register */ |
| 1151 | #define BGE_RDBDIMODE_RESET 0x00000001 |
| 1152 | #define BGE_RDBDIMODE_ENABLE 0x00000002 |
| 1153 | #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 |
| 1154 | #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 |
| 1155 | #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 |
| 1156 | |
| 1157 | /* Receive Data and Receive BD Initiator Status register */ |
| 1158 | #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 |
| 1159 | #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 |
| 1160 | #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 |
| 1161 | |
| 1162 | |
| 1163 | /* |
| 1164 | * Receive Data Completion Control registers |
| 1165 | */ |
| 1166 | #define BGE_RDC_MODE 0x2800 |
| 1167 | |
| 1168 | /* Receive Data Completion Mode register */ |
| 1169 | #define BGE_RDCMODE_RESET 0x00000001 |
| 1170 | #define BGE_RDCMODE_ENABLE 0x00000002 |
| 1171 | #define BGE_RDCMODE_ATTN 0x00000004 |
| 1172 | |
| 1173 | /* |
| 1174 | * Receive BD Initiator Control registers |
| 1175 | */ |
| 1176 | #define BGE_RBDI_MODE 0x2C00 |
| 1177 | #define BGE_RBDI_STATUS 0x2C04 |
| 1178 | #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 |
| 1179 | #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C |
| 1180 | #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 |
| 1181 | #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 |
| 1182 | #define BGE_RBDI_STD_REPL_THRESH 0x2C18 |
| 1183 | #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C |
| 1184 | |
| 1185 | #define BGE_STD_REPL_LWM 0x2D00 |
| 1186 | #define BGE_JUMBO_REPL_LWM 0x2D04 |
| 1187 | |
| 1188 | /* Receive BD Initiator Mode register */ |
| 1189 | #define BGE_RBDIMODE_RESET 0x00000001 |
| 1190 | #define BGE_RBDIMODE_ENABLE 0x00000002 |
| 1191 | #define BGE_RBDIMODE_ATTN 0x00000004 |
| 1192 | |
| 1193 | /* Receive BD Initiator Status register */ |
| 1194 | #define BGE_RBDISTAT_ATTN 0x00000004 |
| 1195 | |
| 1196 | /* |
| 1197 | * Receive BD Completion Control registers |
| 1198 | */ |
| 1199 | #define BGE_RBDC_MODE 0x3000 |
| 1200 | #define BGE_RBDC_STATUS 0x3004 |
| 1201 | #define BGE_RBDC_JUMBO_BD_PROD 0x3008 |
| 1202 | #define BGE_RBDC_STD_BD_PROD 0x300C |
| 1203 | #define BGE_RBDC_MINI_BD_PROD 0x3010 |
| 1204 | |
| 1205 | /* Receive BD completion mode register */ |
| 1206 | #define BGE_RBDCMODE_RESET 0x00000001 |
| 1207 | #define BGE_RBDCMODE_ENABLE 0x00000002 |
| 1208 | #define BGE_RBDCMODE_ATTN 0x00000004 |
| 1209 | |
| 1210 | /* Receive BD completion status register */ |
| 1211 | #define BGE_RBDCSTAT_ERROR 0x00000004 |
| 1212 | |
| 1213 | /* |
| 1214 | * Receive List Selector Control registers |
| 1215 | */ |
| 1216 | #define BGE_RXLS_MODE 0x3400 |
| 1217 | #define BGE_RXLS_STATUS 0x3404 |
| 1218 | |
| 1219 | /* Receive List Selector Mode register */ |
| 1220 | #define BGE_RXLSMODE_RESET 0x00000001 |
| 1221 | #define BGE_RXLSMODE_ENABLE 0x00000002 |
| 1222 | #define BGE_RXLSMODE_ATTN 0x00000004 |
| 1223 | |
| 1224 | /* Receive List Selector Status register */ |
| 1225 | #define BGE_RXLSSTAT_ERROR 0x00000004 |
| 1226 | |
| 1227 | /* |
| 1228 | * Central Power Management Unit (CPMU) registers |
| 1229 | */ |
| 1230 | #define BGE_CPMU_CTRL 0x3600 |
| 1231 | #define BGE_CPMU_LSPD_10MB_CLK 0x3604 |
| 1232 | #define BGE_CPMU_LSPD_1000MB_CLK 0x360C |
| 1233 | #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 |
| 1234 | #define BGE_CPMU_HST_ACC 0x361C |
| 1235 | #define BGE_CPMU_CLCK_ORIDE 0x3624 |
| 1236 | #define BGE_CPMU_CLCK_STAT 0x3630 |
| 1237 | #define BGE_CPMU_MUTEX_REQ 0x365C |
| 1238 | #define BGE_CPMU_MUTEX_GNT 0x3660 |
| 1239 | #define BGE_CPMU_PHY_STRAP 0x3664 |
| 1240 | #define BGE_CPMU_PADRNG_CTL 0x3668 |
| 1241 | |
| 1242 | /* CPMU Control register */ |
| 1243 | #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 |
| 1244 | #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 |
| 1245 | #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 |
| 1246 | #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 |
| 1247 | |
| 1248 | /* Link Speed 10MB/No Link Power Mode Clock Policy register */ |
| 1249 | #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 |
| 1250 | #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 |
| 1251 | |
| 1252 | /* Link Speed 1000MB Power Mode Clock Policy register */ |
| 1253 | #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 |
| 1254 | #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 |
| 1255 | #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 |
| 1256 | |
| 1257 | /* Link Aware Power Mode Clock Policy register */ |
| 1258 | #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 |
| 1259 | #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 |
| 1260 | |
| 1261 | #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 |
| 1262 | #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 |
| 1263 | |
| 1264 | /* Clock Speed Override Policy register */ |
| 1265 | #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 |
| 1266 | |
| 1267 | /* CPMU Clock Status register */ |
| 1268 | #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 |
| 1269 | #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 |
| 1270 | #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 |
| 1271 | #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 |
| 1272 | |
| 1273 | /* CPMU Mutex Request register */ |
| 1274 | #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 |
| 1275 | #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 |
| 1276 | |
| 1277 | /* CPMU GPHY Strap register */ |
| 1278 | #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 |
| 1279 | |
| 1280 | /* CPMU Padring Control register */ |
| 1281 | #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 |
| 1282 | |
| 1283 | /* |
| 1284 | * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) |
| 1285 | */ |
| 1286 | #define BGE_MBCF_MODE 0x3800 |
| 1287 | #define BGE_MBCF_STATUS 0x3804 |
| 1288 | |
| 1289 | /* Mbuf Cluster Free mode register */ |
| 1290 | #define BGE_MBCFMODE_RESET 0x00000001 |
| 1291 | #define BGE_MBCFMODE_ENABLE 0x00000002 |
| 1292 | #define BGE_MBCFMODE_ATTN 0x00000004 |
| 1293 | |
| 1294 | /* Mbuf Cluster Free status register */ |
| 1295 | #define BGE_MBCFSTAT_ERROR 0x00000004 |
| 1296 | |
| 1297 | /* |
| 1298 | * Host Coalescing Control registers |
| 1299 | */ |
| 1300 | #define BGE_HCC_MODE 0x3C00 |
| 1301 | #define BGE_HCC_STATUS 0x3C04 |
| 1302 | #define BGE_HCC_RX_COAL_TICKS 0x3C08 |
| 1303 | #define BGE_HCC_TX_COAL_TICKS 0x3C0C |
| 1304 | #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 |
| 1305 | #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 |
| 1306 | #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ |
| 1307 | #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ |
| 1308 | #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ |
| 1309 | #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ |
| 1310 | #define BGE_HCC_STATS_TICKS 0x3C28 |
| 1311 | #define BGE_HCC_STATS_ADDR_HI 0x3C30 |
| 1312 | #define BGE_HCC_STATS_ADDR_LO 0x3C34 |
| 1313 | #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 |
| 1314 | #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C |
| 1315 | #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ |
| 1316 | #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ |
| 1317 | #define BGE_FLOW_ATTN 0x3C48 |
| 1318 | #define BGE_HCC_JUMBO_BD_CONS 0x3C50 |
| 1319 | #define BGE_HCC_STD_BD_CONS 0x3C54 |
| 1320 | #define BGE_HCC_MINI_BD_CONS 0x3C58 |
| 1321 | #define BGE_HCC_RX_RETURN_PROD0 0x3C80 |
| 1322 | #define BGE_HCC_RX_RETURN_PROD1 0x3C84 |
| 1323 | #define BGE_HCC_RX_RETURN_PROD2 0x3C88 |
| 1324 | #define BGE_HCC_RX_RETURN_PROD3 0x3C8C |
| 1325 | #define BGE_HCC_RX_RETURN_PROD4 0x3C90 |
| 1326 | #define BGE_HCC_RX_RETURN_PROD5 0x3C94 |
| 1327 | #define BGE_HCC_RX_RETURN_PROD6 0x3C98 |
| 1328 | #define BGE_HCC_RX_RETURN_PROD7 0x3C9C |
| 1329 | #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 |
| 1330 | #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 |
| 1331 | #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 |
| 1332 | #define BGE_HCC_RX_RETURN_PROD11 0x3CAC |
| 1333 | #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 |
| 1334 | #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 |
| 1335 | #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 |
| 1336 | #define BGE_HCC_RX_RETURN_PROD15 0x3CBC |
| 1337 | #define BGE_HCC_TX_BD_CONS0 0x3CC0 |
| 1338 | #define BGE_HCC_TX_BD_CONS1 0x3CC4 |
| 1339 | #define BGE_HCC_TX_BD_CONS2 0x3CC8 |
| 1340 | #define BGE_HCC_TX_BD_CONS3 0x3CCC |
| 1341 | #define BGE_HCC_TX_BD_CONS4 0x3CD0 |
| 1342 | #define BGE_HCC_TX_BD_CONS5 0x3CD4 |
| 1343 | #define BGE_HCC_TX_BD_CONS6 0x3CD8 |
| 1344 | #define BGE_HCC_TX_BD_CONS7 0x3CDC |
| 1345 | #define BGE_HCC_TX_BD_CONS8 0x3CE0 |
| 1346 | #define BGE_HCC_TX_BD_CONS9 0x3CE4 |
| 1347 | #define BGE_HCC_TX_BD_CONS10 0x3CE8 |
| 1348 | #define BGE_HCC_TX_BD_CONS11 0x3CEC |
| 1349 | #define BGE_HCC_TX_BD_CONS12 0x3CF0 |
| 1350 | #define BGE_HCC_TX_BD_CONS13 0x3CF4 |
| 1351 | #define BGE_HCC_TX_BD_CONS14 0x3CF8 |
| 1352 | #define BGE_HCC_TX_BD_CONS15 0x3CFC |
| 1353 | |
| 1354 | |
| 1355 | /* Host coalescing mode register */ |
| 1356 | #define BGE_HCCMODE_RESET 0x00000001 |
| 1357 | #define BGE_HCCMODE_ENABLE 0x00000002 |
| 1358 | #define BGE_HCCMODE_ATTN 0x00000004 |
| 1359 | #define BGE_HCCMODE_COAL_NOW 0x00000008 |
| 1360 | #define BGE_HCCMODE_MSI_BITS 0x00000070 |
| 1361 | #define BGE_HCCMODE_64BYTE 0x00000080 |
| 1362 | #define BGE_HCCMODE_32BYTE 0x00000100 |
| 1363 | #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 |
| 1364 | #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 |
| 1365 | #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 |
| 1366 | #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 |
| 1367 | |
| 1368 | #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 |
| 1369 | |
| 1370 | #define BGE_STATBLKSZ_FULL 0x00000000 |
| 1371 | #define BGE_STATBLKSZ_64BYTE 0x00000080 |
| 1372 | #define BGE_STATBLKSZ_32BYTE 0x00000100 |
| 1373 | |
| 1374 | /* Host coalescing status register */ |
| 1375 | #define BGE_HCCSTAT_ERROR 0x00000004 |
| 1376 | |
| 1377 | /* Flow attention register */ |
| 1378 | #define BGE_FLOWATTN_MB_LOWAT 0x00000040 |
| 1379 | #define BGE_FLOWATTN_MEMARB 0x00000080 |
| 1380 | #define BGE_FLOWATTN_HOSTCOAL 0x00008000 |
| 1381 | #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 |
| 1382 | #define BGE_FLOWATTN_RCB_INVAL 0x00020000 |
| 1383 | #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 |
| 1384 | #define BGE_FLOWATTN_RDBDI 0x00080000 |
| 1385 | #define BGE_FLOWATTN_RXLS 0x00100000 |
| 1386 | #define BGE_FLOWATTN_RXLP 0x00200000 |
| 1387 | #define BGE_FLOWATTN_RBDC 0x00400000 |
| 1388 | #define BGE_FLOWATTN_RBDI 0x00800000 |
| 1389 | #define BGE_FLOWATTN_SDC 0x08000000 |
| 1390 | #define BGE_FLOWATTN_SDI 0x10000000 |
| 1391 | #define BGE_FLOWATTN_SRS 0x20000000 |
| 1392 | #define BGE_FLOWATTN_SBDC 0x40000000 |
| 1393 | #define BGE_FLOWATTN_SBDI 0x80000000 |
| 1394 | |
| 1395 | /* |
| 1396 | * Memory arbiter registers |
| 1397 | */ |
| 1398 | #define BGE_MARB_MODE 0x4000 |
| 1399 | #define BGE_MARB_STATUS 0x4004 |
| 1400 | #define BGE_MARB_TRAPADDR_HI 0x4008 |
| 1401 | #define BGE_MARB_TRAPADDR_LO 0x400C |
| 1402 | |
| 1403 | /* Memory arbiter mode register */ |
| 1404 | #define BGE_MARBMODE_RESET 0x00000001 |
| 1405 | #define BGE_MARBMODE_ENABLE 0x00000002 |
| 1406 | #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 |
| 1407 | #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 |
| 1408 | #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 |
| 1409 | #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 |
| 1410 | #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 |
| 1411 | #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 |
| 1412 | #define BGE_MARBMODE_PCI_TRAP 0x00000100 |
| 1413 | #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 |
| 1414 | #define BGE_MARBMODE_RXQ_TRAP 0x00000400 |
| 1415 | #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 |
| 1416 | #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 |
| 1417 | #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 |
| 1418 | #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 |
| 1419 | #define BGE_MARBMODE_MBUF_TRAP 0x00008000 |
| 1420 | #define BGE_MARBMODE_TXDI_TRAP 0x00010000 |
| 1421 | #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 |
| 1422 | #define BGE_MARBMODE_TXBD_TRAP 0x00040000 |
| 1423 | #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 |
| 1424 | #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 |
| 1425 | #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 |
| 1426 | #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 |
| 1427 | #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 |
| 1428 | #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 |
| 1429 | #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 |
| 1430 | |
| 1431 | /* Memory arbiter status register */ |
| 1432 | #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 |
| 1433 | #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 |
| 1434 | #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 |
| 1435 | #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 |
| 1436 | #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 |
| 1437 | #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 |
| 1438 | #define BGE_MARBSTAT_PCI_TRAP 0x00000100 |
| 1439 | #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 |
| 1440 | #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 |
| 1441 | #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 |
| 1442 | #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 |
| 1443 | #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 |
| 1444 | #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 |
| 1445 | #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 |
| 1446 | #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 |
| 1447 | #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 |
| 1448 | #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 |
| 1449 | #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 |
| 1450 | #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 |
| 1451 | #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 |
| 1452 | #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 |
| 1453 | #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 |
| 1454 | #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 |
| 1455 | #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 |
| 1456 | |
| 1457 | /* |
| 1458 | * Buffer manager control registers |
| 1459 | */ |
| 1460 | #define BGE_BMAN_MODE 0x4400 |
| 1461 | #define BGE_BMAN_STATUS 0x4404 |
| 1462 | #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 |
| 1463 | #define BGE_BMAN_MBUFPOOL_LEN 0x440C |
| 1464 | #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 |
| 1465 | #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 |
| 1466 | #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 |
| 1467 | #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C |
| 1468 | #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 |
| 1469 | #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 |
| 1470 | #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 |
| 1471 | #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C |
| 1472 | #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 |
| 1473 | #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 |
| 1474 | #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 |
| 1475 | #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C |
| 1476 | #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 |
| 1477 | #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 |
| 1478 | #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 |
| 1479 | #define BGE_BMAN_HWDIAG_1 0x444C |
| 1480 | #define BGE_BMAN_HWDIAG_2 0x4450 |
| 1481 | #define BGE_BMAN_HWDIAG_3 0x4454 |
| 1482 | |
| 1483 | /* Buffer manager mode register */ |
| 1484 | #define BGE_BMANMODE_RESET 0x00000001 |
| 1485 | #define BGE_BMANMODE_ENABLE 0x00000002 |
| 1486 | #define BGE_BMANMODE_ATTN 0x00000004 |
| 1487 | #define BGE_BMANMODE_TESTMODE 0x00000008 |
| 1488 | #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 |
| 1489 | #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 |
| 1490 | |
| 1491 | /* Buffer manager status register */ |
| 1492 | #define BGE_BMANSTAT_ERRO 0x00000004 |
| 1493 | #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 |
| 1494 | |
| 1495 | /* |
| 1496 | * Read DMA Control registers |
| 1497 | */ |
| 1498 | #define BGE_RDMA_MODE 0x4800 |
| 1499 | #define BGE_RDMA_STATUS 0x4804 |
| 1500 | #define BGE_RDMA_RSRVCTRL 0x4900 |
| 1501 | #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 |
| 1502 | |
| 1503 | /* Read DMA mode register */ |
| 1504 | #define BGE_RDMAMODE_RESET 0x00000001 |
| 1505 | #define BGE_RDMAMODE_ENABLE 0x00000002 |
| 1506 | #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1507 | #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1508 | #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 |
| 1509 | #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 |
| 1510 | #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 |
| 1511 | #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 |
| 1512 | #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 |
| 1513 | #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 |
| 1514 | #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC |
| 1515 | #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 |
| 1516 | #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 |
| 1517 | #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 |
| 1518 | #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 |
| 1519 | #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 |
| 1520 | #define BGE_RDMAMODE_JMB_2K_MMRR 0x00800000 |
| 1521 | #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 |
| 1522 | #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 |
| 1523 | #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 |
| 1524 | #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 |
| 1525 | |
| 1526 | /* Read DMA status register */ |
| 1527 | #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1528 | #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1529 | #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 |
| 1530 | #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 |
| 1531 | #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 |
| 1532 | #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 |
| 1533 | #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 |
| 1534 | #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 |
| 1535 | |
| 1536 | /* Read DMA Reserved Control register */ |
| 1537 | #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 |
| 1538 | #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 |
| 1539 | #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 |
| 1540 | #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 |
| 1541 | #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 |
| 1542 | #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 |
| 1543 | #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 |
| 1544 | |
| 1545 | /* Read DMA Corruption Enable Control register */ |
| 1546 | #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 |
| 1547 | #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 |
| 1548 | #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 |
| 1549 | |
| 1550 | /* |
| 1551 | * Write DMA control registers |
| 1552 | */ |
| 1553 | #define BGE_WDMA_MODE 0x4C00 |
| 1554 | #define BGE_WDMA_STATUS 0x4C04 |
| 1555 | |
| 1556 | /* Write DMA mode register */ |
| 1557 | #define BGE_WDMAMODE_RESET 0x00000001 |
| 1558 | #define BGE_WDMAMODE_ENABLE 0x00000002 |
| 1559 | #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1560 | #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1561 | #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 |
| 1562 | #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 |
| 1563 | #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 |
| 1564 | #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 |
| 1565 | #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 |
| 1566 | #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 |
| 1567 | #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC |
| 1568 | #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 |
| 1569 | #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 |
| 1570 | |
| 1571 | /* Write DMA status register */ |
| 1572 | #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1573 | #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1574 | #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 |
| 1575 | #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 |
| 1576 | #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 |
| 1577 | #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 |
| 1578 | #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 |
| 1579 | #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 |
| 1580 | |
| 1581 | |
| 1582 | /* |
| 1583 | * RX CPU registers |
| 1584 | */ |
| 1585 | #define BGE_RXCPU_MODE 0x5000 |
| 1586 | #define BGE_RXCPU_STATUS 0x5004 |
| 1587 | #define BGE_RXCPU_PC 0x501C |
| 1588 | |
| 1589 | /* RX CPU mode register */ |
| 1590 | #define BGE_RXCPUMODE_RESET 0x00000001 |
| 1591 | #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 |
| 1592 | #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 |
| 1593 | #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 |
| 1594 | #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 |
| 1595 | #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 |
| 1596 | #define BGE_RXCPUMODE_ROMFAIL 0x00000040 |
| 1597 | #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 |
| 1598 | #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 |
| 1599 | #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 |
| 1600 | #define BGE_RXCPUMODE_HALTCPU 0x00000400 |
| 1601 | #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 |
| 1602 | #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 |
| 1603 | #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 |
| 1604 | |
| 1605 | /* RX CPU status register */ |
| 1606 | #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 |
| 1607 | #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 |
| 1608 | #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 |
| 1609 | #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 |
| 1610 | #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 |
| 1611 | #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 |
| 1612 | #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 |
| 1613 | #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 |
| 1614 | #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 |
| 1615 | #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 |
| 1616 | #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 |
| 1617 | #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 |
| 1618 | #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 |
| 1619 | #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 |
| 1620 | #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 |
| 1621 | #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 |
| 1622 | #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 |
| 1623 | |
| 1624 | /* |
| 1625 | * V? CPU registers |
| 1626 | */ |
| 1627 | #define BGE_VCPU_STATUS 0x5100 |
| 1628 | #define BGE_VCPU_EXT_CTRL 0x6890 |
| 1629 | |
| 1630 | #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 |
| 1631 | #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 |
| 1632 | |
| 1633 | #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 |
| 1634 | #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 |
| 1635 | |
| 1636 | /* |
| 1637 | * TX CPU registers |
| 1638 | */ |
| 1639 | #define BGE_TXCPU_MODE 0x5400 |
| 1640 | #define BGE_TXCPU_STATUS 0x5404 |
| 1641 | #define BGE_TXCPU_PC 0x541C |
| 1642 | |
| 1643 | /* TX CPU mode register */ |
| 1644 | #define BGE_TXCPUMODE_RESET 0x00000001 |
| 1645 | #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 |
| 1646 | #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 |
| 1647 | #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 |
| 1648 | #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 |
| 1649 | #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 |
| 1650 | #define BGE_TXCPUMODE_ROMFAIL 0x00000040 |
| 1651 | #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 |
| 1652 | #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 |
| 1653 | #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 |
| 1654 | #define BGE_TXCPUMODE_HALTCPU 0x00000400 |
| 1655 | #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 |
| 1656 | #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 |
| 1657 | |
| 1658 | /* TX CPU status register */ |
| 1659 | #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 |
| 1660 | #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 |
| 1661 | #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 |
| 1662 | #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 |
| 1663 | #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 |
| 1664 | #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 |
| 1665 | #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 |
| 1666 | #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 |
| 1667 | #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 |
| 1668 | #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 |
| 1669 | #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 |
| 1670 | #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 |
| 1671 | #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 |
| 1672 | #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 |
| 1673 | #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 |
| 1674 | #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 |
| 1675 | #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 |
| 1676 | |
| 1677 | |
| 1678 | /* |
| 1679 | * Low priority mailbox registers |
| 1680 | */ |
| 1681 | #define BGE_LPMBX_IRQ0_HI 0x5800 |
| 1682 | #define BGE_LPMBX_IRQ0_LO 0x5804 |
| 1683 | #define BGE_LPMBX_IRQ1_HI 0x5808 |
| 1684 | #define BGE_LPMBX_IRQ1_LO 0x580C |
| 1685 | #define BGE_LPMBX_IRQ2_HI 0x5810 |
| 1686 | #define BGE_LPMBX_IRQ2_LO 0x5814 |
| 1687 | #define BGE_LPMBX_IRQ3_HI 0x5818 |
| 1688 | #define BGE_LPMBX_IRQ3_LO 0x581C |
| 1689 | #define BGE_LPMBX_GEN0_HI 0x5820 |
| 1690 | #define BGE_LPMBX_GEN0_LO 0x5824 |
| 1691 | #define BGE_LPMBX_GEN1_HI 0x5828 |
| 1692 | #define BGE_LPMBX_GEN1_LO 0x582C |
| 1693 | #define BGE_LPMBX_GEN2_HI 0x5830 |
| 1694 | #define BGE_LPMBX_GEN2_LO 0x5834 |
| 1695 | #define BGE_LPMBX_GEN3_HI 0x5828 |
| 1696 | #define BGE_LPMBX_GEN3_LO 0x582C |
| 1697 | #define BGE_LPMBX_GEN4_HI 0x5840 |
| 1698 | #define BGE_LPMBX_GEN4_LO 0x5844 |
| 1699 | #define BGE_LPMBX_GEN5_HI 0x5848 |
| 1700 | #define BGE_LPMBX_GEN5_LO 0x584C |
| 1701 | #define BGE_LPMBX_GEN6_HI 0x5850 |
| 1702 | #define BGE_LPMBX_GEN6_LO 0x5854 |
| 1703 | #define BGE_LPMBX_GEN7_HI 0x5858 |
| 1704 | #define BGE_LPMBX_GEN7_LO 0x585C |
| 1705 | #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 |
| 1706 | #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 |
| 1707 | #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 |
| 1708 | #define BGE_LPMBX_RX_STD_PROD_LO 0x586C |
| 1709 | #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 |
| 1710 | #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 |
| 1711 | #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 |
| 1712 | #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C |
| 1713 | #define BGE_LPMBX_RX_CONS0_HI 0x5880 |
| 1714 | #define BGE_LPMBX_RX_CONS0_LO 0x5884 |
| 1715 | #define BGE_LPMBX_RX_CONS1_HI 0x5888 |
| 1716 | #define BGE_LPMBX_RX_CONS1_LO 0x588C |
| 1717 | #define BGE_LPMBX_RX_CONS2_HI 0x5890 |
| 1718 | #define BGE_LPMBX_RX_CONS2_LO 0x5894 |
| 1719 | #define BGE_LPMBX_RX_CONS3_HI 0x5898 |
| 1720 | #define BGE_LPMBX_RX_CONS3_LO 0x589C |
| 1721 | #define BGE_LPMBX_RX_CONS4_HI 0x58A0 |
| 1722 | #define BGE_LPMBX_RX_CONS4_LO 0x58A4 |
| 1723 | #define BGE_LPMBX_RX_CONS5_HI 0x58A8 |
| 1724 | #define BGE_LPMBX_RX_CONS5_LO 0x58AC |
| 1725 | #define BGE_LPMBX_RX_CONS6_HI 0x58B0 |
| 1726 | #define BGE_LPMBX_RX_CONS6_LO 0x58B4 |
| 1727 | #define BGE_LPMBX_RX_CONS7_HI 0x58B8 |
| 1728 | #define BGE_LPMBX_RX_CONS7_LO 0x58BC |
| 1729 | #define BGE_LPMBX_RX_CONS8_HI 0x58C0 |
| 1730 | #define BGE_LPMBX_RX_CONS8_LO 0x58C4 |
| 1731 | #define BGE_LPMBX_RX_CONS9_HI 0x58C8 |
| 1732 | #define BGE_LPMBX_RX_CONS9_LO 0x58CC |
| 1733 | #define BGE_LPMBX_RX_CONS10_HI 0x58D0 |
| 1734 | #define BGE_LPMBX_RX_CONS10_LO 0x58D4 |
| 1735 | #define BGE_LPMBX_RX_CONS11_HI 0x58D8 |
| 1736 | #define BGE_LPMBX_RX_CONS11_LO 0x58DC |
| 1737 | #define BGE_LPMBX_RX_CONS12_HI 0x58E0 |
| 1738 | #define BGE_LPMBX_RX_CONS12_LO 0x58E4 |
| 1739 | #define BGE_LPMBX_RX_CONS13_HI 0x58E8 |
| 1740 | #define BGE_LPMBX_RX_CONS13_LO 0x58EC |
| 1741 | #define BGE_LPMBX_RX_CONS14_HI 0x58F0 |
| 1742 | #define BGE_LPMBX_RX_CONS14_LO 0x58F4 |
| 1743 | #define BGE_LPMBX_RX_CONS15_HI 0x58F8 |
| 1744 | #define BGE_LPMBX_RX_CONS15_LO 0x58FC |
| 1745 | #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 |
| 1746 | #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 |
| 1747 | #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 |
| 1748 | #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C |
| 1749 | #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 |
| 1750 | #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 |
| 1751 | #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 |
| 1752 | #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C |
| 1753 | #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 |
| 1754 | #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 |
| 1755 | #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 |
| 1756 | #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C |
| 1757 | #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 |
| 1758 | #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 |
| 1759 | #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 |
| 1760 | #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C |
| 1761 | #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 |
| 1762 | #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 |
| 1763 | #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 |
| 1764 | #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C |
| 1765 | #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 |
| 1766 | #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 |
| 1767 | #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 |
| 1768 | #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C |
| 1769 | #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 |
| 1770 | #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 |
| 1771 | #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 |
| 1772 | #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C |
| 1773 | #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 |
| 1774 | #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 |
| 1775 | #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 |
| 1776 | #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C |
| 1777 | #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 |
| 1778 | #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 |
| 1779 | #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 |
| 1780 | #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C |
| 1781 | #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 |
| 1782 | #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 |
| 1783 | #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 |
| 1784 | #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C |
| 1785 | #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 |
| 1786 | #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 |
| 1787 | #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 |
| 1788 | #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC |
| 1789 | #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 |
| 1790 | #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 |
| 1791 | #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 |
| 1792 | #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC |
| 1793 | #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 |
| 1794 | #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 |
| 1795 | #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 |
| 1796 | #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC |
| 1797 | #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 |
| 1798 | #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 |
| 1799 | #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 |
| 1800 | #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC |
| 1801 | #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 |
| 1802 | #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 |
| 1803 | #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 |
| 1804 | #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC |
| 1805 | #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 |
| 1806 | #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 |
| 1807 | #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 |
| 1808 | #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC |
| 1809 | |
| 1810 | /* |
| 1811 | * Flow throw Queue reset register |
| 1812 | */ |
| 1813 | #define BGE_FTQ_RESET 0x5C00 |
| 1814 | |
| 1815 | #define BGE_FTQRESET_DMAREAD 0x00000002 |
| 1816 | #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 |
| 1817 | #define BGE_FTQRESET_DMADONE 0x00000010 |
| 1818 | #define BGE_FTQRESET_SBDC 0x00000020 |
| 1819 | #define BGE_FTQRESET_SDI 0x00000040 |
| 1820 | #define BGE_FTQRESET_WDMA 0x00000080 |
| 1821 | #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 |
| 1822 | #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 |
| 1823 | #define BGE_FTQRESET_SDC 0x00000400 |
| 1824 | #define BGE_FTQRESET_HCC 0x00000800 |
| 1825 | #define BGE_FTQRESET_TXFIFO 0x00001000 |
| 1826 | #define BGE_FTQRESET_MBC 0x00002000 |
| 1827 | #define BGE_FTQRESET_RBDC 0x00004000 |
| 1828 | #define BGE_FTQRESET_RXLP 0x00008000 |
| 1829 | #define BGE_FTQRESET_RDBDI 0x00010000 |
| 1830 | #define BGE_FTQRESET_RDC 0x00020000 |
| 1831 | #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 |
| 1832 | |
| 1833 | /* |
| 1834 | * Message Signaled Interrupt registers |
| 1835 | */ |
| 1836 | #define BGE_MSI_MODE 0x6000 |
| 1837 | #define BGE_MSI_STATUS 0x6004 |
| 1838 | #define BGE_MSI_FIFOACCESS 0x6008 |
| 1839 | |
| 1840 | /* MSI mode register */ |
| 1841 | #define BGE_MSIMODE_RESET 0x00000001 |
| 1842 | #define BGE_MSIMODE_ENABLE 0x00000002 |
| 1843 | #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1844 | #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1845 | #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 |
| 1846 | #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 |
| 1847 | #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 |
| 1848 | |
| 1849 | /* MSI status register */ |
| 1850 | #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 |
| 1851 | #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 |
| 1852 | #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 |
| 1853 | #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 |
| 1854 | #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 |
| 1855 | |
| 1856 | |
| 1857 | /* |
| 1858 | * DMA Completion registers |
| 1859 | */ |
| 1860 | #define BGE_DMAC_MODE 0x6400 |
| 1861 | |
| 1862 | /* DMA Completion mode register */ |
| 1863 | #define BGE_DMACMODE_RESET 0x00000001 |
| 1864 | #define BGE_DMACMODE_ENABLE 0x00000002 |
| 1865 | |
| 1866 | |
| 1867 | /* |
| 1868 | * General control registers. |
| 1869 | */ |
| 1870 | #define BGE_MODE_CTL 0x6800 |
| 1871 | #define BGE_MISC_CFG 0x6804 |
| 1872 | #define BGE_MISC_LOCAL_CTL 0x6808 |
| 1873 | #define BGE_RX_CPU_EVENT 0x6810 |
| 1874 | #define BGE_TX_CPU_EVENT 0x6820 |
| 1875 | #define BGE_EE_ADDR 0x6838 |
| 1876 | #define BGE_EE_DATA 0x683C |
| 1877 | #define BGE_EE_CTL 0x6840 |
| 1878 | #define BGE_MDI_CTL 0x6844 |
| 1879 | #define BGE_EE_DELAY 0x6848 |
| 1880 | #define BGE_FASTBOOT_PC 0x6894 |
| 1881 | |
| 1882 | #define BGE_RX_CPU_DRV_EVENT 0x00004000 |
| 1883 | |
| 1884 | /* |
| 1885 | * NVRAM Control registers |
| 1886 | */ |
| 1887 | #define BGE_NVRAM_CMD 0x7000 |
| 1888 | #define BGE_NVRAM_STAT 0x7004 |
| 1889 | #define BGE_NVRAM_WRDATA 0x7008 |
| 1890 | #define BGE_NVRAM_ADDR 0x700c |
| 1891 | #define BGE_NVRAM_RDDATA 0x7010 |
| 1892 | #define BGE_NVRAM_CFG1 0x7014 |
| 1893 | #define BGE_NVRAM_CFG2 0x7018 |
| 1894 | #define BGE_NVRAM_CFG3 0x701c |
| 1895 | #define BGE_NVRAM_SWARB 0x7020 |
| 1896 | #define BGE_NVRAM_ACCESS 0x7024 |
| 1897 | #define BGE_NVRAM_WRITE1 0x7028 |
| 1898 | |
| 1899 | #define BGE_NVRAMCMD_RESET 0x00000001 |
| 1900 | #define BGE_NVRAMCMD_DONE 0x00000008 |
| 1901 | #define BGE_NVRAMCMD_START 0x00000010 |
| 1902 | #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ |
| 1903 | #define BGE_NVRAMCMD_ERASE 0x00000040 |
| 1904 | #define BGE_NVRAMCMD_FIRST 0x00000080 |
| 1905 | #define BGE_NVRAMCMD_LAST 0x00000100 |
| 1906 | |
| 1907 | #define BGE_NVRAM_READCMD \ |
| 1908 | (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ |
| 1909 | BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) |
| 1910 | #define BGE_NVRAM_WRITECMD \ |
| 1911 | (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ |
| 1912 | BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) |
| 1913 | |
| 1914 | #define BGE_NVRAMSWARB_SET0 0x00000001 |
| 1915 | #define BGE_NVRAMSWARB_SET1 0x00000002 |
| 1916 | #define BGE_NVRAMSWARB_SET2 0x00000003 |
| 1917 | #define BGE_NVRAMSWARB_SET3 0x00000004 |
| 1918 | #define BGE_NVRAMSWARB_CLR0 0x00000010 |
| 1919 | #define BGE_NVRAMSWARB_CLR1 0x00000020 |
| 1920 | #define BGE_NVRAMSWARB_CLR2 0x00000040 |
| 1921 | #define BGE_NVRAMSWARB_CLR3 0x00000080 |
| 1922 | #define BGE_NVRAMSWARB_GNT0 0x00000100 |
| 1923 | #define BGE_NVRAMSWARB_GNT1 0x00000200 |
| 1924 | #define BGE_NVRAMSWARB_GNT2 0x00000400 |
| 1925 | #define BGE_NVRAMSWARB_GNT3 0x00000800 |
| 1926 | #define BGE_NVRAMSWARB_REQ0 0x00001000 |
| 1927 | #define BGE_NVRAMSWARB_REQ1 0x00002000 |
| 1928 | #define BGE_NVRAMSWARB_REQ2 0x00004000 |
| 1929 | #define BGE_NVRAMSWARB_REQ3 0x00008000 |
| 1930 | |
| 1931 | #define BGE_NVRAMACC_ENABLE 0x00000001 |
| 1932 | #define BGE_NVRAMACC_WRENABLE 0x00000002 |
| 1933 | |
| 1934 | /* |
| 1935 | * TLP Control Register |
| 1936 | * Applicable to BCM5721 and BCM5751 only |
| 1937 | */ |
| 1938 | #define BGE_TLP_CONTROL_REG 0x7c00 |
| 1939 | #define BGE_TLP_FTSMAX 0x000c |
| 1940 | #define BGE_TLP_FTSMAX_MSK 0x000000ff |
| 1941 | #define BGE_TLP_FTSMAX_VAL 0x0000002c |
| 1942 | #define BGE_TLP_PHYCTL1 0x0004 |
| 1943 | #define BGE_TLP_PHYCTL1_EN_L1PLLPD 0x00001000 |
| 1944 | #define BGE_TLP_PHYCTL5 0x0014 |
| 1945 | #define BGE_TLP_PHYCTL5_DIS_L2CLKREQ 0x80000000 |
| 1946 | #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 |
| 1947 | |
| 1948 | /* |
| 1949 | * PHY Test Control Register |
| 1950 | * Applicable to BCM5721 and BCM5751 only |
| 1951 | */ |
| 1952 | #define BGE_PHY_TEST_CTRL_REG 0x7e2c |
| 1953 | #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 |
| 1954 | #define BGE_PHY_PCIE_LTASS_MODE 0x0040 |
| 1955 | |
| 1956 | /* Mode control register */ |
| 1957 | #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 |
| 1958 | #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 |
| 1959 | #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 |
| 1960 | #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 |
| 1961 | #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 |
| 1962 | #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 |
| 1963 | #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 |
| 1964 | #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 |
| 1965 | #define BGE_MODECTL_NO_RX_CRC 0x00000400 |
| 1966 | #define BGE_MODECTL_RX_BADFRAMES 0x00000800 |
| 1967 | #define BGE_MODECTL_NO_TX_INTR 0x00002000 |
| 1968 | #define BGE_MODECTL_NO_RX_INTR 0x00004000 |
| 1969 | #define BGE_MODECTL_FORCE_PCI32 0x00008000 |
| 1970 | #define BGE_MODECTL_B2HRX_ENABLE 0x00008000 |
| 1971 | #define BGE_MODECTL_STACKUP 0x00010000 |
| 1972 | #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 |
| 1973 | #define BGE_MODECTL_HTX2B_ENABLE 0x00040000 |
| 1974 | #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 |
| 1975 | #define BGE_MODECTL_PCIE_TLPADDR1 0x00400000 |
| 1976 | #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 |
| 1977 | #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 |
| 1978 | #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 |
| 1979 | #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 |
| 1980 | #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 |
| 1981 | #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 |
| 1982 | #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 |
| 1983 | #define BGE_MODECTL_PCIE_TLPADDR0 0x20000000 |
| 1984 | #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 |
| 1985 | #define BGE_MODECTL_PCIE_TLPADDR2 0x80000000 |
| 1986 | #define BGE_MODECTL_PCIE_TLPADDRMASK (BGE_MODECTL_PCIE_TLPADDR2 | \ |
| 1987 | BGE_MODECTL_PCIE_TLPADDR1 | \ |
| 1988 | BGE_MODECTL_PCIE_TLPADDR0) |
| 1989 | |
| 1990 | /* Misc. config register */ |
| 1991 | #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 |
| 1992 | #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE |
| 1993 | #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 |
| 1994 | #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 |
| 1995 | #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 |
| 1996 | #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 |
| 1997 | #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 |
| 1998 | #define BGE_MISCCFG_GRC_RESET_DISABLE 0x20000000 |
| 1999 | |
| 2000 | #define BGE_32BITTIME_66MHZ (0x41 << 1) |
| 2001 | |
| 2002 | /* Misc. Local Control */ |
| 2003 | #define BGE_MLC_INTR_STATE 0x00000001 |
| 2004 | #define BGE_MLC_INTR_CLR 0x00000002 |
| 2005 | #define BGE_MLC_INTR_SET 0x00000004 |
| 2006 | #define BGE_MLC_INTR_ONATTN 0x00000008 |
| 2007 | #define BGE_MLC_MISCIO_IN0 0x00000100 |
| 2008 | #define BGE_MLC_MISCIO_IN1 0x00000200 |
| 2009 | #define BGE_MLC_MISCIO_IN2 0x00000400 |
| 2010 | #define BGE_MLC_MISCIO_OUTEN0 0x00000800 |
| 2011 | #define BGE_MLC_MISCIO_OUTEN1 0x00001000 |
| 2012 | #define BGE_MLC_MISCIO_OUTEN2 0x00002000 |
| 2013 | #define BGE_MLC_MISCIO_OUT0 0x00004000 |
| 2014 | #define BGE_MLC_MISCIO_OUT1 0x00008000 |
| 2015 | #define BGE_MLC_MISCIO_OUT2 0x00010000 |
| 2016 | #define 0x00020000 |
| 2017 | #define BGE_MLC_SRAM_SIZE 0x001C0000 |
| 2018 | #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ |
| 2019 | #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ |
| 2020 | #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 |
| 2021 | #define BGE_MLC_AUTO_EEPROM 0x01000000 |
| 2022 | |
| 2023 | #define BGE_SSRAMSIZE_256KB 0x00000000 |
| 2024 | #define BGE_SSRAMSIZE_512KB 0x00040000 |
| 2025 | #define BGE_SSRAMSIZE_1MB 0x00080000 |
| 2026 | #define BGE_SSRAMSIZE_2MB 0x000C0000 |
| 2027 | #define BGE_SSRAMSIZE_4MB 0x00100000 |
| 2028 | #define BGE_SSRAMSIZE_8MB 0x00140000 |
| 2029 | #define BGE_SSRAMSIZE_16M 0x00180000 |
| 2030 | |
| 2031 | /* EEPROM address register */ |
| 2032 | #define BGE_EEADDR_ADDRESS 0x0000FFFC |
| 2033 | #define BGE_EEADDR_HALFCLK 0x01FF0000 |
| 2034 | #define BGE_EEADDR_START 0x02000000 |
| 2035 | #define BGE_EEADDR_DEVID 0x1C000000 |
| 2036 | #define BGE_EEADDR_RESET 0x20000000 |
| 2037 | #define BGE_EEADDR_DONE 0x40000000 |
| 2038 | #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ |
| 2039 | |
| 2040 | #define BGE_EEDEVID(x) ((x & 7) << 26) |
| 2041 | #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) |
| 2042 | #define BGE_HALFCLK_384SCL 0x60 |
| 2043 | #define BGE_EE_READCMD \ |
| 2044 | (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ |
| 2045 | BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) |
| 2046 | #define BGE_EE_WRCMD \ |
| 2047 | (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ |
| 2048 | BGE_EEADDR_START|BGE_EEADDR_DONE) |
| 2049 | |
| 2050 | /* EEPROM Control register */ |
| 2051 | #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 |
| 2052 | #define BGE_EECTL_CLKOUT 0x00000002 |
| 2053 | #define BGE_EECTL_CLKIN 0x00000004 |
| 2054 | #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 |
| 2055 | #define BGE_EECTL_DATAOUT 0x00000010 |
| 2056 | #define BGE_EECTL_DATAIN 0x00000020 |
| 2057 | |
| 2058 | /* MDI (MII/GMII) access register */ |
| 2059 | #define BGE_MDI_DATA 0x00000001 |
| 2060 | #define BGE_MDI_DIR 0x00000002 |
| 2061 | #define BGE_MDI_SEL 0x00000004 |
| 2062 | #define BGE_MDI_CLK 0x00000008 |
| 2063 | |
| 2064 | #define BGE_MEMWIN_START 0x00008000 |
| 2065 | #define BGE_MEMWIN_END 0x0000FFFF |
| 2066 | |
| 2067 | /* BAR2 (APE) Register Definitions */ |
| 2068 | |
| 2069 | #define BGE_APE_GPIO_MSG 0x0008 |
| 2070 | #define BGE_APE_EVENT 0x000C |
| 2071 | #define BGE_APE_LOCK_REQ 0x002C |
| 2072 | #define BGE_APE_LOCK_GRANT 0x004C |
| 2073 | |
| 2074 | #define BGE_APE_GPIO_MSG_SHIFT 4 |
| 2075 | |
| 2076 | #define BGE_APE_EVENT_1 0x00000001 |
| 2077 | |
| 2078 | #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 |
| 2079 | |
| 2080 | #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 |
| 2081 | |
| 2082 | /* APE Shared Memory block (writable by APE only) */ |
| 2083 | #define BGE_APE_SEG_SIG 0x4000 |
| 2084 | #define BGE_APE_FW_STATUS 0x400C |
| 2085 | #define BGE_APE_FW_FEATURES 0x4010 |
| 2086 | #define BGE_APE_FW_BEHAVIOR 0x4014 |
| 2087 | #define BGE_APE_FW_VERSION 0x4018 |
| 2088 | #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 |
| 2089 | #define BGE_APE_FW_HEARTBEAT 0x4028 |
| 2090 | #define BGE_APE_FW_ERROR_FLAGS 0x4074 |
| 2091 | |
| 2092 | #define BGE_APE_SEG_SIG_MAGIC 0x41504521 |
| 2093 | |
| 2094 | #define BGE_APE_FW_STATUS_READY 0x00000100 |
| 2095 | |
| 2096 | #define BGE_APE_FW_FEATURE_DASH 0x00000001 |
| 2097 | #define BGE_APE_FW_FEATURE_NCSI 0x00000002 |
| 2098 | |
| 2099 | #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 |
| 2100 | #define BGE_APE_FW_VERSION_MAJSFT 24 |
| 2101 | #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 |
| 2102 | #define BGE_APE_FW_VERSION_MINSFT 16 |
| 2103 | #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 |
| 2104 | #define BGE_APE_FW_VERSION_REVSFT 8 |
| 2105 | #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF |
| 2106 | |
| 2107 | /* Host Shared Memory block (writable by host only) */ |
| 2108 | #define BGE_APE_HOST_SEG_SIG 0x4200 |
| 2109 | #define BGE_APE_HOST_SEG_LEN 0x4204 |
| 2110 | #define BGE_APE_HOST_INIT_COUNT 0x4208 |
| 2111 | #define BGE_APE_HOST_DRIVER_ID 0x420C |
| 2112 | #define BGE_APE_HOST_BEHAVIOR 0x4210 |
| 2113 | #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 |
| 2114 | #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 |
| 2115 | #define BGE_APE_HOST_DRVR_STATE 0x421C |
| 2116 | #define BGE_APE_HOST_WOL_SPEED 0x4224 |
| 2117 | |
| 2118 | #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 |
| 2119 | |
| 2120 | #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 |
| 2121 | |
| 2122 | #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 |
| 2123 | #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ |
| 2124 | (BGE_APE_HOST_DRIVER_ID_FBSD | \ |
| 2125 | ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) |
| 2126 | |
| 2127 | #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 |
| 2128 | |
| 2129 | #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 |
| 2130 | #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 |
| 2131 | |
| 2132 | #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 |
| 2133 | #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 |
| 2134 | #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 |
| 2135 | #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 |
| 2136 | |
| 2137 | #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 |
| 2138 | |
| 2139 | #define BGE_APE_EVENT_STATUS 0x4300 |
| 2140 | |
| 2141 | #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 |
| 2142 | #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 |
| 2143 | #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 |
| 2144 | #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 |
| 2145 | #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 |
| 2146 | #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 |
| 2147 | #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 |
| 2148 | |
| 2149 | #define BGE_APE_DEBUG_LOG 0x4E00 |
| 2150 | #define BGE_APE_DEBUG_LOG_LEN 0x0100 |
| 2151 | |
| 2152 | #define BGE_APE_PER_LOCK_REQ 0x8400 |
| 2153 | #define BGE_APE_PER_LOCK_GRANT 0x8420 |
| 2154 | |
| 2155 | #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 |
| 2156 | #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 |
| 2157 | #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 |
| 2158 | #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 |
| 2159 | |
| 2160 | #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 |
| 2161 | #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 |
| 2162 | #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 |
| 2163 | #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 |
| 2164 | |
| 2165 | /* APE Mutex Resources */ |
| 2166 | #define BGE_APE_LOCK_PHY0 0 |
| 2167 | #define BGE_APE_LOCK_GRC 1 |
| 2168 | #define BGE_APE_LOCK_PHY1 2 |
| 2169 | #define BGE_APE_LOCK_PHY2 3 |
| 2170 | #define BGE_APE_LOCK_MEM 4 |
| 2171 | #define BGE_APE_LOCK_PHY3 5 |
| 2172 | #define BGE_APE_LOCK_GPIO 7 |
| 2173 | |
| 2174 | #define BGE_MEMWIN_READ(pc, tag, x, val) \ |
| 2175 | do { \ |
| 2176 | pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ |
| 2177 | (0xFFFF0000 & x)); \ |
| 2178 | val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ |
| 2179 | } while(0) |
| 2180 | |
| 2181 | #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ |
| 2182 | do { \ |
| 2183 | pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ |
| 2184 | (0xFFFF0000 & x)); \ |
| 2185 | CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ |
| 2186 | } while(0) |
| 2187 | |
| 2188 | /* |
| 2189 | * This magic number is used to prevent PXE restart when we |
| 2190 | * issue a software reset. We write this magic number to the |
| 2191 | * firmware mailbox at 0xB50 in order to prevent the PXE boot |
| 2192 | * code from running. |
| 2193 | */ |
| 2194 | #define BGE_SRAM_FW_MB_MAGIC 0x4B657654 /* == ~0xB49A89AB */ |
| 2195 | |
| 2196 | typedef struct { |
| 2197 | volatile u_int32_t bge_addr_hi; |
| 2198 | volatile u_int32_t bge_addr_lo; |
| 2199 | } bge_hostaddr; |
| 2200 | |
| 2201 | /* Ring control block structure */ |
| 2202 | struct bge_rcb { |
| 2203 | bge_hostaddr bge_hostaddr; |
| 2204 | volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ |
| 2205 | volatile u_int32_t bge_nicaddr; |
| 2206 | }; |
| 2207 | |
| 2208 | #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) |
| 2209 | |
| 2210 | #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 |
| 2211 | #define BGE_RCB_FLAG_RING_DISABLED 0x0002 |
| 2212 | |
| 2213 | struct bge_tx_bd { |
| 2214 | bge_hostaddr bge_addr; |
| 2215 | #if BYTE_ORDER == BIG_ENDIAN |
| 2216 | volatile u_int16_t bge_len; |
| 2217 | volatile u_int16_t bge_flags; |
| 2218 | volatile u_int16_t bge_rsvd; |
| 2219 | volatile u_int16_t bge_vlan_tag; |
| 2220 | #else |
| 2221 | volatile u_int16_t bge_flags; |
| 2222 | volatile u_int16_t bge_len; |
| 2223 | volatile u_int16_t bge_vlan_tag; |
| 2224 | volatile u_int16_t bge_rsvd; |
| 2225 | #endif |
| 2226 | }; |
| 2227 | |
| 2228 | #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 |
| 2229 | #define BGE_TXBDFLAG_IP_CSUM 0x0002 |
| 2230 | #define BGE_TXBDFLAG_END 0x0004 |
| 2231 | #define BGE_TXBDFLAG_IP_FRAG 0x0008 |
| 2232 | #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 |
| 2233 | #define BGE_TXBDFLAG_VLAN_TAG 0x0040 |
| 2234 | #define BGE_TXBDFLAG_COAL_NOW 0x0080 |
| 2235 | #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 |
| 2236 | #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 |
| 2237 | #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 |
| 2238 | #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 |
| 2239 | #define BGE_TXBDFLAG_NO_CRC 0x8000 |
| 2240 | |
| 2241 | #define BGE_NIC_TXRING_ADDR(ringno, size) \ |
| 2242 | BGE_SEND_RING_1_TO_4 + \ |
| 2243 | ((ringno * sizeof(struct bge_tx_bd) * size) / 4) |
| 2244 | |
| 2245 | struct bge_rx_bd { |
| 2246 | bge_hostaddr bge_addr; |
| 2247 | #if BYTE_ORDER == BIG_ENDIAN |
| 2248 | volatile u_int16_t bge_idx; |
| 2249 | volatile u_int16_t bge_len; |
| 2250 | volatile u_int16_t bge_type; |
| 2251 | volatile u_int16_t bge_flags; |
| 2252 | volatile u_int16_t bge_ip_csum; |
| 2253 | volatile u_int16_t bge_tcp_udp_csum; |
| 2254 | volatile u_int16_t bge_error_flag; |
| 2255 | volatile u_int16_t bge_vlan_tag; |
| 2256 | #else |
| 2257 | volatile u_int16_t bge_len; |
| 2258 | volatile u_int16_t bge_idx; |
| 2259 | volatile u_int16_t bge_flags; |
| 2260 | volatile u_int16_t bge_type; |
| 2261 | volatile u_int16_t bge_tcp_udp_csum; |
| 2262 | volatile u_int16_t bge_ip_csum; |
| 2263 | volatile u_int16_t bge_vlan_tag; |
| 2264 | volatile u_int16_t bge_error_flag; |
| 2265 | #endif |
| 2266 | volatile u_int32_t bge_rsvd; |
| 2267 | volatile u_int32_t bge_opaque; |
| 2268 | }; |
| 2269 | |
| 2270 | #define BGE_RXBDFLAG_END 0x0004 |
| 2271 | #define BGE_RXBDFLAG_JUMBO_RING 0x0020 |
| 2272 | #define BGE_RXBDFLAG_VLAN_TAG 0x0040 |
| 2273 | #define BGE_RXBDFLAG_ERROR 0x0400 |
| 2274 | #define BGE_RXBDFLAG_MINI_RING 0x0800 |
| 2275 | #define BGE_RXBDFLAG_IP_CSUM 0x1000 |
| 2276 | #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 |
| 2277 | #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 |
| 2278 | #define BGE_RXBDFLAG_IPV6 0x8000 |
| 2279 | |
| 2280 | #define BGE_RXERRFLAG_BAD_CRC 0x0001 |
| 2281 | #define BGE_RXERRFLAG_COLL_DETECT 0x0002 |
| 2282 | #define BGE_RXERRFLAG_LINK_LOST 0x0004 |
| 2283 | #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 |
| 2284 | #define BGE_RXERRFLAG_MAC_ABORT 0x0010 |
| 2285 | #define BGE_RXERRFLAG_RUNT 0x0020 |
| 2286 | #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 |
| 2287 | #define BGE_RXERRFLAG_GIANT 0x0080 |
| 2288 | #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ |
| 2289 | |
| 2290 | struct bge_sts_idx { |
| 2291 | #if BYTE_ORDER == BIG_ENDIAN |
| 2292 | volatile u_int16_t bge_tx_cons_idx; |
| 2293 | volatile u_int16_t bge_rx_prod_idx; |
| 2294 | #else |
| 2295 | volatile u_int16_t bge_rx_prod_idx; |
| 2296 | volatile u_int16_t bge_tx_cons_idx; |
| 2297 | #endif |
| 2298 | }; |
| 2299 | |
| 2300 | struct bge_status_block { |
| 2301 | volatile u_int32_t bge_status; |
| 2302 | volatile u_int32_t bge_status_tag; |
| 2303 | #if BYTE_ORDER == BIG_ENDIAN |
| 2304 | volatile u_int16_t bge_rx_std_cons_idx; |
| 2305 | volatile u_int16_t bge_rx_jumbo_cons_idx; |
| 2306 | volatile u_int16_t bge_rsvd1; |
| 2307 | volatile u_int16_t bge_rx_mini_cons_idx; |
| 2308 | #else |
| 2309 | volatile u_int16_t bge_rx_jumbo_cons_idx; |
| 2310 | volatile u_int16_t bge_rx_std_cons_idx; |
| 2311 | volatile u_int16_t bge_rx_mini_cons_idx; |
| 2312 | volatile u_int16_t bge_rsvd1; |
| 2313 | #endif |
| 2314 | struct bge_sts_idx bge_idx[16]; |
| 2315 | }; |
| 2316 | |
| 2317 | #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx |
| 2318 | #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx |
| 2319 | |
| 2320 | #define BGE_STATFLAG_UPDATED 0x00000001 |
| 2321 | #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 |
| 2322 | #define BGE_STATFLAG_ERROR 0x00000004 |
| 2323 | |
| 2324 | |
| 2325 | /* |
| 2326 | * Broadcom Vendor ID |
| 2327 | * (Note: the BCM570x still defaults to the Alteon PCI vendor ID |
| 2328 | * even though they're now manufactured by Broadcom) |
| 2329 | */ |
| 2330 | #define BCOM_VENDORID 0x14E4 |
| 2331 | #define BCOM_DEVICEID_BCM5700 0x1644 |
| 2332 | #define BCOM_DEVICEID_BCM5701 0x1645 |
| 2333 | #define BCOM_DEVICEID_BCM5789 0x169d |
| 2334 | |
| 2335 | /* |
| 2336 | * Alteon AceNIC PCI vendor/device ID. |
| 2337 | */ |
| 2338 | #define ALT_VENDORID 0x12AE |
| 2339 | #define ALT_DEVICEID_ACENIC 0x0001 |
| 2340 | #define ALT_DEVICEID_ACENIC_COPPER 0x0002 |
| 2341 | #define ALT_DEVICEID_BCM5700 0x0003 |
| 2342 | #define ALT_DEVICEID_BCM5701 0x0004 |
| 2343 | |
| 2344 | /* |
| 2345 | * 3Com 3c985 PCI vendor/device ID. |
| 2346 | */ |
| 2347 | #define TC_VENDORID 0x10B7 |
| 2348 | #define TC_DEVICEID_3C985 0x0001 |
| 2349 | #define TC_DEVICEID_3C996 0x0003 |
| 2350 | |
| 2351 | /* |
| 2352 | * SysKonnect PCI vendor ID |
| 2353 | */ |
| 2354 | #define SK_VENDORID 0x1148 |
| 2355 | #define SK_DEVICEID_ALTIMA 0x4400 |
| 2356 | #define SK_SUBSYSID_9D21 0x4421 |
| 2357 | #define SK_SUBSYSID_9D41 0x4441 |
| 2358 | |
| 2359 | /* |
| 2360 | * Altima PCI vendor/device ID. |
| 2361 | */ |
| 2362 | #define ALTIMA_VENDORID 0x173b |
| 2363 | #define ALTIMA_DEVICE_AC1000 0x03e8 |
| 2364 | |
| 2365 | /* |
| 2366 | * Offset of MAC address inside EEPROM. |
| 2367 | */ |
| 2368 | #define BGE_EE_MAC_OFFSET 0x7C |
| 2369 | #define BGE_EE_MAC_OFFSET_5906 0x10 |
| 2370 | #define BGE_EE_HWCFG_OFFSET 0xC8 |
| 2371 | |
| 2372 | #define BGE_HWCFG_VOLTAGE 0x00000003 |
| 2373 | #define BGE_HWCFG_PHYLED_MODE 0x0000000C |
| 2374 | #define BGE_HWCFG_MEDIA 0x00000030 |
| 2375 | #define BGE_HWCFG_ASF 0x00000080 |
| 2376 | #define BGE_HWCFG_EEPROM_WP 0x00000100 |
| 2377 | |
| 2378 | #define BGE_VOLTAGE_1POINT3 0x00000000 |
| 2379 | #define BGE_VOLTAGE_1POINT8 0x00000001 |
| 2380 | |
| 2381 | #define BGE_PHYLEDMODE_UNSPEC 0x00000000 |
| 2382 | #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 |
| 2383 | #define BGE_PHYLEDMODE_SINGLELED 0x00000008 |
| 2384 | |
| 2385 | #define BGE_MEDIA_UNSPEC 0x00000000 |
| 2386 | #define BGE_MEDIA_COPPER 0x00000010 |
| 2387 | #define BGE_MEDIA_FIBER 0x00000020 |
| 2388 | |
| 2389 | #define BGE_PCI_READ_CMD 0x06000000 |
| 2390 | #define BGE_PCI_WRITE_CMD 0x70000000 |
| 2391 | |
| 2392 | #define BGE_TICKS_PER_SEC 1000000 |
| 2393 | |
| 2394 | /* |
| 2395 | * Ring size constants. |
| 2396 | */ |
| 2397 | #define BGE_EVENT_RING_CNT 256 |
| 2398 | #define BGE_CMD_RING_CNT 64 |
| 2399 | #define BGE_STD_RX_RING_CNT 512 |
| 2400 | #define BGE_JUMBO_RX_RING_CNT 256 |
| 2401 | #define BGE_MINI_RX_RING_CNT 1024 |
| 2402 | #define BGE_RETURN_RING_CNT 1024 |
| 2403 | #define BGE_RETURN_RING_CNT_5705 512 |
| 2404 | |
| 2405 | /* |
| 2406 | * Possible TX ring sizes. |
| 2407 | */ |
| 2408 | #define BGE_TX_RING_CNT_128 128 |
| 2409 | #define BGE_TX_RING_BASE_128 0x3800 |
| 2410 | |
| 2411 | #define BGE_TX_RING_CNT_256 256 |
| 2412 | #define BGE_TX_RING_BASE_256 0x3000 |
| 2413 | |
| 2414 | #define BGE_TX_RING_CNT_512 512 |
| 2415 | #define BGE_TX_RING_BASE_512 0x2000 |
| 2416 | |
| 2417 | #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 |
| 2418 | #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 |
| 2419 | |
| 2420 | /* |
| 2421 | * Tigon III statistics counters. |
| 2422 | */ |
| 2423 | |
| 2424 | /* Stats counters access through registers */ |
| 2425 | struct bge_mac_stats_regs { |
| 2426 | u_int32_t ifHCOutOctets; |
| 2427 | u_int32_t Reserved0; |
| 2428 | u_int32_t etherStatsCollisions; |
| 2429 | u_int32_t outXonSent; |
| 2430 | u_int32_t outXoffSent; |
| 2431 | u_int32_t Reserved1; |
| 2432 | u_int32_t dot3StatsInternalMacTransmitErrors; |
| 2433 | u_int32_t dot3StatsSingleCollisionFrames; |
| 2434 | u_int32_t dot3StatsMultipleCollisionFrames; |
| 2435 | u_int32_t dot3StatsDeferredTransmissions; |
| 2436 | u_int32_t Reserved2; |
| 2437 | u_int32_t dot3StatsExcessiveCollisions; |
| 2438 | u_int32_t dot3StatsLateCollisions; |
| 2439 | u_int32_t Reserved3[14]; |
| 2440 | u_int32_t ifHCOutUcastPkts; |
| 2441 | u_int32_t ifHCOutMulticastPkts; |
| 2442 | u_int32_t ifHCOutBroadcastPkts; |
| 2443 | u_int32_t Reserved4[2]; |
| 2444 | u_int32_t ifHCInOctets; |
| 2445 | u_int32_t Reserved5; |
| 2446 | u_int32_t etherStatsFragments; |
| 2447 | u_int32_t ifHCInUcastPkts; |
| 2448 | u_int32_t ifHCInMulticastPkts; |
| 2449 | u_int32_t ifHCInBroadcastPkts; |
| 2450 | u_int32_t dot3StatsFCSErrors; |
| 2451 | u_int32_t dot3StatsAlignmentErrors; |
| 2452 | u_int32_t xonPauseFramesReceived; |
| 2453 | u_int32_t xoffPauseFramesReceived; |
| 2454 | u_int32_t macControlFramesReceived; |
| 2455 | u_int32_t xoffStateEntered; |
| 2456 | u_int32_t dot3StatsFramesTooLong; |
| 2457 | u_int32_t etherStatsJabbers; |
| 2458 | u_int32_t etherStatsUndersizePkts; |
| 2459 | }; |
| 2460 | |
| 2461 | struct bge_stats { |
| 2462 | u_int8_t Reserved0[256]; |
| 2463 | |
| 2464 | /* Statistics maintained by Receive MAC. */ |
| 2465 | bge_hostaddr ifHCInOctets; |
| 2466 | bge_hostaddr Reserved1; |
| 2467 | bge_hostaddr etherStatsFragments; |
| 2468 | bge_hostaddr ifHCInUcastPkts; |
| 2469 | bge_hostaddr ifHCInMulticastPkts; |
| 2470 | bge_hostaddr ifHCInBroadcastPkts; |
| 2471 | bge_hostaddr dot3StatsFCSErrors; |
| 2472 | bge_hostaddr dot3StatsAlignmentErrors; |
| 2473 | bge_hostaddr xonPauseFramesReceived; |
| 2474 | bge_hostaddr xoffPauseFramesReceived; |
| 2475 | bge_hostaddr macControlFramesReceived; |
| 2476 | bge_hostaddr xoffStateEntered; |
| 2477 | bge_hostaddr dot3StatsFramesTooLong; |
| 2478 | bge_hostaddr etherStatsJabbers; |
| 2479 | bge_hostaddr etherStatsUndersizePkts; |
| 2480 | bge_hostaddr inRangeLengthError; |
| 2481 | bge_hostaddr outRangeLengthError; |
| 2482 | bge_hostaddr etherStatsPkts64Octets; |
| 2483 | bge_hostaddr etherStatsPkts65Octetsto127Octets; |
| 2484 | bge_hostaddr etherStatsPkts128Octetsto255Octets; |
| 2485 | bge_hostaddr etherStatsPkts256Octetsto511Octets; |
| 2486 | bge_hostaddr etherStatsPkts512Octetsto1023Octets; |
| 2487 | bge_hostaddr etherStatsPkts1024Octetsto1522Octets; |
| 2488 | bge_hostaddr etherStatsPkts1523Octetsto2047Octets; |
| 2489 | bge_hostaddr etherStatsPkts2048Octetsto4095Octets; |
| 2490 | bge_hostaddr etherStatsPkts4096Octetsto8191Octets; |
| 2491 | bge_hostaddr etherStatsPkts8192Octetsto9022Octets; |
| 2492 | |
| 2493 | bge_hostaddr Unused1[37]; |
| 2494 | |
| 2495 | /* Statistics maintained by Transmit MAC. */ |
| 2496 | bge_hostaddr ifHCOutOctets; |
| 2497 | bge_hostaddr Reserved2; |
| 2498 | bge_hostaddr etherStatsCollisions; |
| 2499 | bge_hostaddr outXonSent; |
| 2500 | bge_hostaddr outXoffSent; |
| 2501 | bge_hostaddr flowControlDone; |
| 2502 | bge_hostaddr dot3StatsInternalMacTransmitErrors; |
| 2503 | bge_hostaddr dot3StatsSingleCollisionFrames; |
| 2504 | bge_hostaddr dot3StatsMultipleCollisionFrames; |
| 2505 | bge_hostaddr dot3StatsDeferredTransmissions; |
| 2506 | bge_hostaddr Reserved3; |
| 2507 | bge_hostaddr dot3StatsExcessiveCollisions; |
| 2508 | bge_hostaddr dot3StatsLateCollisions; |
| 2509 | bge_hostaddr dot3Collided2Times; |
| 2510 | bge_hostaddr dot3Collided3Times; |
| 2511 | bge_hostaddr dot3Collided4Times; |
| 2512 | bge_hostaddr dot3Collided5Times; |
| 2513 | bge_hostaddr dot3Collided6Times; |
| 2514 | bge_hostaddr dot3Collided7Times; |
| 2515 | bge_hostaddr dot3Collided8Times; |
| 2516 | bge_hostaddr dot3Collided9Times; |
| 2517 | bge_hostaddr dot3Collided10Times; |
| 2518 | bge_hostaddr dot3Collided11Times; |
| 2519 | bge_hostaddr dot3Collided12Times; |
| 2520 | bge_hostaddr dot3Collided13Times; |
| 2521 | bge_hostaddr dot3Collided14Times; |
| 2522 | bge_hostaddr dot3Collided15Times; |
| 2523 | bge_hostaddr ifHCOutUcastPkts; |
| 2524 | bge_hostaddr ifHCOutMulticastPkts; |
| 2525 | bge_hostaddr ifHCOutBroadcastPkts; |
| 2526 | bge_hostaddr dot3StatsCarrierSenseErrors; |
| 2527 | bge_hostaddr ifOutDiscards; |
| 2528 | bge_hostaddr ifOutErrors; |
| 2529 | |
| 2530 | bge_hostaddr Unused2[31]; |
| 2531 | |
| 2532 | /* Statistics maintained by Receive List Placement. */ |
| 2533 | bge_hostaddr COSIfHCInPkts[16]; |
| 2534 | bge_hostaddr COSFramesDroppedDueToFilters; |
| 2535 | bge_hostaddr nicDmaWriteQueueFull; |
| 2536 | bge_hostaddr nicDmaWriteHighPriQueueFull; |
| 2537 | bge_hostaddr nicNoMoreRxBDs; |
| 2538 | bge_hostaddr ifInDiscards; |
| 2539 | bge_hostaddr ifInErrors; |
| 2540 | bge_hostaddr nicRecvThresholdHit; |
| 2541 | |
| 2542 | bge_hostaddr Unused3[9]; |
| 2543 | |
| 2544 | /* Statistics maintained by Send Data Initiator. */ |
| 2545 | bge_hostaddr COSIfHCOutPkts[16]; |
| 2546 | bge_hostaddr nicDmaReadQueueFull; |
| 2547 | bge_hostaddr nicDmaReadHighPriQueueFull; |
| 2548 | bge_hostaddr nicSendDataCompQueueFull; |
| 2549 | |
| 2550 | /* Statistics maintained by Host Coalescing. */ |
| 2551 | bge_hostaddr nicRingSetSendProdIndex; |
| 2552 | bge_hostaddr nicRingStatusUpdate; |
| 2553 | bge_hostaddr nicInterrupts; |
| 2554 | bge_hostaddr nicAvoidedInterrupts; |
| 2555 | bge_hostaddr nicSendThresholdHit; |
| 2556 | |
| 2557 | u_int8_t Reserved4[320]; |
| 2558 | }; |
| 2559 | |
| 2560 | /* |
| 2561 | * Tigon general information block. This resides in host memory |
| 2562 | * and contains the status counters, ring control blocks and |
| 2563 | * producer pointers. |
| 2564 | */ |
| 2565 | |
| 2566 | struct bge_gib { |
| 2567 | struct bge_stats bge_stats; |
| 2568 | struct bge_rcb bge_tx_rcb[16]; |
| 2569 | struct bge_rcb bge_std_rx_rcb; |
| 2570 | struct bge_rcb bge_jumbo_rx_rcb; |
| 2571 | struct bge_rcb bge_mini_rx_rcb; |
| 2572 | struct bge_rcb bge_return_rcb; |
| 2573 | }; |
| 2574 | |
| 2575 | /* |
| 2576 | * NOTE! On the Alpha, we have an alignment constraint. |
| 2577 | * The first thing in the packet is a 14-byte Ethernet header. |
| 2578 | * This means that the packet is misaligned. To compensate, |
| 2579 | * we actually offset the data 2 bytes into the cluster. This |
| 2580 | * alignes the packet after the Ethernet header at a 32-bit |
| 2581 | * boundary. |
| 2582 | */ |
| 2583 | |
| 2584 | #define ETHER_ALIGN 2 |
| 2585 | |
| 2586 | #define BGE_FRAMELEN ETHER_MAX_LEN |
| 2587 | #define BGE_MAX_FRAMELEN 1536 |
| 2588 | #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO |
| 2589 | #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
| 2590 | #define BGE_PAGE_SIZE PAGE_SIZE |
| 2591 | #define BGE_MIN_FRAMELEN 60 |
| 2592 | |
| 2593 | /* |
| 2594 | * Vital product data and structures. |
| 2595 | */ |
| 2596 | #define BGE_VPD_FLAG 0x8000 |
| 2597 | |
| 2598 | /* VPD structures */ |
| 2599 | struct vpd_res { |
| 2600 | u_int8_t vr_id; |
| 2601 | u_int8_t vr_len; |
| 2602 | u_int8_t vr_pad; |
| 2603 | }; |
| 2604 | |
| 2605 | struct vpd_key { |
| 2606 | char vk_key[2]; |
| 2607 | u_int8_t vk_len; |
| 2608 | }; |
| 2609 | |
| 2610 | #define VPD_RES_ID 0x82 /* ID string */ |
| 2611 | #define VPD_RES_READ 0x90 /* start of read only area */ |
| 2612 | #define VPD_RES_WRITE 0x81 /* start of read/write area */ |
| 2613 | #define VPD_RES_END 0x78 /* end tag */ |
| 2614 | |
| 2615 | /* Flags for bge_flags */ |
| 2616 | #define BGEF_FIBER_TBI 0x00000001 |
| 2617 | #define BGEF_JUMBO_CAPABLE 0x00000002 |
| 2618 | #define BGEF_FIBER_MII 0x00000004 |
| 2619 | #define BGEF_CPMU_PRESENT 0x00000008 |
| 2620 | #define BGEF_APE 0x00000010 |
| 2621 | #define BGEF_MSI 0x00000020 |
| 2622 | #define BGEF_PCIX 0x00000040 |
| 2623 | #define BGEF_PCIE 0x00000080 |
| 2624 | #define BGEF_TSO 0x00000100 |
| 2625 | #define BGEF_NO_EEPROM 0x00000200 |
| 2626 | #define BGEF_5700_FAMILY 0x00000800 |
| 2627 | #define BGEF_5705_PLUS 0x00001000 |
| 2628 | #define BGEF_575X_PLUS 0x00002000 |
| 2629 | #define BGEF_5755_PLUS 0x00004000 |
| 2630 | #define BGEF_IS_5788 0x00008000 |
| 2631 | #define BGEF_5714_FAMILY 0x00010000 |
| 2632 | #define BGEF_5717_PLUS 0x00020000 |
| 2633 | #define BGEF_57765_FAMILY 0x00040000 |
| 2634 | #define BGEF_57765_PLUS 0x00080000 |
| 2635 | #define BGEF_40BIT_BUG 0x00100000 |
| 2636 | #define BGEF_TAGGED_STATUS 0x00200000 |
| 2637 | #define BGEF_RX_ALIGNBUG 0x00800000 |
| 2638 | #define BGEF_TXRING_VALID 0x20000000 |
| 2639 | #define BGEF_RXRING_VALID 0x40000000 |
| 2640 | #define BGEF_JUMBO_RXRING_VALID 0x80000000 |
| 2641 | |
| 2642 | /* PHY related flags in bge_phy_flags. Also used in phyflags in proplib. */ |
| 2643 | #define BGEPHYF_NO_3LED 0x00000001 |
| 2644 | #define BGEPHYF_CRC_BUG 0x00000002 |
| 2645 | #define BGEPHYF_ADC_BUG 0x00000004 |
| 2646 | #define BGEPHYF_5704_A0_BUG 0x00000008 |
| 2647 | #define BGEPHYF_JITTER_BUG 0x00000010 |
| 2648 | #define BGEPHYF_BER_BUG 0x00000020 |
| 2649 | #define BGEPHYF_ADJUST_TRIM 0x00000040 |
| 2650 | #define BGEPHYF_NO_WIRESPEED 0x00000080 |
| 2651 | #define BGEPHYF_JUMBO_CAPABLE 0x00010000 /* Copied from BGEF_JUMBO_CAPAABLE*/ |
| 2652 | |