| 1 | /* $NetBSD: pdcsata.c,v 1.27 2014/03/29 19:28:25 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2004, Manuel Bouyer. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.27 2014/03/29 19:28:25 christos Exp $" ); |
| 29 | |
| 30 | #include <sys/types.h> |
| 31 | #include <sys/malloc.h> |
| 32 | #include <sys/param.h> |
| 33 | #include <sys/systm.h> |
| 34 | |
| 35 | #include <dev/pci/pcivar.h> |
| 36 | #include <dev/pci/pcidevs.h> |
| 37 | #include <dev/pci/pciidereg.h> |
| 38 | #include <dev/pci/pciidevar.h> |
| 39 | #include <dev/ata/atareg.h> |
| 40 | #include <dev/ata/satavar.h> |
| 41 | #include <dev/ata/satareg.h> |
| 42 | |
| 43 | #define PDC203xx_SATA_NCHANNELS 4 |
| 44 | #define PDC203xx_COMBO_NCHANNELS 3 |
| 45 | #define PDC40718_SATA_NCHANNELS 4 |
| 46 | #define PDC20575_COMBO_NCHANNELS 3 |
| 47 | |
| 48 | #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ |
| 49 | |
| 50 | #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) |
| 51 | #define PDC_ERRMASK 0x00780700 |
| 52 | |
| 53 | #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) |
| 54 | #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) |
| 55 | #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) |
| 56 | #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) |
| 57 | #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) |
| 58 | |
| 59 | static void pdcsata_chip_map(struct pciide_softc *, |
| 60 | const struct pci_attach_args *); |
| 61 | static void pdc203xx_setup_channel(struct ata_channel *); |
| 62 | static void pdc203xx_irqack(struct ata_channel *); |
| 63 | static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); |
| 64 | static void pdc203xx_dma_start(void *,int ,int); |
| 65 | static int pdc203xx_dma_finish(void *, int, int, int); |
| 66 | static void pdc203xx_combo_probe(struct ata_channel *); |
| 67 | static int pdcsata_pci_intr(void *); |
| 68 | static void pdcsata_do_reset(struct ata_channel *, int); |
| 69 | |
| 70 | static int pdcsata_match(device_t, cfdata_t, void *); |
| 71 | static void pdcsata_attach(device_t, device_t, void *); |
| 72 | |
| 73 | CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc), |
| 74 | pdcsata_match, pdcsata_attach, pciide_detach, NULL); |
| 75 | |
| 76 | static const struct pciide_product_desc pciide_pdcsata_products[] = { |
| 77 | { PCI_PRODUCT_PROMISE_PDC20318, |
| 78 | 0, |
| 79 | "Promise PDC20318 SATA150 controller" , |
| 80 | pdcsata_chip_map, |
| 81 | }, |
| 82 | { PCI_PRODUCT_PROMISE_PDC20319, |
| 83 | 0, |
| 84 | "Promise PDC20319 SATA150 controller" , |
| 85 | pdcsata_chip_map, |
| 86 | }, |
| 87 | { PCI_PRODUCT_PROMISE_PDC20371, |
| 88 | 0, |
| 89 | "Promise PDC20371 SATA150 controller" , |
| 90 | pdcsata_chip_map, |
| 91 | }, |
| 92 | { PCI_PRODUCT_PROMISE_PDC20375, |
| 93 | 0, |
| 94 | "Promise PDC20375 SATA150 controller" , |
| 95 | pdcsata_chip_map, |
| 96 | }, |
| 97 | { PCI_PRODUCT_PROMISE_PDC20376, |
| 98 | 0, |
| 99 | "Promise PDC20376 SATA150 controller" , |
| 100 | pdcsata_chip_map, |
| 101 | }, |
| 102 | { PCI_PRODUCT_PROMISE_PDC20377, |
| 103 | 0, |
| 104 | "Promise PDC20377 SATA150 controller" , |
| 105 | pdcsata_chip_map, |
| 106 | }, |
| 107 | { PCI_PRODUCT_PROMISE_PDC20378, |
| 108 | 0, |
| 109 | "Promise PDC20378 SATA150 controller" , |
| 110 | pdcsata_chip_map, |
| 111 | }, |
| 112 | { PCI_PRODUCT_PROMISE_PDC20379, |
| 113 | 0, |
| 114 | "Promise PDC20379 SATA150 controller" , |
| 115 | pdcsata_chip_map, |
| 116 | }, |
| 117 | { PCI_PRODUCT_PROMISE_PDC40518, |
| 118 | 0, |
| 119 | "Promise PDC40518 SATA150 controller" , |
| 120 | pdcsata_chip_map, |
| 121 | }, |
| 122 | { PCI_PRODUCT_PROMISE_PDC40519, |
| 123 | 0, |
| 124 | "Promise PDC40519 SATA 150 controller" , |
| 125 | pdcsata_chip_map, |
| 126 | }, |
| 127 | { PCI_PRODUCT_PROMISE_PDC40718, |
| 128 | 0, |
| 129 | "Promise PDC40718 SATA300 controller" , |
| 130 | pdcsata_chip_map, |
| 131 | }, |
| 132 | { PCI_PRODUCT_PROMISE_PDC40719, |
| 133 | 0, |
| 134 | "Promise PDC40719 SATA300 controller" , |
| 135 | pdcsata_chip_map, |
| 136 | }, |
| 137 | { PCI_PRODUCT_PROMISE_PDC40779, |
| 138 | 0, |
| 139 | "Promise PDC40779 SATA300 controller" , |
| 140 | pdcsata_chip_map, |
| 141 | }, |
| 142 | { PCI_PRODUCT_PROMISE_PDC20571, |
| 143 | 0, |
| 144 | "Promise PDC20571 SATA150 controller" , |
| 145 | pdcsata_chip_map, |
| 146 | }, |
| 147 | { PCI_PRODUCT_PROMISE_PDC20575, |
| 148 | 0, |
| 149 | "Promise PDC20575 SATA150 controller" , |
| 150 | pdcsata_chip_map, |
| 151 | }, |
| 152 | { PCI_PRODUCT_PROMISE_PDC20579, |
| 153 | 0, |
| 154 | "Promise PDC20579 SATA150 controller" , |
| 155 | pdcsata_chip_map, |
| 156 | }, |
| 157 | { PCI_PRODUCT_PROMISE_PDC20771, |
| 158 | 0, |
| 159 | "Promise PDC20771 SATA300 controller" , |
| 160 | pdcsata_chip_map, |
| 161 | }, |
| 162 | { PCI_PRODUCT_PROMISE_PDC20775, |
| 163 | 0, |
| 164 | "Promise PDC20775 SATA300 controller" , |
| 165 | pdcsata_chip_map, |
| 166 | }, |
| 167 | { PCI_PRODUCT_PROMISE_PDC20617, |
| 168 | 0, |
| 169 | "Promise PDC2020617 Ultra/133 controller" , |
| 170 | pdcsata_chip_map, |
| 171 | }, |
| 172 | { PCI_PRODUCT_PROMISE_PDC20618, |
| 173 | 0, |
| 174 | "Promise PDC20618 Ultra/133 controller" , |
| 175 | pdcsata_chip_map, |
| 176 | }, |
| 177 | { PCI_PRODUCT_PROMISE_PDC20619, |
| 178 | 0, |
| 179 | "Promise PDC20619 Ultra/133 controller" , |
| 180 | pdcsata_chip_map, |
| 181 | }, |
| 182 | { PCI_PRODUCT_PROMISE_PDC20620, |
| 183 | 0, |
| 184 | "Promise PDC20620 Ultra/133 controller" , |
| 185 | pdcsata_chip_map, |
| 186 | }, |
| 187 | { PCI_PRODUCT_PROMISE_PDC20621, |
| 188 | 0, |
| 189 | "Promise PDC20621 Ultra/133 controller" , |
| 190 | pdcsata_chip_map, |
| 191 | }, |
| 192 | { 0, |
| 193 | 0, |
| 194 | NULL, |
| 195 | NULL |
| 196 | } |
| 197 | }; |
| 198 | |
| 199 | static int |
| 200 | pdcsata_match(device_t parent, cfdata_t match, void *aux) |
| 201 | { |
| 202 | struct pci_attach_args *pa = aux; |
| 203 | |
| 204 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { |
| 205 | if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) |
| 206 | return (2); |
| 207 | } |
| 208 | return (0); |
| 209 | } |
| 210 | |
| 211 | static void |
| 212 | pdcsata_attach(device_t parent, device_t self, void *aux) |
| 213 | { |
| 214 | struct pci_attach_args *pa = aux; |
| 215 | struct pciide_softc *sc = device_private(self); |
| 216 | |
| 217 | sc->sc_wdcdev.sc_atac.atac_dev = self; |
| 218 | |
| 219 | pciide_common_attach(sc, pa, |
| 220 | pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); |
| 221 | } |
| 222 | |
| 223 | static void |
| 224 | pdcsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) |
| 225 | { |
| 226 | struct pciide_channel *cp; |
| 227 | struct ata_channel *wdc_cp; |
| 228 | struct wdc_regs *wdr; |
| 229 | int channel, i; |
| 230 | pci_intr_handle_t intrhandle; |
| 231 | const char *intrstr; |
| 232 | char intrbuf[PCI_INTRSTR_LEN]; |
| 233 | |
| 234 | /* |
| 235 | * Promise SATA controllers have 3 or 4 channels, |
| 236 | * the usual IDE registers are mapped in I/O space, with offsets. |
| 237 | */ |
| 238 | if (pci_intr_map(pa, &intrhandle) != 0) { |
| 239 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 240 | "couldn't map interrupt\n" ); |
| 241 | return; |
| 242 | } |
| 243 | intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); |
| 244 | sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, |
| 245 | intrhandle, IPL_BIO, pdcsata_pci_intr, sc); |
| 246 | |
| 247 | if (sc->sc_pci_ih == NULL) { |
| 248 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 249 | "couldn't establish native-PCI interrupt" ); |
| 250 | if (intrstr != NULL) |
| 251 | aprint_error(" at %s" , intrstr); |
| 252 | aprint_error("\n" ); |
| 253 | return; |
| 254 | } |
| 255 | aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 256 | "interrupting at %s\n" , |
| 257 | intrstr ? intrstr : "unknown interrupt" ); |
| 258 | |
| 259 | sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, |
| 260 | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, |
| 261 | &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) == 0); |
| 262 | if (!sc->sc_dma_ok) { |
| 263 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 264 | "couldn't map bus-master DMA registers\n" ); |
| 265 | pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); |
| 266 | return; |
| 267 | } |
| 268 | |
| 269 | sc->sc_dmat = pa->pa_dmat; |
| 270 | |
| 271 | if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, |
| 272 | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, |
| 273 | &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { |
| 274 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 275 | "couldn't map IDE registers\n" ); |
| 276 | bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); |
| 277 | pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); |
| 278 | return; |
| 279 | } |
| 280 | |
| 281 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 282 | "bus-master DMA support present\n" ); |
| 283 | sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; |
| 284 | if (sc->sc_dma_ok) { |
| 285 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; |
| 286 | } |
| 287 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && |
| 288 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) |
| 289 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; |
| 290 | sc->sc_wdcdev.irqack = pdc203xx_irqack; |
| 291 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
| 292 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
| 293 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; |
| 294 | sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; |
| 295 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
| 296 | sc->sc_wdcdev.wdc_maxdrives = 2; |
| 297 | |
| 298 | sc->sc_wdcdev.reset = pdcsata_do_reset; |
| 299 | |
| 300 | switch (sc->sc_pp->ide_product) { |
| 301 | case PCI_PRODUCT_PROMISE_PDC20318: |
| 302 | case PCI_PRODUCT_PROMISE_PDC20319: |
| 303 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, |
| 304 | 0x00ff0033); |
| 305 | sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; |
| 306 | sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS; |
| 307 | sc->sc_wdcdev.wdc_maxdrives = 1; |
| 308 | break; |
| 309 | case PCI_PRODUCT_PROMISE_PDC20371: |
| 310 | case PCI_PRODUCT_PROMISE_PDC20375: |
| 311 | case PCI_PRODUCT_PROMISE_PDC20376: |
| 312 | case PCI_PRODUCT_PROMISE_PDC20377: |
| 313 | case PCI_PRODUCT_PROMISE_PDC20378: |
| 314 | case PCI_PRODUCT_PROMISE_PDC20379: |
| 315 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, |
| 316 | 0x00ff0033); |
| 317 | sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; |
| 318 | sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS; |
| 319 | break; |
| 320 | |
| 321 | case PCI_PRODUCT_PROMISE_PDC40518: |
| 322 | case PCI_PRODUCT_PROMISE_PDC40519: |
| 323 | case PCI_PRODUCT_PROMISE_PDC40718: |
| 324 | case PCI_PRODUCT_PROMISE_PDC40719: |
| 325 | case PCI_PRODUCT_PROMISE_PDC40779: |
| 326 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, |
| 327 | 0x00ff00ff); |
| 328 | sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS; |
| 329 | sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; |
| 330 | sc->sc_wdcdev.wdc_maxdrives = 1; |
| 331 | break; |
| 332 | |
| 333 | case PCI_PRODUCT_PROMISE_PDC20571: |
| 334 | case PCI_PRODUCT_PROMISE_PDC20575: |
| 335 | case PCI_PRODUCT_PROMISE_PDC20579: |
| 336 | case PCI_PRODUCT_PROMISE_PDC20771: |
| 337 | case PCI_PRODUCT_PROMISE_PDC20775: |
| 338 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, |
| 339 | 0x00ff00ff); |
| 340 | sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS; |
| 341 | sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe; |
| 342 | break; |
| 343 | |
| 344 | case PCI_PRODUCT_PROMISE_PDC20617: |
| 345 | case PCI_PRODUCT_PROMISE_PDC20618: |
| 346 | case PCI_PRODUCT_PROMISE_PDC20619: |
| 347 | case PCI_PRODUCT_PROMISE_PDC20620: |
| 348 | case PCI_PRODUCT_PROMISE_PDC20621: |
| 349 | sc->sc_wdcdev.sc_atac.atac_nchannels = |
| 350 | ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 351 | 0x48) & 0x01) ? 1 : 0) + |
| 352 | ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 353 | 0x48) & 0x02) ? 1 : 0) + |
| 354 | 2; |
| 355 | sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe; |
| 356 | |
| 357 | default: |
| 358 | aprint_error("unknown promise product 0x%x\n" , |
| 359 | sc->sc_pp->ide_product); |
| 360 | } |
| 361 | |
| 362 | wdc_allocate_regs(&sc->sc_wdcdev); |
| 363 | |
| 364 | sc->sc_wdcdev.dma_arg = sc; |
| 365 | sc->sc_wdcdev.dma_init = pdc203xx_dma_init; |
| 366 | sc->sc_wdcdev.dma_start = pdc203xx_dma_start; |
| 367 | sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; |
| 368 | |
| 369 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
| 370 | channel++) { |
| 371 | cp = &sc->pciide_channels[channel]; |
| 372 | sc->wdc_chanarray[channel] = &cp->ata_channel; |
| 373 | |
| 374 | cp->ih = sc->sc_pci_ih; |
| 375 | cp->name = NULL; |
| 376 | cp->ata_channel.ch_channel = channel; |
| 377 | cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; |
| 378 | cp->ata_channel.ch_queue = |
| 379 | malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); |
| 380 | if (cp->ata_channel.ch_queue == NULL) { |
| 381 | aprint_error("%s channel %d: " |
| 382 | "can't allocate memory for command queue\n" , |
| 383 | device_xname(sc->sc_wdcdev.sc_atac.atac_dev), |
| 384 | channel); |
| 385 | goto next_channel; |
| 386 | } |
| 387 | wdc_cp = &cp->ata_channel; |
| 388 | wdr = CHAN_TO_WDC_REGS(wdc_cp); |
| 389 | |
| 390 | wdr->ctl_iot = sc->sc_ba5_st; |
| 391 | wdr->cmd_iot = sc->sc_ba5_st; |
| 392 | |
| 393 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 394 | 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { |
| 395 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 396 | "couldn't map channel %d ctl regs\n" , channel); |
| 397 | goto next_channel; |
| 398 | } |
| 399 | for (i = 0; i < WDC_NREG; i++) { |
| 400 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 401 | 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, |
| 402 | &wdr->cmd_iohs[i]) != 0) { |
| 403 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 404 | "couldn't map channel %d cmd regs\n" , |
| 405 | channel); |
| 406 | goto next_channel; |
| 407 | } |
| 408 | } |
| 409 | wdc_init_shadow_regs(wdc_cp); |
| 410 | |
| 411 | /* |
| 412 | * subregion de busmaster registers. They're spread all over |
| 413 | * the controller's register space :(. They are also 4 bytes |
| 414 | * sized, with some specific extentions in the extra bits. |
| 415 | * It also seems that the IDEDMA_CTL register isn't available. |
| 416 | */ |
| 417 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 418 | 0x260 + (channel << 7), 1, |
| 419 | &cp->dma_iohs[IDEDMA_CMD]) != 0) { |
| 420 | aprint_normal("%s channel %d: can't subregion DMA " |
| 421 | "registers\n" , |
| 422 | device_xname(sc->sc_wdcdev.sc_atac.atac_dev), |
| 423 | channel); |
| 424 | goto next_channel; |
| 425 | } |
| 426 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 427 | 0x244 + (channel << 7), 4, |
| 428 | &cp->dma_iohs[IDEDMA_TBL]) != 0) { |
| 429 | aprint_normal("%s channel %d: can't subregion DMA " |
| 430 | "registers\n" , |
| 431 | device_xname(sc->sc_wdcdev.sc_atac.atac_dev), |
| 432 | channel); |
| 433 | goto next_channel; |
| 434 | } |
| 435 | |
| 436 | /* subregion the SATA registers */ |
| 437 | if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe || |
| 438 | (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe |
| 439 | && channel < 2)) { |
| 440 | wdr->sata_iot = sc->sc_ba5_st; |
| 441 | wdr->sata_baseioh = sc->sc_ba5_sh; |
| 442 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 443 | PDC205_SSTATUS(channel), 1, |
| 444 | &wdr->sata_status) != 0) { |
| 445 | aprint_error_dev( |
| 446 | sc->sc_wdcdev.sc_atac.atac_dev, |
| 447 | "couldn't map channel %d " |
| 448 | "sata_status regs\n" , channel); |
| 449 | goto next_channel; |
| 450 | } |
| 451 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 452 | PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) { |
| 453 | aprint_error_dev( |
| 454 | sc->sc_wdcdev.sc_atac.atac_dev, |
| 455 | "couldn't map channel %d " |
| 456 | "sata_error regs\n" , channel); |
| 457 | goto next_channel; |
| 458 | } |
| 459 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 460 | PDC205_SCONTROL(channel), 1, |
| 461 | &wdr->sata_control) != 0) { |
| 462 | aprint_error_dev( |
| 463 | sc->sc_wdcdev.sc_atac.atac_dev, |
| 464 | "couldn't map channel %d " |
| 465 | "sata_control regs\n" , channel); |
| 466 | goto next_channel; |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | wdcattach(wdc_cp); |
| 471 | bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, |
| 472 | (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], |
| 473 | 0) & ~0x00003f9f) | (channel + 1)); |
| 474 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 475 | (channel + 1) << 2, 0x00000001); |
| 476 | next_channel: |
| 477 | continue; |
| 478 | } |
| 479 | return; |
| 480 | } |
| 481 | |
| 482 | static void |
| 483 | pdc203xx_combo_probe(struct ata_channel *chp) |
| 484 | { |
| 485 | if (chp->ch_channel < 2) |
| 486 | wdc_sataprobe(chp); |
| 487 | else |
| 488 | wdc_drvprobe(chp); |
| 489 | } |
| 490 | |
| 491 | static void |
| 492 | pdc203xx_setup_channel(struct ata_channel *chp) |
| 493 | { |
| 494 | struct ata_drive_datas *drvp; |
| 495 | int drive, s; |
| 496 | struct pciide_channel *cp = CHAN_TO_PCHAN(chp); |
| 497 | |
| 498 | pciide_channel_dma_setup(cp); |
| 499 | |
| 500 | for (drive = 0; drive < 2; drive++) { |
| 501 | drvp = &chp->ch_drive[drive]; |
| 502 | if (drvp->drive_type == ATA_DRIVET_NONE) |
| 503 | continue; |
| 504 | if (drvp->drive_flags & ATA_DRIVE_UDMA) { |
| 505 | s = splbio(); |
| 506 | drvp->drive_flags &= ~ATA_DRIVE_DMA; |
| 507 | splx(s); |
| 508 | } |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | static int |
| 513 | pdcsata_pci_intr(void *arg) |
| 514 | { |
| 515 | struct pciide_softc *sc = arg; |
| 516 | struct pciide_channel *cp; |
| 517 | struct ata_channel *wdc_cp; |
| 518 | int i, rv, crv; |
| 519 | u_int32_t scr, status, chanbase; |
| 520 | |
| 521 | rv = 0; |
| 522 | scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); |
| 523 | if (scr == 0xffffffff) return(rv); |
| 524 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); |
| 525 | scr = scr & 0x0000ffff; |
| 526 | if (!scr) return(rv); |
| 527 | |
| 528 | for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { |
| 529 | cp = &sc->pciide_channels[i]; |
| 530 | wdc_cp = &cp->ata_channel; |
| 531 | if (scr & (1 << (i + 1))) { |
| 532 | chanbase = PDC_CHANNELBASE(i) + 0x48; |
| 533 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 534 | if (status & PDC_ERRMASK) { |
| 535 | chanbase = PDC_CHANNELBASE(i) + 0x60; |
| 536 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 537 | status |= 0x800; |
| 538 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); |
| 539 | status &= ~0x800; |
| 540 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); |
| 541 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 542 | continue; |
| 543 | } |
| 544 | crv = wdcintr(wdc_cp); |
| 545 | if (crv == 0) { |
| 546 | aprint_error("%s:%d: bogus intr (reg 0x%x)\n" , |
| 547 | device_xname( |
| 548 | sc->sc_wdcdev.sc_atac.atac_dev), i, scr); |
| 549 | } else |
| 550 | rv = 1; |
| 551 | } |
| 552 | } |
| 553 | return rv; |
| 554 | } |
| 555 | |
| 556 | static void |
| 557 | pdc203xx_irqack(struct ata_channel *chp) |
| 558 | { |
| 559 | struct pciide_channel *cp = CHAN_TO_PCHAN(chp); |
| 560 | struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); |
| 561 | |
| 562 | bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, |
| 563 | (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], |
| 564 | 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); |
| 565 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, |
| 566 | (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); |
| 567 | } |
| 568 | |
| 569 | static int |
| 570 | pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, |
| 571 | size_t datalen, int flags) |
| 572 | { |
| 573 | struct pciide_softc *sc = v; |
| 574 | |
| 575 | return pciide_dma_dmamap_setup(sc, channel, drive, |
| 576 | databuf, datalen, flags); |
| 577 | } |
| 578 | |
| 579 | static void |
| 580 | pdc203xx_dma_start(void *v, int channel, int drive) |
| 581 | { |
| 582 | struct pciide_softc *sc = v; |
| 583 | struct pciide_channel *cp = &sc->pciide_channels[channel]; |
| 584 | struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; |
| 585 | |
| 586 | /* Write table addr */ |
| 587 | bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, |
| 588 | dma_maps->dmamap_table->dm_segs[0].ds_addr); |
| 589 | /* start DMA engine */ |
| 590 | bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, |
| 591 | (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], |
| 592 | 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); |
| 593 | } |
| 594 | |
| 595 | static int |
| 596 | pdc203xx_dma_finish(void *v, int channel, int drive, int force) |
| 597 | { |
| 598 | struct pciide_softc *sc = v; |
| 599 | struct pciide_channel *cp = &sc->pciide_channels[channel]; |
| 600 | struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; |
| 601 | |
| 602 | /* stop DMA channel */ |
| 603 | bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, |
| 604 | (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], |
| 605 | 0) & ~0x80)); |
| 606 | |
| 607 | /* Unload the map of the data buffer */ |
| 608 | bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, |
| 609 | dma_maps->dmamap_xfer->dm_mapsize, |
| 610 | (dma_maps->dma_flags & WDC_DMA_READ) ? |
| 611 | BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); |
| 612 | bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | |
| 618 | static void |
| 619 | pdcsata_do_reset(struct ata_channel *chp, int poll) |
| 620 | { |
| 621 | struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); |
| 622 | int reset, status, i, chanbase; |
| 623 | |
| 624 | /* reset SATA */ |
| 625 | reset = (1 << 11); |
| 626 | chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; |
| 627 | for (i = 0; i < 11;i ++) { |
| 628 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 629 | if (status & reset) break; |
| 630 | delay(100); |
| 631 | status |= reset; |
| 632 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); |
| 633 | } |
| 634 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 635 | status &= ~reset; |
| 636 | bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); |
| 637 | status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); |
| 638 | |
| 639 | wdc_do_reset(chp, poll); |
| 640 | } |
| 641 | |