| 1 | /* $NetBSD: specialreg.h,v 1.89 2016/08/19 18:53:29 maxv Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 1991 The Regents of the University of California. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. Neither the name of the University nor the names of its contributors |
| 16 | * may be used to endorse or promote products derived from this software |
| 17 | * without specific prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | * |
| 31 | * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 32 | */ |
| 33 | |
| 34 | /* |
| 35 | * Bits in 386 special registers: |
| 36 | */ |
| 37 | #define CR0_PE 0x00000001 /* Protected mode Enable */ |
| 38 | #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ |
| 39 | #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ |
| 40 | #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ |
| 41 | #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ |
| 42 | #define CR0_PG 0x80000000 /* PaGing enable */ |
| 43 | |
| 44 | /* |
| 45 | * Bits in 486 special registers: |
| 46 | */ |
| 47 | #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ |
| 48 | #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ |
| 49 | #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ |
| 50 | #define CR0_NW 0x20000000 /* Not Write-through */ |
| 51 | #define CR0_CD 0x40000000 /* Cache Disable */ |
| 52 | |
| 53 | /* |
| 54 | * Cyrix 486 DLC special registers, accessible as IO ports. |
| 55 | */ |
| 56 | #define CCR0 0xc0 /* configuration control register 0 */ |
| 57 | #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ |
| 58 | #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ |
| 59 | #define CCR0_A20M 0x04 /* enables A20M# input pin */ |
| 60 | #define CCR0_KEN 0x08 /* enables KEN# input pin */ |
| 61 | #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ |
| 62 | #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ |
| 63 | #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ |
| 64 | #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ |
| 65 | |
| 66 | #define CCR1 0xc1 /* configuration control register 1 */ |
| 67 | #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ |
| 68 | /* the remaining 7 bits of this register are reserved */ |
| 69 | |
| 70 | /* |
| 71 | * bits in the %cr4 control register: |
| 72 | */ |
| 73 | #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ |
| 74 | #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ |
| 75 | #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ |
| 76 | #define CR4_DE 0x00000008 /* debugging extension */ |
| 77 | #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ |
| 78 | #define CR4_PAE 0x00000020 /* physical address extension enable */ |
| 79 | #define CR4_MCE 0x00000040 /* machine check enable */ |
| 80 | #define CR4_PGE 0x00000080 /* page global enable */ |
| 81 | #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ |
| 82 | #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ |
| 83 | #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ |
| 84 | #define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ |
| 85 | #define CR4_VMXE 0x00002000 /* enable VMX operations */ |
| 86 | #define CR4_SMXE 0x00004000 /* enable SMX operations */ |
| 87 | #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ |
| 88 | #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ |
| 89 | #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ |
| 90 | #define CR4_SMEP 0x00100000 /* enable SMEP support */ |
| 91 | #define CR4_SMAP 0x00200000 /* enable SMAP support */ |
| 92 | #define CR4_PKE 0x00400000 /* protection key enable */ |
| 93 | |
| 94 | /* |
| 95 | * Extended Control Register XCR0 |
| 96 | */ |
| 97 | #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ |
| 98 | #define XCR0_SSE 0x00000002 /* SSE state */ |
| 99 | #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ |
| 100 | #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ |
| 101 | #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ |
| 102 | #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ |
| 103 | #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ |
| 104 | #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ |
| 105 | |
| 106 | /* |
| 107 | * Known fpu bits - only these get enabled |
| 108 | * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on |
| 109 | * every context switch. |
| 110 | * The save are is sized for all the fields below (max 2680 bytes). |
| 111 | */ |
| 112 | #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ |
| 113 | XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) |
| 114 | |
| 115 | #define XCR0_BND (XCR0_BNDREGS | XCR0_BNDCSR) |
| 116 | |
| 117 | #define XCR0_FLAGS1 "\20" \ |
| 118 | "\1" "x87" "\2" "SSE" "\3" "AVX" \ |
| 119 | "\4" "BNDREGS" "\5" "BNDCSR" \ |
| 120 | "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" |
| 121 | |
| 122 | |
| 123 | /* |
| 124 | * CPUID "features" bits |
| 125 | */ |
| 126 | |
| 127 | /* Fn00000001 %edx features */ |
| 128 | #define CPUID_FPU 0x00000001 /* processor has an FPU? */ |
| 129 | #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ |
| 130 | #define CPUID_DE 0x00000004 /* has debugging extension */ |
| 131 | #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ |
| 132 | #define CPUID_TSC 0x00000010 /* has time stamp counter */ |
| 133 | #define CPUID_MSR 0x00000020 /* has mode specific registers */ |
| 134 | #define CPUID_PAE 0x00000040 /* has phys address extension */ |
| 135 | #define CPUID_MCE 0x00000080 /* has machine check exception */ |
| 136 | #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ |
| 137 | #define CPUID_APIC 0x00000200 /* has enabled APIC */ |
| 138 | #define CPUID_B10 0x00000400 /* reserved, MTRR */ |
| 139 | #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ |
| 140 | #define CPUID_MTRR 0x00001000 /* has memory type range register */ |
| 141 | #define CPUID_PGE 0x00002000 /* has page global extension */ |
| 142 | #define CPUID_MCA 0x00004000 /* has machine check architecture */ |
| 143 | #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ |
| 144 | #define CPUID_PAT 0x00010000 /* Page Attribute Table */ |
| 145 | #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ |
| 146 | #define CPUID_PN 0x00040000 /* processor serial number */ |
| 147 | #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ |
| 148 | #define CPUID_B20 0x00100000 /* reserved */ |
| 149 | #define CPUID_DS 0x00200000 /* Debug Store */ |
| 150 | #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ |
| 151 | #define CPUID_MMX 0x00800000 /* MMX supported */ |
| 152 | #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ |
| 153 | #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ |
| 154 | #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ |
| 155 | #define CPUID_SS 0x08000000 /* self-snoop */ |
| 156 | #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ |
| 157 | #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ |
| 158 | #define CPUID_IA64 0x40000000 /* IA-64 architecture */ |
| 159 | #define CPUID_SBF 0x80000000 /* signal break on FERR */ |
| 160 | |
| 161 | #define CPUID_FLAGS1 "\20" \ |
| 162 | "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ |
| 163 | "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ |
| 164 | "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ |
| 165 | "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ |
| 166 | "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \ |
| 167 | "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ |
| 168 | "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ |
| 169 | "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" |
| 170 | |
| 171 | /* Blacklists of CPUID flags - used to mask certain features */ |
| 172 | #ifdef XEN |
| 173 | /* Not on Xen */ |
| 174 | #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) |
| 175 | #else |
| 176 | #define CPUID_FEAT_BLACKLIST 0 |
| 177 | #endif /* XEN */ |
| 178 | |
| 179 | /* |
| 180 | * CPUID "features" bits in Fn00000001 %ecx |
| 181 | */ |
| 182 | |
| 183 | #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ |
| 184 | #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ |
| 185 | #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ |
| 186 | #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ |
| 187 | #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ |
| 188 | #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ |
| 189 | #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ |
| 190 | #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ |
| 191 | #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ |
| 192 | #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ |
| 193 | #define CPUID2_CID 0x00000400 /* Context ID */ |
| 194 | #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ |
| 195 | #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ |
| 196 | #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ |
| 197 | #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ |
| 198 | #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ |
| 199 | /* bit 16 unused 0x00010000 */ |
| 200 | #define CPUID2_PCID 0x00020000 /* Process Context ID */ |
| 201 | #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ |
| 202 | #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ |
| 203 | #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ |
| 204 | #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ |
| 205 | #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ |
| 206 | #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ |
| 207 | #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ |
| 208 | #define CPUID2_AES 0x02000000 /* AES instructions */ |
| 209 | #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ |
| 210 | #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ |
| 211 | #define CPUID2_AVX 0x10000000 /* AVX instructions */ |
| 212 | #define CPUID2_F16C 0x20000000 /* half precision conversion */ |
| 213 | #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ |
| 214 | #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ |
| 215 | |
| 216 | #define CPUID2_FLAGS1 "\20" \ |
| 217 | "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ |
| 218 | "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ |
| 219 | "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ |
| 220 | "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ |
| 221 | "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ |
| 222 | "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ |
| 223 | "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ |
| 224 | "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" |
| 225 | |
| 226 | /* CPUID Fn00000001 %eax */ |
| 227 | |
| 228 | #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) |
| 229 | #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) |
| 230 | #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) |
| 231 | |
| 232 | /* |
| 233 | * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() |
| 234 | * returns 15. They are use to encode family value 16 to 270 (add 15). |
| 235 | * The Extended model bits are the high 4 bits of the model. |
| 236 | * They are only valid for family >= 15 or family 6 (intel, but all amd |
| 237 | * family 6 are documented to return zero bits for them). |
| 238 | */ |
| 239 | #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) |
| 240 | #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) |
| 241 | |
| 242 | /* The macros for the Display Family and the Display Model */ |
| 243 | #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ |
| 244 | + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ |
| 245 | ? 0 : CPUID_TO_EXTFAMILY(cpuid))) |
| 246 | #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ |
| 247 | | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ |
| 248 | && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ |
| 249 | ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) |
| 250 | |
| 251 | /* |
| 252 | * Intel Deterministic Cache Parameter Leaf |
| 253 | * Fn0000_0004 |
| 254 | */ |
| 255 | |
| 256 | /* %eax */ |
| 257 | #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ |
| 258 | #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ |
| 259 | #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ |
| 260 | #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ |
| 261 | #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ |
| 262 | #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ |
| 263 | #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ |
| 264 | #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ |
| 265 | #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ |
| 266 | #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ |
| 267 | |
| 268 | /* %ebx */ |
| 269 | #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ |
| 270 | #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ |
| 271 | #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ |
| 272 | |
| 273 | /* Number of sets: %ecx */ |
| 274 | |
| 275 | /* %edx */ |
| 276 | #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ |
| 277 | #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ |
| 278 | #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ |
| 279 | |
| 280 | /* |
| 281 | * Intel Digital Thermal Sensor and |
| 282 | * Power Management, Fn0000_0006 - %eax. |
| 283 | */ |
| 284 | #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ |
| 285 | #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ |
| 286 | #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ |
| 287 | #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ |
| 288 | #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ |
| 289 | #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ |
| 290 | #define CPUID_DSPM_HWP __BIT(7) /* HWP */ |
| 291 | #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ |
| 292 | #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ |
| 293 | #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ |
| 294 | #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ |
| 295 | #define CPUID_DSPM_HDC __BIT(13) /* HDC */ |
| 296 | |
| 297 | #define CPUID_DSPM_FLAGS "\20" \ |
| 298 | "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ |
| 299 | "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ |
| 300 | "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ |
| 301 | "\16" "HDC" |
| 302 | |
| 303 | /* |
| 304 | * Intel Digital Thermal Sensor and |
| 305 | * Power Management, Fn0000_0006 - %ecx. |
| 306 | */ |
| 307 | #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ |
| 308 | #define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */ |
| 309 | |
| 310 | #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" |
| 311 | |
| 312 | /* |
| 313 | * Intel Structured Extended Feature leaf Fn0000_0007 |
| 314 | * %eax == 0: Subleaf 0 |
| 315 | * %eax: The Maximum input value for supported subleaf. |
| 316 | * %ebx: Feature bits. |
| 317 | * %ecx: Feature bits. |
| 318 | */ |
| 319 | |
| 320 | /* %ebx */ |
| 321 | #define CPUID_SEF_FSGSBASE __BIT(0) |
| 322 | #define CPUID_SEF_TSC_ADJUST __BIT(1) |
| 323 | #define CPUID_SEF_SGX __BIT(2) |
| 324 | #define CPUID_SEF_BMI1 __BIT(3) |
| 325 | #define CPUID_SEF_HLE __BIT(4) |
| 326 | #define CPUID_SEF_AVX2 __BIT(5) |
| 327 | #define CPUID_SEF_FDPEXONLY __BIT(6) |
| 328 | #define CPUID_SEF_SMEP __BIT(7) |
| 329 | #define CPUID_SEF_BMI2 __BIT(8) |
| 330 | #define CPUID_SEF_ERMS __BIT(9) |
| 331 | #define CPUID_SEF_INVPCID __BIT(10) |
| 332 | #define CPUID_SEF_RTM __BIT(11) |
| 333 | #define CPUID_SEF_QM __BIT(12) |
| 334 | #define CPUID_SEF_FPUCSDS __BIT(13) |
| 335 | #define CPUID_SEF_MPX __BIT(14) |
| 336 | #define CPUID_SEF_PQE __BIT(15) |
| 337 | #define CPUID_SEF_AVX512F __BIT(16) |
| 338 | #define CPUID_SEF_AVX512DQ __BIT(17) |
| 339 | #define CPUID_SEF_RDSEED __BIT(18) |
| 340 | #define CPUID_SEF_ADX __BIT(19) |
| 341 | #define CPUID_SEF_SMAP __BIT(20) |
| 342 | #define CPUID_SEF_CLFLUSHOPT __BIT(23) |
| 343 | #define CPUID_SEF_PT __BIT(25) |
| 344 | #define CPUID_SEF_AVX512PF __BIT(26) |
| 345 | #define CPUID_SEF_AVX512ER __BIT(27) |
| 346 | #define CPUID_SEF_AVX512CD __BIT(28) |
| 347 | #define CPUID_SEF_SHA __BIT(29) |
| 348 | #define CPUID_SEF_AVX512BW __BIT(30) |
| 349 | #define CPUID_SEF_AVX512VL __BIT(31) |
| 350 | |
| 351 | #define CPUID_SEF_FLAGS "\20" \ |
| 352 | "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ |
| 353 | "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ |
| 354 | "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ |
| 355 | "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ |
| 356 | "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ |
| 357 | "\25" "SMAP" "\28" "CLFLUSHOPT" \ |
| 358 | "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ |
| 359 | "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\38" "AVX512VL" |
| 360 | |
| 361 | /* %ecx */ |
| 362 | #define CPUID_SEF_PREFETCHWT1 __BIT(0) |
| 363 | #define CPUID_SEF_UMIP __BIT(2) |
| 364 | #define CPUID_SEF_PKU __BIT(3) |
| 365 | #define CPUID_SEF_OSPKE __BIT(4) |
| 366 | #define CPUID_SEF_RDPID __BIT(22) |
| 367 | #define CPUID_SEF_SGXLC __BIT(30) |
| 368 | |
| 369 | #define CPUID_SEF_FLAGS1 "\20" \ |
| 370 | "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \ |
| 371 | "\5" "OSPKE" \ |
| 372 | "\27" "RDPID" \ |
| 373 | "\37" "SGXLC" |
| 374 | |
| 375 | /* |
| 376 | * CPUID Processor extended state Enumeration Fn0000000d |
| 377 | * |
| 378 | * %ecx == 0: supported features info: |
| 379 | * %eax: Valid bits of lower 32bits of XCR0 |
| 380 | * %ebx: Maximum save area size for features enabled in XCR0 |
| 381 | * %ecx: Maximum save area size for all cpu features |
| 382 | * %edx: Valid bits of upper 32bits of XCR0 |
| 383 | * |
| 384 | * %ecx == 1: |
| 385 | * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) |
| 386 | * %ebx: Save area size for features enabled by XCR0 | IA32_XSS |
| 387 | * %ecx: Valid bits of lower 32bits of IA32_XSS |
| 388 | * %edx: Valid bits of upper 32bits of IA32_XSS |
| 389 | * |
| 390 | * %ecx >= 2: Save area details for XCR0 bit n |
| 391 | * %eax: size of save area for this feature |
| 392 | * %ebx: offset of save area for this feature |
| 393 | * %ecx, %edx: reserved |
| 394 | * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. |
| 395 | */ |
| 396 | |
| 397 | /* %ecx=1 %eax */ |
| 398 | #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ |
| 399 | #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ |
| 400 | #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ |
| 401 | #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ |
| 402 | |
| 403 | #define CPUID_PES1_FLAGS "\20" \ |
| 404 | "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" |
| 405 | |
| 406 | /* Intel Fn80000001 extended features - %edx */ |
| 407 | #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ |
| 408 | #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ |
| 409 | #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ |
| 410 | #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ |
| 411 | #define CPUID_EM64T 0x20000000 /* Intel EM64T */ |
| 412 | |
| 413 | #define CPUID_INTEL_EXT_FLAGS "\20" \ |
| 414 | "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ |
| 415 | "\34" "RDTSCP" "\36" "EM64T" |
| 416 | |
| 417 | /* Intel Fn80000001 extended features - %ecx */ |
| 418 | #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ |
| 419 | /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ |
| 420 | #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ |
| 421 | |
| 422 | #define CPUID_INTEL_FLAGS4 "\20" \ |
| 423 | "\1" "LAHF" "\02" "B01" "\03" "B02" \ |
| 424 | "\06" "LZCNT" \ |
| 425 | "\11" "PREFETCHW" |
| 426 | |
| 427 | /* AMD/VIA Fn80000001 extended features - %edx */ |
| 428 | /* CPUID_SYSCALL SYSCALL/SYSRET */ |
| 429 | #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ |
| 430 | #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ |
| 431 | #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ |
| 432 | #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ |
| 433 | /* CPUID_P1GB 1GB Large Page Support */ |
| 434 | /* CPUID_RDTSCP Read TSC Pair Instruction */ |
| 435 | /* CPUID_EM64T Long mode */ |
| 436 | #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ |
| 437 | #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ |
| 438 | |
| 439 | #define CPUID_EXT_FLAGS "\20" \ |
| 440 | "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \ |
| 441 | "\27" "MMXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ |
| 442 | "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" |
| 443 | |
| 444 | /* AMD Fn80000001 extended features - %ecx */ |
| 445 | /* CPUID_LAHF LAHF/SAHF instruction */ |
| 446 | #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ |
| 447 | #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ |
| 448 | #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ |
| 449 | #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ |
| 450 | #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ |
| 451 | #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ |
| 452 | #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ |
| 453 | #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ |
| 454 | #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ |
| 455 | #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ |
| 456 | #define CPUID_XOP 0x00000800 /* XOP instruction set */ |
| 457 | #define CPUID_SKINIT 0x00001000 /* SKINIT */ |
| 458 | #define CPUID_WDT 0x00002000 /* watchdog timer support */ |
| 459 | #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ |
| 460 | #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ |
| 461 | #define CPUID_TCE 0x00020000 /* Translation cache Extension */ |
| 462 | #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ |
| 463 | #define CPUID_TBM 0x00200000 /* TBM instructions */ |
| 464 | #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ |
| 465 | #define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */ |
| 466 | #define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */ |
| 467 | #define CPUID_SPM 0x02000000 /* Stream Perf Mon */ |
| 468 | #define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */ |
| 469 | #define CPUID_PTSC 0x08000000 /* PerfTsc */ |
| 470 | #define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */ |
| 471 | #define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */ |
| 472 | |
| 473 | #define CPUID_AMD_FLAGS4 "\20" \ |
| 474 | "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ |
| 475 | "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ |
| 476 | "\11" "3DNOWPREFETCH" \ |
| 477 | "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ |
| 478 | "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ |
| 479 | "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ |
| 480 | "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ |
| 481 | "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ |
| 482 | "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" |
| 483 | |
| 484 | /* |
| 485 | * AMD Advanced Power Management |
| 486 | * CPUID Fn8000_0007 %edx |
| 487 | */ |
| 488 | #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ |
| 489 | #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ |
| 490 | #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ |
| 491 | #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ |
| 492 | #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ |
| 493 | #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ |
| 494 | #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ |
| 495 | #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ |
| 496 | #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ |
| 497 | #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ |
| 498 | #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ |
| 499 | |
| 500 | #define CPUID_APM_FLAGS "\20" \ |
| 501 | "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ |
| 502 | "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ |
| 503 | "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ |
| 504 | "\15" "B12" |
| 505 | |
| 506 | /* AMD Fn8000000a %edx features (SVM features) */ |
| 507 | #define CPUID_AMD_SVM_NP 0x00000001 |
| 508 | #define CPUID_AMD_SVM_LbrVirt 0x00000002 |
| 509 | #define CPUID_AMD_SVM_SVML 0x00000004 |
| 510 | #define CPUID_AMD_SVM_NRIPS 0x00000008 |
| 511 | #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 |
| 512 | #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 |
| 513 | #define CPUID_AMD_SVM_FlushByASID 0x00000040 |
| 514 | #define CPUID_AMD_SVM_DecodeAssist 0x00000080 |
| 515 | #define CPUID_AMD_SVM_PauseFilter 0x00000400 |
| 516 | #define CPUID_AMD_SVM_FLAGS "\20" \ |
| 517 | "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ |
| 518 | "\5" "TSCRate" "\6" "VMCBCleanBits" \ |
| 519 | "\7" "FlushByASID" "\10" "DecodeAssist" \ |
| 520 | "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ |
| 521 | "\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \ |
| 522 | "\21" "B19" |
| 523 | |
| 524 | /* |
| 525 | * Centaur Extended Feature flags |
| 526 | */ |
| 527 | #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ |
| 528 | #define CPUID_VIA_DO_RNG 0x00000008 |
| 529 | #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ |
| 530 | #define CPUID_VIA_DO_ACE 0x00000080 |
| 531 | #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ |
| 532 | #define CPUID_VIA_DO_ACE2 0x00000200 |
| 533 | #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ |
| 534 | #define CPUID_VIA_DO_PHE 0x00000800 |
| 535 | #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ |
| 536 | #define CPUID_VIA_DO_PMM 0x00002000 |
| 537 | |
| 538 | #define CPUID_FLAGS_PADLOCK "\20" \ |
| 539 | "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ |
| 540 | "\15" "RSA" |
| 541 | |
| 542 | /* |
| 543 | * Model-specific registers for the i386 family |
| 544 | */ |
| 545 | #define MSR_P5_MC_ADDR 0x000 /* P5 only */ |
| 546 | #define MSR_P5_MC_TYPE 0x001 /* P5 only */ |
| 547 | #define MSR_TSC 0x010 |
| 548 | #define MSR_CESR 0x011 /* P5 only (trap on P6) */ |
| 549 | #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ |
| 550 | #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ |
| 551 | #define MSR_IA32_PLATFORM_ID 0x017 |
| 552 | #define MSR_APICBASE 0x01b |
| 553 | #define MSR_EBL_CR_POWERON 0x02a |
| 554 | #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ |
| 555 | #define MSR_TEST_CTL 0x033 |
| 556 | #define MSR_BIOS_UPDT_TRIG 0x079 |
| 557 | #define MSR_BBL_CR_D0 0x088 /* PII+ only */ |
| 558 | #define MSR_BBL_CR_D1 0x089 /* PII+ only */ |
| 559 | #define MSR_BBL_CR_D2 0x08a /* PII+ only */ |
| 560 | #define MSR_BIOS_SIGN 0x08b |
| 561 | #define MSR_PERFCTR0 0x0c1 |
| 562 | #define MSR_PERFCTR1 0x0c2 |
| 563 | #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ |
| 564 | #define MSR_MPERF 0x0e7 |
| 565 | #define MSR_APERF 0x0e8 |
| 566 | #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ |
| 567 | #define MSR_MTRRcap 0x0fe |
| 568 | #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ |
| 569 | #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ |
| 570 | #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ |
| 571 | #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ |
| 572 | #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ |
| 573 | #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ |
| 574 | #define MSR_SYSENTER_CS 0x174 /* PII+ only */ |
| 575 | #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ |
| 576 | #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ |
| 577 | #define MSR_MCG_CAP 0x179 |
| 578 | #define MSR_MCG_STATUS 0x17a |
| 579 | #define MSR_MCG_CTL 0x17b |
| 580 | #define MSR_EVNTSEL0 0x186 |
| 581 | #define MSR_EVNTSEL1 0x187 |
| 582 | #define MSR_PERF_STATUS 0x198 /* Pentium M */ |
| 583 | #define MSR_PERF_CTL 0x199 /* Pentium M */ |
| 584 | #define MSR_THERM_CONTROL 0x19a |
| 585 | #define MSR_THERM_INTERRUPT 0x19b |
| 586 | #define MSR_THERM_STATUS 0x19c |
| 587 | #define MSR_THERM2_CTL 0x19d /* Pentium M */ |
| 588 | #define MSR_MISC_ENABLE 0x1a0 |
| 589 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
| 590 | #define MSR_DEBUGCTLMSR 0x1d9 |
| 591 | #define MSR_LASTBRANCHFROMIP 0x1db |
| 592 | #define MSR_LASTBRANCHTOIP 0x1dc |
| 593 | #define MSR_LASTINTFROMIP 0x1dd |
| 594 | #define MSR_LASTINTTOIP 0x1de |
| 595 | #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 |
| 596 | #define MSR_MTRRphysBase0 0x200 |
| 597 | #define MSR_MTRRphysMask0 0x201 |
| 598 | #define MSR_MTRRphysBase1 0x202 |
| 599 | #define MSR_MTRRphysMask1 0x203 |
| 600 | #define MSR_MTRRphysBase2 0x204 |
| 601 | #define MSR_MTRRphysMask2 0x205 |
| 602 | #define MSR_MTRRphysBase3 0x206 |
| 603 | #define MSR_MTRRphysMask3 0x207 |
| 604 | #define MSR_MTRRphysBase4 0x208 |
| 605 | #define MSR_MTRRphysMask4 0x209 |
| 606 | #define MSR_MTRRphysBase5 0x20a |
| 607 | #define MSR_MTRRphysMask5 0x20b |
| 608 | #define MSR_MTRRphysBase6 0x20c |
| 609 | #define MSR_MTRRphysMask6 0x20d |
| 610 | #define MSR_MTRRphysBase7 0x20e |
| 611 | #define MSR_MTRRphysMask7 0x20f |
| 612 | #define MSR_MTRRphysBase8 0x210 |
| 613 | #define MSR_MTRRphysMask8 0x211 |
| 614 | #define MSR_MTRRphysBase9 0x212 |
| 615 | #define MSR_MTRRphysMask9 0x213 |
| 616 | #define MSR_MTRRphysBase10 0x214 |
| 617 | #define MSR_MTRRphysMask10 0x215 |
| 618 | #define MSR_MTRRphysBase11 0x216 |
| 619 | #define MSR_MTRRphysMask11 0x217 |
| 620 | #define MSR_MTRRphysBase12 0x218 |
| 621 | #define MSR_MTRRphysMask12 0x219 |
| 622 | #define MSR_MTRRphysBase13 0x21a |
| 623 | #define MSR_MTRRphysMask13 0x21b |
| 624 | #define MSR_MTRRphysBase14 0x21c |
| 625 | #define MSR_MTRRphysMask14 0x21d |
| 626 | #define MSR_MTRRphysBase15 0x21e |
| 627 | #define MSR_MTRRphysMask15 0x21f |
| 628 | #define MSR_MTRRfix64K_00000 0x250 |
| 629 | #define MSR_MTRRfix16K_80000 0x258 |
| 630 | #define MSR_MTRRfix16K_A0000 0x259 |
| 631 | #define MSR_MTRRfix4K_C0000 0x268 |
| 632 | #define MSR_MTRRfix4K_C8000 0x269 |
| 633 | #define MSR_MTRRfix4K_D0000 0x26a |
| 634 | #define MSR_MTRRfix4K_D8000 0x26b |
| 635 | #define MSR_MTRRfix4K_E0000 0x26c |
| 636 | #define MSR_MTRRfix4K_E8000 0x26d |
| 637 | #define MSR_MTRRfix4K_F0000 0x26e |
| 638 | #define MSR_MTRRfix4K_F8000 0x26f |
| 639 | #define MSR_CR_PAT 0x277 |
| 640 | #define MSR_MTRRdefType 0x2ff |
| 641 | #define MSR_MC0_CTL 0x400 |
| 642 | #define MSR_MC0_STATUS 0x401 |
| 643 | #define MSR_MC0_ADDR 0x402 |
| 644 | #define MSR_MC0_MISC 0x403 |
| 645 | #define MSR_MC1_CTL 0x404 |
| 646 | #define MSR_MC1_STATUS 0x405 |
| 647 | #define MSR_MC1_ADDR 0x406 |
| 648 | #define MSR_MC1_MISC 0x407 |
| 649 | #define MSR_MC2_CTL 0x408 |
| 650 | #define MSR_MC2_STATUS 0x409 |
| 651 | #define MSR_MC2_ADDR 0x40a |
| 652 | #define MSR_MC2_MISC 0x40b |
| 653 | #define MSR_MC4_CTL 0x40c |
| 654 | #define MSR_MC4_STATUS 0x40d |
| 655 | #define MSR_MC4_ADDR 0x40e |
| 656 | #define MSR_MC4_MISC 0x40f |
| 657 | #define MSR_MC3_CTL 0x410 |
| 658 | #define MSR_MC3_STATUS 0x411 |
| 659 | #define MSR_MC3_ADDR 0x412 |
| 660 | #define MSR_MC3_MISC 0x413 |
| 661 | /* 0x480 - 0x490 VMX */ |
| 662 | |
| 663 | /* |
| 664 | * VIA "Nehemiah" MSRs |
| 665 | */ |
| 666 | #define MSR_VIA_RNG 0x0000110b |
| 667 | #define MSR_VIA_RNG_ENABLE 0x00000040 |
| 668 | #define MSR_VIA_RNG_NOISE_MASK 0x00000300 |
| 669 | #define MSR_VIA_RNG_NOISE_A 0x00000000 |
| 670 | #define MSR_VIA_RNG_NOISE_B 0x00000100 |
| 671 | #define MSR_VIA_RNG_2NOISE 0x00000300 |
| 672 | #define MSR_VIA_ACE 0x00001107 |
| 673 | #define MSR_VIA_ACE_ENABLE 0x10000000 |
| 674 | |
| 675 | /* |
| 676 | * VIA "Eden" MSRs |
| 677 | */ |
| 678 | #define MSR_VIA_FCR MSR_VIA_ACE |
| 679 | |
| 680 | /* |
| 681 | * AMD K6/K7 MSRs. |
| 682 | */ |
| 683 | #define MSR_K6_UWCCR 0xc0000085 |
| 684 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 685 | #define MSR_K7_EVNTSEL1 0xc0010001 |
| 686 | #define MSR_K7_EVNTSEL2 0xc0010002 |
| 687 | #define MSR_K7_EVNTSEL3 0xc0010003 |
| 688 | #define MSR_K7_PERFCTR0 0xc0010004 |
| 689 | #define MSR_K7_PERFCTR1 0xc0010005 |
| 690 | #define MSR_K7_PERFCTR2 0xc0010006 |
| 691 | #define MSR_K7_PERFCTR3 0xc0010007 |
| 692 | |
| 693 | /* |
| 694 | * AMD K8 (Opteron) MSRs. |
| 695 | */ |
| 696 | #define MSR_SYSCFG 0xc0000010 |
| 697 | |
| 698 | #define MSR_EFER 0xc0000080 /* Extended feature enable */ |
| 699 | #define EFER_SCE 0x00000001 /* SYSCALL extension */ |
| 700 | #define EFER_LME 0x00000100 /* Long Mode Active */ |
| 701 | #define EFER_LMA 0x00000400 /* Long Mode Enabled */ |
| 702 | #define EFER_NXE 0x00000800 /* No-Execute Enabled */ |
| 703 | |
| 704 | #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ |
| 705 | #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ |
| 706 | #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ |
| 707 | #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ |
| 708 | |
| 709 | #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ |
| 710 | #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ |
| 711 | #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ |
| 712 | |
| 713 | #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ |
| 714 | #define VMCR_DPD 0x00000001 /* Debug port disable */ |
| 715 | #define VMCR_RINIT 0x00000002 /* intercept init */ |
| 716 | #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ |
| 717 | #define VMCR_LOCK 0x00000008 /* SVM Lock */ |
| 718 | #define VMCR_SVMED 0x00000010 /* SVME Disable */ |
| 719 | #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ |
| 720 | |
| 721 | /* |
| 722 | * These require a 'passcode' for access. See cpufunc.h. |
| 723 | */ |
| 724 | #define MSR_HWCR 0xc0010015 |
| 725 | #define HWCR_TLBCACHEDIS 0x00000008 |
| 726 | #define HWCR_FFDIS 0x00000040 |
| 727 | |
| 728 | #define MSR_NB_CFG 0xc001001f |
| 729 | #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL |
| 730 | #define NB_CFG_DISDATMSK 0x0000001000000000ULL |
| 731 | #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) |
| 732 | |
| 733 | #define MSR_LS_CFG 0xc0011020 |
| 734 | #define LS_CFG_DIS_LS2_SQUISH 0x02000000 |
| 735 | |
| 736 | #define MSR_IC_CFG 0xc0011021 |
| 737 | #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 |
| 738 | |
| 739 | #define MSR_DC_CFG 0xc0011022 |
| 740 | #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 |
| 741 | #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 |
| 742 | #define DC_CFG_ERRATA_261 0x01000000 |
| 743 | |
| 744 | #define MSR_BU_CFG 0xc0011023 |
| 745 | #define BU_CFG_ERRATA_298 0x0000000000000002ULL |
| 746 | #define BU_CFG_ERRATA_254 0x0000000000200000ULL |
| 747 | #define BU_CFG_ERRATA_309 0x0000000000800000ULL |
| 748 | #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL |
| 749 | #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL |
| 750 | #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL |
| 751 | |
| 752 | #define MSR_DE_CFG 0xc0011029 |
| 753 | #define DE_CFG_ERRATA_721 0x00000001 |
| 754 | |
| 755 | /* AMD Family10h MSRs */ |
| 756 | #define MSR_OSVW_ID_LENGTH 0xc0010140 |
| 757 | #define MSR_OSVW_STATUS 0xc0010141 |
| 758 | #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b |
| 759 | #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 |
| 760 | |
| 761 | /* X86 MSRs */ |
| 762 | #define MSR_RDTSCP_AUX 0xc0000103 |
| 763 | |
| 764 | /* |
| 765 | * Constants related to MTRRs |
| 766 | */ |
| 767 | #define MTRR_N64K 8 /* numbers of fixed-size entries */ |
| 768 | #define MTRR_N16K 16 |
| 769 | #define MTRR_N4K 64 |
| 770 | |
| 771 | /* |
| 772 | * the following four 3-byte registers control the non-cacheable regions. |
| 773 | * These registers must be written as three separate bytes. |
| 774 | * |
| 775 | * NCRx+0: A31-A24 of starting address |
| 776 | * NCRx+1: A23-A16 of starting address |
| 777 | * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. |
| 778 | * |
| 779 | * The non-cacheable region's starting address must be aligned to the |
| 780 | * size indicated by the NCR_SIZE_xx field. |
| 781 | */ |
| 782 | #define NCR1 0xc4 |
| 783 | #define NCR2 0xc7 |
| 784 | #define NCR3 0xca |
| 785 | #define NCR4 0xcd |
| 786 | |
| 787 | #define NCR_SIZE_0K 0 |
| 788 | #define NCR_SIZE_4K 1 |
| 789 | #define NCR_SIZE_8K 2 |
| 790 | #define NCR_SIZE_16K 3 |
| 791 | #define NCR_SIZE_32K 4 |
| 792 | #define NCR_SIZE_64K 5 |
| 793 | #define NCR_SIZE_128K 6 |
| 794 | #define NCR_SIZE_256K 7 |
| 795 | #define NCR_SIZE_512K 8 |
| 796 | #define NCR_SIZE_1M 9 |
| 797 | #define NCR_SIZE_2M 10 |
| 798 | #define NCR_SIZE_4M 11 |
| 799 | #define NCR_SIZE_8M 12 |
| 800 | #define NCR_SIZE_16M 13 |
| 801 | #define NCR_SIZE_32M 14 |
| 802 | #define NCR_SIZE_4G 15 |
| 803 | |
| 804 | /* |
| 805 | * Performance monitor events. |
| 806 | * |
| 807 | * Note that 586-class and 686-class CPUs have different performance |
| 808 | * monitors available, and they are accessed differently: |
| 809 | * |
| 810 | * 686-class: `rdpmc' instruction |
| 811 | * 586-class: `rdmsr' instruction, CESR MSR |
| 812 | * |
| 813 | * The descriptions of these events are too lengthy to include here. |
| 814 | * See Appendix A of "Intel Architecture Software Developer's |
| 815 | * Manual, Volume 3: System Programming" for more information. |
| 816 | */ |
| 817 | |
| 818 | /* |
| 819 | * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits |
| 820 | * is CTR1. |
| 821 | */ |
| 822 | |
| 823 | #define PMC5_CESR_EVENT 0x003f |
| 824 | #define PMC5_CESR_OS 0x0040 |
| 825 | #define PMC5_CESR_USR 0x0080 |
| 826 | #define PMC5_CESR_E 0x0100 |
| 827 | #define PMC5_CESR_P 0x0200 |
| 828 | |
| 829 | #define PMC5_DATA_READ 0x00 |
| 830 | #define PMC5_DATA_WRITE 0x01 |
| 831 | #define PMC5_DATA_TLB_MISS 0x02 |
| 832 | #define PMC5_DATA_READ_MISS 0x03 |
| 833 | #define PMC5_DATA_WRITE_MISS 0x04 |
| 834 | #define PMC5_WRITE_M_E 0x05 |
| 835 | #define PMC5_DATA_LINES_WBACK 0x06 |
| 836 | #define PMC5_DATA_CACHE_SNOOP 0x07 |
| 837 | #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 |
| 838 | #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 |
| 839 | #define PMC5_BANK_CONFLICTS 0x0a |
| 840 | #define PMC5_MISALIGNED_DATA 0x0b |
| 841 | #define PMC5_INST_READ 0x0c |
| 842 | #define PMC5_INST_TLB_MISS 0x0d |
| 843 | #define PMC5_INST_CACHE_MISS 0x0e |
| 844 | #define PMC5_SEGMENT_REG_LOAD 0x0f |
| 845 | #define PMC5_BRANCHES 0x12 |
| 846 | #define PMC5_BTB_HITS 0x13 |
| 847 | #define PMC5_BRANCH_TAKEN 0x14 |
| 848 | #define PMC5_PIPELINE_FLUSH 0x15 |
| 849 | #define PMC5_INST_EXECUTED 0x16 |
| 850 | #define PMC5_INST_EXECUTED_V_PIPE 0x17 |
| 851 | #define PMC5_BUS_UTILIZATION 0x18 |
| 852 | #define PMC5_WRITE_BACKUP_STALL 0x19 |
| 853 | #define PMC5_DATA_READ_STALL 0x1a |
| 854 | #define PMC5_WRITE_E_M_STALL 0x1b |
| 855 | #define PMC5_LOCKED_BUS 0x1c |
| 856 | #define PMC5_IO_CYCLE 0x1d |
| 857 | #define PMC5_NONCACHE_MEM_READ 0x1e |
| 858 | #define PMC5_AGI_STALL 0x1f |
| 859 | #define PMC5_FLOPS 0x22 |
| 860 | #define PMC5_BP0_MATCH 0x23 |
| 861 | #define PMC5_BP1_MATCH 0x24 |
| 862 | #define PMC5_BP2_MATCH 0x25 |
| 863 | #define PMC5_BP3_MATCH 0x26 |
| 864 | #define PMC5_HARDWARE_INTR 0x27 |
| 865 | #define PMC5_DATA_RW 0x28 |
| 866 | #define PMC5_DATA_RW_MISS 0x29 |
| 867 | |
| 868 | /* |
| 869 | * 686-class Event Selector MSR format. |
| 870 | */ |
| 871 | |
| 872 | #define PMC6_EVTSEL_EVENT 0x000000ff |
| 873 | #define PMC6_EVTSEL_UNIT 0x0000ff00 |
| 874 | #define PMC6_EVTSEL_UNIT_SHIFT 8 |
| 875 | #define PMC6_EVTSEL_USR (1 << 16) |
| 876 | #define PMC6_EVTSEL_OS (1 << 17) |
| 877 | #define PMC6_EVTSEL_E (1 << 18) |
| 878 | #define PMC6_EVTSEL_PC (1 << 19) |
| 879 | #define PMC6_EVTSEL_INT (1 << 20) |
| 880 | #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ |
| 881 | #define PMC6_EVTSEL_INV (1 << 23) |
| 882 | #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 |
| 883 | #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 |
| 884 | |
| 885 | /* Data Cache Unit */ |
| 886 | #define PMC6_DATA_MEM_REFS 0x43 |
| 887 | #define PMC6_DCU_LINES_IN 0x45 |
| 888 | #define PMC6_DCU_M_LINES_IN 0x46 |
| 889 | #define PMC6_DCU_M_LINES_OUT 0x47 |
| 890 | #define PMC6_DCU_MISS_OUTSTANDING 0x48 |
| 891 | |
| 892 | /* Instruction Fetch Unit */ |
| 893 | #define PMC6_IFU_IFETCH 0x80 |
| 894 | #define PMC6_IFU_IFETCH_MISS 0x81 |
| 895 | #define PMC6_ITLB_MISS 0x85 |
| 896 | #define PMC6_IFU_MEM_STALL 0x86 |
| 897 | #define PMC6_ILD_STALL 0x87 |
| 898 | |
| 899 | /* L2 Cache */ |
| 900 | #define PMC6_L2_IFETCH 0x28 |
| 901 | #define PMC6_L2_LD 0x29 |
| 902 | #define PMC6_L2_ST 0x2a |
| 903 | #define PMC6_L2_LINES_IN 0x24 |
| 904 | #define PMC6_L2_LINES_OUT 0x26 |
| 905 | #define PMC6_L2_M_LINES_INM 0x25 |
| 906 | #define PMC6_L2_M_LINES_OUTM 0x27 |
| 907 | #define PMC6_L2_RQSTS 0x2e |
| 908 | #define PMC6_L2_ADS 0x21 |
| 909 | #define PMC6_L2_DBUS_BUSY 0x22 |
| 910 | #define PMC6_L2_DBUS_BUSY_RD 0x23 |
| 911 | |
| 912 | /* External Bus Logic */ |
| 913 | #define PMC6_BUS_DRDY_CLOCKS 0x62 |
| 914 | #define PMC6_BUS_LOCK_CLOCKS 0x63 |
| 915 | #define PMC6_BUS_REQ_OUTSTANDING 0x60 |
| 916 | #define PMC6_BUS_TRAN_BRD 0x65 |
| 917 | #define PMC6_BUS_TRAN_RFO 0x66 |
| 918 | #define PMC6_BUS_TRANS_WB 0x67 |
| 919 | #define PMC6_BUS_TRAN_IFETCH 0x68 |
| 920 | #define PMC6_BUS_TRAN_INVAL 0x69 |
| 921 | #define PMC6_BUS_TRAN_PWR 0x6a |
| 922 | #define PMC6_BUS_TRANS_P 0x6b |
| 923 | #define PMC6_BUS_TRANS_IO 0x6c |
| 924 | #define PMC6_BUS_TRAN_DEF 0x6d |
| 925 | #define PMC6_BUS_TRAN_BURST 0x6e |
| 926 | #define PMC6_BUS_TRAN_ANY 0x70 |
| 927 | #define PMC6_BUS_TRAN_MEM 0x6f |
| 928 | #define PMC6_BUS_DATA_RCV 0x64 |
| 929 | #define PMC6_BUS_BNR_DRV 0x61 |
| 930 | #define PMC6_BUS_HIT_DRV 0x7a |
| 931 | #define PMC6_BUS_HITM_DRDV 0x7b |
| 932 | #define PMC6_BUS_SNOOP_STALL 0x7e |
| 933 | |
| 934 | /* Floating Point Unit */ |
| 935 | #define PMC6_FLOPS 0xc1 |
| 936 | #define PMC6_FP_COMP_OPS_EXE 0x10 |
| 937 | #define PMC6_FP_ASSIST 0x11 |
| 938 | #define PMC6_MUL 0x12 |
| 939 | #define PMC6_DIV 0x12 |
| 940 | #define PMC6_CYCLES_DIV_BUSY 0x14 |
| 941 | |
| 942 | /* Memory Ordering */ |
| 943 | #define PMC6_LD_BLOCKS 0x03 |
| 944 | #define PMC6_SB_DRAINS 0x04 |
| 945 | #define PMC6_MISALIGN_MEM_REF 0x05 |
| 946 | #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ |
| 947 | #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ |
| 948 | |
| 949 | /* Instruction Decoding and Retirement */ |
| 950 | #define PMC6_INST_RETIRED 0xc0 |
| 951 | #define PMC6_UOPS_RETIRED 0xc2 |
| 952 | #define PMC6_INST_DECODED 0xd0 |
| 953 | #define PMC6_EMON_KNI_INST_RETIRED 0xd8 |
| 954 | #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 |
| 955 | |
| 956 | /* Interrupts */ |
| 957 | #define PMC6_HW_INT_RX 0xc8 |
| 958 | #define PMC6_CYCLES_INT_MASKED 0xc6 |
| 959 | #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 |
| 960 | |
| 961 | /* Branches */ |
| 962 | #define PMC6_BR_INST_RETIRED 0xc4 |
| 963 | #define PMC6_BR_MISS_PRED_RETIRED 0xc5 |
| 964 | #define PMC6_BR_TAKEN_RETIRED 0xc9 |
| 965 | #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca |
| 966 | #define PMC6_BR_INST_DECODED 0xe0 |
| 967 | #define PMC6_BTB_MISSES 0xe2 |
| 968 | #define PMC6_BR_BOGUS 0xe4 |
| 969 | #define PMC6_BACLEARS 0xe6 |
| 970 | |
| 971 | /* Stalls */ |
| 972 | #define PMC6_RESOURCE_STALLS 0xa2 |
| 973 | #define PMC6_PARTIAL_RAT_STALLS 0xd2 |
| 974 | |
| 975 | /* Segment Register Loads */ |
| 976 | #define PMC6_SEGMENT_REG_LOADS 0x06 |
| 977 | |
| 978 | /* Clocks */ |
| 979 | #define PMC6_CPU_CLK_UNHALTED 0x79 |
| 980 | |
| 981 | /* MMX Unit */ |
| 982 | #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ |
| 983 | #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ |
| 984 | #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ |
| 985 | #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ |
| 986 | #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ |
| 987 | #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ |
| 988 | #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ |
| 989 | |
| 990 | /* Segment Register Renaming */ |
| 991 | #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ |
| 992 | #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ |
| 993 | #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ |
| 994 | |
| 995 | /* |
| 996 | * AMD K7 Event Selector MSR format. |
| 997 | */ |
| 998 | |
| 999 | #define K7_EVTSEL_EVENT 0x000000ff |
| 1000 | #define K7_EVTSEL_UNIT 0x0000ff00 |
| 1001 | #define K7_EVTSEL_UNIT_SHIFT 8 |
| 1002 | #define K7_EVTSEL_USR (1 << 16) |
| 1003 | #define K7_EVTSEL_OS (1 << 17) |
| 1004 | #define K7_EVTSEL_E (1 << 18) |
| 1005 | #define K7_EVTSEL_PC (1 << 19) |
| 1006 | #define K7_EVTSEL_INT (1 << 20) |
| 1007 | #define K7_EVTSEL_EN (1 << 22) |
| 1008 | #define K7_EVTSEL_INV (1 << 23) |
| 1009 | #define K7_EVTSEL_COUNTER_MASK 0xff000000 |
| 1010 | #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 |
| 1011 | |
| 1012 | /* Segment Register Loads */ |
| 1013 | #define K7_SEGMENT_REG_LOADS 0x20 |
| 1014 | |
| 1015 | #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 |
| 1016 | |
| 1017 | /* Data Cache Unit */ |
| 1018 | #define K7_DATA_CACHE_ACCESS 0x40 |
| 1019 | #define K7_DATA_CACHE_MISS 0x41 |
| 1020 | #define K7_DATA_CACHE_REFILL 0x42 |
| 1021 | #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 |
| 1022 | #define K7_DATA_CACHE_WBACK 0x44 |
| 1023 | #define K7_L2_DTLB_HIT 0x45 |
| 1024 | #define K7_L2_DTLB_MISS 0x46 |
| 1025 | #define K7_MISALIGNED_DATA_REF 0x47 |
| 1026 | #define K7_SYSTEM_REQUEST 0x64 |
| 1027 | #define K7_SYSTEM_REQUEST_TYPE 0x65 |
| 1028 | |
| 1029 | #define K7_SNOOP_HIT 0x73 |
| 1030 | #define K7_SINGLE_BIT_ECC_ERROR 0x74 |
| 1031 | #define K7_CACHE_LINE_INVAL 0x75 |
| 1032 | #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 |
| 1033 | #define K7_L2_REQUEST 0x79 |
| 1034 | #define K7_L2_REQUEST_BUSY 0x7a |
| 1035 | |
| 1036 | /* Instruction Fetch Unit */ |
| 1037 | #define K7_IFU_IFETCH 0x80 |
| 1038 | #define K7_IFU_IFETCH_MISS 0x81 |
| 1039 | #define K7_IFU_REFILL_FROM_L2 0x82 |
| 1040 | #define K7_IFU_REFILL_FROM_SYSTEM 0x83 |
| 1041 | #define K7_ITLB_L1_MISS 0x84 |
| 1042 | #define K7_ITLB_L2_MISS 0x85 |
| 1043 | #define K7_SNOOP_RESYNC 0x86 |
| 1044 | #define K7_IFU_STALL 0x87 |
| 1045 | |
| 1046 | #define K7_RETURN_STACK_HITS 0x88 |
| 1047 | #define K7_RETURN_STACK_OVERFLOW 0x89 |
| 1048 | |
| 1049 | /* Retired */ |
| 1050 | #define K7_RETIRED_INST 0xc0 |
| 1051 | #define K7_RETIRED_OPS 0xc1 |
| 1052 | #define K7_RETIRED_BRANCHES 0xc2 |
| 1053 | #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 |
| 1054 | #define K7_RETIRED_TAKEN_BRANCH 0xc4 |
| 1055 | #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 |
| 1056 | #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 |
| 1057 | #define K7_RETIRED_RESYNC_BRANCH 0xc7 |
| 1058 | #define K7_RETIRED_NEAR_RETURNS 0xc8 |
| 1059 | #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 |
| 1060 | #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca |
| 1061 | |
| 1062 | /* Interrupts */ |
| 1063 | #define K7_CYCLES_INT_MASKED 0xcd |
| 1064 | #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce |
| 1065 | #define K7_HW_INTR_RECV 0xcf |
| 1066 | |
| 1067 | #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 |
| 1068 | #define K7_DISPATCH_STALLS 0xd1 |
| 1069 | #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 |
| 1070 | #define K7_SERIALIZE 0xd3 |
| 1071 | #define K7_SEGMENT_LOAD_STALL 0xd4 |
| 1072 | #define K7_ICU_FULL 0xd5 |
| 1073 | #define K7_RESERVATION_STATIONS_FULL 0xd6 |
| 1074 | #define K7_FPU_FULL 0xd7 |
| 1075 | #define K7_LS_FULL 0xd8 |
| 1076 | #define K7_ALL_QUIET_STALL 0xd9 |
| 1077 | #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda |
| 1078 | |
| 1079 | #define K7_BP0_MATCH 0xdc |
| 1080 | #define K7_BP1_MATCH 0xdd |
| 1081 | #define K7_BP2_MATCH 0xde |
| 1082 | #define K7_BP3_MATCH 0xdf |
| 1083 | |