| 1 | /* $NetBSD: atwreg.h,v 1.23 2009/02/06 02:02:26 dyoung Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. |
| 5 | * |
| 6 | * This code is derived from software contributed to The NetBSD Foundation |
| 7 | * by David Young. |
| 8 | * |
| 9 | * Redistribution and use in source and binary forms, with or without |
| 10 | * modification, are permitted provided that the following conditions |
| 11 | * are met: |
| 12 | * 1. Redistributions of source code must retain the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer. |
| 14 | * 2. Redistributions in binary form must reproduce the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer in the |
| 16 | * documentation and/or other materials provided with the distribution. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 19 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 20 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 21 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 22 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | /* glossary */ |
| 32 | |
| 33 | /* DTIM Delivery Traffic Indication Map, sent by AP |
| 34 | * ATIM Ad Hoc Traffic Indication Map |
| 35 | * TU 1024 microseconds |
| 36 | * TSF time synchronization function |
| 37 | * TBTT target beacon transmission time |
| 38 | * DIFS distributed inter-frame space |
| 39 | * SIFS short inter-frame space |
| 40 | * EIFS extended inter-frame space |
| 41 | */ |
| 42 | |
| 43 | #include <lib/libkern/libkern.h> |
| 44 | #include <dev/ic/rf3000reg.h> |
| 45 | #include <dev/ic/hfa3861areg.h> |
| 46 | |
| 47 | /* ADM8211 Host Control and Status Registers */ |
| 48 | |
| 49 | #define ATW_PAR 0x00 /* PCI access */ |
| 50 | #define ATW_FRCTL 0x04 /* Frame control */ |
| 51 | #define ATW_TDR 0x08 /* Transmit demand */ |
| 52 | #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ |
| 53 | #define ATW_RDR 0x10 /* Receive demand */ |
| 54 | #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ |
| 55 | #define ATW_RDB 0x18 /* Receive descriptor base address */ |
| 56 | #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ |
| 57 | #define ATW_C_TDBH 0x1C /* Transmit descriptor base address, |
| 58 | * high-priority packet |
| 59 | */ |
| 60 | #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ |
| 61 | #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ |
| 62 | #define ATW_STSR 0x28 /* Status */ |
| 63 | #define ATW_CSR5A 0x2C /* Unused */ |
| 64 | #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered |
| 65 | * broadcast/multicast packet |
| 66 | */ |
| 67 | #define ATW_NAR 0x30 /* Network access */ |
| 68 | #define ATW_CSR6A 0x34 /* Unused */ |
| 69 | #define ATW_IER 0x38 /* Interrupt enable */ |
| 70 | #define ATW_CSR7A 0x3C |
| 71 | #define ATW_LPC 0x40 /* Lost packet counter */ |
| 72 | #define ATW_TEST1 0x44 /* Test register 1 */ |
| 73 | #define ATW_SPR 0x48 /* Serial port */ |
| 74 | #define ATW_TEST0 0x4C /* Test register 0 */ |
| 75 | #define ATW_WCSR 0x50 /* Wake-up control/status */ |
| 76 | #define ATW_WPDR 0x54 /* Wake-up pattern data */ |
| 77 | #define ATW_GPTMR 0x58 /* General purpose timer */ |
| 78 | #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ |
| 79 | #define ATW_BBPCTL 0x60 /* BBP control port */ |
| 80 | #define ATW_SYNCTL 0x64 /* synthesizer control port */ |
| 81 | #define ATW_PLCPHD 0x68 /* PLCP header setting */ |
| 82 | #define ATW_MMIWADDR 0x6C /* MMI write address */ |
| 83 | #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ |
| 84 | #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ |
| 85 | #define ATW_TXBR 0x78 /* Transmit burst counter */ |
| 86 | #define ATW_CSR15A 0x7C /* Unused */ |
| 87 | #define ATW_ALCSTAT 0x80 /* ALC statistics */ |
| 88 | #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ |
| 89 | #define ATW_CMDR 0x88 /* Command */ |
| 90 | #define ATW_PCIC 0x8C /* PCI bus performance counter */ |
| 91 | #define ATW_PMCSR 0x90 /* Power management command and status */ |
| 92 | #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ |
| 93 | #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ |
| 94 | #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ |
| 95 | #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ |
| 96 | #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) |
| 97 | * frame DA, byte[3:0] |
| 98 | */ |
| 99 | #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; |
| 100 | * ATIM frame DA byte[5:4] |
| 101 | */ |
| 102 | #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ |
| 103 | #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; |
| 104 | * Max TX MSDU lifetime, 16b |
| 105 | */ |
| 106 | #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ |
| 107 | #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ |
| 108 | #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ |
| 109 | #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ |
| 110 | #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ |
| 111 | #define ATW_BPLI 0xC8 /* Beacon interval, 16b. |
| 112 | * STA listen interval, 16b. |
| 113 | */ |
| 114 | #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ |
| 115 | #define ATW_CAP1 0xD0 /* Capability information, 16b. |
| 116 | * ATIM window, 1b. |
| 117 | */ |
| 118 | #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ |
| 119 | #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ |
| 120 | #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ |
| 121 | #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ |
| 122 | #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ |
| 123 | #define ATW_RSPT 0xE8 /* Response time, 24b */ |
| 124 | #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ |
| 125 | #define ATW_WEPCTL 0xF0 /* WEP control */ |
| 126 | #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ |
| 127 | #define ATW_WEPCNT 0xF8 /* WEP count */ |
| 128 | #define ATW_MACTEST 0xFC |
| 129 | |
| 130 | #define ATW_FER 0x100 /* Function event */ |
| 131 | #define ATW_FEMR 0x104 /* Function event mask */ |
| 132 | #define ATW_FPSR 0x108 /* Function present state */ |
| 133 | #define ATW_FFER 0x10C /* Function force event */ |
| 134 | |
| 135 | |
| 136 | #define ATW_PAR_MWIE __BIT(24) /* memory write and invalidate |
| 137 | * enable |
| 138 | */ |
| 139 | #define ATW_PAR_MRLE __BIT(23) /* memory read line enable */ |
| 140 | #define ATW_PAR_MRME __BIT(21) /* memory read multiple |
| 141 | * enable |
| 142 | */ |
| 143 | #define ATW_PAR_RAP_MASK __BITS(17, 18) /* receive auto-polling in |
| 144 | * receive suspended state |
| 145 | */ |
| 146 | #define ATW_PAR_CAL_MASK __BITS(14, 15) /* cache alignment */ |
| 147 | #define ATW_PAR_CAL_PBL 0x0 |
| 148 | /* min(8 DW, PBL) */ |
| 149 | #define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK) |
| 150 | /* min(16 DW, PBL) */ |
| 151 | #define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK) |
| 152 | /* min(32 DW, PBL) */ |
| 153 | #define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK) |
| 154 | #define ATW_PAR_PBL_MASK __BITS(8, 13) /* programmable burst length */ |
| 155 | #define ATW_PAR_PBL_UNLIMITED 0x0 |
| 156 | #define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK) |
| 157 | #define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK) |
| 158 | #define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK) |
| 159 | #define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK) |
| 160 | #define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK) |
| 161 | #define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK) |
| 162 | #define ATW_PAR_BLE __BIT(7) /* big/little endian selection */ |
| 163 | #define ATW_PAR_DSL_MASK __BITS(2, 6) /* descriptor skip length */ |
| 164 | #define ATW_PAR_BAR __BIT(1) /* bus arbitration */ |
| 165 | #define ATW_PAR_SWR __BIT(0) /* software reset */ |
| 166 | |
| 167 | #define ATW_FRCTL_PWRMGMT __BIT(31) /* power management */ |
| 168 | #define ATW_FRCTL_VER_MASK __BITS(29, 30) /* protocol version */ |
| 169 | #define ATW_FRCTL_ORDER __BIT(28) /* order bit */ |
| 170 | #define ATW_FRCTL_MAXPSP __BIT(27) /* maximum power saving */ |
| 171 | #define ATW_C_FRCTL_PRSP __BIT(26) /* 1: driver sends probe |
| 172 | * response |
| 173 | * 0: ASIC sends prresp |
| 174 | */ |
| 175 | #define ATW_C_FRCTL_DRVBCON __BIT(25) /* 1: driver sends beacons |
| 176 | * 0: ASIC sends beacons |
| 177 | */ |
| 178 | #define ATW_C_FRCTL_DRVLINKCTRL __BIT(24) /* 1: driver controls link LED |
| 179 | * 0: ASIC controls link LED |
| 180 | */ |
| 181 | #define ATW_C_FRCTL_DRVLINKON __BIT(23) /* 1: turn on link LED |
| 182 | * 0: turn off link LED |
| 183 | */ |
| 184 | #define ATW_C_FRCTL_CTX_DATA __BIT(22) /* 0: set by CSR28 |
| 185 | * 1: random |
| 186 | */ |
| 187 | #define ATW_C_FRCTL_RSVFRM __BIT(21) /* 1: receive "reserved" |
| 188 | * frames, 0: ignore |
| 189 | * reserved frames |
| 190 | */ |
| 191 | #define ATW_C_FRCTL_CFEND __BIT(19) /* write to send CF_END, |
| 192 | * ADM8211C/CR clears |
| 193 | */ |
| 194 | #define ATW_FRCTL_DOZEFRM __BIT(18) /* select pre-sleep frame */ |
| 195 | #define ATW_FRCTL_PSAWAKE __BIT(17) /* MAC is awake (?) */ |
| 196 | #define ATW_FRCTL_PSMODE __BIT(16) /* MAC is power-saving (?) */ |
| 197 | #define ATW_FRCTL_AID_MASK __BITS(0, 15) /* STA Association ID */ |
| 198 | |
| 199 | #define ATW_INTR_PCF __BIT(31) /* started/ended CFP */ |
| 200 | #define ATW_INTR_BCNTC __BIT(30) /* transmitted IBSS beacon */ |
| 201 | #define ATW_INTR_GPINT __BIT(29) /* GPIO interrupt */ |
| 202 | #define ATW_INTR_LINKOFF __BIT(28) /* lost ATW_WCSR_BLN beacons */ |
| 203 | #define ATW_INTR_ATIMTC __BIT(27) /* transmitted ATIM */ |
| 204 | #define ATW_INTR_TSFTF __BIT(26) /* TSFT out of range */ |
| 205 | #define ATW_INTR_TSCZ __BIT(25) /* TSC countdown expired */ |
| 206 | #define ATW_INTR_LINKON __BIT(24) /* matched SSID, BSSID */ |
| 207 | #define ATW_INTR_SQL __BIT(23) /* Marvel signal quality */ |
| 208 | #define ATW_INTR_WEPTD __BIT(22) /* switched WEP table */ |
| 209 | #define ATW_INTR_ATIME __BIT(21) /* ended ATIM window */ |
| 210 | #define ATW_INTR_TBTT __BIT(20) /* (TBTT) Target Beacon TX Time |
| 211 | * passed |
| 212 | */ |
| 213 | #define ATW_INTR_NISS __BIT(16) /* normal interrupt status |
| 214 | * summary: any of 31, 30, 27, |
| 215 | * 24, 14, 12, 6, 2, 0. |
| 216 | */ |
| 217 | #define ATW_INTR_AISS __BIT(15) /* abnormal interrupt status |
| 218 | * summary: any of 29, 28, 26, |
| 219 | * 25, 23, 22, 13, 11, 8, 7, 5, |
| 220 | * 4, 3, 1. |
| 221 | */ |
| 222 | #define ATW_INTR_TEIS __BIT(14) /* transmit early interrupt |
| 223 | * status: moved TX packet to |
| 224 | * FIFO |
| 225 | */ |
| 226 | #define ATW_INTR_FBE __BIT(13) /* fatal bus error */ |
| 227 | #define ATW_INTR_REIS __BIT(12) /* receive early interrupt |
| 228 | * status: RX packet filled |
| 229 | * its first descriptor |
| 230 | */ |
| 231 | #define ATW_INTR_GPTT __BIT(11) /* general purpose timer expired */ |
| 232 | #define ATW_INTR_RPS __BIT(8) /* stopped receive process */ |
| 233 | #define ATW_INTR_RDU __BIT(7) /* receive descriptor |
| 234 | * unavailable |
| 235 | */ |
| 236 | #define ATW_INTR_RCI __BIT(6) /* completed packet reception */ |
| 237 | #define ATW_INTR_TUF __BIT(5) /* transmit underflow */ |
| 238 | #define ATW_INTR_TRT __BIT(4) /* transmit retry count |
| 239 | * expired |
| 240 | */ |
| 241 | #define ATW_INTR_TLT __BIT(3) /* transmit lifetime exceeded */ |
| 242 | #define ATW_INTR_TDU __BIT(2) /* transmit descriptor |
| 243 | * unavailable |
| 244 | */ |
| 245 | #define ATW_INTR_TPS __BIT(1) /* stopped transmit process */ |
| 246 | #define ATW_INTR_TCI __BIT(0) /* completed transmit */ |
| 247 | #define ATW_NAR_TXCF __BIT(31) /* stop process on TX failure */ |
| 248 | #define ATW_NAR_HF __BIT(30) /* flush TX FIFO to host (?) */ |
| 249 | #define ATW_NAR_UTR __BIT(29) /* select retry count source */ |
| 250 | #define ATW_NAR_PCF __BIT(28) /* use one/both transmit |
| 251 | * descriptor base addresses |
| 252 | */ |
| 253 | #define ATW_NAR_CFP __BIT(27) /* indicate more TX data to |
| 254 | * point coordinator |
| 255 | */ |
| 256 | #define ATW_C_NAR_APSTA __BIT(26) /* 0: STA mode |
| 257 | * 1: AP mode |
| 258 | */ |
| 259 | #define ATW_C_NAR_TDBBE __BIT(25) /* 0: disable TDBB |
| 260 | * 1: enable TDBB |
| 261 | */ |
| 262 | #define ATW_C_NAR_TDBHE __BIT(24) /* 0: disable TDBH |
| 263 | * 1: enable TDBH |
| 264 | */ |
| 265 | #define ATW_C_NAR_TDBHT __BIT(23) /* write 1 to make ASIC |
| 266 | * poll TDBH once; ASIC clears |
| 267 | */ |
| 268 | #define ATW_NAR_SF __BIT(21) /* store and forward: ignore |
| 269 | * TX threshold |
| 270 | */ |
| 271 | #define ATW_NAR_TR_MASK __BITS(14, 15) /* TX threshold */ |
| 272 | #define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK) |
| 273 | #define ATW_NAR_TR_L160 __SHIFTIN(0x2, ATW_NAR_TR_MASK) |
| 274 | #define ATW_NAR_TR_L192 __SHIFTIN(0x3, ATW_NAR_TR_MASK) |
| 275 | #define ATW_NAR_TR_H96 __SHIFTIN(0x0, ATW_NAR_TR_MASK) |
| 276 | #define ATW_NAR_TR_H288 __SHIFTIN(0x2, ATW_NAR_TR_MASK) |
| 277 | #define ATW_NAR_TR_H544 __SHIFTIN(0x3, ATW_NAR_TR_MASK) |
| 278 | #define ATW_NAR_ST __BIT(13) /* start/stop transmit */ |
| 279 | #define ATW_NAR_OM_MASK __BITS(10, 11) /* operating mode */ |
| 280 | #define ATW_NAR_OM_NORMAL 0x0 |
| 281 | #define ATW_NAR_OM_LOOPBACK __SHIFTIN(0x1, ATW_NAR_OM_MASK) |
| 282 | #define ATW_NAR_MM __BIT(7) /* RX any multicast */ |
| 283 | #define ATW_NAR_PR __BIT(6) /* promiscuous mode */ |
| 284 | #define ATW_NAR_EA __BIT(5) /* match ad hoc packets (?) */ |
| 285 | #define ATW_NAR_DISPCF __BIT(4) /* 1: PCF *not* supported |
| 286 | * 0: PCF supported |
| 287 | */ |
| 288 | #define ATW_NAR_PB __BIT(3) /* pass bad packets */ |
| 289 | #define ATW_NAR_STPDMA __BIT(2) /* stop DMA, abort packet */ |
| 290 | #define ATW_NAR_SR __BIT(1) /* start/stop receive */ |
| 291 | #define ATW_NAR_CTX __BIT(0) /* continuous TX mode */ |
| 292 | |
| 293 | /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ |
| 294 | #if 0 |
| 295 | #define ATW_IER_NIE __BIT(16) /* normal interrupt enable */ |
| 296 | #define ATW_IER_AIE __BIT(15) /* abnormal interrupt enable */ |
| 297 | /* normal interrupts: combine with ATW_IER_NIE */ |
| 298 | #define ATW_IER_PCFIE __BIT(31) /* STA entered CFP */ |
| 299 | #define ATW_IER_BCNTCIE __BIT(30) /* STA TX'd beacon */ |
| 300 | #define ATW_IER_ATIMTCIE __BIT(27) /* transmitted ATIM */ |
| 301 | #define ATW_IER_LINKONIE __BIT(24) /* matched beacon */ |
| 302 | #define ATW_IER_ATIMIE __BIT(21) /* ended ATIM window */ |
| 303 | #define ATW_IER_TBTTIE __BIT(20) /* TBTT */ |
| 304 | #define ATW_IER_TEIE __BIT(14) /* moved TX packet to FIFO */ |
| 305 | #define ATW_IER_REIE __BIT(12) /* RX packet filled its first |
| 306 | * descriptor |
| 307 | */ |
| 308 | #define ATW_IER_RCIE __BIT(6) /* completed RX */ |
| 309 | #define ATW_IER_TDUIE __BIT(2) /* transmit descriptor |
| 310 | * unavailable |
| 311 | */ |
| 312 | #define ATW_IER_TCIE __BIT(0) /* completed TX */ |
| 313 | /* abnormal interrupts: combine with ATW_IER_AIE */ |
| 314 | #define ATW_IER_GPIE __BIT(29) /* GPIO interrupt */ |
| 315 | #define ATW_IER_LINKOFFIE __BIT(28) /* lost beacon */ |
| 316 | #define ATW_IER_TSFTFIE __BIT(26) /* TSFT out of range */ |
| 317 | #define ATW_IER_TSCIE __BIT(25) /* TSC countdown expired */ |
| 318 | #define ATW_IER_SQLIE __BIT(23) /* signal quality */ |
| 319 | #define ATW_IER_WEPIE __BIT(22) /* finished WEP table switch */ |
| 320 | #define ATW_IER_FBEIE __BIT(13) /* fatal bus error */ |
| 321 | #define ATW_IER_GPTIE __BIT(11) /* general purpose timer expired */ |
| 322 | #define ATW_IER_RPSIE __BIT(8) /* stopped receive process */ |
| 323 | #define ATW_IER_RUIE __BIT(7) /* receive descriptor unavailable */ |
| 324 | #define ATW_IER_TUIE __BIT(5) /* transmit underflow */ |
| 325 | #define ATW_IER_TRTIE __BIT(4) /* exceeded transmit retry count */ |
| 326 | #define ATW_IER_TLTTIE __BIT(3) /* transmit lifetime exceeded */ |
| 327 | #define ATW_IER_TPSIE __BIT(1) /* stopped transmit process */ |
| 328 | #endif |
| 329 | |
| 330 | #define ATW_LPC_LPCO __BIT(16) /* lost packet counter overflow */ |
| 331 | #define ATW_LPC_LPC_MASK __BITS(0, 15) /* lost packet counter */ |
| 332 | |
| 333 | #define ATW_TEST1_RRA_MASK __BITS(20,12) |
| 334 | #define ATW_TEST1_RWA_MASK __BITS(10,2) |
| 335 | #define ATW_TEST1_RXPKT1IN __BIT(1) |
| 336 | |
| 337 | #define ATW_TEST1_CONTROL __BIT(31) /* "0: read from dxfer_control, |
| 338 | * 1: read from dxfer_state" |
| 339 | */ |
| 340 | #define ATW_TEST1_DBGREAD_MASK __BITS(30,28) /* "control of read data, |
| 341 | * debug only" |
| 342 | */ |
| 343 | #define ATW_TEST1_TXWP_MASK __BITS(27,25) /* select ATW_WTDP content? */ |
| 344 | #define ATW_TEST1_TXWP_TDBD __SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) |
| 345 | #define ATW_TEST1_TXWP_TDBH __SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) |
| 346 | #define ATW_TEST1_TXWP_TDBB __SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) |
| 347 | #define ATW_TEST1_TXWP_TDBP __SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) |
| 348 | #define ATW_TEST1_RSVD0_MASK __BITS(24,6) /* reserved */ |
| 349 | #define ATW_TEST1_TESTMODE_MASK __BITS(5,4) |
| 350 | /* normal operation */ |
| 351 | #define ATW_TEST1_TESTMODE_NORMAL __SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) |
| 352 | /* MAC-only mode */ |
| 353 | #define ATW_TEST1_TESTMODE_MACONLY __SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) |
| 354 | /* normal operation */ |
| 355 | #define ATW_TEST1_TESTMODE_NORMAL2 __SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) |
| 356 | /* monitor mode */ |
| 357 | #define ATW_TEST1_TESTMODE_MONITOR __SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) |
| 358 | |
| 359 | #define ATW_TEST1_DUMP_MASK __BITS(3,0) /* select dump signal |
| 360 | * from dxfer (huh?) |
| 361 | */ |
| 362 | |
| 363 | #define ATW_SPR_SRS __BIT(11) /* activate SEEPROM access */ |
| 364 | #define ATW_SPR_SDO __BIT(3) /* data out of SEEPROM */ |
| 365 | #define ATW_SPR_SDI __BIT(2) /* data into SEEPROM */ |
| 366 | #define ATW_SPR_SCLK __BIT(1) /* SEEPROM clock */ |
| 367 | #define ATW_SPR_SCS __BIT(0) /* SEEPROM chip select */ |
| 368 | |
| 369 | #define ATW_TEST0_BE_MASK __BITS(31, 29) /* Bus error state */ |
| 370 | #define ATW_TEST0_TS_MASK __BITS(28, 26) /* Transmit process state */ |
| 371 | |
| 372 | /* Stopped */ |
| 373 | #define ATW_TEST0_TS_STOPPED __SHIFTIN(0, ATW_TEST0_TS_MASK) |
| 374 | /* Running - fetch transmit descriptor */ |
| 375 | #define ATW_TEST0_TS_FETCH __SHIFTIN(1, ATW_TEST0_TS_MASK) |
| 376 | /* Running - wait for end of transmission */ |
| 377 | #define ATW_TEST0_TS_WAIT __SHIFTIN(2, ATW_TEST0_TS_MASK) |
| 378 | /* Running - read buffer from memory and queue into FIFO */ |
| 379 | #define ATW_TEST0_TS_READING __SHIFTIN(3, ATW_TEST0_TS_MASK) |
| 380 | #define ATW_TEST0_TS_RESERVED1 __SHIFTIN(4, ATW_TEST0_TS_MASK) |
| 381 | #define ATW_TEST0_TS_RESERVED2 __SHIFTIN(5, ATW_TEST0_TS_MASK) |
| 382 | /* Suspended */ |
| 383 | #define ATW_TEST0_TS_SUSPENDED __SHIFTIN(6, ATW_TEST0_TS_MASK) |
| 384 | /* Running - close transmit descriptor */ |
| 385 | #define ATW_TEST0_TS_CLOSE __SHIFTIN(7, ATW_TEST0_TS_MASK) |
| 386 | |
| 387 | /* ADM8211C/CR registers */ |
| 388 | /* Suspended */ |
| 389 | #define ATW_C_TEST0_TS_SUSPENDED __SHIFTIN(4, ATW_TEST0_TS_MASK) |
| 390 | /* Descriptor write */ |
| 391 | #define ATW_C_TEST0_TS_CLOSE __SHIFTIN(5, ATW_TEST0_TS_MASK) |
| 392 | /* Last descriptor write */ |
| 393 | #define ATW_C_TEST0_TS_CLOSELAST __SHIFTIN(6, ATW_TEST0_TS_MASK) |
| 394 | /* FIFO full */ |
| 395 | #define ATW_C_TEST0_TS_FIFOFULL __SHIFTIN(7, ATW_TEST0_TS_MASK) |
| 396 | |
| 397 | #define ATW_TEST0_RS_MASK __BITS(25, 23) /* Receive process state */ |
| 398 | |
| 399 | /* Stopped */ |
| 400 | #define ATW_TEST0_RS_STOPPED __SHIFTIN(0, ATW_TEST0_RS_MASK) |
| 401 | /* Running - fetch receive descriptor */ |
| 402 | #define ATW_TEST0_RS_FETCH __SHIFTIN(1, ATW_TEST0_RS_MASK) |
| 403 | /* Running - check for end of receive */ |
| 404 | #define ATW_TEST0_RS_CHECK __SHIFTIN(2, ATW_TEST0_RS_MASK) |
| 405 | /* Running - wait for packet */ |
| 406 | #define ATW_TEST0_RS_WAIT __SHIFTIN(3, ATW_TEST0_RS_MASK) |
| 407 | /* Suspended */ |
| 408 | #define ATW_TEST0_RS_SUSPENDED __SHIFTIN(4, ATW_TEST0_RS_MASK) |
| 409 | /* Running - close receive descriptor */ |
| 410 | #define ATW_TEST0_RS_CLOSE __SHIFTIN(5, ATW_TEST0_RS_MASK) |
| 411 | /* Running - flush current frame from FIFO */ |
| 412 | #define ATW_TEST0_RS_FLUSH __SHIFTIN(6, ATW_TEST0_RS_MASK) |
| 413 | /* Running - queue current frame from FIFO into buffer */ |
| 414 | #define ATW_TEST0_RS_QUEUE __SHIFTIN(7, ATW_TEST0_RS_MASK) |
| 415 | |
| 416 | #define ATW_TEST0_EPNE __BIT(18) /* SEEPROM not detected */ |
| 417 | #define ATW_TEST0_EPSNM __BIT(17) /* SEEPROM bad signature */ |
| 418 | #define ATW_TEST0_EPTYP_MASK __BIT(16) /* SEEPROM type |
| 419 | * 1: 93c66, |
| 420 | * 0: 93c46 |
| 421 | */ |
| 422 | #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK |
| 423 | #define ATW_TEST0_EPTYP_93c46 0 |
| 424 | #define ATW_TEST0_EPRLD __BIT(15) /* recall SEEPROM (write 1) */ |
| 425 | |
| 426 | #define ATW_WCSR_CRCT __BIT(30) /* CRC-16 type */ |
| 427 | #define ATW_WCSR_WP1E __BIT(29) /* match wake-up pattern 1 */ |
| 428 | #define ATW_WCSR_WP2E __BIT(28) /* match wake-up pattern 2 */ |
| 429 | #define ATW_WCSR_WP3E __BIT(27) /* match wake-up pattern 3 */ |
| 430 | #define ATW_WCSR_WP4E __BIT(26) /* match wake-up pattern 4 */ |
| 431 | #define ATW_WCSR_WP5E __BIT(25) /* match wake-up pattern 5 */ |
| 432 | #define ATW_WCSR_BLN_MASK __BITS(21, 23) /* lose link after BLN lost |
| 433 | * beacons |
| 434 | */ |
| 435 | #define ATW_WCSR_TSFTWE __BIT(20) /* wake up on TSFT out of |
| 436 | * range |
| 437 | */ |
| 438 | #define ATW_WCSR_TIMWE __BIT(19) /* wake up on TIM */ |
| 439 | #define ATW_WCSR_ATIMWE __BIT(18) /* wake up on ATIM */ |
| 440 | #define ATW_WCSR_KEYWE __BIT(17) /* wake up on key update */ |
| 441 | #define ATW_WCSR_WFRE __BIT(10) /* wake up on wake-up frame */ |
| 442 | #define ATW_WCSR_MPRE __BIT(9) /* wake up on magic packet */ |
| 443 | #define ATW_WCSR_LSOE __BIT(8) /* wake up on link loss */ |
| 444 | /* wake-up reasons correspond to enable bits */ |
| 445 | #define ATW_WCSR_KEYUP __BIT(6) /* */ |
| 446 | #define ATW_WCSR_TSFTW __BIT(5) /* */ |
| 447 | #define ATW_WCSR_TIMW __BIT(4) /* */ |
| 448 | #define ATW_WCSR_ATIMW __BIT(3) /* */ |
| 449 | #define ATW_WCSR_WFR __BIT(2) /* */ |
| 450 | #define ATW_WCSR_MPR __BIT(1) /* */ |
| 451 | #define ATW_WCSR_LSO __BIT(0) /* */ |
| 452 | |
| 453 | #define ATW_GPTMR_COM_MASK __BIT(16) /* continuous operation mode */ |
| 454 | #define ATW_GPTMR_GTV_MASK __BITS(0, 15) /* set countdown in 204us ticks */ |
| 455 | |
| 456 | #define ATW_GPIO_EC1_MASK __BITS(25, 24) /* GPIO1 event configuration */ |
| 457 | #define ATW_GPIO_LAT_MASK __BITS(21, 20) /* input latch */ |
| 458 | #define ATW_GPIO_INTEN_MASK __BITS(19, 18) /* interrupt enable */ |
| 459 | #define ATW_GPIO_EN_MASK __BITS(17, 12) /* output enable */ |
| 460 | #define ATW_GPIO_O_MASK __BITS(11, 6) /* output value */ |
| 461 | #define ATW_GPIO_I_MASK __BITS(5, 0) /* pin static input */ |
| 462 | |
| 463 | /* Intersil 3-wire interface */ |
| 464 | #define ATW_BBPCTL_TWI __BIT(31) |
| 465 | #define ATW_BBPCTL_RF3KADDR_MASK __BITS(30, 24) /* Address for RF3000 */ |
| 466 | #define ATW_BBPCTL_RF3KADDR_ADDR __SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) |
| 467 | /* data-out on negative edge */ |
| 468 | #define ATW_BBPCTL_NEGEDGE_DO __BIT(23) |
| 469 | /* data-in on negative edge */ |
| 470 | #define ATW_BBPCTL_NEGEDGE_DI __BIT(22) |
| 471 | #define ATW_BBPCTL_CCA_ACTLO __BIT(21) /* 1: CCA signal is low |
| 472 | * when channel is busy, |
| 473 | * CCA signal is high |
| 474 | * when channel is |
| 475 | * clear. |
| 476 | * 0: vice-versa |
| 477 | * 1 is suitable for |
| 478 | * the embedded |
| 479 | * RFMD RF3000. |
| 480 | */ |
| 481 | #define ATW_BBPCTL_TYPE_MASK __BITS(20, 18) /* BBP type */ |
| 482 | /* start write; reset on completion */ |
| 483 | #define ATW_BBPCTL_WR __BIT(17) |
| 484 | #define ATW_BBPCTL_RD __BIT(16) /* start read; reset on |
| 485 | * completion |
| 486 | */ |
| 487 | #define ATW_BBPCTL_ADDR_MASK __BITS(15, 8) /* BBP address */ |
| 488 | #define ATW_BBPCTL_DATA_MASK __BITS(7, 0) /* BBP data */ |
| 489 | |
| 490 | #define ATW_SYNCTL_WR __BIT(31) /* start write; reset on |
| 491 | * completion |
| 492 | */ |
| 493 | #define ATW_SYNCTL_RD __BIT(30) /* start read; reset on |
| 494 | * completion |
| 495 | */ |
| 496 | #define ATW_SYNCTL_CS0 __BIT(29) /* chip select */ |
| 497 | #define ATW_SYNCTL_CS1 __BIT(28) |
| 498 | #define ATW_SYNCTL_CAL __BIT(27) /* generate RF CAL pulse after |
| 499 | * Rx |
| 500 | */ |
| 501 | #define ATW_SYNCTL_SELCAL __BIT(26) /* RF CAL source, 0: CAL bit, |
| 502 | * 1: MAC; needed by Intersil |
| 503 | * BBP |
| 504 | */ |
| 505 | #define ATW_C_SYNCTL_MMICE __BIT(25) /* ADM8211C/CR define this |
| 506 | * bit. 0: latch data on |
| 507 | * negative edge, 1: positive |
| 508 | * edge. |
| 509 | */ |
| 510 | #define ATW_SYNCTL_RFTYPE_MASK __BITS(24, 22) /* RF type */ |
| 511 | #define ATW_SYNCTL_DATA_MASK __BITS(21, 0) /* synthesizer setting */ |
| 512 | |
| 513 | #define ATW_PLCPHD_SIGNAL_MASK __BITS(31, 24) /* signal field in PLCP header, |
| 514 | * only for beacon, ATIM, and |
| 515 | * RTS. |
| 516 | */ |
| 517 | #define ATW_PLCPHD_SERVICE_MASK __BITS(23, 16) /* service field in PLCP |
| 518 | * header; with RFMD BBP, |
| 519 | * sets Tx power for beacon, |
| 520 | * RTS, ATIM. |
| 521 | */ |
| 522 | #define ATW_PLCPHD_PMBL __BIT(15) /* 0: long preamble, 1: short */ |
| 523 | |
| 524 | #define ATW_MMIWADDR_LENLO_MASK __BITS(31,24) /* tx: written 4th */ |
| 525 | #define ATW_MMIWADDR_LENHI_MASK __BITS(23,16) /* tx: written 3rd */ |
| 526 | #define ATW_MMIWADDR_GAIN_MASK __BITS(15,8) /* tx: written 2nd */ |
| 527 | #define ATW_MMIWADDR_RATE_MASK __BITS(7,0) /* tx: written 1st */ |
| 528 | |
| 529 | /* was magic 0x100E0C0A */ |
| 530 | #define ATW_MMIWADDR_INTERSIL \ |
| 531 | (__SHIFTIN(HFA3861A_CR6, ATW_MMIWADDR_GAIN_MASK) | \ |
| 532 | __SHIFTIN(HFA3861A_CR5, ATW_MMIWADDR_RATE_MASK) | \ |
| 533 | __SHIFTIN(HFA3861A_CR7, ATW_MMIWADDR_LENHI_MASK) | \ |
| 534 | __SHIFTIN(HFA3861A_CR8, ATW_MMIWADDR_LENLO_MASK)) |
| 535 | |
| 536 | /* was magic 0x00009101 |
| 537 | * |
| 538 | * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to |
| 539 | * put the RF3000 into auto-increment mode so that it can write Tx gain, |
| 540 | * Tx length (high) and Tx length (low) registers back-to-back. |
| 541 | */ |
| 542 | #define ATW_MMIWADDR_RFMD \ |
| 543 | (__SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ |
| 544 | __SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) |
| 545 | |
| 546 | #define ATW_MMIRADDR1_RSVD_MASK __BITS(31, 24) |
| 547 | #define ATW_MMIRADDR1_PWRLVL_MASK __BITS(23, 16) |
| 548 | #define __BITS(15, 8) |
| 549 | #define ATW_MMIRADDR1_RXSTAT_MASK __BITS(7, 0) |
| 550 | |
| 551 | /* was magic 0x00007c7e */ |
| 552 | #define ATW_MMIRADDR1_INTERSIL \ |
| 553 | (__SHIFTIN(HFA3861A_CR61, ATW_MMIRADDR1_RSSI_MASK) | \ |
| 554 | __SHIFTIN(HFA3861A_CR62, ATW_MMIRADDR1_RXSTAT_MASK)) |
| 555 | |
| 556 | /* was magic 0x00000301 */ |
| 557 | #define ATW_MMIRADDR1_RFMD \ |
| 558 | (__SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ |
| 559 | __SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) |
| 560 | |
| 561 | /* was magic 0x00100000 */ |
| 562 | #define ATW_MMIRADDR2_INTERSIL \ |
| 563 | (__SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ |
| 564 | __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) |
| 565 | |
| 566 | /* was magic 0x7e100000 */ |
| 567 | #define ATW_MMIRADDR2_RFMD \ |
| 568 | (__SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ |
| 569 | __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) |
| 570 | |
| 571 | #define ATW_MMIRADDR2_ID_MASK __BITS(31, 24) /* 1st element ID in WEP table |
| 572 | * for Probe Response (huh?) |
| 573 | */ |
| 574 | /* RXPE is re-asserted after RXPECNT * 22MHz. */ |
| 575 | #define ATW_MMIRADDR2_RXPECNT_MASK __BITS(23, 16) |
| 576 | #define ATW_MMIRADDR2_PROREXT __BIT(15) /* Probe Response |
| 577 | * 11Mb/s length |
| 578 | * extension. |
| 579 | */ |
| 580 | #define ATW_MMIRADDR2_PRORLEN_MASK __BITS(14, 0) /* Probe Response |
| 581 | * microsecond length |
| 582 | */ |
| 583 | |
| 584 | /* auto-update BBP with ALCSET */ |
| 585 | #define ATW_TXBR_ALCUPDATE_MASK __BIT(31) |
| 586 | #define ATW_TXBR_TBCNT_MASK __BITS(16, 20) /* transmit burst count */ |
| 587 | #define ATW_TXBR_ALCSET_MASK __BITS(8, 15) /* TX power level set point */ |
| 588 | #define ATW_TXBR_ALCREF_MASK __BITS(0, 7) /* TX power level reference point */ |
| 589 | |
| 590 | #define ATW_ALCSTAT_MCOV_MASK __BIT(27) /* MPDU count overflow */ |
| 591 | #define ATW_ALCSTAT_ESOV_MASK __BIT(26) /* error sum overflow */ |
| 592 | #define ATW_ALCSTAT_MCNT_MASK __BITS(16, 25) /* MPDU count, unsigned integer */ |
| 593 | #define ATW_ALCSTAT_ERSUM_MASK __BITS(0, 15) /* power error sum, |
| 594 | * 2's complement signed integer |
| 595 | */ |
| 596 | |
| 597 | #define ATW_TOFS2_PWR1UP_MASK __BITS(31, 28) /* delay of Tx/Rx from PE1, |
| 598 | * Radio, PHYRST change after |
| 599 | * power-up, in 2ms units |
| 600 | */ |
| 601 | #define ATW_TOFS2_PWR0PAPE_MASK __BITS(27, 24) /* delay of PAPE going low |
| 602 | * after internal data |
| 603 | * transmit end, in us |
| 604 | */ |
| 605 | #define ATW_TOFS2_PWR1PAPE_MASK __BITS(23, 20) /* delay of PAPE going high |
| 606 | * after TXPE asserted, in us |
| 607 | */ |
| 608 | #define ATW_TOFS2_PWR0TRSW_MASK __BITS(19, 16) /* delay of TRSW going low |
| 609 | * after internal data transmit |
| 610 | * end, in us |
| 611 | */ |
| 612 | #define ATW_TOFS2_PWR1TRSW_MASK __BITS(15, 12) /* delay of TRSW going high |
| 613 | * after TXPE asserted, in us |
| 614 | */ |
| 615 | #define ATW_TOFS2_PWR0PE2_MASK __BITS(11, 8) /* delay of PE2 going low |
| 616 | * after internal data transmit |
| 617 | * end, in us |
| 618 | */ |
| 619 | #define ATW_TOFS2_PWR1PE2_MASK __BITS(7, 4) /* delay of PE2 going high |
| 620 | * after TXPE asserted, in us |
| 621 | */ |
| 622 | #define ATW_TOFS2_PWR0TXPE_MASK __BITS(3, 0) /* delay of TXPE going low |
| 623 | * after internal data transmit |
| 624 | * end, in us |
| 625 | */ |
| 626 | |
| 627 | #define ATW_CMDR_PM __BIT(19) /* enables power mgmt |
| 628 | * capabilities. |
| 629 | */ |
| 630 | #define ATW_CMDR_APM __BIT(18) /* APM mode, effective when |
| 631 | * PM = 1. |
| 632 | */ |
| 633 | #define ATW_CMDR_RTE __BIT(4) /* enable Rx FIFO threshold */ |
| 634 | #define ATW_CMDR_DRT_MASK __BITS(3, 2) /* drain Rx FIFO threshold */ |
| 635 | /* 32 bytes */ |
| 636 | #define ATW_CMDR_DRT_8DW __SHIFTIN(0x0, ATW_CMDR_DRT_MASK) |
| 637 | /* 64 bytes */ |
| 638 | #define ATW_CMDR_DRT_16DW __SHIFTIN(0x1, ATW_CMDR_DRT_MASK) |
| 639 | /* Store & Forward */ |
| 640 | #define ATW_CMDR_DRT_SF __SHIFTIN(0x2, ATW_CMDR_DRT_MASK) |
| 641 | /* Reserved */ |
| 642 | #define ATW_CMDR_DRT_RSVD __SHIFTIN(0x3, ATW_CMDR_DRT_MASK) |
| 643 | #define ATW_CMDR_SINT_MASK __BIT(1) /* software interrupt---huh? */ |
| 644 | |
| 645 | /* TBD PCIC */ |
| 646 | |
| 647 | /* TBD PMCSR */ |
| 648 | |
| 649 | |
| 650 | #define ATW_PAR0_PAB0_MASK __BITS(0, 7) /* MAC address byte 0 */ |
| 651 | #define ATW_PAR0_PAB1_MASK __BITS(8, 15) /* MAC address byte 1 */ |
| 652 | #define ATW_PAR0_PAB2_MASK __BITS(16, 23) /* MAC address byte 2 */ |
| 653 | #define ATW_PAR0_PAB3_MASK __BITS(24, 31) /* MAC address byte 3 */ |
| 654 | |
| 655 | #define ATW_C_PAR1_CTD __BITS(16,31) /* Continuous Tx pattern */ |
| 656 | #define ATW_PAR1_PAB5_MASK __BITS(8, 15) /* MAC address byte 5 */ |
| 657 | #define ATW_PAR1_PAB4_MASK __BITS(0, 7) /* MAC address byte 4 */ |
| 658 | |
| 659 | #define ATW_MAR0_MAB3_MASK __BITS(31, 24) /* multicast table bits 31:24 */ |
| 660 | #define ATW_MAR0_MAB2_MASK __BITS(23, 16) /* multicast table bits 23:16 */ |
| 661 | #define ATW_MAR0_MAB1_MASK __BITS(15, 8) /* multicast table bits 15:8 */ |
| 662 | #define ATW_MAR0_MAB0_MASK __BITS(7, 0) /* multicast table bits 7:0 */ |
| 663 | |
| 664 | #define ATW_MAR1_MAB7_MASK __BITS(31, 24) /* multicast table bits 63:56 */ |
| 665 | #define ATW_MAR1_MAB6_MASK __BITS(23, 16) /* multicast table bits 55:48 */ |
| 666 | #define ATW_MAR1_MAB5_MASK __BITS(15, 8) /* multicast table bits 47:40 */ |
| 667 | #define ATW_MAR1_MAB4_MASK __BITS(7, 0) /* multicast table bits 39:32 */ |
| 668 | |
| 669 | /* ATIM destination address */ |
| 670 | #define ATW_ATIMDA0_ATIMB3_MASK __BITS(31,24) |
| 671 | #define ATW_ATIMDA0_ATIMB2_MASK __BITS(23,16) |
| 672 | #define ATW_ATIMDA0_ATIMB1_MASK __BITS(15,8) |
| 673 | #define ATW_ATIMDA0_ATIMB0_MASK __BITS(7,0) |
| 674 | |
| 675 | /* ATIM destination address, BSSID */ |
| 676 | #define ATW_ABDA1_BSSIDB5_MASK __BITS(31,24) |
| 677 | #define ATW_ABDA1_BSSIDB4_MASK __BITS(23,16) |
| 678 | #define ATW_ABDA1_ATIMB5_MASK __BITS(15,8) |
| 679 | #define ATW_ABDA1_ATIMB4_MASK __BITS(7,0) |
| 680 | |
| 681 | /* BSSID */ |
| 682 | #define ATW_BSSID0_BSSIDB3_MASK __BITS(31,24) |
| 683 | #define ATW_BSSID0_BSSIDB2_MASK __BITS(23,16) |
| 684 | #define ATW_BSSID0_BSSIDB1_MASK __BITS(15,8) |
| 685 | #define ATW_BSSID0_BSSIDB0_MASK __BITS(7,0) |
| 686 | |
| 687 | #define ATW_TXLMT_MTMLT_MASK __BITS(31,16) /* max TX MSDU lifetime in TU */ |
| 688 | #define ATW_TXLMT_SRTYLIM_MASK __BITS(7,0) /* short retry limit */ |
| 689 | |
| 690 | #define ATW_MIBCNT_FFCNT_MASK __BITS(31,24) /* FCS failure count */ |
| 691 | #define ATW_MIBCNT_AFCNT_MASK __BITS(23,16) /* ACK failure count */ |
| 692 | #define ATW_MIBCNT_RSCNT_MASK __BITS(15,8) /* RTS success count */ |
| 693 | #define ATW_MIBCNT_RFCNT_MASK __BITS(7,0) /* RTS failure count */ |
| 694 | |
| 695 | #define ATW_BCNT_PLCPH_MASK __BITS(23,16) /* 11M PLCP length (us) */ |
| 696 | #define ATW_BCNT_PLCPL_MASK __BITS(15,8) /* 5.5M PLCP length (us) */ |
| 697 | #define ATW_BCNT_BCNT_MASK __BITS(7,0) /* byte count of beacon frame */ |
| 698 | |
| 699 | /* For ADM8211C/CR */ |
| 700 | /* ATW_C_TSC_TIMTABSEL = 1 */ |
| 701 | #define ATW_C_BCNT_EXTEN1 __BIT(31) /* 11M beacon len. extension */ |
| 702 | #define ATW_C_BCNT_BEANLEN1 __BITS(30,16) /* beacon length in us */ |
| 703 | /* ATW_C_TSC_TIMTABSEL = 0 */ |
| 704 | #define ATW_C_BCNT_EXTEN0 __BIT(15) /* 11M beacon len. extension */ |
| 705 | #define ATW_C_BCNT_BEANLEN0 __BIT(14,0) /* beacon length in us */ |
| 706 | |
| 707 | #define ATW_C_TSC_TIMOFS __BITS(31,24) /* I think this is the |
| 708 | * SRAM offset for the TIM |
| 709 | */ |
| 710 | #define ATW_C_TSC_TIMLEN __BITS(21,12) /* length of TIM */ |
| 711 | #define ATW_C_TSC_TIMTABSEL __BIT(4) /* select TIM table 0 or 1 */ |
| 712 | #define ATW_TSC_TSC_MASK __BITS(3,0) /* TSFT countdown value, 0 |
| 713 | * disables |
| 714 | */ |
| 715 | |
| 716 | #define ATW_SYNRF_SELSYN __BIT(31) /* 0: MAC controls SYN IF pins, |
| 717 | * 1: ATW_SYNRF |
| 718 | * controls SYN IF |
| 719 | * pins. |
| 720 | */ |
| 721 | #define ATW_SYNRF_SELRF __BIT(30) /* 0: MAC controls RF IF pins, |
| 722 | * 1: ATW_SYNRF |
| 723 | * controls RF IF pins. |
| 724 | */ |
| 725 | #define ATW_SYNRF_LERF __BIT(29) /* if SELSYN = 1, direct control |
| 726 | * of LERF# pin |
| 727 | */ |
| 728 | #define ATW_SYNRF_LEIF __BIT(28) /* if SELSYN = 1, direct control |
| 729 | * of LEIF# pin |
| 730 | */ |
| 731 | #define ATW_SYNRF_SYNCLK __BIT(27) /* if SELSYN = 1, direct control |
| 732 | * of SYNCLK pin |
| 733 | */ |
| 734 | #define ATW_SYNRF_SYNDATA __BIT(26) /* if SELSYN = 1, direct control |
| 735 | * of SYNDATA pin |
| 736 | */ |
| 737 | #define ATW_SYNRF_PE1 __BIT(25) /* if SELRF = 1, direct control |
| 738 | * of PE1 pin |
| 739 | */ |
| 740 | #define ATW_SYNRF_PE2 __BIT(24) /* if SELRF = 1, direct control |
| 741 | * of PE2 pin |
| 742 | */ |
| 743 | #define ATW_SYNRF_PAPE __BIT(23) /* if SELRF = 1, direct control |
| 744 | * of PAPE pin |
| 745 | */ |
| 746 | #define ATW_C_SYNRF_TRSW __BIT(22) /* if SELRF = 1, direct control |
| 747 | * of TRSW pin |
| 748 | */ |
| 749 | #define ATW_C_SYNRF_TRSWN __BIT(21) /* if SELRF = 1, direct control |
| 750 | * of TRSWn pin |
| 751 | */ |
| 752 | #define ATW_SYNRF_INTERSIL_EN __BIT(20) /* if SELRF = 1, enables |
| 753 | * some signal used by the |
| 754 | * Intersil RF front-end? |
| 755 | * Undocumented. |
| 756 | */ |
| 757 | #define ATW_SYNRF_PHYRST __BIT(18) /* if SELRF = 1, direct control |
| 758 | * of PHYRST# pin |
| 759 | */ |
| 760 | /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ |
| 761 | #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST |
| 762 | |
| 763 | #define ATW_BPLI_BP_MASK __BITS(31,16) /* beacon interval in TU */ |
| 764 | #define ATW_BPLI_LI_MASK __BITS(15,0) /* STA listen interval in |
| 765 | * beacon intervals |
| 766 | */ |
| 767 | |
| 768 | #define ATW_C_CAP0_TIMLEN1 __BITS(31,24) /* TIM table 1 len in bytes |
| 769 | * including TIM ID (XXX huh?) |
| 770 | */ |
| 771 | #define ATW_C_CAP0_TIMLEN0 __BITS(23,16) /* TIM table 0 len in bytes, |
| 772 | * including TIM ID (XXX huh?) |
| 773 | */ |
| 774 | #define ATW_C_CAP0_CWMAX __BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? |
| 775 | * 5 < CWMAX <= 9 sets max? |
| 776 | * 10? |
| 777 | * default 0 |
| 778 | */ |
| 779 | #define ATW_CAP0_RCVDTIM __BIT(4) /* receive every DTIM */ |
| 780 | #define ATW_CAP0_CHN_MASK __BITS(3,0) /* current DSSS channel */ |
| 781 | |
| 782 | #define ATW_CAP1_CAPI_MASK __BITS(31,16) /* capability information */ |
| 783 | #define ATW_CAP1_ATIMW_MASK __BITS(15,0) /* ATIM window in TU */ |
| 784 | |
| 785 | #define ATW_RMD_ATIMST __BIT(31) /* ATIM frame TX status */ |
| 786 | #define ATW_RMD_CFP __BIT(30) /* CFP indicator */ |
| 787 | #define ATW_RMD_PCNT __BITS(27,16) /* idle time between |
| 788 | * awake/ps mode, in seconds |
| 789 | */ |
| 790 | #define ATW_RMD_RMRD_MASK __BITS(15,0) /* max RX reception duration |
| 791 | * in us |
| 792 | */ |
| 793 | |
| 794 | #define ATW_CFPP_CFPP __BITS(31,24) /* CFP unit DTIM */ |
| 795 | #define ATW_CFPP_CFPMD __BITS(23,8) /* CFP max duration in TU */ |
| 796 | #define ATW_CFPP_DTIMP __BITS(7,0) /* DTIM period in beacon |
| 797 | * intervals |
| 798 | */ |
| 799 | #define ATW_TOFS0_USCNT_MASK __BITS(29,24) /* number of system clocks |
| 800 | * in 1 microsecond. |
| 801 | * Depends PCI bus speed? |
| 802 | */ |
| 803 | #define ATW_C_TOFS0_TUCNT_MASK __BITS(14,10) /* PIFS (microseconds) */ |
| 804 | #define ATW_TOFS0_TUCNT_MASK __BITS(9,0) /* TU counter in microseconds */ |
| 805 | |
| 806 | /* TBD TOFS1 */ |
| 807 | #define ATW_TOFS1_TSFTOFSR_MASK __BITS(31,24) /* RX TSFT offset in |
| 808 | * microseconds: RF+BBP |
| 809 | * latency |
| 810 | */ |
| 811 | #define ATW_TOFS1_TBTTPRE_MASK __BITS(23,8) /* prediction time, (next |
| 812 | * Nth TBTT - TBTTOFS) in |
| 813 | * microseconds (huh?). To |
| 814 | * match TSFT[25:10] (huh?). |
| 815 | */ |
| 816 | #define ATW_TBTTPRE_MASK __BITS(25, 10) |
| 817 | #define ATW_TOFS1_TBTTOFS_MASK __BITS(7,0) /* wake-up time offset before |
| 818 | * TBTT in TU |
| 819 | */ |
| 820 | #define ATW_IFST_SLOT_MASK __BITS(27,23) /* SLOT time in us */ |
| 821 | #define ATW_IFST_SIFS_MASK __BITS(22,15) /* SIFS time in us */ |
| 822 | #define ATW_IFST_DIFS_MASK __BITS(14,9) /* DIFS time in us */ |
| 823 | #define ATW_IFST_EIFS_MASK __BITS(8,0) /* EIFS time in us */ |
| 824 | |
| 825 | #define ATW_RSPT_MART_MASK __BITS(31,16) /* max response time in us */ |
| 826 | #define ATW_RSPT_MIRT_MASK __BITS(15,8) /* min response time in us */ |
| 827 | #define ATW_RSPT_TSFTOFST_MASK __BITS(7,0) /* TX TSFT offset in us */ |
| 828 | |
| 829 | #define ATW_WEPCTL_WEPENABLE __BIT(31) /* enable WEP engine */ |
| 830 | #define ATW_WEPCTL_AUTOSWITCH __BIT(30) /* auto-switch enable (huh?) */ |
| 831 | #define ATW_WEPCTL_CURTBL __BIT(29) /* current table in use */ |
| 832 | #define ATW_WEPCTL_WR __BIT(28) /* */ |
| 833 | #define ATW_WEPCTL_RD __BIT(27) /* */ |
| 834 | #define ATW_WEPCTL_WEPRXBYP __BIT(25) /* bypass WEP on RX */ |
| 835 | #define ATW_WEPCTL_SHKEY __BIT(24) /* 1: pass to host if tbl |
| 836 | * lookup fails, 0: use |
| 837 | * shared-key |
| 838 | */ |
| 839 | #define ATW_WEPCTL_UNKNOWN0 __BIT(23) /* has something to do with |
| 840 | * revision 0x20. Possibly |
| 841 | * selects a different WEP |
| 842 | * table. |
| 843 | */ |
| 844 | #define ATW_WEPCTL_TBLADD_MASK __BITS(8,0) /* add to table */ |
| 845 | |
| 846 | /* set these bits in the second byte of a SRAM shared key record to affect |
| 847 | * the use and interpretation of the key in the record. |
| 848 | */ |
| 849 | #define ATW_WEP_ENABLED __BIT(7) |
| 850 | #define ATW_WEP_104BIT __BIT(6) |
| 851 | |
| 852 | #define ATW_WESK_DATA_MASK __BITS(15,0) /* data */ |
| 853 | #define ATW_WEPCNT_WIEC_MASK __BITS(15,0) /* WEP ICV error count */ |
| 854 | |
| 855 | #define ATW_MACTEST_FORCE_IV __BIT(23) |
| 856 | #define ATW_MACTEST_FORCE_KEYID __BIT(22) |
| 857 | #define ATW_MACTEST_KEYID_MASK __BITS(21,20) |
| 858 | #define ATW_MACTEST_MMI_USETXCLK __BIT(11) |
| 859 | |
| 860 | /* Function Event/Status registers */ |
| 861 | |
| 862 | /* interrupt: set regardless of mask */ |
| 863 | #define ATW_FER_INTR __BIT(15) |
| 864 | /* general wake-up: set regardless of mask */ |
| 865 | #define ATW_FER_GWAKE __BIT(4) |
| 866 | |
| 867 | #define ATW_FEMR_INTR_EN __BIT(15) /* enable INTA# */ |
| 868 | #define ATW_FEMR_WAKEUP_EN __BIT(14) /* enable wake-up */ |
| 869 | #define ATW_FEMR_GWAKE_EN __BIT(4) /* enable general wake-up */ |
| 870 | |
| 871 | #define ATW_FPSR_INTR_STATUS __BIT(15) /* interrupt status */ |
| 872 | #define ATW_FPSR_WAKEUP_STATUS __BIT(4) /* CSTSCHG state */ |
| 873 | /* activate INTA (if not masked) */ |
| 874 | #define ATW_FFER_INTA_FORCE __BIT(15) |
| 875 | /* activate CSTSCHG (if not masked) */ |
| 876 | #define ATW_FFER_GWAKE_FORCE __BIT(4) |
| 877 | |
| 878 | /* Serial EEPROM offsets */ |
| 879 | #define ATW_SR_CLASS_CODE (0x00/2) |
| 880 | #define ATW_SR_FORMAT_VERSION (0x02/2) |
| 881 | #define ATW_SR_MAJOR_MASK __BITS(7, 0) |
| 882 | #define ATW_SR_MINOR_MASK __BITS(15,8) |
| 883 | #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ |
| 884 | #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ |
| 885 | #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ |
| 886 | #define ATW_SR_CSR20 (0x16/2) |
| 887 | #define ATW_SR_ANT_MASK __BITS(12, 10) |
| 888 | #define ATW_SR_PWRSCALE_MASK __BITS(9, 8) |
| 889 | #define ATW_SR_CLKSAVE_MASK __BITS(7, 6) |
| 890 | #define ATW_SR_RFTYPE_MASK __BITS(5, 3) |
| 891 | #define ATW_SR_BBPTYPE_MASK __BITS(2, 0) |
| 892 | #define ATW_SR_CR28_CR03 (0x18/2) |
| 893 | #define ATW_SR_CR28_MASK __BITS(15,8) |
| 894 | #define ATW_SR_CR03_MASK __BITS(7, 0) |
| 895 | #define ATW_SR_CTRY_CR29 (0x1A/2) |
| 896 | #define ATW_SR_CTRY_MASK __BITS(15,8) /* country code */ |
| 897 | #define COUNTRY_FCC 0 |
| 898 | #define COUNTRY_IC 1 |
| 899 | #define COUNTRY_ETSI 2 |
| 900 | #define COUNTRY_SPAIN 3 |
| 901 | #define COUNTRY_FRANCE 4 |
| 902 | #define COUNTRY_MMK 5 |
| 903 | #define COUNTRY_MMK2 6 |
| 904 | #define ATW_SR_CR29_MASK __BITS(7, 0) |
| 905 | #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ |
| 906 | #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ |
| 907 | #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ |
| 908 | #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ |
| 909 | #define ATW_SR_CR15 (0x28/2) |
| 910 | #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ |
| 911 | #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ |
| 912 | #define ATW_SR_CSR18 (0x2E/2) |
| 913 | #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ |
| 914 | #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ |
| 915 | #define ATW_SR_CIS_WORDS (0x52/2) |
| 916 | /* CR17 of RFMD RF3000 BBP: returns TWO channels */ |
| 917 | #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) |
| 918 | /* CR20 of RFMD RF3000 BBP: returns TWO channels */ |
| 919 | #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) |
| 920 | /* CR21 of RFMD RF3000 BBP: returns TWO channels */ |
| 921 | #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) |
| 922 | #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ |
| 923 | #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ |
| 924 | |
| 925 | /* Tx descriptor */ |
| 926 | struct atw_txdesc { |
| 927 | volatile uint32_t at_ctl; |
| 928 | #define at_stat at_ctl |
| 929 | volatile uint32_t at_flags; |
| 930 | volatile uint32_t at_buf1; |
| 931 | volatile uint32_t at_buf2; |
| 932 | } __packed __aligned(4); |
| 933 | |
| 934 | #define ATW_TXCTL_OWN __BIT(31) /* 1: ready to transmit */ |
| 935 | #define ATW_TXCTL_DONE __BIT(30) /* 0: not processed */ |
| 936 | #define ATW_TXCTL_TXDR_MASK __BITS(27,20) /* TX data rate (?) */ |
| 937 | #define ATW_TXCTL_TL_MASK __BITS(19,0) /* retry limit, 0 - 255 */ |
| 938 | |
| 939 | #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ |
| 940 | #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ |
| 941 | #define ATW_TXSTAT_ES __BIT(29) /* 0: TX successful */ |
| 942 | #define ATW_TXSTAT_TLT __BIT(28) /* TX lifetime expired */ |
| 943 | #define ATW_TXSTAT_TRT __BIT(27) /* TX retry limit expired */ |
| 944 | #define ATW_TXSTAT_TUF __BIT(26) /* TX under-run error */ |
| 945 | #define ATW_TXSTAT_TRO __BIT(25) /* TX over-run error */ |
| 946 | #define ATW_TXSTAT_SOFBR __BIT(24) /* packet size != buffer size |
| 947 | * (?) |
| 948 | */ |
| 949 | #define ATW_TXSTAT_ARC_MASK __BITS(11,0) /* accumulated retry count */ |
| 950 | |
| 951 | #define ATW_TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | \ |
| 952 | ATW_TXSTAT_TRT | ATW_TXSTAT_TRO | \ |
| 953 | ATW_TXSTAT_SOFBR) |
| 954 | #define ATW_TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO" \ |
| 955 | "\33ATW_TXSTAT_TUF\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" |
| 956 | |
| 957 | #define ATW_TXFLAG_IC __BIT(31) /* interrupt on completion */ |
| 958 | #define ATW_TXFLAG_LS __BIT(30) /* packet's last descriptor */ |
| 959 | #define ATW_TXFLAG_FS __BIT(29) /* packet's first descriptor */ |
| 960 | #define ATW_TXFLAG_TER __BIT(25) /* end of ring */ |
| 961 | #define ATW_TXFLAG_TCH __BIT(24) /* at_buf2 is 2nd chain */ |
| 962 | #define ATW_TXFLAG_TBS2_MASK __BITS(23,12) /* at_buf2 byte count */ |
| 963 | #define ATW_TXFLAG_TBS1_MASK __BITS(11,0) /* at_buf1 byte count */ |
| 964 | |
| 965 | /* Rx descriptor */ |
| 966 | struct atw_rxdesc { |
| 967 | volatile uint32_t ar_stat; |
| 968 | volatile uint32_t ; |
| 969 | volatile uint32_t ar_buf1; |
| 970 | volatile uint32_t ar_buf2; |
| 971 | } __packed __aligned(4); |
| 972 | |
| 973 | #define ATW_RXCTL_RER __BIT(25) /* end of ring */ |
| 974 | #define ATW_RXCTL_RCH __BIT(24) /* ar_buf2 is 2nd chain */ |
| 975 | #define ATW_RXCTL_RBS2_MASK __BITS(23,12) /* ar_buf2 byte count */ |
| 976 | #define ATW_RXCTL_RBS1_MASK __BITS(11,0) /* ar_buf1 byte count */ |
| 977 | |
| 978 | #define ATW_RXSTAT_OWN __BIT(31) /* 1: NIC may fill descriptor */ |
| 979 | #define ATW_RXSTAT_ES __BIT(30) /* error summary, 0 on |
| 980 | * success |
| 981 | */ |
| 982 | #define ATW_RXSTAT_SQL __BIT(29) /* has signal quality (?) */ |
| 983 | #define ATW_RXSTAT_DE __BIT(28) /* descriptor error---packet is |
| 984 | * truncated. last descriptor |
| 985 | * only |
| 986 | */ |
| 987 | #define ATW_RXSTAT_FS __BIT(27) /* packet's first descriptor */ |
| 988 | #define ATW_RXSTAT_LS __BIT(26) /* packet's last descriptor */ |
| 989 | #define ATW_RXSTAT_PCF __BIT(25) /* received during CFP */ |
| 990 | #define ATW_RXSTAT_SFDE __BIT(24) /* PLCP SFD error */ |
| 991 | #define ATW_RXSTAT_SIGE __BIT(23) /* PLCP signal error */ |
| 992 | #define ATW_RXSTAT_CRC16E __BIT(22) /* PLCP CRC16 error */ |
| 993 | #define ATW_RXSTAT_RXTOE __BIT(21) /* RX time-out, last descriptor |
| 994 | * only. |
| 995 | */ |
| 996 | #define ATW_RXSTAT_CRC32E __BIT(20) /* CRC32 error */ |
| 997 | #define ATW_RXSTAT_ICVE __BIT(19) /* WEP ICV error */ |
| 998 | #define ATW_RXSTAT_DA1 __BIT(17) /* DA bit 1, admin'd address */ |
| 999 | #define ATW_RXSTAT_DA0 __BIT(16) /* DA bit 0, group address */ |
| 1000 | #define ATW_RXSTAT_RXDR_MASK __BITS(15,12) /* RX data rate */ |
| 1001 | #define ATW_RXSTAT_FL_MASK __BITS(11,0) /* RX frame length, last |
| 1002 | * descriptor only |
| 1003 | */ |
| 1004 | |
| 1005 | /* Static RAM (contains WEP keys, beacon content). Addresses and size |
| 1006 | * are in 16-bit words. |
| 1007 | */ |
| 1008 | #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 |
| 1009 | #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) |
| 1010 | #define ATW_SRAM_ADDR_SSID (0x180 * 2) |
| 1011 | #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) |
| 1012 | #define ATW_SRAM_MAXSIZE (0x200 * 2) |
| 1013 | #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE |
| 1014 | #define ATW_SRAM_B_SIZE (0x1c0 * 2) |
| 1015 | |
| 1016 | |