| 1 | /* $NetBSD: if_auereg.h,v 1.27 2016/04/23 10:15:31 skrll Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 1997, 1998, 1999 |
| 4 | * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by Bill Paul. |
| 17 | * 4. Neither the name of the author nor the names of any co-contributors |
| 18 | * may be used to endorse or promote products derived from this software |
| 19 | * without specific prior written permission. |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 31 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | * |
| 33 | * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.2 2000/01/08 06:52:36 wpaul Exp $ |
| 34 | */ |
| 35 | |
| 36 | /* |
| 37 | * Register definitions for ADMtek Pegasus AN986 USB to Ethernet |
| 38 | * chip. The Pegasus uses a total of four USB endpoints: the control |
| 39 | * endpoint (0), a bulk read endpoint for receiving packets (1), |
| 40 | * a bulk write endpoint for sending packets (2) and an interrupt |
| 41 | * endpoint for passing RX and TX status (3). Endpoint 0 is used |
| 42 | * to read and write the ethernet module's registers. All registers |
| 43 | * are 8 bits wide. |
| 44 | * |
| 45 | * Packet transfer is done in 64 byte chunks. The last chunk in a |
| 46 | * transfer is denoted by having a length less that 64 bytes. For |
| 47 | * the RX case, the data includes an optional RX status word. |
| 48 | */ |
| 49 | |
| 50 | #include <sys/rndsource.h> |
| 51 | |
| 52 | #define AUE_UR_READREG 0xF0 |
| 53 | #define AUE_UR_WRITEREG 0xF1 |
| 54 | |
| 55 | #define AUE_CONFIG_NO 1 |
| 56 | #define AUE_IFACE_IDX 0 |
| 57 | |
| 58 | /* |
| 59 | * Note that while the ADMtek technically has four |
| 60 | * endpoints, the control endpoint (endpoint 0) is |
| 61 | * regarded as special by the USB code and drivers |
| 62 | * don't have direct access to it. (We access it |
| 63 | * using usbd_do_request() when reading/writing |
| 64 | * registers.) Consequently, our endpoint indexes |
| 65 | * don't match those in the ADMtek Pegasus manual: |
| 66 | * we consider the RX data endpoint to be index 0 |
| 67 | * and work up from there. |
| 68 | */ |
| 69 | #define AUE_ENDPT_RX 0x0 |
| 70 | #define AUE_ENDPT_TX 0x1 |
| 71 | #define AUE_ENDPT_INTR 0x2 |
| 72 | #define AUE_ENDPT_MAX 0x3 |
| 73 | |
| 74 | #define AUE_CTL0 0x00 |
| 75 | #define AUE_CTL1 0x01 |
| 76 | #define AUE_CTL2 0x02 |
| 77 | #define AUE_MAR0 0x08 |
| 78 | #define AUE_MAR1 0x09 |
| 79 | #define AUE_MAR2 0x0A |
| 80 | #define AUE_MAR3 0x0B |
| 81 | #define AUE_MAR4 0x0C |
| 82 | #define AUE_MAR5 0x0D |
| 83 | #define AUE_MAR6 0x0E |
| 84 | #define AUE_MAR7 0x0F |
| 85 | #define AUE_MAR AUE_MAR0 |
| 86 | #define AUE_PAR0 0x10 |
| 87 | #define AUE_PAR1 0x11 |
| 88 | #define AUE_PAR2 0x12 |
| 89 | #define AUE_PAR3 0x13 |
| 90 | #define AUE_PAR4 0x14 |
| 91 | #define AUE_PAR5 0x15 |
| 92 | #define AUE_PAR AUE_PAR0 |
| 93 | #define AUE_PAUSE0 0x18 |
| 94 | #define AUE_PAUSE1 0x19 |
| 95 | #define AUE_PAUSE AUE_PAUSE0 |
| 96 | #define AUE_RX_FLOWCTL_CNT 0x1A |
| 97 | #define AUE_RX_FLOWCTL_FIFO 0x1B |
| 98 | #define AUE_REG_1D 0x1D |
| 99 | #define AUE_EE_REG 0x20 |
| 100 | #define AUE_EE_DATA0 0x21 |
| 101 | #define AUE_EE_DATA1 0x22 |
| 102 | #define AUE_EE_DATA AUE_EE_DATA0 |
| 103 | #define AUE_EE_CTL 0x23 |
| 104 | #define AUE_PHY_ADDR 0x25 |
| 105 | #define AUE_PHY_DATA0 0x26 |
| 106 | #define AUE_PHY_DATA1 0x27 |
| 107 | #define AUE_PHY_DATA AUE_PHY_DATA0 |
| 108 | #define AUE_PHY_CTL 0x28 |
| 109 | #define AUE_USB_STS 0x2A |
| 110 | #define AUE_TXSTAT0 0x2B |
| 111 | #define AUE_TXSTAT1 0x2C |
| 112 | #define AUE_TXSTAT AUE_TXSTAT0 |
| 113 | #define AUE_RXSTAT 0x2D |
| 114 | #define AUE_PKTLOST0 0x2E |
| 115 | #define AUE_PKTLOST1 0x2F |
| 116 | #define AUE_PKTLOST AUE_PKTLOST0 |
| 117 | |
| 118 | #define AUE_REG_7B 0x7B |
| 119 | #define AUE_GPIO0 0x7E |
| 120 | #define AUE_GPIO1 0x7F |
| 121 | #define AUE_REG_81 0x81 |
| 122 | |
| 123 | #define AUE_CTL0_INCLUDE_RXCRC 0x01 |
| 124 | #define AUE_CTL0_ALLMULTI 0x02 |
| 125 | #define AUE_CTL0_STOP_BACKOFF 0x04 |
| 126 | #define AUE_CTL0_RXSTAT_APPEND 0x08 |
| 127 | #define AUE_CTL0_WAKEON_ENB 0x10 |
| 128 | #define AUE_CTL0_RXPAUSE_ENB 0x20 |
| 129 | #define AUE_CTL0_RX_ENB 0x40 |
| 130 | #define AUE_CTL0_TX_ENB 0x80 |
| 131 | |
| 132 | #define AUE_CTL1_HOMELAN 0x04 |
| 133 | #define AUE_CTL1_RESETMAC 0x08 |
| 134 | #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ |
| 135 | #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ |
| 136 | #define AUE_CTL1_DELAYHOME 0x40 |
| 137 | |
| 138 | #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ |
| 139 | #define AUE_CTL2_RX_BADFRAMES 0x02 |
| 140 | #define AUE_CTL2_RX_PROMISC 0x04 |
| 141 | #define AUE_CTL2_LOOPBACK 0x08 |
| 142 | #define AUE_CTL2_EEPROMWR_ENB 0x10 |
| 143 | #define AUE_CTL2_EEPROM_LOAD 0x20 |
| 144 | |
| 145 | #define AUE_EECTL_WRITE 0x01 |
| 146 | #define AUE_EECTL_READ 0x02 |
| 147 | #define AUE_EECTL_DONE 0x04 |
| 148 | |
| 149 | #define AUE_PHYCTL_PHYREG 0x1F |
| 150 | #define AUE_PHYCTL_WRITE 0x20 |
| 151 | #define AUE_PHYCTL_READ 0x40 |
| 152 | #define AUE_PHYCTL_DONE 0x80 |
| 153 | |
| 154 | #define AUE_USBSTS_SUSPEND 0x01 |
| 155 | #define AUE_USBSTS_RESUME 0x02 |
| 156 | |
| 157 | #define AUE_TXSTAT0_JABTIMO 0x04 |
| 158 | #define AUE_TXSTAT0_CARLOSS 0x08 |
| 159 | #define AUE_TXSTAT0_NOCARRIER 0x10 |
| 160 | #define AUE_TXSTAT0_LATECOLL 0x20 |
| 161 | #define AUE_TXSTAT0_EXCESSCOLL 0x40 |
| 162 | #define AUE_TXSTAT0_UNDERRUN 0x80 |
| 163 | |
| 164 | #define AUE_TXSTAT1_PKTCNT 0x0F |
| 165 | #define AUE_TXSTAT1_FIFO_EMPTY 0x40 |
| 166 | #define AUE_TXSTAT1_FIFO_FULL 0x80 |
| 167 | |
| 168 | #define AUE_RXSTAT_OVERRUN 0x01 |
| 169 | #define AUE_RXSTAT_PAUSE 0x02 |
| 170 | |
| 171 | #define AUE_GPIO_IN0 0x01 |
| 172 | #define AUE_GPIO_OUT0 0x02 |
| 173 | #define AUE_GPIO_SEL0 0x04 |
| 174 | #define AUE_GPIO_IN1 0x08 |
| 175 | #define AUE_GPIO_OUT1 0x10 |
| 176 | #define AUE_GPIO_SEL1 0x20 |
| 177 | |
| 178 | struct aue_intrpkt { |
| 179 | uint8_t aue_txstat0; |
| 180 | uint8_t aue_txstat1; |
| 181 | uint8_t aue_rxstat; |
| 182 | uint8_t aue_rxlostpkt0; |
| 183 | uint8_t aue_rxlostpkt1; |
| 184 | uint8_t aue_wakeupstat; |
| 185 | uint8_t aue_rsvd; |
| 186 | uint8_t _pad; |
| 187 | }; |
| 188 | #define AUE_INTR_PKTLEN 8 |
| 189 | |
| 190 | struct aue_rxpkt { |
| 191 | uWord aue_pktlen; |
| 192 | uByte aue_rxstat; |
| 193 | }; |
| 194 | |
| 195 | #define AUE_RXSTAT_MCAST 0x01 |
| 196 | #define AUE_RXSTAT_GIANT 0x02 |
| 197 | #define AUE_RXSTAT_RUNT 0x04 |
| 198 | #define AUE_RXSTAT_CRCERR 0x08 |
| 199 | #define AUE_RXSTAT_DRIBBLE 0x10 |
| 200 | #define AUE_RXSTAT_MASK 0x1E |
| 201 | |
| 202 | |
| 203 | /*************** The rest belongs in if_auevar.h *************/ |
| 204 | |
| 205 | #define AUE_TX_LIST_CNT 1 |
| 206 | #define AUE_RX_LIST_CNT 1 |
| 207 | |
| 208 | struct aue_softc; |
| 209 | |
| 210 | struct aue_chain { |
| 211 | struct aue_softc *aue_sc; |
| 212 | struct usbd_xfer *aue_xfer; |
| 213 | char *aue_buf; |
| 214 | struct mbuf *aue_mbuf; |
| 215 | int aue_idx; |
| 216 | }; |
| 217 | |
| 218 | struct aue_cdata { |
| 219 | struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT]; |
| 220 | struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT]; |
| 221 | struct aue_intrpkt aue_ibuf; |
| 222 | int aue_tx_prod; |
| 223 | int aue_tx_cons; |
| 224 | int aue_tx_cnt; |
| 225 | int aue_rx_prod; |
| 226 | }; |
| 227 | |
| 228 | struct aue_softc { |
| 229 | device_t aue_dev; |
| 230 | |
| 231 | struct ethercom aue_ec; |
| 232 | struct mii_data aue_mii; |
| 233 | krndsource_t rnd_source; |
| 234 | struct lwp *aue_thread; |
| 235 | int aue_closing; |
| 236 | kcondvar_t aue_domc; |
| 237 | kcondvar_t aue_closemc; |
| 238 | kmutex_t aue_mcmtx; |
| 239 | #define GET_IFP(sc) (&(sc)->aue_ec.ec_if) |
| 240 | #define GET_MII(sc) (&(sc)->aue_mii) |
| 241 | |
| 242 | struct callout aue_stat_ch; |
| 243 | |
| 244 | struct usbd_device *aue_udev; |
| 245 | struct usbd_interface *aue_iface; |
| 246 | uint16_t aue_vendor; |
| 247 | uint16_t aue_product; |
| 248 | int aue_ed[AUE_ENDPT_MAX]; |
| 249 | struct usbd_pipe *aue_ep[AUE_ENDPT_MAX]; |
| 250 | uint8_t aue_link; |
| 251 | int aue_if_flags; |
| 252 | struct aue_cdata aue_cdata; |
| 253 | |
| 254 | uint16_t aue_flags; |
| 255 | |
| 256 | int aue_refcnt; |
| 257 | char aue_dying; |
| 258 | char aue_attached; |
| 259 | u_int aue_rx_errs; |
| 260 | u_int aue_intr_errs; |
| 261 | struct timeval aue_rx_notice; |
| 262 | |
| 263 | struct usb_task aue_tick_task; |
| 264 | struct usb_task aue_stop_task; |
| 265 | |
| 266 | kmutex_t aue_mii_lock; |
| 267 | }; |
| 268 | |
| 269 | #define AUE_TIMEOUT 1000 |
| 270 | #define ETHER_ALIGN 2 |
| 271 | #define AUE_BUFSZ 1536 |
| 272 | #define AUE_MIN_FRAMELEN 60 |
| 273 | #define AUE_TX_TIMEOUT 10000 /* ms */ |
| 274 | #define AUE_INTR_INTERVAL 100 /* ms */ |
| 275 | |