| 1 | /* $NetBSD: if_urtwnreg.h,v 1.10 2016/10/12 03:23:29 nat Exp $ */ |
| 2 | /* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> |
| 6 | * |
| 7 | * Permission to use, copy, modify, and distribute this software for any |
| 8 | * purpose with or without fee is hereby granted, provided that the above |
| 9 | * copyright notice and this permission notice appear in all copies. |
| 10 | * |
| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 18 | */ |
| 19 | |
| 20 | #define URTWN_NOISE_FLOOR -95 |
| 21 | |
| 22 | #define R92C_MAX_CHAINS 2 |
| 23 | |
| 24 | /* Maximum number of output pipes is 3. */ |
| 25 | #define R92C_MAX_EPOUT 3 |
| 26 | #define R92C_MAX_EPIN 3 |
| 27 | |
| 28 | #define R92C_MAX_TX_PWR 0x3f |
| 29 | |
| 30 | #define R92C_PUBQ_NPAGES 231 |
| 31 | #define R92C_TXPKTBUF_COUNT 256 |
| 32 | #define R92C_TX_PAGE_COUNT 248 |
| 33 | #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) |
| 34 | #define R88E_TXPKTBUF_COUNT 177 |
| 35 | #define R88E_TX_PAGE_COUNT 169 |
| 36 | #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) |
| 37 | #define R92E_TXPKTBUF_COUNT 256 |
| 38 | #define R92E_TX_PAGE_COUNT 243 |
| 39 | #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) |
| 40 | #define R92C_TXDESC_SUMSIZE 32 |
| 41 | |
| 42 | #define R92C_H2C_NBOX 4 |
| 43 | |
| 44 | /* USB Requests. */ |
| 45 | #define R92C_REQ_REGS 0x05 |
| 46 | |
| 47 | /* |
| 48 | * MAC registers. |
| 49 | */ |
| 50 | /* System Configuration. */ |
| 51 | #define R92C_SYS_ISO_CTRL 0x000 |
| 52 | #define R92C_SYS_FUNC_EN 0x002 |
| 53 | #define R92C_APS_FSMCO 0x004 |
| 54 | #define R92C_SYS_CLKR 0x008 |
| 55 | #define R92C_AFE_MISC 0x010 |
| 56 | #define R92C_SPS0_CTRL 0x011 |
| 57 | #define R92C_SYS_SWR_CTRL2 0x014 |
| 58 | #define R92C_SPS_OCP_CFG 0x018 |
| 59 | #define R92C_RSV_CTRL 0x01c |
| 60 | #define R92C_RF_CTRL 0x01f |
| 61 | #define R92C_LDOA15_CTRL 0x020 |
| 62 | #define R92C_LDOV12D_CTRL 0x021 |
| 63 | #define R92C_LDOHCI12_CTRL 0x022 |
| 64 | #define R92C_LPLDO_CTRL 0x023 |
| 65 | #define R92C_AFE_XTAL_CTRL 0x024 |
| 66 | #define R92C_AFE_PLL_CTRL 0x028 |
| 67 | #define R92C_AFE_CTRL3 0x02c |
| 68 | #define R92C_EFUSE_CTRL 0x030 |
| 69 | #define R92C_EFUSE_TEST 0x034 |
| 70 | #define R92C_PWR_DATA 0x038 |
| 71 | #define R92C_CAL_TIMER 0x03c |
| 72 | #define R92C_ACLK_MON 0x03e |
| 73 | #define R92C_GPIO_MUXCFG 0x040 |
| 74 | #define R92C_GPIO_IO_SEL 0x042 |
| 75 | #define R92C_MAC_PINMUX_CFG 0x043 |
| 76 | #define R92C_GPIO_PIN_CTRL 0x044 |
| 77 | #define R92C_GPIO_INTM 0x048 |
| 78 | #define R92C_LEDCFG0 0x04c |
| 79 | #define R92C_LEDCFG1 0x04d |
| 80 | #define R92C_LEDCFG2 0x04e |
| 81 | #define R92C_LEDCFG3 0x04f |
| 82 | #define R92C_FSIMR 0x050 |
| 83 | #define R92C_FSISR 0x054 |
| 84 | #define R92C_HSIMR 0x058 |
| 85 | #define R92C_HSISR 0x05c |
| 86 | #define R92C_AFE_CTRL4 0x078 |
| 87 | #define R92C_MCUFWDL 0x080 |
| 88 | #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) |
| 89 | #define R88E_HIMR 0x0b0 |
| 90 | #define R88E_HISR 0x0b4 |
| 91 | #define R88E_HIMRE 0x0b8 |
| 92 | #define R88E_HISRE 0x0bc |
| 93 | #define R92C_EFUSE_ACCESS 0x0cf |
| 94 | #define R92C_BIST_SCAN 0x0d0 |
| 95 | #define R92C_BIST_RPT 0x0d4 |
| 96 | #define R92C_BIST_ROM_RPT 0x0d8 |
| 97 | #define R92C_USB_SIE_INTF 0x0e0 |
| 98 | #define R92C_PCIE_MIO_INTF 0x0e4 |
| 99 | #define R92C_PCIE_MIO_INTD 0x0e8 |
| 100 | #define R92C_HPON_FSM 0x0ec |
| 101 | #define R92C_SYS_CFG 0x0f0 |
| 102 | /* MAC General Configuration. */ |
| 103 | #define R92C_CR 0x100 |
| 104 | #define R92C_MSR 0x102 |
| 105 | #define R92C_PBP 0x104 |
| 106 | #define R92C_TRXDMA_CTRL 0x10c |
| 107 | #define R92C_TRXFF_BNDY 0x114 |
| 108 | #define R92C_TRXFF_STATUS 0x118 |
| 109 | #define R92C_RXFF_PTR 0x11c |
| 110 | #define R92C_HIMR 0x120 |
| 111 | #define R92C_HISR 0x124 |
| 112 | #define R92C_HIMRE 0x128 |
| 113 | #define R92C_HISRE 0x12c |
| 114 | #define R92C_CPWM 0x12f |
| 115 | #define R92C_FWIMR 0x130 |
| 116 | #define R92C_FWISR 0x134 |
| 117 | #define R92C_PKTBUF_DBG_CTRL 0x140 |
| 118 | #define R92C_PKTBUF_DBG_DATA_L 0x144 |
| 119 | #define R92C_PKTBUF_DBG_DATA_H 0x148 |
| 120 | #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) |
| 121 | #define R92C_TCUNIT_BASE 0x164 |
| 122 | #define R92C_MBIST_START 0x174 |
| 123 | #define R92C_MBIST_DONE 0x178 |
| 124 | #define R92C_MBIST_FAIL 0x17c |
| 125 | #define R92C_C2HEVT_MSG_NORMAL 0x1a0 |
| 126 | #define R92C_C2HEVT_MSG_TEST 0x1b8 |
| 127 | #define R92C_C2HEVT_CLEAR 0x1bf |
| 128 | #define R92C_MCUTST_1 0x1c0 |
| 129 | #define R92C_FMETHR 0x1c8 |
| 130 | #define R92C_HMETFR 0x1cc |
| 131 | #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) |
| 132 | #define R92C_LLT_INIT 0x1e0 |
| 133 | #define R92C_BB_ACCESS_CTRL 0x1e8 |
| 134 | #define R92C_BB_ACCESS_DATA 0x1ec |
| 135 | #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) |
| 136 | #define R92E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) |
| 137 | /* Tx DMA Configuration. */ |
| 138 | #define R92C_RQPN 0x200 |
| 139 | #define R92C_FIFOPAGE 0x204 |
| 140 | #define R92C_TDECTRL 0x208 |
| 141 | #define R92C_TXDMA_OFFSET_CHK 0x20c |
| 142 | #define R92C_TXDMA_STATUS 0x210 |
| 143 | #define R92C_RQPN_NPQ 0x214 |
| 144 | /* Rx DMA Configuration. */ |
| 145 | #define R92C_RXDMA_AGG_PG_TH 0x280 |
| 146 | #define R92C_RXPKT_NUM 0x284 |
| 147 | #define R92C_RXDMA_STATUS 0x288 |
| 148 | /* Protocol Configuration. */ |
| 149 | #define R92C_FWHW_TXQ_CTRL 0x420 |
| 150 | #define R92C_HWSEQ_CTRL 0x423 |
| 151 | #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 |
| 152 | #define R92C_TXPKTBUF_MGQ_BDNY 0x425 |
| 153 | #define R92C_SPEC_SIFS 0x428 |
| 154 | #define R92C_RL 0x42a |
| 155 | #define R92C_DARFRC 0x430 |
| 156 | #define R92C_RARFRC 0x438 |
| 157 | #define R92C_RRSR 0x440 |
| 158 | #define R92C_ARFR(i) (0x444 + (i) * 4) |
| 159 | #define R92C_AGGLEN_LMT 0x458 |
| 160 | #define R92C_AMPDU_MIN_SPACE 0x45c |
| 161 | #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d |
| 162 | #define R92C_FAST_EDCA_CTRL 0x460 |
| 163 | #define R92C_RD_RESP_PKT_TH 0x463 |
| 164 | #define R92C_INIRTS_RATE_SEL 0x480 |
| 165 | #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) |
| 166 | #define R92C_MAX_AGGR_NUM 0x4ca |
| 167 | #define R92C_PROT_MODE_CTRL 0x4c8 |
| 168 | #define R92C_BAR_MODE_CTRL 0x4cc |
| 169 | /* EDCA Configuration. */ |
| 170 | #define R92C_EDCA_VO_PARAM 0x500 |
| 171 | #define R92C_EDCA_VI_PARAM 0x504 |
| 172 | #define R92C_EDCA_BE_PARAM 0x508 |
| 173 | #define R92C_EDCA_BK_PARAM 0x50c |
| 174 | #define R92C_BCNTCFG 0x510 |
| 175 | #define R92C_PIFS 0x512 |
| 176 | #define R92C_RDG_PIFS 0x513 |
| 177 | #define R92C_SIFS_CCK 0x514 |
| 178 | #define R92C_SIFS_OFDM 0x516 |
| 179 | #define R92C_AGGR_BREAK_TIME 0x51a |
| 180 | #define R92C_SLOT 0x51b |
| 181 | #define R92C_TX_PTCL_CTRL 0x520 |
| 182 | #define R92C_TXPAUSE 0x522 |
| 183 | #define R92C_DIS_TXREQ_CLR 0x523 |
| 184 | #define R92C_RD_CTRL 0x524 |
| 185 | #define R92C_TBTT_PROHIBIT 0x540 |
| 186 | #define R92C_RD_NAV_NXT 0x544 |
| 187 | #define R92C_NAV_PROT_LEN 0x546 |
| 188 | #define R92C_BCN_CTRL 0x550 |
| 189 | #define R92C_USTIME_TSF 0x551 |
| 190 | #define R92C_MBID_NUM 0x552 |
| 191 | #define R92C_DUAL_TSF_RST 0x553 |
| 192 | #define R92C_BCN_INTERVAL 0x554 |
| 193 | #define R92C_DRVERLYINT 0x558 |
| 194 | #define R92C_BCNDMATIM 0x559 |
| 195 | #define R92C_ATIMWND 0x55a |
| 196 | #define R92C_BCN_MAX_ERR 0x55d |
| 197 | #define R92C_RXTSF_OFFSET_CCK 0x55e |
| 198 | #define R92C_RXTSF_OFFSET_OFDM 0x55f |
| 199 | #define R92C_TSFTR 0x560 |
| 200 | #define R92C_INIT_TSFTR 0x564 |
| 201 | #define R92C_PSTIMER 0x580 |
| 202 | #define R92C_TIMER0 0x584 |
| 203 | #define R92C_TIMER1 0x588 |
| 204 | #define R92C_ACMHWCTRL 0x5c0 |
| 205 | #define R92C_ACMRSTCTRL 0x5c1 |
| 206 | #define R92C_ACMAVG 0x5c2 |
| 207 | #define R92C_VO_ADMTIME 0x5c4 |
| 208 | #define R92C_VI_ADMTIME 0x5c6 |
| 209 | #define R92C_BE_ADMTIME 0x5c8 |
| 210 | #define R92C_EDCA_RANDOM_GEN 0x5cc |
| 211 | #define R92C_SCH_TXCMD 0x5d0 |
| 212 | /* WMAC Configuration. */ |
| 213 | #define R92C_APSD_CTRL 0x600 |
| 214 | #define R92C_BWOPMODE 0x603 |
| 215 | #define R92C_TCR 0x604 |
| 216 | #define R92C_RCR 0x608 |
| 217 | #define R92C_RX_PKT_LIMIT 0x60c |
| 218 | #define R92C_RX_DLK_TIME 0x60d |
| 219 | #define R92C_RX_DRVINFO_SZ 0x60f |
| 220 | #define R92C_MACID 0x610 |
| 221 | #define R92C_BSSID 0x618 |
| 222 | #define R92C_MAR 0x620 |
| 223 | #define R92C_MBIDCAMCFG 0x628 |
| 224 | #define R92C_USTIME_EDCA 0x638 |
| 225 | #define R92C_MAC_SPEC_SIFS 0x63a |
| 226 | #define R92C_R2T_SIFS 0x63c |
| 227 | #define R92C_T2T_SIFS 0x63e |
| 228 | #define R92C_ACKTO 0x640 |
| 229 | #define R92C_CTS2TO 0x641 |
| 230 | #define R92C_EIFS 0x642 |
| 231 | #define R92C_NAV_CTRL 0x650 |
| 232 | #define R92C_BACAMCMD 0x654 |
| 233 | #define R92C_BACAMCONTENT 0x658 |
| 234 | #define R92C_LBDLY 0x660 |
| 235 | #define R92C_FWDLY 0x661 |
| 236 | #define R92C_RXERR_RPT 0x664 |
| 237 | #define R92C_WMAC_TRXPTCL_CTL 0x668 |
| 238 | #define R92C_CAMCMD 0x670 |
| 239 | #define R92C_CAMWRITE 0x674 |
| 240 | #define R92C_CAMREAD 0x678 |
| 241 | #define R92C_CAMDBG 0x67c |
| 242 | #define R92C_SECCFG 0x680 |
| 243 | #define R92C_WOW_CTRL 0x690 |
| 244 | #define R92C_PSSTATUS 0x691 |
| 245 | #define R92C_PS_RX_INFO 0x692 |
| 246 | #define R92C_LPNAV_CTRL 0x694 |
| 247 | #define R92C_WKFMCAM_CMD 0x698 |
| 248 | #define R92C_WKFMCAM_RWD 0x69c |
| 249 | #define R92C_RXFLTMAP0 0x6a0 |
| 250 | #define R92C_RXFLTMAP1 0x6a2 |
| 251 | #define R92C_RXFLTMAP2 0x6a4 |
| 252 | #define R92C_BCN_PSR_RPT 0x6a8 |
| 253 | #define R92C_CALB32K_CTRL 0x6ac |
| 254 | #define R92C_PKT_MON_CTRL 0x6b4 |
| 255 | #define R92C_BT_COEX_TABLE 0x6c0 |
| 256 | #define R92C_WMAC_RESP_TXINFO 0x6d8 |
| 257 | |
| 258 | /* Bits for R92C_SYS_ISO_CTRL. */ |
| 259 | #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 |
| 260 | #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 |
| 261 | #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 |
| 262 | #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 |
| 263 | #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 |
| 264 | #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 |
| 265 | #define R92C_SYS_ISO_CTRL_DIOP 0x0040 |
| 266 | #define R92C_SYS_ISO_CTRL_DIOE 0x0080 |
| 267 | #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 |
| 268 | #define R92C_SYS_ISO_CTRL_DIOR 0x0200 |
| 269 | #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 |
| 270 | #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 |
| 271 | |
| 272 | /* Bits for R92C_SYS_FUNC_EN. */ |
| 273 | #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 |
| 274 | #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 |
| 275 | #define R92C_SYS_FUNC_EN_USBA 0x0004 |
| 276 | #define R92C_SYS_FUNC_EN_UPLL 0x0008 |
| 277 | #define R92C_SYS_FUNC_EN_USBD 0x0010 |
| 278 | #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 |
| 279 | #define R92C_SYS_FUNC_EN_PCIEA 0x0040 |
| 280 | #define R92C_SYS_FUNC_EN_PPLL 0x0080 |
| 281 | #define R92C_SYS_FUNC_EN_PCIED 0x0100 |
| 282 | #define R92C_SYS_FUNC_EN_DIOE 0x0200 |
| 283 | #define R92C_SYS_FUNC_EN_CPUEN 0x0400 |
| 284 | #define R92C_SYS_FUNC_EN_DCORE 0x0800 |
| 285 | #define R92C_SYS_FUNC_EN_ELDR 0x1000 |
| 286 | #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 |
| 287 | #define R92C_SYS_FUNC_EN_HWPDN 0x4000 |
| 288 | #define R92C_SYS_FUNC_EN_MREGEN 0x8000 |
| 289 | |
| 290 | /* Bits for R92C_APS_FSMCO. */ |
| 291 | #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 |
| 292 | #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 |
| 293 | #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 |
| 294 | #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 |
| 295 | #define R92C_APS_FSMCO_PDN_EN 0x00000010 |
| 296 | #define R92C_APS_FSMCO_PDN_PL 0x00000020 |
| 297 | #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 |
| 298 | #define R92C_APS_FSMCO_APFM_OFF 0x00000200 |
| 299 | #define R92C_APS_FSMCO_APFM_RSM 0x00000400 |
| 300 | #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 |
| 301 | #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 |
| 302 | #define R92C_APS_FSMCO_APDM_MAC 0x00002000 |
| 303 | #define R92C_APS_FSMCO_APDM_HOST 0x00004000 |
| 304 | #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 |
| 305 | #define R92C_APS_FSMCO_RDY_MACON 0x00010000 |
| 306 | #define R92C_APS_FSMCO_SUS_HOST 0x00020000 |
| 307 | #define R92C_APS_FSMCO_ROP_ALD 0x00100000 |
| 308 | #define R92C_APS_FSMCO_ROP_PWR 0x00200000 |
| 309 | #define R92C_APS_FSMCO_ROP_SPS 0x00400000 |
| 310 | #define R92C_APS_FSMCO_SOP_MRST 0x02000000 |
| 311 | #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 |
| 312 | #define R92C_APS_FSMCO_SOP_ABG 0x08000000 |
| 313 | #define R92C_APS_FSMCO_SOP_AMB 0x10000000 |
| 314 | #define R92C_APS_FSMCO_SOP_RCK 0x20000000 |
| 315 | #define R92C_APS_FSMCO_SOP_A8M 0x40000000 |
| 316 | #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 |
| 317 | |
| 318 | /* Bits for R92C_SYS_CLKR. */ |
| 319 | #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 |
| 320 | #define R92C_SYS_CLKR_ANA8M 0x00000002 |
| 321 | #define R92C_SYS_CLKR_MACSLP 0x00000010 |
| 322 | #define R92C_SYS_CLKR_LOADER_EN 0x00000020 |
| 323 | #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 |
| 324 | #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 |
| 325 | #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 |
| 326 | #define R92C_SYS_CLKR_SEC_EN 0x00000400 |
| 327 | #define R92C_SYS_CLKR_MAC_EN 0x00000800 |
| 328 | #define R92C_SYS_CLKR_SYS_EN 0x00001000 |
| 329 | #define R92C_SYS_CLKR_RING_EN 0x00002000 |
| 330 | |
| 331 | /* Bits for R92C_RF_CTRL. */ |
| 332 | #define R92C_RF_CTRL_EN 0x01 |
| 333 | #define R92C_RF_CTRL_RSTB 0x02 |
| 334 | #define R92C_RF_CTRL_SDMRSTB 0x04 |
| 335 | |
| 336 | /* Bits for R92C_LDOV12D_CTRL. */ |
| 337 | #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 |
| 338 | |
| 339 | /* Bits for R92C_AFE_XTAL_CTRL. */ |
| 340 | #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 |
| 341 | #define R92C_AFE_XTAL_CTRL_ADDR_S 11 |
| 342 | |
| 343 | /* Bits for R92C_EFUSE_CTRL. */ |
| 344 | #define R92C_EFUSE_CTRL_DATA_M 0x000000ff |
| 345 | #define R92C_EFUSE_CTRL_DATA_S 0 |
| 346 | #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 |
| 347 | #define R92C_EFUSE_CTRL_ADDR_S 8 |
| 348 | #define R92C_EFUSE_CTRL_VALID 0x80000000 |
| 349 | |
| 350 | /* Bits for R92C_GPIO_MUXCFG. */ |
| 351 | #define R92C_GPIO_MUXCFG_ENBT 0x0020 |
| 352 | |
| 353 | /* Bits for R92C_LEDCFG0. */ |
| 354 | #define R92C_LEDCFG0_DIS 0x08 |
| 355 | |
| 356 | /* Bits for R92C_MCUFWDL. */ |
| 357 | #define R92C_MCUFWDL_EN 0x00000001 |
| 358 | #define R92C_MCUFWDL_RDY 0x00000002 |
| 359 | #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 |
| 360 | #define R92C_MCUFWDL_MACINI_RDY 0x00000008 |
| 361 | #define R92C_MCUFWDL_BBINI_RDY 0x00000010 |
| 362 | #define R92C_MCUFWDL_RFINI_RDY 0x00000020 |
| 363 | #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 |
| 364 | #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 |
| 365 | #define R92C_MCUFWDL_PAGE_M 0x00070000 |
| 366 | #define R92C_MCUFWDL_PAGE_S 16 |
| 367 | #define R92C_MCUFWDL_CPRST 0x00800000 |
| 368 | |
| 369 | /* Bits for R88E_HIMR. */ |
| 370 | #define R88E_HIMR_CPWM 0x00000100 |
| 371 | #define R88E_HIMR_CPWM2 0x00000200 |
| 372 | #define R88E_HIMR_TBDER 0x04000000 |
| 373 | #define R88E_HIMR_PSTIMEOUT 0x20000000 |
| 374 | |
| 375 | /* Bits for R88E_HIMRE.*/ |
| 376 | #define R88E_HIMRE_RXFOVW 0x00000100 |
| 377 | #define R88E_HIMRE_TXFOVW 0x00000200 |
| 378 | #define R88E_HIMRE_RXERR 0x00000400 |
| 379 | #define R88E_HIMRE_TXERR 0x00000800 |
| 380 | |
| 381 | /* Bits for R92C_EFUSE_ACCESS. */ |
| 382 | #define R92C_EFUSE_ACCESS_OFF 0x00 |
| 383 | #define R92C_EFUSE_ACCESS_ON 0x69 |
| 384 | |
| 385 | /* Bits for R92C_HPON_FSM. */ |
| 386 | #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 |
| 387 | #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 |
| 388 | #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 |
| 389 | |
| 390 | /* Bits for R92C_SYS_CFG. */ |
| 391 | #define R92C_SYS_CFG_XCLK_VLD 0x00000001 |
| 392 | #define R92C_SYS_CFG_ACLK_VLD 0x00000002 |
| 393 | #define R92C_SYS_CFG_UCLK_VLD 0x00000004 |
| 394 | #define R92C_SYS_CFG_PCLK_VLD 0x00000008 |
| 395 | #define R92C_SYS_CFG_PCIRSTB 0x00000010 |
| 396 | #define R92C_SYS_CFG_V15_VLD 0x00000020 |
| 397 | #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 |
| 398 | #define R92C_SYS_CFG_SIC_IDLE 0x00000100 |
| 399 | #define R92C_SYS_CFG_BD_MAC2 0x00000200 |
| 400 | #define R92C_SYS_CFG_BD_MAC1 0x00000400 |
| 401 | #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 |
| 402 | #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 |
| 403 | #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 |
| 404 | #define R92C_SYS_CFG_BT_FUNC 0x00010000 |
| 405 | #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 |
| 406 | #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 |
| 407 | #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 |
| 408 | #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 |
| 409 | #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 |
| 410 | #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 |
| 411 | #define R92C_SYS_CFG_TYPE_92C 0x08000000 |
| 412 | |
| 413 | /* Bits for R92C_CR. */ |
| 414 | #define R92C_CR_HCI_TXDMA_EN 0x00000001 |
| 415 | #define R92C_CR_HCI_RXDMA_EN 0x00000002 |
| 416 | #define R92C_CR_TXDMA_EN 0x00000004 |
| 417 | #define R92C_CR_RXDMA_EN 0x00000008 |
| 418 | #define R92C_CR_PROTOCOL_EN 0x00000010 |
| 419 | #define R92C_CR_SCHEDULE_EN 0x00000020 |
| 420 | #define R92C_CR_MACTXEN 0x00000040 |
| 421 | #define R92C_CR_MACRXEN 0x00000080 |
| 422 | #define R92C_CR_ENSEC 0x00000200 |
| 423 | #define R92C_CR_CALTMR_EN 0x00000400 |
| 424 | #define R92C_CR_NETTYPE_S 16 |
| 425 | #define R92C_CR_NETTYPE_M 0x00030000 |
| 426 | #define R92C_CR_NETTYPE_NOLINK 0 |
| 427 | #define R92C_CR_NETTYPE_ADHOC 1 |
| 428 | #define R92C_CR_NETTYPE_INFRA 2 |
| 429 | #define R92C_CR_NETTYPE_AP 3 |
| 430 | |
| 431 | /* Bits for R92C_MSR. */ |
| 432 | #define R92C_MSR_NOLINK 0x00 |
| 433 | #define R92C_MSR_ADHOC 0x01 |
| 434 | #define R92C_MSR_INFRA 0x02 |
| 435 | #define R92C_MSR_AP 0x03 |
| 436 | #define R92C_MSR_MASK (~R92C_MSR_AP) |
| 437 | |
| 438 | /* Bits for R92C_PBP. */ |
| 439 | #define R92C_PBP_PSRX_M 0x0f |
| 440 | #define R92C_PBP_PSRX_S 0 |
| 441 | #define R92C_PBP_PSTX_M 0xf0 |
| 442 | #define R92C_PBP_PSTX_S 4 |
| 443 | #define R92C_PBP_64 0 |
| 444 | #define R92C_PBP_128 1 |
| 445 | #define R92C_PBP_256 2 |
| 446 | #define R92C_PBP_512 3 |
| 447 | #define R92C_PBP_1024 4 |
| 448 | |
| 449 | /* Bits for R92C_TXPAUSE. */ |
| 450 | #define TP_STOPBECON 0x40 |
| 451 | #define TP_STOPHIGH 0x20 |
| 452 | #define TP_STOPMGT 0x10 |
| 453 | #define TP_STOPVO 0x08 |
| 454 | #define TP_STOPVI 0x04 |
| 455 | #define TP_STOPBE 0x02 |
| 456 | #define TP_STOPBK 0x01 |
| 457 | #define TP_STOPALL 0x6f |
| 458 | |
| 459 | /* Bits for R92C_TRXDMA_CTRL. */ |
| 460 | #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 |
| 461 | #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 |
| 462 | #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 |
| 463 | #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 |
| 464 | #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 |
| 465 | #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 |
| 466 | #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 |
| 467 | #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 |
| 468 | #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 |
| 469 | #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 |
| 470 | #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 |
| 471 | #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 |
| 472 | #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 |
| 473 | #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 |
| 474 | #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 |
| 475 | #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 |
| 476 | #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 |
| 477 | /* Shortcuts. */ |
| 478 | #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 |
| 479 | #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 |
| 480 | #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 |
| 481 | #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 |
| 482 | #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 |
| 483 | #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 |
| 484 | |
| 485 | /* Bits for R92C_LLT_INIT. */ |
| 486 | #define R92C_LLT_INIT_DATA_M 0x000000ff |
| 487 | #define R92C_LLT_INIT_DATA_S 0 |
| 488 | #define R92C_LLT_INIT_ADDR_M 0x0000ff00 |
| 489 | #define R92C_LLT_INIT_ADDR_S 8 |
| 490 | #define R92C_LLT_INIT_OP_M 0xc0000000 |
| 491 | #define R92C_LLT_INIT_OP_S 30 |
| 492 | #define R92C_LLT_INIT_OP_NO_ACTIVE 0 |
| 493 | #define R92C_LLT_INIT_OP_WRITE 1 |
| 494 | #define R92C_LLT_INIT_OP_READ 2 |
| 495 | |
| 496 | /* Bits for R92C_RQPN. */ |
| 497 | #define R92C_RQPN_HPQ_M 0x000000ff |
| 498 | #define R92C_RQPN_HPQ_S 0 |
| 499 | #define R92C_RQPN_LPQ_M 0x0000ff00 |
| 500 | #define R92C_RQPN_LPQ_S 8 |
| 501 | #define R92C_RQPN_PUBQ_M 0x00ff0000 |
| 502 | #define R92C_RQPN_PUBQ_S 16 |
| 503 | #define R92C_RQPN_LD 0x80000000 |
| 504 | |
| 505 | /* Bits for R92C_TDECTRL. */ |
| 506 | #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f |
| 507 | #define R92C_TDECTRL_BLK_DESC_NUM_S 4 |
| 508 | |
| 509 | /* Bits for R92C_FWHW_TXQ_CTRL. */ |
| 510 | #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 |
| 511 | |
| 512 | /* Bits for R92C_SPEC_SIFS. */ |
| 513 | #define R92C_SPEC_SIFS_CCK_M 0x00ff |
| 514 | #define R92C_SPEC_SIFS_CCK_S 0 |
| 515 | #define R92C_SPEC_SIFS_OFDM_M 0xff00 |
| 516 | #define R92C_SPEC_SIFS_OFDM_S 8 |
| 517 | |
| 518 | /* Bits for R92C_RL. */ |
| 519 | #define R92C_RL_LRL_M 0x003f |
| 520 | #define R92C_RL_LRL_S 0 |
| 521 | #define R92C_RL_SRL_M 0x3f00 |
| 522 | #define R92C_RL_SRL_S 8 |
| 523 | |
| 524 | /* Bits for R92C_RRSR. */ |
| 525 | #define R92C_RRSR_RATE_BITMAP_M 0x000fffff |
| 526 | #define R92C_RRSR_RATE_BITMAP_S 0 |
| 527 | #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 |
| 528 | #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 |
| 529 | #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 |
| 530 | #define R92C_RRSR_SHORT 0x00800000 |
| 531 | |
| 532 | /* Bits for R92C_EDCA_XX_PARAM. */ |
| 533 | #define R92C_EDCA_PARAM_AIFS_M 0x000000ff |
| 534 | #define R92C_EDCA_PARAM_AIFS_S 0 |
| 535 | #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 |
| 536 | #define R92C_EDCA_PARAM_ECWMIN_S 8 |
| 537 | #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 |
| 538 | #define R92C_EDCA_PARAM_ECWMAX_S 12 |
| 539 | #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 |
| 540 | #define R92C_EDCA_PARAM_TXOP_S 16 |
| 541 | |
| 542 | /* Bits for R92C_BCN_CTRL. */ |
| 543 | #define R92C_BCN_CTRL_EN_MBSSID 0x02 |
| 544 | #define R92C_BCN_CTRL_TXBCN_RPT 0x04 |
| 545 | #define R92C_BCN_CTRL_EN_BCN 0x08 |
| 546 | #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 |
| 547 | |
| 548 | /* Bits for R92C_DRVERLYINT */ |
| 549 | #define R92C_DRIVER_EARLY_INT_TIME 0x05 |
| 550 | |
| 551 | /* Bits for R92C_BCNDMATIM */ |
| 552 | #define R92C_DMA_ATIME_INT_TIME 0x02 |
| 553 | |
| 554 | /* Bits for R92C_APSD_CTRL. */ |
| 555 | #define R92C_APSD_CTRL_OFF 0x40 |
| 556 | #define R92C_APSD_CTRL_OFF_STATUS 0x80 |
| 557 | |
| 558 | /* Bits for R92C_BWOPMODE. */ |
| 559 | #define R92C_BWOPMODE_11J 0x01 |
| 560 | #define R92C_BWOPMODE_5G 0x02 |
| 561 | #define R92C_BWOPMODE_20MHZ 0x04 |
| 562 | |
| 563 | /* Bits for R92C_RCR. */ |
| 564 | #define R92C_RCR_AAP 0x00000001 // Accept all unicast packet |
| 565 | #define R92C_RCR_APM 0x00000002 // Accept physical match packet |
| 566 | #define R92C_RCR_AM 0x00000004 // Accept multicast packet |
| 567 | #define R92C_RCR_AB 0x00000008 // Accept broadcast packet |
| 568 | #define R92C_RCR_ADD3 0x00000010 // Accept address 3 match packet |
| 569 | #define R92C_RCR_APWRMGT 0x00000020 // Accept power management packet |
| 570 | #define R92C_RCR_CBSSID_DATA 0x00000040 // Accept BSSID match packet (Data) |
| 571 | #define R92C_RCR_CBSSID_BCN 0x00000080 // Accept BSSID match packet (Rx beacon, probe rsp) |
| 572 | #define R92C_RCR_ACRC32 0x00000100 // Accept CRC32 error packet |
| 573 | #define R92C_RCR_AICV 0x00000200 // Accept ICV error packet |
| 574 | #define R92C_RCR_ADF 0x00000800 // Accept data type frame |
| 575 | #define R92C_RCR_ACF 0x00001000 // Accept control type frame |
| 576 | #define R92C_RCR_AMF 0x00002000 // Accept management type frame |
| 577 | #define R92C_RCR_HTC_LOC_CTRL 0x00004000 // MFC<--HTC=1 MFC-->HTC=0 |
| 578 | #define R92C_RCR_MFBEN 0x00400000 |
| 579 | #define R92C_RCR_LSIGEN 0x00800000 |
| 580 | #define R92C_RCR_ENMBID 0x01000000 // Enable Multiple BssId. |
| 581 | #define R92C_RCR_APP_BA_SSN 0x08000000 // Accept BA SSN |
| 582 | #define R92C_RCR_APP_PHYSTS 0x10000000 |
| 583 | #define R92C_RCR_APP_ICV 0x20000000 |
| 584 | #define R92C_RCR_APP_MIC 0x40000000 |
| 585 | #define R92C_RCR_APPFCS 0x80000000 // WMAC append FCS after payload |
| 586 | |
| 587 | /* Bits for R92C_CAMCMD. */ |
| 588 | #define R92C_CAMCMD_ADDR_M 0x0000ffff |
| 589 | #define R92C_CAMCMD_ADDR_S 0 |
| 590 | #define R92C_CAMCMD_WRITE 0x00010000 |
| 591 | #define R92C_CAMCMD_CLR 0x40000000 |
| 592 | #define R92C_CAMCMD_POLLING 0x80000000 |
| 593 | |
| 594 | |
| 595 | /* |
| 596 | * Baseband registers. |
| 597 | */ |
| 598 | #define R92C_FPGA0_RFMOD 0x800 |
| 599 | #define R92C_FPGA0_TXINFO 0x804 |
| 600 | #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) |
| 601 | #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) |
| 602 | #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) |
| 603 | #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) |
| 604 | #define R92C_TXAGC_A_CCK1_MCS32 0xe08 |
| 605 | #define R92C_FPGA0_XA_HSSIPARAM1 0x820 |
| 606 | #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 |
| 607 | #define R92C_FPGA0_XCD_SWITCHCTL 0x85c |
| 608 | #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c |
| 609 | #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) |
| 610 | #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) |
| 611 | #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) |
| 612 | #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) |
| 613 | #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) |
| 614 | #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) |
| 615 | #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) |
| 616 | #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) |
| 617 | #define R92C_FPGA0_ANAPARAM2 0x884 |
| 618 | #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) |
| 619 | #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) |
| 620 | #define R92C_FPGA1_RFMOD 0x900 |
| 621 | #define R92C_FPGA1_TXINFO 0x90c |
| 622 | #define R92C_CCK0_SYSTEM 0xa00 |
| 623 | #define R92C_CCK0_AFESETTING 0xa04 |
| 624 | #define R92C_CONFIG_ANT_A 0xb68 |
| 625 | #define R92C_CONFIG_ANT_B 0xb6c |
| 626 | #define R92C_OFDM0_TRXPATHENA 0xc04 |
| 627 | #define R92C_OFDM0_TRMUXPAR 0xc08 |
| 628 | #define R92C_OFDM0_XARXIQIMBALANCE 0xc14 |
| 629 | #define R92C_OFDM0_ECCATHRESHOLD 0xc4c |
| 630 | #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) |
| 631 | #define R92C_OFDM0_AGCPARAM1 0xc70 |
| 632 | #define 0xc78 |
| 633 | #define R92C_OFDM0_HTSTFAGC 0xc7c |
| 634 | #define R92C_OFDM0_XATXIQIMBALANCE 0xc80 |
| 635 | #define R92C_OFDM0_XBTXIQIMBALANCE 0xc88 |
| 636 | #define R92C_OFDM0_XCTXIQIMBALANCE 0xc90 |
| 637 | #define R92C_OFDM0_XCTXAFE 0xc94 |
| 638 | #define R92C_OFDM0_XDTXAFE 0xc9c |
| 639 | #define R92C_OFDM0_RXIQEXTANTA 0xca0 |
| 640 | #define R92C_OFDM1_LSTF 0xd00 |
| 641 | #define R92C_FPGA0_IQK 0xe28 |
| 642 | #define R92C_TX_IQK 0xe40 |
| 643 | #define R92C_RX_IQK 0xe44 |
| 644 | #define R92C_BLUETOOTH 0xe6c |
| 645 | #define R92C_RX_WAIT_CCA 0xe70 |
| 646 | #define R92C_TX_CCK_RFON 0xe74 |
| 647 | #define R92C_TX_CCK_BBON 0xe78 |
| 648 | #define R92C_TX_OFDM_RFON 0xe7c |
| 649 | #define R92C_TX_OFDM_BBON 0xe80 |
| 650 | #define R92C_TX_TO_RX 0xe84 |
| 651 | #define R92C_TX_TO_TX 0xe88 |
| 652 | #define R92C_RX_CCK 0xe8c |
| 653 | #define R92C_RX_OFDM 0xed0 |
| 654 | #define R92C_RX_WAIT_RIFS 0xed4 |
| 655 | #define R92C_RX_TO_RX 0xed8 |
| 656 | #define R92C_STANDBY 0xedc |
| 657 | #define R92C_SLEEP 0xee0 |
| 658 | #define R92C_PMPD_ANAEN 0xeec |
| 659 | |
| 660 | /* Bits for R92C_FPGA[01]_RFMOD. */ |
| 661 | #define R92C_RFMOD_40MHZ 0x00000001 |
| 662 | #define R92C_RFMOD_JAPAN 0x00000002 |
| 663 | #define R92C_RFMOD_CCK_TXSC 0x00000030 |
| 664 | #define R92C_RFMOD_CCK_EN 0x01000000 |
| 665 | #define R92C_RFMOD_OFDM_EN 0x02000000 |
| 666 | |
| 667 | /* Bits for R92C_HSSI_PARAM1(i). */ |
| 668 | #define R92C_HSSI_PARAM1_PI 0x00000100 |
| 669 | |
| 670 | /* Bits for R92C_HSSI_PARAM2(i). */ |
| 671 | #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 |
| 672 | #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 |
| 673 | #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 |
| 674 | #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 |
| 675 | #define R92C_HSSI_PARAM2_READ_ADDR_S 23 |
| 676 | #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 |
| 677 | |
| 678 | /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ |
| 679 | #define R92C_TXAGC_A_CCK1_M 0x0000ff00 |
| 680 | #define R92C_TXAGC_A_CCK1_S 8 |
| 681 | |
| 682 | /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ |
| 683 | #define R92C_TXAGC_B_CCK11_M 0x000000ff |
| 684 | #define R92C_TXAGC_B_CCK11_S 0 |
| 685 | #define R92C_TXAGC_A_CCK2_M 0x0000ff00 |
| 686 | #define R92C_TXAGC_A_CCK2_S 8 |
| 687 | #define R92C_TXAGC_A_CCK55_M 0x00ff0000 |
| 688 | #define R92C_TXAGC_A_CCK55_S 16 |
| 689 | #define R92C_TXAGC_A_CCK11_M 0xff000000 |
| 690 | #define R92C_TXAGC_A_CCK11_S 24 |
| 691 | |
| 692 | /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ |
| 693 | #define R92C_TXAGC_B_CCK1_M 0x0000ff00 |
| 694 | #define R92C_TXAGC_B_CCK1_S 8 |
| 695 | #define R92C_TXAGC_B_CCK2_M 0x00ff0000 |
| 696 | #define R92C_TXAGC_B_CCK2_S 16 |
| 697 | #define R92C_TXAGC_B_CCK55_M 0xff000000 |
| 698 | #define R92C_TXAGC_B_CCK55_S 24 |
| 699 | |
| 700 | /* Bits for R92C_TXAGC_RATE18_06(x). */ |
| 701 | #define R92C_TXAGC_RATE06_M 0x000000ff |
| 702 | #define R92C_TXAGC_RATE06_S 0 |
| 703 | #define R92C_TXAGC_RATE09_M 0x0000ff00 |
| 704 | #define R92C_TXAGC_RATE09_S 8 |
| 705 | #define R92C_TXAGC_RATE12_M 0x00ff0000 |
| 706 | #define R92C_TXAGC_RATE12_S 16 |
| 707 | #define R92C_TXAGC_RATE18_M 0xff000000 |
| 708 | #define R92C_TXAGC_RATE18_S 24 |
| 709 | |
| 710 | /* Bits for R92C_TXAGC_RATE54_24(x). */ |
| 711 | #define R92C_TXAGC_RATE24_M 0x000000ff |
| 712 | #define R92C_TXAGC_RATE24_S 0 |
| 713 | #define R92C_TXAGC_RATE36_M 0x0000ff00 |
| 714 | #define R92C_TXAGC_RATE36_S 8 |
| 715 | #define R92C_TXAGC_RATE48_M 0x00ff0000 |
| 716 | #define R92C_TXAGC_RATE48_S 16 |
| 717 | #define R92C_TXAGC_RATE54_M 0xff000000 |
| 718 | #define R92C_TXAGC_RATE54_S 24 |
| 719 | |
| 720 | /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ |
| 721 | #define R92C_TXAGC_MCS00_M 0x000000ff |
| 722 | #define R92C_TXAGC_MCS00_S 0 |
| 723 | #define R92C_TXAGC_MCS01_M 0x0000ff00 |
| 724 | #define R92C_TXAGC_MCS01_S 8 |
| 725 | #define R92C_TXAGC_MCS02_M 0x00ff0000 |
| 726 | #define R92C_TXAGC_MCS02_S 16 |
| 727 | #define R92C_TXAGC_MCS03_M 0xff000000 |
| 728 | #define R92C_TXAGC_MCS03_S 24 |
| 729 | |
| 730 | /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ |
| 731 | #define R92C_TXAGC_MCS04_M 0x000000ff |
| 732 | #define R92C_TXAGC_MCS04_S 0 |
| 733 | #define R92C_TXAGC_MCS05_M 0x0000ff00 |
| 734 | #define R92C_TXAGC_MCS05_S 8 |
| 735 | #define R92C_TXAGC_MCS06_M 0x00ff0000 |
| 736 | #define R92C_TXAGC_MCS06_S 16 |
| 737 | #define R92C_TXAGC_MCS07_M 0xff000000 |
| 738 | #define R92C_TXAGC_MCS07_S 24 |
| 739 | |
| 740 | /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ |
| 741 | #define R92C_TXAGC_MCS08_M 0x000000ff |
| 742 | #define R92C_TXAGC_MCS08_S 0 |
| 743 | #define R92C_TXAGC_MCS09_M 0x0000ff00 |
| 744 | #define R92C_TXAGC_MCS09_S 8 |
| 745 | #define R92C_TXAGC_MCS10_M 0x00ff0000 |
| 746 | #define R92C_TXAGC_MCS10_S 16 |
| 747 | #define R92C_TXAGC_MCS11_M 0xff000000 |
| 748 | #define R92C_TXAGC_MCS11_S 24 |
| 749 | |
| 750 | /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ |
| 751 | #define R92C_TXAGC_MCS12_M 0x000000ff |
| 752 | #define R92C_TXAGC_MCS12_S 0 |
| 753 | #define R92C_TXAGC_MCS13_M 0x0000ff00 |
| 754 | #define R92C_TXAGC_MCS13_S 8 |
| 755 | #define R92C_TXAGC_MCS14_M 0x00ff0000 |
| 756 | #define R92C_TXAGC_MCS14_S 16 |
| 757 | #define R92C_TXAGC_MCS15_M 0xff000000 |
| 758 | #define R92C_TXAGC_MCS15_S 24 |
| 759 | |
| 760 | /* Bits for R92C_LSSI_PARAM(i). */ |
| 761 | #define R92C_LSSI_PARAM_DATA_M 0x000fffff |
| 762 | #define R92C_LSSI_PARAM_DATA_S 0 |
| 763 | #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 |
| 764 | #define R92C_LSSI_PARAM_ADDR_S 20 |
| 765 | #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 |
| 766 | #define R88E_LSSI_PARAM_ADDR_S 20 |
| 767 | |
| 768 | /* Bits for R92C_FPGA0_ANAPARAM2. */ |
| 769 | #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 |
| 770 | |
| 771 | /* Bits for R92C_LSSI_READBACK(i). */ |
| 772 | #define R92C_LSSI_READBACK_DATA_M 0x000fffff |
| 773 | #define R92C_LSSI_READBACK_DATA_S 0 |
| 774 | |
| 775 | /* Bits for R92C_OFDM0_AGCCORE1(i). */ |
| 776 | #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f |
| 777 | #define R92C_OFDM0_AGCCORE1_GAIN_S 0 |
| 778 | |
| 779 | /* |
| 780 | * USB registers. |
| 781 | */ |
| 782 | #define R92C_USB_INFO 0xfe17 |
| 783 | #define R92C_TEST_USB_TXQS 0xfe48 |
| 784 | #define R92C_USB_SPECIAL_OPTION 0xfe55 |
| 785 | #define R92C_USB_HCPWM 0xfe57 |
| 786 | #define R92C_USB_HRPWM 0xfe58 |
| 787 | #define R92C_USB_DMA_AGG_TO 0xfe5b |
| 788 | #define R92C_USB_AGG_TO 0xfe5c |
| 789 | #define R92C_USB_AGG_TH 0xfe5d |
| 790 | #define R92C_USB_VID 0xfe60 |
| 791 | #define R92C_USB_PID 0xfe62 |
| 792 | #define R92C_USB_OPTIONAL 0xfe64 |
| 793 | #define R92C_USB_EP 0xfe65 |
| 794 | #define R92C_USB_PHY 0xfe68 /* XXX: linux-3.7.4(rtlwifi/rtl8192ce/reg.h) has 0xfe66 */ |
| 795 | #define R92C_USB_MAC_ADDR 0xfe70 |
| 796 | #define R92C_USB_STRING 0xfe80 |
| 797 | |
| 798 | /* Bits for R92C_USB_SPECIAL_OPTION. */ |
| 799 | #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 |
| 800 | #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 |
| 801 | |
| 802 | /* Bits for R92C_USB_EP. */ |
| 803 | #define R92C_USB_EP_HQ_M 0x000f |
| 804 | #define R92C_USB_EP_HQ_S 0 |
| 805 | #define R92C_USB_EP_NQ_M 0x00f0 |
| 806 | #define R92C_USB_EP_NQ_S 4 |
| 807 | #define R92C_USB_EP_LQ_M 0x0f00 |
| 808 | #define R92C_USB_EP_LQ_S 8 |
| 809 | |
| 810 | /* Bits for R92C_RD_CTRL. */ |
| 811 | #define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) |
| 812 | |
| 813 | /* Bits for R92C_INIDATA_RATE_SEL. */ |
| 814 | #define R92C_RATE_SHORTGI __BIT(6) |
| 815 | |
| 816 | /* |
| 817 | * Firmware base address. |
| 818 | */ |
| 819 | #define R92C_FW_START_ADDR 0x1000 |
| 820 | #define R92C_FW_PAGE_SIZE 4096 |
| 821 | |
| 822 | |
| 823 | /* |
| 824 | * RF (6052) registers. |
| 825 | */ |
| 826 | #define R92C_RF_AC 0x00 |
| 827 | #define R92C_RF_IQADJ_G(i) (0x01 + (i)) |
| 828 | #define R92C_RF_POW_TRSW 0x05 |
| 829 | #define R92C_RF_GAIN_RX 0x06 |
| 830 | #define R92C_RF_GAIN_TX 0x07 |
| 831 | #define R92C_RF_TXM_IDAC 0x08 |
| 832 | #define R92C_RF_BS_IQGEN 0x0f |
| 833 | #define R92C_RF_MODE1 0x10 |
| 834 | #define R92C_RF_MODE2 0x11 |
| 835 | #define R92C_RF_RX_AGC_HP 0x12 |
| 836 | #define R92C_RF_TX_AGC 0x13 |
| 837 | #define R92C_RF_BIAS 0x14 |
| 838 | #define R92C_RF_IPA 0x15 |
| 839 | #define R92C_RF_POW_ABILITY 0x17 |
| 840 | #define R92C_RF_CHNLBW 0x18 |
| 841 | #define R92C_RF_RX_G1 0x1a |
| 842 | #define R92C_RF_RX_G2 0x1b |
| 843 | #define R92C_RF_RX_BB2 0x1c |
| 844 | #define R92C_RF_RX_BB1 0x1d |
| 845 | #define R92C_RF_RCK1 0x1e |
| 846 | #define R92C_RF_RCK2 0x1f |
| 847 | #define R92C_RF_TX_G(i) (0x20 + (i)) |
| 848 | #define R92C_RF_TX_BB1 0x23 |
| 849 | #define R92C_RF_T_METER 0x24 |
| 850 | #define R92C_RF_SYN_G(i) (0x25 + (i)) |
| 851 | #define R92C_RF_RCK_OS 0x30 |
| 852 | #define R92C_RF_TXPA_G(i) (0x31 + (i)) |
| 853 | |
| 854 | /* Bits for R92C_RF_AC. */ |
| 855 | #define R92C_RF_AC_MODE_M 0x70000 |
| 856 | #define R92C_RF_AC_MODE_S 16 |
| 857 | #define R92C_RF_AC_MODE_STANDBY 1 |
| 858 | |
| 859 | /* Bits for R92C_RF_CHNLBW. */ |
| 860 | #define R92C_RF_CHNLBW_CHNL_M 0x003ff |
| 861 | #define R92C_RF_CHNLBW_CHNL_S 0 |
| 862 | #define R92C_RF_CHNLBW_BW20 0x00400 |
| 863 | #define R88E_RF_CHNLBW_BW20 0x00c00 |
| 864 | #define R92C_RF_CHNLBW_LCSTART 0x08000 |
| 865 | |
| 866 | |
| 867 | /* |
| 868 | * CAM entries. |
| 869 | */ |
| 870 | #define R92C_CAM_ENTRY_COUNT 32 |
| 871 | |
| 872 | #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) |
| 873 | #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) |
| 874 | #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) |
| 875 | |
| 876 | /* Bits for R92C_CAM_CTL0(i). */ |
| 877 | #define R92C_CAM_KEYID_M 0x00000003 |
| 878 | #define R92C_CAM_KEYID_S 0 |
| 879 | #define R92C_CAM_ALGO_M 0x0000001c |
| 880 | #define R92C_CAM_ALGO_S 2 |
| 881 | #define R92C_CAM_ALGO_NONE 0 |
| 882 | #define R92C_CAM_ALGO_WEP40 1 |
| 883 | #define R92C_CAM_ALGO_TKIP 2 |
| 884 | #define R92C_CAM_ALGO_AES 4 |
| 885 | #define R92C_CAM_ALGO_WEP104 5 |
| 886 | #define R92C_CAM_VALID 0x00008000 |
| 887 | #define R92C_CAM_MACLO_M 0xffff0000 |
| 888 | #define R92C_CAM_MACLO_S 16 |
| 889 | |
| 890 | /* Rate adaptation modes. */ |
| 891 | #define R92C_RAID_11BGN 0 |
| 892 | #define R92C_RAID_11GN 1 |
| 893 | #define R92C_RAID_11N 3 |
| 894 | #define R92C_RAID_11BG 4 |
| 895 | #define R92C_RAID_11G 5 /* "pure" 11g */ |
| 896 | #define R92C_RAID_11B 6 |
| 897 | |
| 898 | |
| 899 | /* Macros to access unaligned little-endian memory. */ |
| 900 | #define LE_READ_2(x) ((x)[0] | ((x)[1]<<8)) |
| 901 | #define LE_READ_4(x) ((x)[0] | ((x)[1]<<8) | ((x)[2]<<16) | ((x)[3]<<24)) |
| 902 | |
| 903 | /* |
| 904 | * Macros to access subfields in registers. |
| 905 | */ |
| 906 | /* Mask and Shift (getter). */ |
| 907 | #define MS(val, field) \ |
| 908 | (((val) & field##_M) >> field##_S) |
| 909 | |
| 910 | /* Shift and Mask (setter). */ |
| 911 | #define SM(field, val) \ |
| 912 | (((val) << field##_S) & field##_M) |
| 913 | |
| 914 | /* Rewrite. */ |
| 915 | #define RW(var, field, val) \ |
| 916 | (((var) & ~field##_M) | SM(field, val)) |
| 917 | |
| 918 | /* |
| 919 | * Firmware image header. |
| 920 | */ |
| 921 | struct r92c_fw_hdr { |
| 922 | /* QWORD0 */ |
| 923 | uint16_t signature; |
| 924 | uint8_t category; |
| 925 | uint8_t function; |
| 926 | uint16_t version; |
| 927 | uint16_t subversion; |
| 928 | /* QWORD1 */ |
| 929 | uint8_t month; |
| 930 | uint8_t date; |
| 931 | uint8_t hour; |
| 932 | uint8_t minute; |
| 933 | uint16_t ramcodesize; |
| 934 | uint16_t reserved2; |
| 935 | /* QWORD2 */ |
| 936 | uint32_t svnidx; |
| 937 | uint32_t reserved3; |
| 938 | /* QWORD3 */ |
| 939 | uint32_t reserved4; |
| 940 | uint32_t reserved5; |
| 941 | } __packed; |
| 942 | |
| 943 | /* |
| 944 | * Host to firmware commands. |
| 945 | */ |
| 946 | struct r92c_fw_cmd { |
| 947 | uint8_t id; |
| 948 | #define R92C_CMD_AP_OFFLOAD 0 |
| 949 | #define R92C_CMD_SET_PWRMODE 1 |
| 950 | #define R92C_CMD_JOINBSS_RPT 2 |
| 951 | #define R92C_CMD_RSVD_PAGE 3 |
| 952 | #define 4 |
| 953 | #define 5 |
| 954 | #define R92C_CMD_MACID_CONFIG 6 |
| 955 | #define R92C_CMD_MACID_PS_MODE 7 |
| 956 | #define R92C_CMD_P2P_PS_OFFLOAD 8 |
| 957 | #define R92C_CMD_SELECTIVE_SUSPEND 9 |
| 958 | #define R92C_CMD_USB_SUSPEND 43 |
| 959 | #define R92C_CMD_FLAG_EXT 0x80 |
| 960 | |
| 961 | uint8_t msg[5]; |
| 962 | } __packed; |
| 963 | |
| 964 | /* Structure for R92C_CMD_RSSI_SETTING. */ |
| 965 | struct { |
| 966 | uint8_t ; |
| 967 | uint8_t ; |
| 968 | uint8_t ; |
| 969 | } __packed; |
| 970 | |
| 971 | /* Structure for R92C_CMD_MACID_CONFIG. */ |
| 972 | struct r92c_fw_cmd_macid_cfg { |
| 973 | uint8_t mask[4]; |
| 974 | uint8_t macid; |
| 975 | #define URTWN_MACID_BSS 0 |
| 976 | #define URTWN_MACID_BC 4 /* Broadcast. */ |
| 977 | #define URTWN_MACID_VALID 0x80 |
| 978 | #define URTWN_MACID_SHORTGI 0x20 |
| 979 | } __packed; |
| 980 | |
| 981 | /* Structure for R92C_CMD_SET_PWRMODE. */ |
| 982 | struct r92c_fw_cmd_setpwrmode { |
| 983 | uint8_t mode; |
| 984 | uint8_t smartps; |
| 985 | uint8_t bcn_time; /* 100ms increments */ |
| 986 | } __packed; |
| 987 | |
| 988 | #define R92E_CMD_KEEP_ALIVE 0x03 |
| 989 | #define R92E_CMD_SET_PWRMODE 0x20 |
| 990 | #define 0x42 |
| 991 | |
| 992 | /* Structure for R92E_CMD_KEEP_ALIVE. */ |
| 993 | struct r92e_fw_cmd_keepalive { |
| 994 | uint8_t mode; |
| 995 | uint8_t period; |
| 996 | } __packed; |
| 997 | |
| 998 | /* Structure for R92E_CMD_SET_PWRMODE. */ |
| 999 | struct r92e_fw_cmd_setpwrmode { |
| 1000 | uint8_t mode; |
| 1001 | #define FWMODE_ACTIVE 0 |
| 1002 | #define FWMODE_LOW_POWER 1 |
| 1003 | #define FWMODE_WMMPS 2 |
| 1004 | uint8_t smartps; |
| 1005 | #define SRTPS_LOW_POWER 0 |
| 1006 | #define SRTPS_POLL 0x10 |
| 1007 | #define SRTPS_WMMPS 0x20 |
| 1008 | uint8_t awake_int; /* 100ms increments. */ |
| 1009 | uint8_t all_queue_apsd; |
| 1010 | uint8_t pwr_state; |
| 1011 | #define PS_RFOFF 0x0 |
| 1012 | #define PS_RFON 0x4 |
| 1013 | #define PS_ALLON 0xc |
| 1014 | } __packed; |
| 1015 | |
| 1016 | /* Structure for R92E_CMD_RSSI_REPORT. */ |
| 1017 | struct { |
| 1018 | uint8_t ; |
| 1019 | uint8_t ; |
| 1020 | uint8_t ; |
| 1021 | uint8_t ; |
| 1022 | } __packed; |
| 1023 | |
| 1024 | /* |
| 1025 | * RTL8192CU ROM image. |
| 1026 | */ |
| 1027 | struct r92c_rom { |
| 1028 | uint16_t id; /* 0x8192 */ |
| 1029 | uint8_t reserved1[5]; |
| 1030 | uint8_t dbg_sel; |
| 1031 | uint16_t reserved2; |
| 1032 | uint16_t vid; |
| 1033 | uint16_t pid; |
| 1034 | uint8_t usb_opt; |
| 1035 | uint8_t ep_setting; |
| 1036 | uint16_t reserved3; |
| 1037 | uint8_t usb_phy; |
| 1038 | uint8_t reserved4[3]; |
| 1039 | uint8_t macaddr[6]; |
| 1040 | uint8_t string[61]; /* "Realtek" */ |
| 1041 | uint8_t subcustomer_id; |
| 1042 | uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; |
| 1043 | uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; |
| 1044 | uint8_t ht40_2s_tx_pwr_diff[3]; |
| 1045 | uint8_t ht20_tx_pwr_diff[3]; |
| 1046 | uint8_t ofdm_tx_pwr_diff[3]; |
| 1047 | uint8_t ht40_max_pwr[3]; |
| 1048 | uint8_t ht20_max_pwr[3]; |
| 1049 | uint8_t xtal_calib; |
| 1050 | uint8_t tssi[R92C_MAX_CHAINS]; |
| 1051 | uint8_t thermal_meter; |
| 1052 | uint8_t rf_opt1; |
| 1053 | #define R92C_ROM_RF1_REGULATORY_M 0x07 |
| 1054 | #define R92C_ROM_RF1_REGULATORY_S 0 |
| 1055 | #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 |
| 1056 | #define R92C_ROM_RF1_BOARD_TYPE_S 5 |
| 1057 | #define R92C_BOARD_TYPE_DONGLE 0 |
| 1058 | #define R92C_BOARD_TYPE_HIGHPA 1 |
| 1059 | #define R92C_BOARD_TYPE_MINICARD 2 |
| 1060 | #define R92C_BOARD_TYPE_SOLO 3 |
| 1061 | #define R92C_BOARD_TYPE_COMBO 4 |
| 1062 | |
| 1063 | uint8_t rf_opt2; |
| 1064 | uint8_t rf_opt3; |
| 1065 | uint8_t rf_opt4; |
| 1066 | uint8_t channel_plan; |
| 1067 | uint8_t version; |
| 1068 | uint8_t curstomer_id; |
| 1069 | } __packed; |
| 1070 | |
| 1071 | /* Rx MAC descriptor. */ |
| 1072 | struct r92c_rx_stat { |
| 1073 | uint32_t rxdw0; |
| 1074 | #define R92C_RXDW0_PKTLEN_M 0x00003fff |
| 1075 | #define R92C_RXDW0_PKTLEN_S 0 |
| 1076 | #define R92C_RXDW0_CRCERR 0x00004000 |
| 1077 | #define R92C_RXDW0_ICVERR 0x00008000 |
| 1078 | #define R92C_RXDW0_INFOSZ_M 0x000f0000 |
| 1079 | #define R92C_RXDW0_INFOSZ_S 16 |
| 1080 | #define R92C_RXDW0_QOS 0x00800000 |
| 1081 | #define R92C_RXDW0_SHIFT_M 0x03000000 |
| 1082 | #define R92C_RXDW0_SHIFT_S 24 |
| 1083 | #define R92C_RXDW0_PHYST 0x04000000 |
| 1084 | #define R92C_RXDW0_DECRYPTED 0x08000000 |
| 1085 | |
| 1086 | uint32_t rxdw1; |
| 1087 | uint32_t rxdw2; |
| 1088 | #define R92C_RXDW2_PKTCNT_M 0x00ff0000 |
| 1089 | #define R92C_RXDW2_PKTCNT_S 16 |
| 1090 | |
| 1091 | uint32_t rxdw3; |
| 1092 | #define R92C_RXDW3_RATE_M 0x0000003f |
| 1093 | #define R92C_RXDW3_RATE_S 0 |
| 1094 | #define R92C_RXDW3_HT 0x00000040 |
| 1095 | #define R92C_RXDW3_HTC 0x00000400 |
| 1096 | |
| 1097 | uint32_t rxdw4; |
| 1098 | uint32_t rxdw5; |
| 1099 | } __packed __aligned(4); |
| 1100 | |
| 1101 | /* Rx PHY descriptor. */ |
| 1102 | struct r92c_rx_phystat { |
| 1103 | uint32_t phydw0; |
| 1104 | uint32_t phydw1; |
| 1105 | uint32_t phydw2; |
| 1106 | uint32_t phydw3; |
| 1107 | uint32_t phydw4; |
| 1108 | uint32_t phydw5; |
| 1109 | uint32_t phydw6; |
| 1110 | uint32_t phydw7; |
| 1111 | } __packed __aligned(4); |
| 1112 | |
| 1113 | /* Rx PHY CCK descriptor. */ |
| 1114 | struct r92c_rx_cck { |
| 1115 | uint8_t adc_pwdb[4]; |
| 1116 | uint8_t sq_rpt; |
| 1117 | uint8_t agc_rpt; |
| 1118 | } __packed; |
| 1119 | |
| 1120 | struct r88e_rx_cck { |
| 1121 | uint8_t path_agc[2]; |
| 1122 | uint8_t sig_qual; |
| 1123 | uint8_t agc_rpt; |
| 1124 | uint8_t rpt_b; |
| 1125 | uint8_t reserved1; |
| 1126 | uint8_t noise_power; |
| 1127 | uint8_t path_cfotail[2]; |
| 1128 | uint8_t pcts_mask[2]; |
| 1129 | uint8_t stream_rxevm[2]; |
| 1130 | uint8_t path_rxsnr[2]; |
| 1131 | uint8_t noise_power_db_lsb; |
| 1132 | uint8_t reserved2[3]; |
| 1133 | uint8_t stream_csi[2]; |
| 1134 | uint8_t stream_target_csi[2]; |
| 1135 | uint8_t sig_evm; |
| 1136 | uint8_t reserved3; |
| 1137 | uint8_t reserved4; |
| 1138 | } __packed; |
| 1139 | |
| 1140 | /* Tx MAC descriptor. */ |
| 1141 | struct r92c_tx_desc { |
| 1142 | uint32_t txdw0; |
| 1143 | #define R92C_TXDW0_PKTLEN_M 0x0000ffff |
| 1144 | #define R92C_TXDW0_PKTLEN_S 0 |
| 1145 | #define R92C_TXDW0_OFFSET_M 0x00ff0000 |
| 1146 | #define R92C_TXDW0_OFFSET_S 16 |
| 1147 | #define R92C_TXDW0_BMCAST 0x01000000 |
| 1148 | #define R92C_TXDW0_LSG 0x04000000 |
| 1149 | #define R92C_TXDW0_FSG 0x08000000 |
| 1150 | #define R92C_TXDW0_OWN 0x80000000 |
| 1151 | |
| 1152 | uint32_t txdw1; |
| 1153 | #define R92C_TXDW1_MACID_M 0x0000001f |
| 1154 | #define R92C_TXDW1_MACID_S 0 |
| 1155 | #define R88E_TXDW1_MACID_M 0x0000003f |
| 1156 | #define R88E_TXDW1_MACID_S 0 |
| 1157 | #define R92C_TXDW1_AGGEN 0x00000020 |
| 1158 | #define R92C_TXDW1_AGGBK 0x00000040 |
| 1159 | #define R92C_TXDW1_QSEL_M 0x00001f00 |
| 1160 | #define R92C_TXDW1_QSEL_S 8 |
| 1161 | #define R92C_TXDW1_QSEL_BE 0x00 |
| 1162 | #define R92C_TXDW1_QSEL_MGNT 0x12 |
| 1163 | #define R92C_TXDW1_RAID_M 0x000f0000 |
| 1164 | #define R92C_TXDW1_RAID_S 16 |
| 1165 | #define R92C_TXDW1_CIPHER_M 0x00c00000 |
| 1166 | #define R92C_TXDW1_CIPHER_S 22 |
| 1167 | #define R92C_TXDW1_CIPHER_NONE 0 |
| 1168 | #define R92C_TXDW1_CIPHER_RC4 1 |
| 1169 | #define R92C_TXDW1_CIPHER_AES 3 |
| 1170 | #define R92C_TXDW1_PKTOFF_M 0x7c000000 |
| 1171 | #define R92C_TXDW1_PKTOFF_S 26 |
| 1172 | |
| 1173 | uint32_t txdw2; |
| 1174 | #define R88E_TXDW2_AGGBK 0x00010000 |
| 1175 | |
| 1176 | uint16_t txdw3; |
| 1177 | #define R92E_TXDW3_AGGBK 0x00000100 |
| 1178 | uint16_t txdseq; |
| 1179 | #define R92C_HWSEQ_EN 0x00008000 |
| 1180 | |
| 1181 | uint32_t txdw4; |
| 1182 | #define R92C_TXDW4_RTSRATE_M 0x0000003f |
| 1183 | #define R92C_TXDW4_RTSRATE_S 0 |
| 1184 | #define R92C_TXDW4_QOS 0x00000040 |
| 1185 | #define R92C_TXDW4_HWSEQ 0x00000080 |
| 1186 | #define R92C_TXDW4_DRVRATE 0x00000100 |
| 1187 | #define R92C_TXDW4_CTS2SELF 0x00000800 |
| 1188 | #define R92C_TXDW4_RTSEN 0x00001000 |
| 1189 | #define R92C_TXDW4_HWRTSEN 0x00002000 |
| 1190 | #define R92C_TXDW4_SCO_M 0x003f0000 |
| 1191 | #define R92C_TXDW4_SCO_S 20 |
| 1192 | #define R92C_TXDW4_SCO_SCA 1 |
| 1193 | #define R92C_TXDW4_SCO_SCB 2 |
| 1194 | #define R92C_TXDW4_40MHZ 0x02000000 |
| 1195 | |
| 1196 | uint32_t txdw5; |
| 1197 | #define R92C_TXDW5_DATARATE_M 0x0000003f |
| 1198 | #define R92C_TXDW5_DATARATE_S 0 |
| 1199 | #define R92C_TXDW5_SGI 0x00000040 |
| 1200 | #define R92C_TXDW5_AGGNUM_M 0xff000000 |
| 1201 | #define R92C_TXDW5_AGGNUM_S 24 |
| 1202 | |
| 1203 | uint32_t txdw6; |
| 1204 | uint16_t txdsum; |
| 1205 | uint16_t pad; |
| 1206 | uint32_t txdw7; |
| 1207 | uint16_t txdseq2; |
| 1208 | #define R92E_HWSEQ_SHIFT 11 |
| 1209 | #define R92E_HWSEQ_MASK 0x00000fffff |
| 1210 | |
| 1211 | uint16_t txdw8; |
| 1212 | } __packed __aligned(4); |
| 1213 | #define R92E_RF_T_METER 0x042 |
| 1214 | #define R92E_STBC_SETTING 0x04c4 |
| 1215 | #define R92E_SYS_CFG1_8192E 0x00f0 |
| 1216 | #define R92E_LDO_SWR_CTRL 0x007C |
| 1217 | #define R92E_AUTO_LLT 0x224 |
| 1218 | #define R92E_AUTO_LLT_EN __BIT(16) |
| 1219 | #define R92E_RSV_MIO_EN 0x0100 |
| 1220 | #define R92E_LEDSON 0x60 |
| 1221 | |
| 1222 | /* Bits for SYS_CFG1_8192E. */ |
| 1223 | #define R92E_SPSLDO_SEL __BIT(24) |
| 1224 | |
| 1225 | /* Values for R92C_CMD_USB_SUSPEND. */ |
| 1226 | #define USB_RESUME 0 |
| 1227 | #define USB_SLEEP 1 |
| 1228 | |
| 1229 | /* Values for IQ calibration. */ |
| 1230 | #define R92C_IQK_TRXPATHENA 0x5600 |
| 1231 | #define R92C_IQK_TRMUXPAR 0x00e4 |
| 1232 | #define R92C_IQK_RFIFACESW1 0x8200 |
| 1233 | #define R92C_IQK_LSSI_PARAM 0x00010000 |
| 1234 | #define R92C_IQK_LSSI_RESTORE 0x00032ed3 |
| 1235 | #define R92C_IQK_CONFIG_ANT 0x00080000 |
| 1236 | #define R92C_TX_IQK_SETTING 0x01007c00 |
| 1237 | #define R92C_RX_IQK_SETTING 0x01004800 |
| 1238 | #define R92C_FPGA0_IQK_SETTING 0x80800000 |
| 1239 | |