| 1 | /* $NetBSD: nouveau_engine_graph_ctxnvd7.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2013 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs <bskeggs@redhat.com> |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_ctxnvd7.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $" ); |
| 29 | |
| 30 | #include "ctxnvc0.h" |
| 31 | |
| 32 | /******************************************************************************* |
| 33 | * PGRAPH context register lists |
| 34 | ******************************************************************************/ |
| 35 | |
| 36 | static const struct nvc0_graph_init |
| 37 | nvd7_grctx_init_ds_0[] = { |
| 38 | { 0x405800, 1, 0x04, 0x0f8000bf }, |
| 39 | { 0x405830, 1, 0x04, 0x02180324 }, |
| 40 | { 0x405834, 1, 0x04, 0x08000000 }, |
| 41 | { 0x405838, 1, 0x04, 0x00000000 }, |
| 42 | { 0x405854, 1, 0x04, 0x00000000 }, |
| 43 | { 0x405870, 4, 0x04, 0x00000001 }, |
| 44 | { 0x405a00, 2, 0x04, 0x00000000 }, |
| 45 | { 0x405a18, 1, 0x04, 0x00000000 }, |
| 46 | {} |
| 47 | }; |
| 48 | |
| 49 | static const struct nvc0_graph_init |
| 50 | nvd7_grctx_init_pd_0[] = { |
| 51 | { 0x406020, 1, 0x04, 0x000103c1 }, |
| 52 | { 0x406028, 4, 0x04, 0x00000001 }, |
| 53 | { 0x4064a8, 1, 0x04, 0x00000000 }, |
| 54 | { 0x4064ac, 1, 0x04, 0x00003fff }, |
| 55 | { 0x4064b4, 3, 0x04, 0x00000000 }, |
| 56 | { 0x4064c0, 1, 0x04, 0x801a0078 }, |
| 57 | { 0x4064c4, 1, 0x04, 0x00c9ffff }, |
| 58 | { 0x4064d0, 8, 0x04, 0x00000000 }, |
| 59 | {} |
| 60 | }; |
| 61 | |
| 62 | static const struct nvc0_graph_pack |
| 63 | nvd7_grctx_pack_hub[] = { |
| 64 | { nvc0_grctx_init_main_0 }, |
| 65 | { nvd9_grctx_init_fe_0 }, |
| 66 | { nvc0_grctx_init_pri_0 }, |
| 67 | { nvc0_grctx_init_memfmt_0 }, |
| 68 | { nvd7_grctx_init_ds_0 }, |
| 69 | { nvd7_grctx_init_pd_0 }, |
| 70 | { nvc0_grctx_init_rstr2d_0 }, |
| 71 | { nvc0_grctx_init_scc_0 }, |
| 72 | { nvd9_grctx_init_be_0 }, |
| 73 | {} |
| 74 | }; |
| 75 | |
| 76 | static const struct nvc0_graph_init |
| 77 | nvd7_grctx_init_setup_0[] = { |
| 78 | { 0x418800, 1, 0x04, 0x7006860a }, |
| 79 | { 0x418808, 3, 0x04, 0x00000000 }, |
| 80 | { 0x418828, 1, 0x04, 0x00008442 }, |
| 81 | { 0x418830, 1, 0x04, 0x10000001 }, |
| 82 | { 0x4188d8, 1, 0x04, 0x00000008 }, |
| 83 | { 0x4188e0, 1, 0x04, 0x01000000 }, |
| 84 | { 0x4188e8, 5, 0x04, 0x00000000 }, |
| 85 | { 0x4188fc, 1, 0x04, 0x20100018 }, |
| 86 | {} |
| 87 | }; |
| 88 | |
| 89 | static const struct nvc0_graph_pack |
| 90 | nvd7_grctx_pack_gpc[] = { |
| 91 | { nvc0_grctx_init_gpc_unk_0 }, |
| 92 | { nvd9_grctx_init_prop_0 }, |
| 93 | { nvd9_grctx_init_gpc_unk_1 }, |
| 94 | { nvd7_grctx_init_setup_0 }, |
| 95 | { nvc0_grctx_init_zcull_0 }, |
| 96 | { nvd9_grctx_init_crstr_0 }, |
| 97 | { nvc1_grctx_init_gpm_0 }, |
| 98 | { nvc0_grctx_init_gcc_0 }, |
| 99 | {} |
| 100 | }; |
| 101 | |
| 102 | const struct nvc0_graph_init |
| 103 | nvd7_grctx_init_pe_0[] = { |
| 104 | { 0x419848, 1, 0x04, 0x00000000 }, |
| 105 | { 0x419864, 1, 0x04, 0x00000129 }, |
| 106 | { 0x419888, 1, 0x04, 0x00000000 }, |
| 107 | {} |
| 108 | }; |
| 109 | |
| 110 | static const struct nvc0_graph_init |
| 111 | nvd7_grctx_init_tex_0[] = { |
| 112 | { 0x419a00, 1, 0x04, 0x000001f0 }, |
| 113 | { 0x419a04, 1, 0x04, 0x00000001 }, |
| 114 | { 0x419a08, 1, 0x04, 0x00000023 }, |
| 115 | { 0x419a0c, 1, 0x04, 0x00020000 }, |
| 116 | { 0x419a10, 1, 0x04, 0x00000000 }, |
| 117 | { 0x419a14, 1, 0x04, 0x00000200 }, |
| 118 | { 0x419a1c, 1, 0x04, 0x00008000 }, |
| 119 | { 0x419a20, 1, 0x04, 0x00000800 }, |
| 120 | { 0x419ac4, 1, 0x04, 0x0017f440 }, |
| 121 | {} |
| 122 | }; |
| 123 | |
| 124 | static const struct nvc0_graph_init |
| 125 | nvd7_grctx_init_mpc_0[] = { |
| 126 | { 0x419c00, 1, 0x04, 0x0000000a }, |
| 127 | { 0x419c04, 1, 0x04, 0x00000006 }, |
| 128 | { 0x419c08, 1, 0x04, 0x00000002 }, |
| 129 | { 0x419c20, 1, 0x04, 0x00000000 }, |
| 130 | { 0x419c24, 1, 0x04, 0x00084210 }, |
| 131 | { 0x419c28, 1, 0x04, 0x3efbefbe }, |
| 132 | {} |
| 133 | }; |
| 134 | |
| 135 | static const struct nvc0_graph_pack |
| 136 | nvd7_grctx_pack_tpc[] = { |
| 137 | { nvd7_grctx_init_pe_0 }, |
| 138 | { nvd7_grctx_init_tex_0 }, |
| 139 | { nvd7_grctx_init_mpc_0 }, |
| 140 | { nvc4_grctx_init_l1c_0 }, |
| 141 | { nvd9_grctx_init_sm_0 }, |
| 142 | {} |
| 143 | }; |
| 144 | |
| 145 | static const struct nvc0_graph_init |
| 146 | nvd7_grctx_init_pes_0[] = { |
| 147 | { 0x41be24, 1, 0x04, 0x00000002 }, |
| 148 | {} |
| 149 | }; |
| 150 | |
| 151 | static const struct nvc0_graph_init |
| 152 | nvd7_grctx_init_cbm_0[] = { |
| 153 | { 0x41bec0, 1, 0x04, 0x12180000 }, |
| 154 | { 0x41bec4, 1, 0x04, 0x00003fff }, |
| 155 | { 0x41bee4, 1, 0x04, 0x03240218 }, |
| 156 | {} |
| 157 | }; |
| 158 | |
| 159 | const struct nvc0_graph_init |
| 160 | nvd7_grctx_init_wwdx_0[] = { |
| 161 | { 0x41bf00, 1, 0x04, 0x0a418820 }, |
| 162 | { 0x41bf04, 1, 0x04, 0x062080e6 }, |
| 163 | { 0x41bf08, 1, 0x04, 0x020398a4 }, |
| 164 | { 0x41bf0c, 1, 0x04, 0x0e629062 }, |
| 165 | { 0x41bf10, 1, 0x04, 0x0a418820 }, |
| 166 | { 0x41bf14, 1, 0x04, 0x000000e6 }, |
| 167 | { 0x41bfd0, 1, 0x04, 0x00900103 }, |
| 168 | { 0x41bfe0, 1, 0x04, 0x00400001 }, |
| 169 | { 0x41bfe4, 1, 0x04, 0x00000000 }, |
| 170 | {} |
| 171 | }; |
| 172 | |
| 173 | static const struct nvc0_graph_pack |
| 174 | nvd7_grctx_pack_ppc[] = { |
| 175 | { nvd7_grctx_init_pes_0 }, |
| 176 | { nvd7_grctx_init_cbm_0 }, |
| 177 | { nvd7_grctx_init_wwdx_0 }, |
| 178 | {} |
| 179 | }; |
| 180 | |
| 181 | /******************************************************************************* |
| 182 | * PGRAPH context implementation |
| 183 | ******************************************************************************/ |
| 184 | |
| 185 | static void |
| 186 | nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) |
| 187 | { |
| 188 | u32 magic[GPC_MAX][2]; |
| 189 | u32 offset; |
| 190 | int gpc; |
| 191 | |
| 192 | mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); |
| 193 | mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); |
| 194 | mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); |
| 195 | mmio_list(0x40800c, 0x00000000, 8, 1); |
| 196 | mmio_list(0x408010, 0x80000000, 0, 0); |
| 197 | mmio_list(0x419004, 0x00000000, 8, 1); |
| 198 | mmio_list(0x419008, 0x00000000, 0, 0); |
| 199 | mmio_list(0x408004, 0x00000000, 8, 0); |
| 200 | mmio_list(0x408008, 0x80000018, 0, 0); |
| 201 | mmio_list(0x418808, 0x00000000, 8, 0); |
| 202 | mmio_list(0x41880c, 0x80000018, 0, 0); |
| 203 | mmio_list(0x418810, 0x80000000, 12, 2); |
| 204 | mmio_list(0x419848, 0x10000000, 12, 2); |
| 205 | |
| 206 | mmio_list(0x405830, 0x02180324, 0, 0); |
| 207 | mmio_list(0x4064c4, 0x00c9ffff, 0, 0); |
| 208 | |
| 209 | for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { |
| 210 | u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; |
| 211 | u16 magic1 = 0x0324 * priv->tpc_nr[gpc]; |
| 212 | magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; |
| 213 | magic[gpc][1] = 0x00000000 | (magic1 << 16); |
| 214 | offset += 0x0324 * priv->tpc_nr[gpc]; |
| 215 | } |
| 216 | |
| 217 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
| 218 | mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); |
| 219 | mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); |
| 220 | offset += 0x07ff * priv->tpc_nr[gpc]; |
| 221 | } |
| 222 | mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */ |
| 223 | } |
| 224 | |
| 225 | static void |
| 226 | nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) |
| 227 | { |
| 228 | struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; |
| 229 | int i; |
| 230 | |
| 231 | nv_mask(priv, 0x000260, 0x00000001, 0x00000000); |
| 232 | |
| 233 | nvc0_graph_mmio(priv, oclass->hub); |
| 234 | nvc0_graph_mmio(priv, oclass->gpc); |
| 235 | nvc0_graph_mmio(priv, oclass->zcull); |
| 236 | nvc0_graph_mmio(priv, oclass->tpc); |
| 237 | nvc0_graph_mmio(priv, oclass->ppc); |
| 238 | |
| 239 | nv_wr32(priv, 0x404154, 0x00000000); |
| 240 | |
| 241 | oclass->mods(priv, info); |
| 242 | oclass->unkn(priv); |
| 243 | |
| 244 | nvc0_grctx_generate_tpcid(priv); |
| 245 | nvc0_grctx_generate_r406028(priv); |
| 246 | nvc0_grctx_generate_r4060a8(priv); |
| 247 | nve4_grctx_generate_r418bb8(priv); |
| 248 | nvc0_grctx_generate_r406800(priv); |
| 249 | |
| 250 | for (i = 0; i < 8; i++) |
| 251 | nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); |
| 252 | |
| 253 | nvc0_graph_icmd(priv, oclass->icmd); |
| 254 | nv_wr32(priv, 0x404154, 0x00000400); |
| 255 | nvc0_graph_mthd(priv, oclass->mthd); |
| 256 | nv_mask(priv, 0x000260, 0x00000001, 0x00000001); |
| 257 | } |
| 258 | |
| 259 | struct nouveau_oclass * |
| 260 | nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { |
| 261 | .base.handle = NV_ENGCTX(GR, 0xd7), |
| 262 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 263 | .ctor = nvc0_graph_context_ctor, |
| 264 | .dtor = nvc0_graph_context_dtor, |
| 265 | .init = _nouveau_graph_context_init, |
| 266 | .fini = _nouveau_graph_context_fini, |
| 267 | .rd32 = _nouveau_graph_context_rd32, |
| 268 | .wr32 = _nouveau_graph_context_wr32, |
| 269 | }, |
| 270 | .main = nvd7_grctx_generate_main, |
| 271 | .mods = nvd7_grctx_generate_mods, |
| 272 | .unkn = nve4_grctx_generate_unkn, |
| 273 | .hub = nvd7_grctx_pack_hub, |
| 274 | .gpc = nvd7_grctx_pack_gpc, |
| 275 | .zcull = nvc0_grctx_pack_zcull, |
| 276 | .tpc = nvd7_grctx_pack_tpc, |
| 277 | .ppc = nvd7_grctx_pack_ppc, |
| 278 | .icmd = nvd9_grctx_pack_icmd, |
| 279 | .mthd = nvd9_grctx_pack_mthd, |
| 280 | }.base; |
| 281 | |