| 1 | /* $NetBSD: hdaudioreg.h,v 1.1 2015/03/28 14:09:59 jmcneill Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2009 Precedence Technologies Ltd <support@precedence.co.uk> |
| 5 | * Copyright (c) 2009 Jared D. McNeill <jmcneill@invisible.ca> |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * This code is derived from software contributed to The NetBSD Foundation |
| 9 | * by Precedence Technologies Ltd |
| 10 | * |
| 11 | * Redistribution and use in source and binary forms, with or without |
| 12 | * modification, are permitted provided that the following conditions |
| 13 | * are met: |
| 14 | * 1. Redistributions of source code must retain the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer. |
| 16 | * 2. The name of the author may not be used to endorse or promote products |
| 17 | * derived from this software without specific prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 24 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 26 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #ifndef _HDAUDIOREG_H |
| 33 | #define _HDAUDIOREG_H |
| 34 | |
| 35 | /* |
| 36 | * High Definition Audio Audio PCI Configuration Space |
| 37 | */ |
| 38 | #define HDAUDIO_PCI_AZBARL 0x10 |
| 39 | #define HDAUDIO_PCI_AZBARU 0x14 |
| 40 | #define HDAUDIO_PCI_AZCTL 0x40 |
| 41 | #define HDAUDIO_PCI_TCSEL 0x44 |
| 42 | |
| 43 | /* |
| 44 | * High Definition Audio Memory Mapped Configuration Registers |
| 45 | */ |
| 46 | #define HDAUDIO_MMIO_GCAP 0x000 |
| 47 | #define HDAUDIO_GCAP_64OK(x) ((x) & 1) |
| 48 | #define HDAUDIO_GCAP_NSDO(x) ((((x) & 6) != 0) ? ((x) & 6) : 1) |
| 49 | #define HDAUDIO_GCAP_BSS(x) (((x) >> 3) & 0x1f) |
| 50 | #define HDAUDIO_GCAP_ISS(x) (((x) >> 8) & 0x0f) |
| 51 | #define HDAUDIO_GCAP_OSS(x) (((x) >> 12) & 0x0f) |
| 52 | #define HDAUDIO_MMIO_VMIN 0x002 |
| 53 | #define HDAUDIO_MMIO_VMAJ 0x003 |
| 54 | #define HDAUDIO_MMIO_OUTPAY 0x004 |
| 55 | #define HDAUDIO_MMIO_INPAY 0x006 |
| 56 | #define HDAUDIO_MMIO_GCTL 0x008 |
| 57 | #define HDAUDIO_GCTL_UNSOL_EN (1 << 8) |
| 58 | #define HDAUDIO_GCTL_FLUSH_CTL (1 << 1) |
| 59 | #define HDAUDIO_GCTL_CRST (1 << 0) |
| 60 | #define HDAUDIO_MMIO_WAKEEN 0x00c |
| 61 | #define HDAUDIO_MMIO_STATESTS 0x00e |
| 62 | #define HDAUDIO_STATESTS_SDIWAKE 0x7fff |
| 63 | #define HDAUDIO_MMIO_GSTS 0x010 |
| 64 | #define HDAUDIO_MMIO_INTCTL 0x020 |
| 65 | #define HDAUDIO_INTCTL_GIE (1 << 31) |
| 66 | #define HDAUDIO_INTCTL_CIE (1 << 30) |
| 67 | #define HDAUDIO_MMIO_INTSTS 0x024 |
| 68 | #define HDAUDIO_INTSTS_GIS (1 << 31) |
| 69 | #define HDAUDIO_INTSTS_CIS (1 << 30) |
| 70 | #define HDAUDIO_INTSTS_SIS_MASK 0x3fffffff |
| 71 | #define HDAUDIO_MMIO_WALCLK 0x030 |
| 72 | #define HDAUDIO_MMIO_SYNC 0x034 |
| 73 | #define HDAUDIO_MMIO_CORBLBASE 0x040 |
| 74 | #define HDAUDIO_MMIO_CORBUBASE 0x044 |
| 75 | #define HDAUDIO_MMIO_CORBWP 0x048 |
| 76 | #define HDAUDIO_MMIO_CORBRP 0x04a |
| 77 | #define HDAUDIO_CORBRP_RP_RESET (1 << 15) |
| 78 | #define HDAUDIO_MMIO_CORBCTL 0x04c |
| 79 | #define HDAUDIO_CORBCTL_RUN (1 << 1) |
| 80 | #define HDAUDIO_CORBCTL_CMEI_EN (1 << 0) |
| 81 | #define HDAUDIO_MMIO_CORBST 0x04d |
| 82 | #define HDAUDIO_MMIO_CORBSIZE 0x04e |
| 83 | #define HDAUDIO_MMIO_RIRBLBASE 0x050 |
| 84 | #define HDAUDIO_MMIO_RIRBUBASE 0x054 |
| 85 | #define HDAUDIO_MMIO_RIRBWP 0x058 |
| 86 | #define HDAUDIO_RIRBWP_WP_RESET (1 << 15) |
| 87 | #define HDAUDIO_MMIO_RINTCNT 0x05a |
| 88 | #define HDAUDIO_MMIO_RIRBCTL 0x05c |
| 89 | #define HDAUDIO_RIRBCTL_ROI_EN (1 << 2) |
| 90 | #define HDAUDIO_RIRBCTL_RUN (1 << 1) |
| 91 | #define HDAUDIO_RIRBCTL_INT_EN (1 << 0) |
| 92 | #define HDAUDIO_MMIO_RIRBSTS 0x05d |
| 93 | #define HDAUDIO_RIRBSTS_RIRBOIS (1 << 2) |
| 94 | #define HDAUDIO_RIRBSTS_RINTFL (1 << 0) |
| 95 | #define HDAUDIO_MMIO_RIRBSIZE 0x05e |
| 96 | #define HDAUDIO_MMIO_IC 0x060 |
| 97 | #define HDAUDIO_MMIO_IR 0x064 |
| 98 | #define HDAUDIO_MMIO_IRS 0x068 |
| 99 | #define HDAUDIO_MMIO_DPLBASE 0x070 |
| 100 | #define HDAUDIO_MMIO_DPUBASE 0x074 |
| 101 | |
| 102 | #define HDAUDIO_MMIO_SD_SIZE 0x20 |
| 103 | #define HDAUDIO_MMIO_SD_BASE 0x080 |
| 104 | |
| 105 | #define HDAUDIO_SD_REG(off, x) \ |
| 106 | (HDAUDIO_MMIO_SD_BASE + ((x) * HDAUDIO_MMIO_SD_SIZE) + (off)) |
| 107 | #define HDAUDIO_SD_CTL0(x) HDAUDIO_SD_REG(0x00, x) |
| 108 | #define HDAUDIO_CTL_SRST (1 << 0) |
| 109 | #define HDAUDIO_CTL_RUN (1 << 1) |
| 110 | #define HDAUDIO_CTL_IOCE (1 << 2) |
| 111 | #define HDAUDIO_CTL_FEIE (1 << 3) |
| 112 | #define HDAUDIO_CTL_DEIE (1 << 4) |
| 113 | #define HDAUDIO_SD_CTL1(x) HDAUDIO_SD_REG(0x01, x) |
| 114 | #define HDAUDIO_SD_CTL2(x) HDAUDIO_SD_REG(0x02, x) |
| 115 | #define HDAUDIO_SD_STS(x) HDAUDIO_SD_REG(0x03, x) |
| 116 | #define HDAUDIO_STS_FIFORDY (1 << 5) |
| 117 | #define HDAUDIO_STS_DESE (1 << 4) |
| 118 | #define HDAUDIO_STS_FIFOE (1 << 3) |
| 119 | #define HDAUDIO_STS_BCIS (1 << 2) |
| 120 | #define HDAUDIO_SD_LPIB(x) HDAUDIO_SD_REG(0x04, x) |
| 121 | #define HDAUDIO_SD_CBL(x) HDAUDIO_SD_REG(0x08, x) |
| 122 | #define HDAUDIO_SD_LVI(x) HDAUDIO_SD_REG(0x0c, x) |
| 123 | #define HDAUDIO_SD_FIFOW(x) HDAUDIO_SD_REG(0x0e, x) |
| 124 | #define HDAUDIO_SD_FIFOS(x) HDAUDIO_SD_REG(0x10, x) |
| 125 | #define HDAUDIO_SD_FMT(x) HDAUDIO_SD_REG(0x12, x) |
| 126 | #define HDAUDIO_FMT_TYPE_MASK 0x8000 |
| 127 | #define HDAUDIO_FMT_TYPE_PCM 0x0000 |
| 128 | #define HDAUDIO_FMT_TYPE_NONPCM 0x8000 |
| 129 | #define HDAUDIO_FMT_BASE_MASK 0x4000 |
| 130 | #define HDAUDIO_FMT_BASE_48 0x0000 |
| 131 | #define HDAUDIO_FMT_BASE_44 0x4000 |
| 132 | #define HDAUDIO_FMT_MULT_MASK 0x3800 |
| 133 | #define HDAUDIO_FMT_MULT(x) ((((x) - 1) << 11) & HDAUDIO_FMT_MULT_MASK) |
| 134 | #define HDAUDIO_FMT_DIV_MASK 0x0700 |
| 135 | #define HDAUDIO_FMT_DIV(x) ((((x) - 1) << 8) & HDAUDIO_FMT_DIV_MASK) |
| 136 | #define HDAUDIO_FMT_BITS_MASK 0x0070 |
| 137 | #define HDAUDIO_FMT_BITS_8_16 (0 << 4) |
| 138 | #define HDAUDIO_FMT_BITS_16_16 (1 << 4) |
| 139 | #define HDAUDIO_FMT_BITS_20_32 (2 << 4) |
| 140 | #define HDAUDIO_FMT_BITS_24_32 (3 << 4) |
| 141 | #define HDAUDIO_FMT_BITS_32_32 (4 << 4) |
| 142 | #define HDAUDIO_FMT_CHAN_MASK 0x000f |
| 143 | #define HDAUDIO_FMT_CHAN(x) (((x) - 1) & HDAUDIO_FMT_CHAN_MASK) |
| 144 | #define HDAUDIO_SD_BDPL(x) HDAUDIO_SD_REG(0x18, x) |
| 145 | #define HDAUDIO_SD_BDPU(x) HDAUDIO_SD_REG(0x1c, x) |
| 146 | |
| 147 | /* |
| 148 | * Codec Parameters and Controls |
| 149 | */ |
| 150 | #define CORB_GET_PARAMETER 0xf00 |
| 151 | #define COP_VENDOR_ID 0x00 |
| 152 | #define COP_REVISION_ID 0x02 |
| 153 | #define COP_SUBORDINATE_NODE_COUNT 0x04 |
| 154 | #define COP_NODECNT_STARTNODE(x) (((x) >> 16) & 0xff) |
| 155 | #define COP_NODECNT_NUMNODES(x) (((x) >> 0) & 0xff) |
| 156 | #define COP_FUNCTION_GROUP_TYPE 0x05 |
| 157 | #define COP_AUDIO_FUNCTION_GROUP_CAPABILITIES 0x08 |
| 158 | #define COP_AUDIO_WIDGET_CAPABILITIES 0x09 |
| 159 | #define COP_AWCAP_CHANNEL_COUNT(x) \ |
| 160 | (((((x) & (0x7 << 13)) >> 12) | ((x) & 0x1)) + 1) |
| 161 | #define COP_AWCAP_INAMP_PRESENT (1 << 1) |
| 162 | #define COP_AWCAP_OUTAMP_PRESENT (1 << 2) |
| 163 | #define COP_AWCAP_AMP_PARAM_OVERRIDE (1 << 3) |
| 164 | #define COP_AWCAP_FORMAT_OVERRIDE (1 << 4) |
| 165 | #define COP_AWCAP_STRIPE (1 << 5) |
| 166 | #define COP_AWCAP_PROC_WIDGET (1 << 6) |
| 167 | #define COP_AWCAP_UNSOL_CAPABLE (1 << 7) |
| 168 | #define COP_AWCAP_CONN_LIST (1 << 8) |
| 169 | #define COP_AWCAP_DIGITAL (1 << 9) |
| 170 | #define COP_AWCAP_POWER_CNTRL (1 << 10) |
| 171 | #define COP_AWCAP_LR_SWAP (1 << 11) |
| 172 | #define COP_AWCAP_CP_CAPS (1 << 12) |
| 173 | #define COP_AWCAP_CHAN_COUNT_EXT(x) (((x) >> 13) & 0x7) |
| 174 | #define COP_AWCAP_DELAY(x) (((x) >> 16) & 0xf) |
| 175 | #define COP_AWCAP_TYPE(x) (((x) >> 20) & 0xf) |
| 176 | #define COP_AWCAP_TYPE_MASK 0x00f00000 |
| 177 | #define COP_AWCAP_TYPE_SHIFT 20 |
| 178 | #define COP_AWCAP_TYPE_AUDIO_OUTPUT 0x0 |
| 179 | #define COP_AWCAP_TYPE_AUDIO_INPUT 0x1 |
| 180 | #define COP_AWCAP_TYPE_AUDIO_MIXER 0x2 |
| 181 | #define COP_AWCAP_TYPE_AUDIO_SELECTOR 0x3 |
| 182 | #define COP_AWCAP_TYPE_PIN_COMPLEX 0x4 |
| 183 | #define COP_AWCAP_TYPE_POWER_WIDGET 0x5 |
| 184 | #define COP_AWCAP_TYPE_VOLUME_KNOB 0x6 |
| 185 | #define COP_AWCAP_TYPE_BEEP_GENERATOR 0x7 |
| 186 | #define COP_AWCAP_TYPE_VENDOR_DEFINED 0xf |
| 187 | #define COP_SUPPORTED_PCM_SIZE_RATES 0x0a |
| 188 | #define COP_SUPPORTED_STREAM_FORMATS 0x0b |
| 189 | #define COP_STREAM_FORMAT_PCM (1 << 0) |
| 190 | #define COP_STREAM_FORMAT_FLOAT32 (1 << 1) |
| 191 | #define COP_STREAM_FORMAT_AC3 (1 << 2) |
| 192 | #define COP_PIN_CAPABILITIES 0x0c |
| 193 | #define COP_PINCAP_IMPEDANCE_SENSE_CAPABLE (1 << 0) |
| 194 | #define COP_PINCAP_TRIGGER_REQD (1 << 1) |
| 195 | #define COP_PINCAP_PRESENSE_DETECT_CAPABLE (1 << 2) |
| 196 | #define COP_PINCAP_HEADPHONE_DRIVE_CAPABLE (1 << 3) |
| 197 | #define COP_PINCAP_OUTPUT_CAPABLE (1 << 4) |
| 198 | #define COP_PINCAP_INPUT_CAPABLE (1 << 5) |
| 199 | #define COP_PINCAP_BALANCED_IO_PINS (1 << 6) |
| 200 | #define COP_PINCAP_HDMI (1 << 7) |
| 201 | #define COP_PINCAP_VREF_CONTROL(x) (((x) >> 8) & 0xff) |
| 202 | #define COP_VREF_HIZ (1 << 0) |
| 203 | #define COP_VREF_50 (1 << 1) |
| 204 | #define COP_VREF_GROUND (1 << 2) |
| 205 | #define COP_VREF_80 (1 << 4) |
| 206 | #define COP_VREF_100 (1 << 5) |
| 207 | #define COP_PINCAP_EAPD_CAPABLE (1 << 16) |
| 208 | #define COP_PINCAP_DP (1 << 24) |
| 209 | #define COP_PINCAP_HBR (1 << 27) |
| 210 | #define COP_AMPLIFIER_CAPABILITIES_INAMP 0x0d |
| 211 | #define COP_AMPLIFIER_CAPABILITIES_OUTAMP 0x12 |
| 212 | #define COP_AMPCAP_OFFSET(x) (((x) >> 0) & 0x7f) |
| 213 | #define COP_AMPCAP_NUM_STEPS(x) (((x) >> 8) & 0x7f) |
| 214 | #define COP_AMPCAP_STEP_SIZE(x) (((x) >> 16) & 0x7f) |
| 215 | #define COP_AMPCAP_MUTE_CAPABLE(x) (((x) >> 31) & 0x1) |
| 216 | #define COP_CONNECTION_LIST_LENGTH 0x0e |
| 217 | #define COP_CONNECTION_LIST_LENGTH_LEN(x) ((x) & 0x7f) |
| 218 | #define COP_CONNECTION_LIST_LENGTH_LONG_FORM (1 << 7) |
| 219 | #define COP_SUPPORTED_POWER_STATES 0x0f |
| 220 | #define COP_PROCESSING_CAPABILITIES 0x10 |
| 221 | #define COP_GPIO_COUNT 0x11 |
| 222 | #define COP_GPIO_COUNT_NUM_GPIO(x) ((x) & 0xff) |
| 223 | #define COP_VOLUME_KNOB_CAPABILITIES 0x13 |
| 224 | #define COP_HDMI_LPCM_CAD 0x20 |
| 225 | #define COP_LPCM_CAD_44_1_MS (1 << 31) |
| 226 | #define COP_LPCM_CAD_44_1 (1 << 30) |
| 227 | #define COP_LPCM_CAD_192K_24BIT (1 << 29) |
| 228 | #define COP_LPCM_CAD_192K_20BIT (1 << 28) |
| 229 | #define COP_LPCM_CAD_192K_MAXCHAN(x) (((x) >> 24) & 0xf) |
| 230 | #define COP_LPCM_CAD_192K_MAXCHAN_CP(x) (((x) >> 20) & 0xf) |
| 231 | #define COP_LPCM_CAD_96K_24BIT (1 << 19) |
| 232 | #define COP_LPCM_CAD_96K_20BIT (1 << 18) |
| 233 | #define COP_LPCM_CAD_96K_MAXCHAN(x) (((x) >> 14) & 0xf) |
| 234 | #define COP_LPCM_CAD_96K_MAXCHAN_CP(x) (((x) >> 10) & 0xf) |
| 235 | #define COP_LPCM_CAD_48K_24BIT (1 << 9) |
| 236 | #define COP_LPCM_CAD_48K_20BIT (1 << 8) |
| 237 | #define COP_LPCM_CAD_48K_MAXCHAN(x) (((x) >> 4) & 0xf) |
| 238 | #define COP_LPCM_CAD_48K_MAXCHAN_CP(x) (((x) >> 0) & 0xf) |
| 239 | #define CORB_GET_CONNECTION_SELECT_CONTROL 0xf01 |
| 240 | #define CORB_SET_CONNECTION_SELECT_CONTROL 0x701 |
| 241 | #define CORB_GET_CONNECTION_LIST_ENTRY 0xf02 |
| 242 | #define CORB_GET_PROCESSING_STATE 0xf03 |
| 243 | #define CORB_SET_PROCESSING_STATE 0x703 |
| 244 | #define CORB_GET_COEFFICIENT_INDEX 0xd00 |
| 245 | #define CORB_SET_COEFFICIENT_INDEX 0x500 |
| 246 | #define CORB_GET_PROCESSING_COEFFICIENT 0xc00 |
| 247 | #define CORB_SET_PROCESSING_COEFFICIENT 0x400 |
| 248 | #define CORB_GET_AMPLIFIER_GAIN_MUTE 0xb00 |
| 249 | #define CORB_SET_AMPLIFIER_GAIN_MUTE 0x300 |
| 250 | #define CORB_GET_CONVERTER_FORMAT 0xa00 |
| 251 | #define CORB_SET_CONVERTER_FORMAT 0x200 |
| 252 | #define CORB_GET_DIGITAL_CONVERTER_CONTROL 0xf0d |
| 253 | #define CORB_SET_DIGITAL_CONVERTER_CONTROL_1 0x70d |
| 254 | #define COP_DIGITAL_CONVCTRL1_DIGEN (1 << 0) |
| 255 | #define COP_DIGITAL_CONVCTRL1_V (1 << 1) |
| 256 | #define COP_DIGITAL_CONVCTRL1_VCFG (1 << 2) |
| 257 | #define COP_DIGITAL_CONVCTRL1_PRE (1 << 3) |
| 258 | #define COP_DIGITAL_CONVCTRL1_COPY (1 << 4) |
| 259 | #define COP_DIGITAL_CONVCTRL1_NAUDIO (1 << 5) |
| 260 | #define COP_DIGITAL_CONVCTRL1_PRO (1 << 6) |
| 261 | #define COP_DIGITAL_CONVCTRL1_L (1 << 7) |
| 262 | #define CORB_SET_DIGITAL_CONVERTER_CONTROL_2 0x70e |
| 263 | #define COP_DIGITAL_CONVCTRL2_CC_MASK 0x7f |
| 264 | #define CORB_GET_POWER_STATE 0xf05 |
| 265 | #define CORB_SET_POWER_STATE 0x705 |
| 266 | #define COP_POWER_STATE_D0 0x00 |
| 267 | #define COP_POWER_STATE_D1 0x01 |
| 268 | #define COP_POWER_STATE_D2 0x02 |
| 269 | #define COP_POWER_STATE_D3 0x03 |
| 270 | #define CORB_GET_CONVERTER_STREAM_CHANNEL 0xf06 |
| 271 | #define CORB_SET_CONVERTER_STREAM_CHANNEL 0x706 |
| 272 | #define CORB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04 |
| 273 | #define CORB_SET_INPUT_CONVERTER_SDI_SELECT 0x704 |
| 274 | #define CORB_GET_PIN_WIDGET_CONTROL 0xf07 |
| 275 | #define CORB_SET_PIN_WIDGET_CONTROL 0x707 |
| 276 | #define COP_PWC_VREF_ENABLE_MASK 0x7 |
| 277 | #define COP_PWC_VREF_HIZ 0x00 |
| 278 | #define COP_PWC_VREF_50 0x01 |
| 279 | #define COP_PWC_VREF_GND 0x02 |
| 280 | #define COP_PWC_VREF_80 0x04 |
| 281 | #define COP_PWC_VREF_100 0x05 |
| 282 | #define COP_PWC_IN_ENABLE (1 << 5) |
| 283 | #define COP_PWC_OUT_ENABLE (1 << 6) |
| 284 | #define COP_PWC_HPHN_ENABLE (1 << 7) |
| 285 | #define COP_PWC_EPT_MASK 0x3 |
| 286 | #define COP_PWC_EPT_NATIVE 0x0 |
| 287 | #define COP_PWC_EPT_HIGH_BIT_RATE 0x3 |
| 288 | #define CORB_GET_UNSOLICITED_RESPONSE 0xf08 |
| 289 | #define CORB_SET_UNSOLICITED_RESPONSE 0x708 |
| 290 | #define COP_SET_UNSOLICITED_RESPONSE_ENABLE (1 << 7) |
| 291 | #define CORB_GET_PIN_SENSE 0xf09 |
| 292 | #define COP_GET_PIN_SENSE_PRESENSE_DETECT (1 << 31) |
| 293 | #define COP_GET_PIN_SENSE_ELD_VALID (1 << 30) /* digital */ |
| 294 | #define COP_GET_PIN_SENSE_IMPEDENCE_SENSE(x) ((x) & 0x7fffffff) /* analog */ |
| 295 | #define CORB_SET_PIN_SENSE 0x709 |
| 296 | #define CORB_GET_EAPD_BTL_ENABLE 0xf0c |
| 297 | #define CORB_SET_EAPD_BTL_ENABLE 0x70c |
| 298 | #define COP_EAPD_ENABLE_BTL (1 << 0) |
| 299 | #define COP_EAPD_ENABLE_EAPD (1 << 1) |
| 300 | #define COP_EAPD_ENABLE_LR_SWAP (1 << 2) |
| 301 | #define CORB_GET_GPI_DATA 0xf10 |
| 302 | #define CORB_SET_GPI_DATA 0x710 |
| 303 | #define CORB_GET_GPI_WAKE_ENABLE_MASK 0xf11 |
| 304 | #define CORB_SET_GPI_WAKE_ENABLE_MASK 0x711 |
| 305 | #define CORB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12 |
| 306 | #define CORB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712 |
| 307 | #define CORB_GET_GPI_STICKY_MASK 0xf13 |
| 308 | #define CORB_SET_GPI_STICKY_MASK 0x713 |
| 309 | #define CORB_GET_GPO_DATA 0xf14 |
| 310 | #define CORB_SET_GPO_DATA 0x714 |
| 311 | #define CORB_GET_GPIO_DATA 0xf15 |
| 312 | #define CORB_SET_GPIO_DATA 0x715 |
| 313 | #define CORB_GET_GPIO_ENABLE_MASK 0xf16 |
| 314 | #define CORB_SET_GPIO_ENABLE_MASK 0x716 |
| 315 | #define CORB_GET_GPIO_DIRECTION 0xf17 |
| 316 | #define CORB_SET_GPIO_DIRECTION 0x717 |
| 317 | #define CORB_GET_GPIO_WAKE_ENABLE_MASK 0xf18 |
| 318 | #define CORB_SET_GPIO_WAKE_ENABLE_MASK 0x718 |
| 319 | #define CORB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19 |
| 320 | #define CORB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719 |
| 321 | #define CORB_GET_GPIO_STICKY_MASK 0xf1a |
| 322 | #define CORB_SET_GPIO_STICKY_MASK 0x71a |
| 323 | #define CORB_GET_BEEP_GENERATION 0xf0a |
| 324 | #define CORB_SET_BEEP_GENERATION 0x70a |
| 325 | #define CORB_GET_VOLUME_KNOB 0xf0f |
| 326 | #define CORB_SET_VOLUME_KNOB 0x70f |
| 327 | #define CORB_GET_SUBSYSTEM_ID 0xf20 |
| 328 | #define CORB_SET_SUBSYSTEM_ID_1 0x720 |
| 329 | #define CORB_SET_SUBSYSTEM_ID_2 0x721 |
| 330 | #define CORB_SET_SUBSYSTEM_ID_3 0x722 |
| 331 | #define CORB_SET_SUBSYSTEM_ID_4 0x723 |
| 332 | #define CORB_GET_CONFIGURATION_DEFAULT 0xf1c |
| 333 | #define COP_CFG_SEQUENCE(x) (((x) >> 0) & 0xf) |
| 334 | #define COP_CFG_DEFAULT_ASSOCIATION(x) (((x) >> 4) & 0xf) |
| 335 | #define COP_CFG_MISC(x) (((x) >> 8) & 0xf) |
| 336 | #define COP_CFG_COLOR(x) (((x) >> 12) & 0xf) |
| 337 | #define COP_CFG_CONNECTION_TYPE(x) (((x) >> 16) & 0xf) |
| 338 | #define COP_CONN_TYPE_UNKNOWN 0x0 |
| 339 | #define COP_CONN_TYPE_18INCH 0x1 |
| 340 | #define COP_CONN_TYPE_14INCH 0x2 |
| 341 | #define COP_CONN_TYPE_ATAPI_INTERNAL 0x3 |
| 342 | #define COP_CONN_TYPE_RCA 0x4 |
| 343 | #define COP_CONN_TYPE_OPTICAL 0x5 |
| 344 | #define COP_CONN_TYPE_OTHER_DIGITAL 0x6 |
| 345 | #define COP_CONN_TYPE_OTHER_ANALOG 0x7 |
| 346 | #define COP_CONN_TYPE_DIN 0x8 |
| 347 | #define COP_CONN_TYPE_XLR 0x9 |
| 348 | #define COP_CONN_TYPE_RJ11 0xa |
| 349 | #define COP_CONN_TYPE_COMBINATION 0xb |
| 350 | #define COP_CONN_TYPE_OTHER 0xf |
| 351 | #define COP_CFG_DEFAULT_DEVICE(x) (((x) >> 20) & 0xf) |
| 352 | #define COP_DEVICE_MASK 0x00f00000 |
| 353 | #define COP_DEVICE_SHIFT 20 |
| 354 | #define COP_DEVICE_LINE_OUT 0x0 |
| 355 | #define COP_DEVICE_SPEAKER 0x1 |
| 356 | #define COP_DEVICE_HP_OUT 0x2 |
| 357 | #define COP_DEVICE_CD 0x3 |
| 358 | #define COP_DEVICE_SPDIF_OUT 0x4 |
| 359 | #define COP_DEVICE_DIGITAL_OTHER_OUT 0x5 |
| 360 | #define COP_DEVICE_MODEM_LINE_SIDE 0x6 |
| 361 | #define COP_DEVICE_MODEM_HANDSET_SIDE 0x7 |
| 362 | #define COP_DEVICE_LINE_IN 0x8 |
| 363 | #define COP_DEVICE_AUX 0x9 |
| 364 | #define COP_DEVICE_MIC_IN 0xa |
| 365 | #define COP_DEVICE_TELEPHONY 0xb |
| 366 | #define COP_DEVICE_SPDIF_IN 0xc |
| 367 | #define COP_DEVICE_DIGITAL_OTHER_IN 0xd |
| 368 | #define COP_DEVICE_OTHER 0xf |
| 369 | #define COP_CFG_LOCATION(x) (((x) >> 24) & 0x3f) |
| 370 | #define COP_CFG_PORT_CONNECTIVITY(x) (((x) >> 30) & 0x3) |
| 371 | #define COP_PORT_JACK 0x0 |
| 372 | #define COP_PORT_NONE 0x1 |
| 373 | #define COP_PORT_FIXED_FUNCTION 0x2 |
| 374 | #define COP_PORT_BOTH 0x3 |
| 375 | #define CORB_SET_CONFIGURATION_DEFAULT_1 0x71c |
| 376 | #define CORB_SET_CONFIGURATION_DEFAULT_2 0x71d |
| 377 | #define CORB_SET_CONFIGURATION_DEFAULT_3 0x71e |
| 378 | #define CORB_SET_CONFIGURATION_DEFAULT_4 0x71f |
| 379 | #define CORB_GET_STRIPE_CONTROL 0xf24 |
| 380 | #define CORB_SET_STRIPE_CONTROL 0x720 |
| 381 | #define CORB_EXECUTE_RESET 0x7ff |
| 382 | #define CORB_GET_CONVERTER_CHANNEL_COUNT 0xf2d |
| 383 | #define CORB_SET_CONVERTER_CHANNEL_COUNT 0x72d |
| 384 | #define CORB_GET_HDMI_DIP_SIZE 0xf2e |
| 385 | #define COP_DIP_ELD_SIZE (1 << 3) |
| 386 | #define COP_DIP_PI_GP(x) ((x) & 0x7) |
| 387 | #define COP_DIP_PI_AUDIO_INFO COP_DIP_PI_GP(0) |
| 388 | #define COP_DIP_BUFFER_SIZE(x) ((x) & 0xff) |
| 389 | #define CORB_GET_HDMI_ELD_DATA 0xf2f |
| 390 | #define COP_ELD_VALID (1 << 31) |
| 391 | #define COP_ELD_DATA(x) (((x) >> 0) & 0xff) |
| 392 | #define CORB_GET_HDMI_DIP_INDEX 0xf30 |
| 393 | #define CORB_SET_HDMI_DIP_INDEX 0x730 |
| 394 | #define COP_DIP_INDEX_BYTE_SHIFT 0 |
| 395 | #define COP_DIP_INDEX_BYTE_MASK 0xf |
| 396 | #define COP_DIP_INDEX_PACKET_INDEX_SHIFT 4 |
| 397 | #define COP_DIP_INDEX_PACKET_INDEX_MASK 0xf |
| 398 | #define CORB_GET_HDMI_DIP_DATA 0xf31 |
| 399 | #define CORB_SET_HDMI_DIP_DATA 0x731 |
| 400 | #define CORB_GET_HDMI_DIP_XMIT_CTRL 0xf32 |
| 401 | #define CORB_SET_HDMI_DIP_XMIT_CTRL 0x732 |
| 402 | #define COP_DIP_XMIT_CTRL_DISABLE (0x0 << 6) |
| 403 | #define COP_DIP_XMIT_CTRL_ONCE (0x2 << 6) |
| 404 | #define COP_DIP_XMIT_CTRL_BEST_EFFORT (0x3 << 6) |
| 405 | #define CORB_GET_PROTECTION_CONTROL 0xf33 |
| 406 | #define CORB_SET_PROTECTION_CONTROL 0x733 |
| 407 | #define COP_PROTECTION_CONTROL_CES_ON (1 << 9) |
| 408 | #define COP_PROTECTION_CONTROL_READY (1 << 8) |
| 409 | #define COP_PROTECTION_CONTROL_URSUBTAG_SHIFT 3 |
| 410 | #define COP_PROTECTION_CONTROL_URSUBTAG_MASK 0x1f |
| 411 | #define COP_PROTECTION_CONTROL_CPSTATE_MASK 0x3 |
| 412 | #define COP_PROTECTION_CONTROL_CPSTATE_DONTCARE (0 << 0) |
| 413 | #define COP_PROTECTION_CONTROL_CPSTATE_OFF (2 << 0) |
| 414 | #define COP_PROTECTION_CONTROL_CPSTATE_ON (3 << 0) |
| 415 | #define CORB_ASP_GET_CHANNEL_MAPPING 0xf34 |
| 416 | #define CORB_ASP_SET_CHANNEL_MAPPING 0x734 |
| 417 | |
| 418 | |
| 419 | /* |
| 420 | * RIRB Entry Format |
| 421 | */ |
| 422 | struct rirb_entry { |
| 423 | uint32_t resp; |
| 424 | uint32_t resp_ex; |
| 425 | #define RIRB_CODEC_ID(entry) ((entry)->resp_ex & 0xf) |
| 426 | #define RIRB_UNSOL(entry) ((entry)->resp_ex & 0x10) |
| 427 | } __packed; |
| 428 | |
| 429 | #endif /* !_HDAUDIOREG_H */ |
| 430 | |