| 1 | /* $NetBSD: makphyreg.h,v 1.6 2014/05/13 02:53:54 christos Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Jason R. Thorpe. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #ifndef _DEV_MII_MAKPHYREG_H_ |
| 33 | #define _DEV_MII_MAKPHYREG_H_ |
| 34 | |
| 35 | /* |
| 36 | * Marvell 88E1000 ``Alaska'' 10/100/1000 PHY registers. |
| 37 | */ |
| 38 | |
| 39 | #define MII_MAKPHY_PSCR 0x10 /* PHY specific control register */ |
| 40 | #define PSCR_DIS_JABBER (1U << 0) /* disable jabber */ |
| 41 | #define PSCR_POL_REV (1U << 1) /* polarity reversal */ |
| 42 | #define PSCR_SQE_TEST (1U << 2) /* SQE test */ |
| 43 | #define PSCR_MBO (1U << 3) /* must be one */ |
| 44 | #define PSCR_DIS_125CLK (1U << 4) /* 125CLK low */ |
| 45 | #define PSCR_MDI_XOVER_MODE(x) ((x) << 5) /* crossover mode */ |
| 46 | #define PSCR_LOW_10T_THRESH (1U << 7) /* lower 10BASE-T Rx threshold */ |
| 47 | #define PSCR_FORCE_LINK_GOOD (1U << 10) /* force link good */ |
| 48 | #define PSCR_CRS_ON_TX (1U << 11) /* assert CRS on transmit */ |
| 49 | #define PSCR_RX_FIFO(x) ((x) << 12) /* Rx FIFO depth */ |
| 50 | #define PSCR_TX_FIFO(x) ((x) << 14) /* Tx FIFO depth */ |
| 51 | |
| 52 | #define XOVER_MODE_MDI 0 |
| 53 | #define XOVER_MODE_MDIX 1 |
| 54 | #define XOVER_MODE_AUTO 2 |
| 55 | |
| 56 | #define MII_MAKPHY_PSSR 0x11 /* PHY specific status register */ |
| 57 | #define PSSR_JABBER (1U << 0) /* jabber indication */ |
| 58 | #define PSSR_POLARITY (1U << 1) /* polarity indiciation */ |
| 59 | #define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */ |
| 60 | #define PSSR_CABLE_LENGTH_get(x) (((x) >> 7) & 0x3) |
| 61 | #define PSSR_LINK (1U << 10) /* link indication */ |
| 62 | #define PSSR_RESOLVED (1U << 11) /* speed and duplex resolved */ |
| 63 | #define PSSR_PAGE_RECEIVED (1U << 12) /* page received */ |
| 64 | #define PSSR_DUPLEX (1U << 13) /* 1 = FDX */ |
| 65 | #define PSSR_SPEED_get(x) (((x) >> 14) & 0x3) |
| 66 | |
| 67 | #define SPEED_10 0 |
| 68 | #define SPEED_100 1 |
| 69 | #define SPEED_1000 2 |
| 70 | #define SPEED_reserved 3 |
| 71 | |
| 72 | #define MII_MAKPHY_IE 0x12 /* Interrupt enable */ |
| 73 | #define IE_JABBER (1U << 0) /* jabber indication */ |
| 74 | #define IE_POL_CHANGED (1U << 1) /* polarity changed */ |
| 75 | #define IE_MDI_XOVER_CHANGED (1U << 6) /* MDI/MDIX changed */ |
| 76 | #define IE_FIFO_OVER_UNDER (1U << 7) /* FIFO over/underflow */ |
| 77 | #define IE_FALSE_CARRIER (1U << 8) /* false carrier detected */ |
| 78 | #define IE_SYMBOL_ERROR (1U << 9) /* symbol error occurred */ |
| 79 | #define IE_LINK_CHANGED (1U << 10) /* link status changed */ |
| 80 | #define IE_ANEG_COMPLETE (1U << 11) /* autonegotiation completed */ |
| 81 | #define IE_PAGE_RECEIVED (1U << 12) /* page received */ |
| 82 | #define IE_DUPLEX_CHANGED (1U << 13) /* duplex changed */ |
| 83 | #define IE_SPEED_CHANGED (1U << 14) /* speed changed */ |
| 84 | #define IE_ANEG_ERROR (1U << 15) /* autonegotiation error occurred */ |
| 85 | |
| 86 | #define MII_MAKPHY_IS 0x13 /* Interrupt status */ |
| 87 | /* See Interrupt enable bits */ |
| 88 | |
| 89 | #define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */ |
| 90 | #define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */ |
| 91 | #define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */ |
| 92 | #define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */ |
| 93 | #define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */ |
| 94 | |
| 95 | #define MII_MAKPHY_REC 0x15 /* receive error counter */ |
| 96 | |
| 97 | #define MII_MAKPHY_EADR 0x16 /* extended address register */ |
| 98 | |
| 99 | #define MII_MAKPHY_LEDCTRL 0x18 /* LED control */ |
| 100 | #define LEDCTRL_LED_TX (1U << 0) /* 1 = activ/link, 0 = xmit */ |
| 101 | #define LEDCTRL_LED_RX (1U << 1) /* 1 = activ/link, 1 = recv */ |
| 102 | #define LEDCTRL_LED_DUPLEX (1U << 2) /* 1 = duplex, 0 = dup/coll */ |
| 103 | #define LEDCTRL_LED_LINK (1U << 3) /* 1 = spd/link, 0 = link */ |
| 104 | #define LEDCTRL_BLINK_RATE(x) ((x) << 8) |
| 105 | #define LEDCTRL_PULSE_STRCH(x) ((x) << 12) |
| 106 | #define LEDCTRL_DISABLE (1U << 15) /* disable LED */ |
| 107 | |
| 108 | #define MII_MAKPHY_ESSR 0x1b /* Extended PHY specific status */ |
| 109 | #define ESSR_FIBER_LINK 0x2000 |
| 110 | #define ESSR_GMII_COPPER 0x000f |
| 111 | #define ESSR_GMII_FIBER 0x0007 |
| 112 | #define ESSR_TBI_COPPER 0x000d |
| 113 | #define ESSR_TBI_FIBER 0x0005 |
| 114 | |
| 115 | |
| 116 | #endif /* _DEV_MII_MAKPHYREG_H_ */ |
| 117 | |