| 1 | /* $NetBSD: if_wi_pci.c,v 1.56 2016/07/14 04:00:46 msaitoh Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Hideaki Imaizumi <hiddy@sfc.wide.ad.jp> |
| 9 | * and Ichiro FUKUHARA (ichiro@ichiro.org). |
| 10 | * |
| 11 | * Redistribution and use in source and binary forms, with or without |
| 12 | * modification, are permitted provided that the following conditions |
| 13 | * are met: |
| 14 | * 1. Redistributions of source code must retain the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer. |
| 16 | * 2. Redistributions in binary form must reproduce the above copyright |
| 17 | * notice, this list of conditions and the following disclaimer in the |
| 18 | * documentation and/or other materials provided with the distribution. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 30 | * POSSIBILITY OF SUCH DAMAGE. |
| 31 | */ |
| 32 | |
| 33 | /* |
| 34 | * PCI bus front-end for the Intersil PCI WaveLan. |
| 35 | * Works with Prism2.5 Mini-PCI wavelan. |
| 36 | */ |
| 37 | |
| 38 | #include <sys/cdefs.h> |
| 39 | __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.56 2016/07/14 04:00:46 msaitoh Exp $" ); |
| 40 | |
| 41 | #include <sys/param.h> |
| 42 | #include <sys/systm.h> |
| 43 | #include <sys/mbuf.h> |
| 44 | #include <sys/syslog.h> |
| 45 | #include <sys/socket.h> |
| 46 | #include <sys/device.h> |
| 47 | #include <sys/callout.h> |
| 48 | |
| 49 | #include <net/if.h> |
| 50 | #include <net/if_ether.h> |
| 51 | #include <net/if_media.h> |
| 52 | |
| 53 | #include <net80211/ieee80211_netbsd.h> |
| 54 | #include <net80211/ieee80211_var.h> |
| 55 | #include <net80211/ieee80211_radiotap.h> |
| 56 | #include <net80211/ieee80211_rssadapt.h> |
| 57 | |
| 58 | #include <sys/bus.h> |
| 59 | #include <sys/intr.h> |
| 60 | |
| 61 | #include <dev/pci/pcireg.h> |
| 62 | #include <dev/pci/pcivar.h> |
| 63 | #include <dev/pci/pcidevs.h> |
| 64 | |
| 65 | #include <dev/ic/wi_ieee.h> |
| 66 | #include <dev/ic/wireg.h> |
| 67 | #include <dev/ic/wivar.h> |
| 68 | |
| 69 | #define WI_PCI_CBMA PCI_BAR(0) /* Configuration Base Memory Address */ |
| 70 | #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ |
| 71 | #define WI_PCI_PLX_LOIO PCI_BAR(1) /* PLX chip iobase */ |
| 72 | #define WI_PCI_LOMEM PCI_BAR(2) /* ISA membase */ |
| 73 | #define WI_PCI_LOIO PCI_BAR(3) /* ISA iobase */ |
| 74 | |
| 75 | #define CHIP_PLX_OTHER 0x01 |
| 76 | #define CHIP_PLX_9052 0x02 |
| 77 | #define CHIP_TMD_7160 0x03 |
| 78 | |
| 79 | #define WI_PLX_COR_OFFSET 0x3E0 |
| 80 | #define WI_PLX_COR_VALUE 0x41 |
| 81 | |
| 82 | struct wi_pci_softc { |
| 83 | struct wi_softc psc_wi; /* real "wi" softc */ |
| 84 | |
| 85 | /* PCI-specific goo */ |
| 86 | pci_intr_handle_t psc_ih; |
| 87 | pci_chipset_tag_t psc_pc; |
| 88 | pcitag_t psc_pcitag; |
| 89 | }; |
| 90 | |
| 91 | static int wi_pci_match(device_t, cfdata_t, void *); |
| 92 | static void wi_pci_attach(device_t, device_t, void *); |
| 93 | static int wi_pci_enable(device_t, int); |
| 94 | static void wi_pci_reset(struct wi_softc *); |
| 95 | |
| 96 | static const struct wi_pci_product |
| 97 | *wi_pci_lookup(struct pci_attach_args *); |
| 98 | |
| 99 | CFATTACH_DECL_NEW(wi_pci, sizeof(struct wi_pci_softc), |
| 100 | wi_pci_match, wi_pci_attach, NULL, NULL); |
| 101 | |
| 102 | static const struct wi_pci_product { |
| 103 | pci_vendor_id_t wpp_vendor; /* vendor ID */ |
| 104 | pci_product_id_t wpp_product; /* product ID */ |
| 105 | int wpp_chip; /* uses other chip */ |
| 106 | } wi_pci_products[] = { |
| 107 | { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, |
| 108 | CHIP_PLX_OTHER }, |
| 109 | { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, |
| 110 | CHIP_PLX_OTHER }, |
| 111 | { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, |
| 112 | CHIP_PLX_OTHER }, |
| 113 | { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, |
| 114 | CHIP_PLX_OTHER }, |
| 115 | { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, |
| 116 | CHIP_PLX_OTHER }, |
| 117 | { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, |
| 118 | 0 }, |
| 119 | { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, |
| 120 | CHIP_PLX_9052 }, |
| 121 | { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, |
| 122 | CHIP_PLX_OTHER }, |
| 123 | { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, |
| 124 | CHIP_TMD_7160 }, |
| 125 | { 0, 0, |
| 126 | 0}, |
| 127 | }; |
| 128 | |
| 129 | static int |
| 130 | wi_pci_enable(device_t self, int onoff) |
| 131 | { |
| 132 | struct wi_pci_softc *psc = device_private(self); |
| 133 | struct wi_softc *sc = &psc->psc_wi; |
| 134 | |
| 135 | if (onoff) { |
| 136 | /* establish the interrupt. */ |
| 137 | sc->sc_ih = pci_intr_establish(psc->psc_pc, |
| 138 | psc->psc_ih, IPL_NET, wi_intr, sc); |
| 139 | if (sc->sc_ih == NULL) { |
| 140 | aprint_error_dev(sc->sc_dev, |
| 141 | "couldn't establish interrupt\n" ); |
| 142 | return EIO; |
| 143 | } |
| 144 | |
| 145 | /* reset HFA3842 MAC core */ |
| 146 | if (sc->sc_reset != NULL) |
| 147 | wi_pci_reset(sc); |
| 148 | |
| 149 | } else |
| 150 | pci_intr_disestablish(psc->psc_pc, sc->sc_ih); |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static void |
| 155 | wi_pci_reset(struct wi_softc *sc) |
| 156 | { |
| 157 | int i, secs, usecs; |
| 158 | |
| 159 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
| 160 | WI_PCI_COR, WI_COR_SOFT_RESET); |
| 161 | DELAY(250*1000); /* 1/4 second */ |
| 162 | |
| 163 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
| 164 | WI_PCI_COR, WI_COR_CLEAR); |
| 165 | DELAY(500*1000); /* 1/2 second */ |
| 166 | |
| 167 | /* wait 2 seconds for firmware to complete initialization. */ |
| 168 | |
| 169 | for (i = 200000; i--; DELAY(10)) |
| 170 | if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) |
| 171 | break; |
| 172 | |
| 173 | if (i < 0) { |
| 174 | printf("%s: PCI reset timed out\n" , device_xname(sc->sc_dev)); |
| 175 | } else if (sc->sc_if.if_flags & IFF_DEBUG) { |
| 176 | usecs = (200000 - i) * 10; |
| 177 | secs = usecs / 1000000; |
| 178 | usecs %= 1000000; |
| 179 | |
| 180 | printf("%s: PCI reset in %d.%06d seconds\n" , |
| 181 | device_xname(sc->sc_dev), secs, usecs); |
| 182 | } |
| 183 | |
| 184 | return; |
| 185 | } |
| 186 | |
| 187 | static const struct wi_pci_product * |
| 188 | wi_pci_lookup(struct pci_attach_args *pa) |
| 189 | { |
| 190 | const struct wi_pci_product *wpp; |
| 191 | |
| 192 | for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { |
| 193 | if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && |
| 194 | PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) |
| 195 | return (wpp); |
| 196 | } |
| 197 | return (NULL); |
| 198 | } |
| 199 | |
| 200 | static int |
| 201 | wi_pci_match(device_t parent, cfdata_t match, void *aux) |
| 202 | { |
| 203 | struct pci_attach_args *pa = aux; |
| 204 | |
| 205 | if (wi_pci_lookup(pa) != NULL) |
| 206 | return (1); |
| 207 | return (0); |
| 208 | } |
| 209 | |
| 210 | static void |
| 211 | wi_pci_attach(device_t parent, device_t self, void *aux) |
| 212 | { |
| 213 | struct wi_pci_softc *psc = device_private(self); |
| 214 | struct wi_softc *sc = &psc->psc_wi; |
| 215 | struct pci_attach_args *pa = aux; |
| 216 | pci_chipset_tag_t pc = pa->pa_pc; |
| 217 | const char *intrstr; |
| 218 | const struct wi_pci_product *wpp; |
| 219 | pci_intr_handle_t ih; |
| 220 | bus_space_tag_t memt, iot, plxt, tmdt; |
| 221 | bus_space_handle_t memh, ioh, plxh, tmdh; |
| 222 | char intrbuf[PCI_INTRSTR_LEN]; |
| 223 | |
| 224 | sc->sc_dev = self; |
| 225 | psc->psc_pc = pc; |
| 226 | psc->psc_pcitag = pa->pa_tag; |
| 227 | |
| 228 | wpp = wi_pci_lookup(pa); |
| 229 | #ifdef DIAGNOSTIC |
| 230 | if (wpp == NULL) { |
| 231 | printf("\n" ); |
| 232 | panic("wi_pci_attach: impossible" ); |
| 233 | } |
| 234 | #endif |
| 235 | |
| 236 | switch (wpp->wpp_chip) { |
| 237 | case CHIP_PLX_OTHER: |
| 238 | case CHIP_PLX_9052: |
| 239 | /* Map memory and I/O registers. */ |
| 240 | if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, |
| 241 | &memt, &memh, NULL, NULL) != 0) { |
| 242 | aprint_error(": can't map mem space\n" ); |
| 243 | return; |
| 244 | } |
| 245 | if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, |
| 246 | &iot, &ioh, NULL, NULL) != 0) { |
| 247 | aprint_error(": can't map I/O space\n" ); |
| 248 | return; |
| 249 | } |
| 250 | |
| 251 | if (wpp->wpp_chip == CHIP_PLX_OTHER) { |
| 252 | /* The PLX 9052 doesn't have IO at 0x14. Perhaps |
| 253 | other chips have, so we'll make this conditional. */ |
| 254 | if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, |
| 255 | PCI_MAPREG_TYPE_IO, 0, &plxt, &plxh, NULL, NULL) |
| 256 | != 0) { |
| 257 | aprint_error(": can't map PLX\n" ); |
| 258 | return; |
| 259 | } |
| 260 | } |
| 261 | break; |
| 262 | case CHIP_TMD_7160: |
| 263 | /* Used instead of PLX on at least one revision of |
| 264 | * the National Datacomm Corporation NCP130. Values |
| 265 | * for registers acquired from OpenBSD, which in |
| 266 | * turn got them from a Linux driver. |
| 267 | */ |
| 268 | /* Map COR and I/O registers. */ |
| 269 | if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, |
| 270 | &tmdt, &tmdh, NULL, NULL) != 0) { |
| 271 | aprint_error(": can't map TMD\n" ); |
| 272 | return; |
| 273 | } |
| 274 | if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, |
| 275 | &iot, &ioh, NULL, NULL) != 0) { |
| 276 | aprint_error(": can't map I/O space\n" ); |
| 277 | return; |
| 278 | } |
| 279 | break; |
| 280 | default: |
| 281 | if (pci_mapreg_map(pa, WI_PCI_CBMA, |
| 282 | PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, |
| 283 | 0, &iot, &ioh, NULL, NULL) != 0) { |
| 284 | aprint_error(": can't map mem space\n" ); |
| 285 | return; |
| 286 | } |
| 287 | |
| 288 | memt = iot; |
| 289 | memh = ioh; |
| 290 | sc->sc_pci = 1; |
| 291 | break; |
| 292 | } |
| 293 | |
| 294 | pci_aprint_devinfo(pa, NULL); |
| 295 | |
| 296 | sc->sc_enabled = 1; |
| 297 | sc->sc_enable = wi_pci_enable; |
| 298 | |
| 299 | sc->sc_iot = iot; |
| 300 | sc->sc_ioh = ioh; |
| 301 | /* Make sure interrupts are disabled. */ |
| 302 | CSR_WRITE_2(sc, WI_INT_EN, 0); |
| 303 | CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); |
| 304 | |
| 305 | if (wpp->wpp_chip == CHIP_PLX_OTHER) { |
| 306 | uint32_t command; |
| 307 | #define WI_LOCAL_INTCSR 0x4c |
| 308 | #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ |
| 309 | |
| 310 | command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); |
| 311 | command |= WI_LOCAL_INTEN; |
| 312 | bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); |
| 313 | } |
| 314 | |
| 315 | /* Map and establish the interrupt. */ |
| 316 | if (pci_intr_map(pa, &ih)) { |
| 317 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
| 318 | return; |
| 319 | } |
| 320 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
| 321 | |
| 322 | psc->psc_ih = ih; |
| 323 | sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); |
| 324 | if (sc->sc_ih == NULL) { |
| 325 | aprint_error_dev(self, "couldn't establish interrupt" ); |
| 326 | if (intrstr != NULL) |
| 327 | aprint_error(" at %s" , intrstr); |
| 328 | aprint_error("\n" ); |
| 329 | return; |
| 330 | } |
| 331 | |
| 332 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
| 333 | |
| 334 | switch (wpp->wpp_chip) { |
| 335 | case CHIP_PLX_OTHER: |
| 336 | case CHIP_PLX_9052: |
| 337 | /* |
| 338 | * Setup the PLX chip for level interrupts and config index 1 |
| 339 | * XXX - should really reset the PLX chip too. |
| 340 | */ |
| 341 | bus_space_write_1(memt, memh, |
| 342 | WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); |
| 343 | break; |
| 344 | case CHIP_TMD_7160: |
| 345 | /* Enable I/O mode and level interrupts on the embedded |
| 346 | * card. The card's COR is the first byte of BAR 0. |
| 347 | */ |
| 348 | bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); |
| 349 | break; |
| 350 | default: |
| 351 | /* reset HFA3842 MAC core */ |
| 352 | wi_pci_reset(sc); |
| 353 | break; |
| 354 | } |
| 355 | |
| 356 | printf("%s:" , device_xname(self)); |
| 357 | |
| 358 | if (wi_attach(sc, 0) != 0) { |
| 359 | aprint_error_dev(self, "failed to attach controller\n" ); |
| 360 | pci_intr_disestablish(pa->pa_pc, sc->sc_ih); |
| 361 | return; |
| 362 | } |
| 363 | |
| 364 | if (!wpp->wpp_chip) |
| 365 | sc->sc_reset = wi_pci_reset; |
| 366 | |
| 367 | if (pmf_device_register(self, NULL, NULL)) |
| 368 | pmf_class_network_register(self, &sc->sc_if); |
| 369 | else |
| 370 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 371 | } |
| 372 | |