| 1 | /* $NetBSD: if_iwmreg.h,v 1.2 2015/02/16 13:22:19 nonaka Exp $ */ |
| 2 | /* OpenBSD: if_iwmreg.h,v 1.2 2015/02/06 23:52:23 stsp Exp */ |
| 3 | |
| 4 | /****************************************************************************** |
| 5 | * |
| 6 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 7 | * redistributing this file, you may do so under either license. |
| 8 | * |
| 9 | * GPL LICENSE SUMMARY |
| 10 | * |
| 11 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of version 2 of the GNU General Public License as |
| 15 | * published by the Free Software Foundation. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, but |
| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 20 | * General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 25 | * USA |
| 26 | * |
| 27 | * The full GNU General Public License is included in this distribution |
| 28 | * in the file called COPYING. |
| 29 | * |
| 30 | * Contact Information: |
| 31 | * Intel Linux Wireless <ilw@linux.intel.com> |
| 32 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 33 | * |
| 34 | * BSD LICENSE |
| 35 | * |
| 36 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
| 37 | * All rights reserved. |
| 38 | * |
| 39 | * Redistribution and use in source and binary forms, with or without |
| 40 | * modification, are permitted provided that the following conditions |
| 41 | * are met: |
| 42 | * |
| 43 | * * Redistributions of source code must retain the above copyright |
| 44 | * notice, this list of conditions and the following disclaimer. |
| 45 | * * Redistributions in binary form must reproduce the above copyright |
| 46 | * notice, this list of conditions and the following disclaimer in |
| 47 | * the documentation and/or other materials provided with the |
| 48 | * distribution. |
| 49 | * * Neither the name Intel Corporation nor the names of its |
| 50 | * contributors may be used to endorse or promote products derived |
| 51 | * from this software without specific prior written permission. |
| 52 | * |
| 53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 54 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 55 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 56 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 57 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 58 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 59 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 60 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 61 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 62 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 64 | * |
| 65 | *****************************************************************************/ |
| 66 | |
| 67 | /* |
| 68 | * BEGIN iwl-csr.h |
| 69 | */ |
| 70 | |
| 71 | /* |
| 72 | * CSR (control and status registers) |
| 73 | * |
| 74 | * CSR registers are mapped directly into PCI bus space, and are accessible |
| 75 | * whenever platform supplies power to device, even when device is in |
| 76 | * low power states due to driver-invoked device resets |
| 77 | * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. |
| 78 | * |
| 79 | * Use iwl_write32() and iwl_read32() family to access these registers; |
| 80 | * these provide simple PCI bus access, without waking up the MAC. |
| 81 | * Do not use iwl_write_direct32() family for these registers; |
| 82 | * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. |
| 83 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing |
| 84 | * the CSR registers. |
| 85 | * |
| 86 | * NOTE: Device does need to be awake in order to read this memory |
| 87 | * via IWM_CSR_EEPROM and IWM_CSR_OTP registers |
| 88 | */ |
| 89 | #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ |
| 90 | #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ |
| 91 | #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ |
| 92 | #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ |
| 93 | #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ |
| 94 | #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ |
| 95 | #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ |
| 96 | #define IWM_CSR_GP_CNTRL (0x024) |
| 97 | |
| 98 | /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ |
| 99 | #define IWM_CSR_INT_PERIODIC_REG (0x005) |
| 100 | |
| 101 | /* |
| 102 | * Hardware revision info |
| 103 | * Bit fields: |
| 104 | * 31-16: Reserved |
| 105 | * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions |
| 106 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
| 107 | * 1-0: "Dash" (-) value, as in A-1, etc. |
| 108 | */ |
| 109 | #define IWM_CSR_HW_REV (0x028) |
| 110 | |
| 111 | /* |
| 112 | * EEPROM and OTP (one-time-programmable) memory reads |
| 113 | * |
| 114 | * NOTE: Device must be awake, initialized via apm_ops.init(), |
| 115 | * in order to read. |
| 116 | */ |
| 117 | #define IWM_CSR_EEPROM_REG (0x02c) |
| 118 | #define IWM_CSR_EEPROM_GP (0x030) |
| 119 | #define IWM_CSR_OTP_GP_REG (0x034) |
| 120 | |
| 121 | #define IWM_CSR_GIO_REG (0x03C) |
| 122 | #define IWM_CSR_GP_UCODE_REG (0x048) |
| 123 | #define IWM_CSR_GP_DRIVER_REG (0x050) |
| 124 | |
| 125 | /* |
| 126 | * UCODE-DRIVER GP (general purpose) mailbox registers. |
| 127 | * SET/CLR registers set/clear bit(s) if "1" is written. |
| 128 | */ |
| 129 | #define IWM_CSR_UCODE_DRV_GP1 (0x054) |
| 130 | #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) |
| 131 | #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) |
| 132 | #define IWM_CSR_UCODE_DRV_GP2 (0x060) |
| 133 | |
| 134 | #define IWM_CSR_LED_REG (0x094) |
| 135 | #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) |
| 136 | #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ |
| 137 | |
| 138 | |
| 139 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
| 140 | #define IWM_CSR_GIO_CHICKEN_BITS (0x100) |
| 141 | |
| 142 | /* Analog phase-lock-loop configuration */ |
| 143 | #define IWM_CSR_ANA_PLL_CFG (0x20c) |
| 144 | |
| 145 | /* |
| 146 | * CSR Hardware Revision Workaround Register. Indicates hardware rev; |
| 147 | * "step" determines CCK backoff for txpower calculation. Used for 4965 only. |
| 148 | * See also IWM_CSR_HW_REV register. |
| 149 | * Bit fields: |
| 150 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step |
| 151 | * 1-0: "Dash" (-) value, as in C-1, etc. |
| 152 | */ |
| 153 | #define IWM_CSR_HW_REV_WA_REG (0x22C) |
| 154 | |
| 155 | #define IWM_CSR_DBG_HPET_MEM_REG (0x240) |
| 156 | #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) |
| 157 | |
| 158 | /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ |
| 159 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) |
| 160 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) |
| 161 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) |
| 162 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) |
| 163 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
| 164 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) |
| 165 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) |
| 166 | #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) |
| 167 | |
| 168 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) |
| 169 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) |
| 170 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) |
| 171 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) |
| 172 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) |
| 173 | #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) |
| 174 | |
| 175 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
| 176 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
| 177 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ |
| 178 | #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ |
| 179 | #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ |
| 180 | |
| 181 | #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ |
| 182 | #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ |
| 183 | |
| 184 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
| 185 | * acknowledged (reset) by host writing "1" to flagged bits. */ |
| 186 | #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ |
| 187 | #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ |
| 188 | #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
| 189 | #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
| 190 | #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ |
| 191 | #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ |
| 192 | #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
| 193 | #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ |
| 194 | #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ |
| 195 | #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
| 196 | #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ |
| 197 | |
| 198 | #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ |
| 199 | IWM_CSR_INT_BIT_HW_ERR | \ |
| 200 | IWM_CSR_INT_BIT_FH_TX | \ |
| 201 | IWM_CSR_INT_BIT_SW_ERR | \ |
| 202 | IWM_CSR_INT_BIT_RF_KILL | \ |
| 203 | IWM_CSR_INT_BIT_SW_RX | \ |
| 204 | IWM_CSR_INT_BIT_WAKEUP | \ |
| 205 | IWM_CSR_INT_BIT_ALIVE | \ |
| 206 | IWM_CSR_INT_BIT_RX_PERIODIC) |
| 207 | |
| 208 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ |
| 209 | #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ |
| 210 | #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ |
| 211 | #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
| 212 | #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ |
| 213 | #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
| 214 | #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ |
| 215 | |
| 216 | #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ |
| 217 | IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ |
| 218 | IWM_CSR_FH_INT_BIT_RX_CHNL0) |
| 219 | |
| 220 | #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ |
| 221 | IWM_CSR_FH_INT_BIT_TX_CHNL0) |
| 222 | |
| 223 | /* GPIO */ |
| 224 | #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) |
| 225 | #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) |
| 226 | #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) |
| 227 | |
| 228 | /* RESET */ |
| 229 | #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) |
| 230 | #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) |
| 231 | #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) |
| 232 | #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) |
| 233 | #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) |
| 234 | #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
| 235 | |
| 236 | /* |
| 237 | * GP (general purpose) CONTROL REGISTER |
| 238 | * Bit fields: |
| 239 | * 27: HW_RF_KILL_SW |
| 240 | * Indicates state of (platform's) hardware RF-Kill switch |
| 241 | * 26-24: POWER_SAVE_TYPE |
| 242 | * Indicates current power-saving mode: |
| 243 | * 000 -- No power saving |
| 244 | * 001 -- MAC power-down |
| 245 | * 010 -- PHY (radio) power-down |
| 246 | * 011 -- Error |
| 247 | * 9-6: SYS_CONFIG |
| 248 | * Indicates current system configuration, reflecting pins on chip |
| 249 | * as forced high/low by device circuit board. |
| 250 | * 4: GOING_TO_SLEEP |
| 251 | * Indicates MAC is entering a power-saving sleep power-down. |
| 252 | * Not a good time to access device-internal resources. |
| 253 | * 3: MAC_ACCESS_REQ |
| 254 | * Host sets this to request and maintain MAC wakeup, to allow host |
| 255 | * access to device-internal resources. Host must wait for |
| 256 | * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR |
| 257 | * device registers. |
| 258 | * 2: INIT_DONE |
| 259 | * Host sets this to put device into fully operational D0 power mode. |
| 260 | * Host resets this after SW_RESET to put device into low power mode. |
| 261 | * 0: MAC_CLOCK_READY |
| 262 | * Indicates MAC (ucode processor, etc.) is powered up and can run. |
| 263 | * Internal resources are accessible. |
| 264 | * NOTE: This does not indicate that the processor is actually running. |
| 265 | * NOTE: This does not indicate that device has completed |
| 266 | * init or post-power-down restore of internal SRAM memory. |
| 267 | * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that |
| 268 | * SRAM is restored and uCode is in normal operation mode. |
| 269 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and |
| 270 | * do not need to save/restore it. |
| 271 | * NOTE: After device reset, this bit remains "0" until host sets |
| 272 | * INIT_DONE |
| 273 | */ |
| 274 | #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
| 275 | #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) |
| 276 | #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) |
| 277 | #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) |
| 278 | |
| 279 | #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) |
| 280 | |
| 281 | #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) |
| 282 | #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) |
| 283 | #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) |
| 284 | |
| 285 | |
| 286 | /* HW REV */ |
| 287 | #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) |
| 288 | #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) |
| 289 | |
| 290 | #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) |
| 291 | #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) |
| 292 | #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) |
| 293 | #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) |
| 294 | #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) |
| 295 | #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) |
| 296 | #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) |
| 297 | #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) |
| 298 | #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) |
| 299 | #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) |
| 300 | #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 |
| 301 | #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 |
| 302 | #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) |
| 303 | #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) |
| 304 | #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) |
| 305 | #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) |
| 306 | #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) |
| 307 | |
| 308 | /* EEPROM REG */ |
| 309 | #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) |
| 310 | #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) |
| 311 | #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
| 312 | #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) |
| 313 | |
| 314 | /* EEPROM GP */ |
| 315 | #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
| 316 | #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
| 317 | #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) |
| 318 | #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) |
| 319 | #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) |
| 320 | #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) |
| 321 | |
| 322 | /* One-time-programmable memory general purpose reg */ |
| 323 | #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ |
| 324 | #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ |
| 325 | #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ |
| 326 | #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ |
| 327 | |
| 328 | /* GP REG */ |
| 329 | #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
| 330 | #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) |
| 331 | #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) |
| 332 | #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) |
| 333 | #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) |
| 334 | |
| 335 | |
| 336 | /* CSR GIO */ |
| 337 | #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) |
| 338 | |
| 339 | /* |
| 340 | * UCODE-DRIVER GP (general purpose) mailbox register 1 |
| 341 | * Host driver and uCode write and/or read this register to communicate with |
| 342 | * each other. |
| 343 | * Bit fields: |
| 344 | * 4: UCODE_DISABLE |
| 345 | * Host sets this to request permanent halt of uCode, same as |
| 346 | * sending CARD_STATE command with "halt" bit set. |
| 347 | * 3: CT_KILL_EXIT |
| 348 | * Host sets this to request exit from CT_KILL state, i.e. host thinks |
| 349 | * device temperature is low enough to continue normal operation. |
| 350 | * 2: CMD_BLOCKED |
| 351 | * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) |
| 352 | * to release uCode to clear all Tx and command queues, enter |
| 353 | * unassociated mode, and power down. |
| 354 | * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. |
| 355 | * 1: SW_BIT_RFKILL |
| 356 | * Host sets this when issuing CARD_STATE command to request |
| 357 | * device sleep. |
| 358 | * 0: MAC_SLEEP |
| 359 | * uCode sets this when preparing a power-saving power-down. |
| 360 | * uCode resets this when power-up is complete and SRAM is sane. |
| 361 | * NOTE: device saves internal SRAM data to host when powering down, |
| 362 | * and must restore this data after powering back up. |
| 363 | * MAC_SLEEP is the best indication that restore is complete. |
| 364 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and |
| 365 | * do not need to save/restore it. |
| 366 | */ |
| 367 | #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
| 368 | #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) |
| 369 | #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) |
| 370 | #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) |
| 371 | #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) |
| 372 | |
| 373 | /* GP Driver */ |
| 374 | #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) |
| 375 | #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) |
| 376 | #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) |
| 377 | #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) |
| 378 | #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) |
| 379 | #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) |
| 380 | |
| 381 | #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) |
| 382 | |
| 383 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
| 384 | #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
| 385 | #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
| 386 | |
| 387 | /* LED */ |
| 388 | #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) |
| 389 | #define IWM_CSR_LED_REG_TURN_ON (0x60) |
| 390 | #define IWM_CSR_LED_REG_TURN_OFF (0x20) |
| 391 | |
| 392 | /* ANA_PLL */ |
| 393 | #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) |
| 394 | |
| 395 | /* HPET MEM debug */ |
| 396 | #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) |
| 397 | |
| 398 | /* DRAM INT TABLE */ |
| 399 | #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) |
| 400 | #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) |
| 401 | |
| 402 | /* SECURE boot registers */ |
| 403 | #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) |
| 404 | enum iwm_secure_boot_config_reg { |
| 405 | IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, |
| 406 | IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, |
| 407 | }; |
| 408 | |
| 409 | #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) |
| 410 | #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) |
| 411 | enum iwm_secure_boot_status_reg { |
| 412 | IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, |
| 413 | IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, |
| 414 | IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, |
| 415 | IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, |
| 416 | IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, |
| 417 | }; |
| 418 | |
| 419 | #define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100) |
| 420 | enum iwm_secure_load_status_reg { |
| 421 | IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001, |
| 422 | IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002, |
| 423 | IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, |
| 424 | IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, |
| 425 | }; |
| 426 | |
| 427 | #define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100) |
| 428 | #define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100) |
| 429 | |
| 430 | #define IWM_CSR_SECURE_TIME_OUT (100) |
| 431 | |
| 432 | #define IWM_FH_TCSR_0_REG0 (0x1D00) |
| 433 | |
| 434 | /* |
| 435 | * HBUS (Host-side Bus) |
| 436 | * |
| 437 | * HBUS registers are mapped directly into PCI bus space, but are used |
| 438 | * to indirectly access device's internal memory or registers that |
| 439 | * may be powered-down. |
| 440 | * |
| 441 | * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; |
| 442 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ |
| 443 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing |
| 444 | * internal resources. |
| 445 | * |
| 446 | * Do not use iwl_write32()/iwl_read32() family to access these registers; |
| 447 | * these provide only simple PCI bus access, without waking up the MAC. |
| 448 | */ |
| 449 | #define IWM_HBUS_BASE (0x400) |
| 450 | |
| 451 | /* |
| 452 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM |
| 453 | * structures, error log, event log, verifying uCode load). |
| 454 | * First write to address register, then read from or write to data register |
| 455 | * to complete the job. Once the address register is set up, accesses to |
| 456 | * data registers auto-increment the address by one dword. |
| 457 | * Bit usage for address registers (read or write): |
| 458 | * 0-31: memory address within device |
| 459 | */ |
| 460 | #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) |
| 461 | #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) |
| 462 | #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) |
| 463 | #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) |
| 464 | |
| 465 | /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ |
| 466 | #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) |
| 467 | #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) |
| 468 | |
| 469 | /* |
| 470 | * Registers for accessing device's internal peripheral registers |
| 471 | * (e.g. SCD, BSM, etc.). First write to address register, |
| 472 | * then read from or write to data register to complete the job. |
| 473 | * Bit usage for address registers (read or write): |
| 474 | * 0-15: register address (offset) within device |
| 475 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) |
| 476 | */ |
| 477 | #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) |
| 478 | #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) |
| 479 | #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) |
| 480 | #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) |
| 481 | |
| 482 | /* Used to enable DBGM */ |
| 483 | #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) |
| 484 | |
| 485 | /* |
| 486 | * Per-Tx-queue write pointer (index, really!) |
| 487 | * Indicates index to next TFD that driver will fill (1 past latest filled). |
| 488 | * Bit usage: |
| 489 | * 0-7: queue write index |
| 490 | * 11-8: queue selector |
| 491 | */ |
| 492 | #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) |
| 493 | |
| 494 | /********************************************************** |
| 495 | * CSR values |
| 496 | **********************************************************/ |
| 497 | /* |
| 498 | * host interrupt timeout value |
| 499 | * used with setting interrupt coalescing timer |
| 500 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit |
| 501 | * |
| 502 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs |
| 503 | */ |
| 504 | #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) |
| 505 | #define IWM_HOST_INT_TIMEOUT_DEF (0x40) |
| 506 | #define IWM_HOST_INT_TIMEOUT_MIN (0x0) |
| 507 | #define IWM_HOST_INT_OPER_MODE (1 << 31) |
| 508 | |
| 509 | /***************************************************************************** |
| 510 | * 7000/3000 series SHR DTS addresses * |
| 511 | *****************************************************************************/ |
| 512 | |
| 513 | /* Diode Results Register Structure: */ |
| 514 | enum iwm_dtd_diode_reg { |
| 515 | IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ |
| 516 | IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ |
| 517 | IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ |
| 518 | IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ |
| 519 | IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ |
| 520 | IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ |
| 521 | /* Those are the masks INSIDE the flags bit-field: */ |
| 522 | IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, |
| 523 | IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ |
| 524 | IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, |
| 525 | IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ |
| 526 | }; |
| 527 | |
| 528 | /* |
| 529 | * END iwl-csr.h |
| 530 | */ |
| 531 | |
| 532 | /* |
| 533 | * BEGIN iwl-fw.h |
| 534 | */ |
| 535 | |
| 536 | /** |
| 537 | * enum iwl_ucode_tlv_flag - ucode API flags |
| 538 | * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously |
| 539 | * was a separate TLV but moved here to save space. |
| 540 | * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, |
| 541 | * treats good CRC threshold as a boolean |
| 542 | * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). |
| 543 | * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. |
| 544 | * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS |
| 545 | * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD |
| 546 | * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan |
| 547 | * offload profile config command. |
| 548 | * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api |
| 549 | * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. |
| 550 | * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six |
| 551 | * (rather than two) IPv6 addresses |
| 552 | * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API |
| 553 | * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element |
| 554 | * from the probe request template. |
| 555 | * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping |
| 556 | * connection when going back to D0 |
| 557 | * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) |
| 558 | * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) |
| 559 | * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. |
| 560 | * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API |
| 561 | * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command |
| 562 | * containing CAM (Continuous Active Mode) indication. |
| 563 | * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a |
| 564 | * single bound interface). |
| 565 | * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save |
| 566 | */ |
| 567 | enum iwm_ucode_tlv_flag { |
| 568 | IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), |
| 569 | IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), |
| 570 | IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), |
| 571 | IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), |
| 572 | IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), |
| 573 | IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), |
| 574 | IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), |
| 575 | IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), |
| 576 | IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), |
| 577 | IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), |
| 578 | IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), |
| 579 | IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), |
| 580 | IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), |
| 581 | IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), |
| 582 | IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), |
| 583 | IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), |
| 584 | IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), |
| 585 | IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), |
| 586 | IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), |
| 587 | IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), |
| 588 | IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), |
| 589 | IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), |
| 590 | }; |
| 591 | |
| 592 | /* The default calibrate table size if not specified by firmware file */ |
| 593 | #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 |
| 594 | #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 |
| 595 | #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 |
| 596 | |
| 597 | /* The default max probe length if not specified by the firmware file */ |
| 598 | #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 |
| 599 | |
| 600 | /* |
| 601 | * enumeration of ucode section. |
| 602 | * This enumeration is used directly for older firmware (before 16.0). |
| 603 | * For new firmware, there can be up to 4 sections (see below) but the |
| 604 | * first one packaged into the firmware file is the DATA section and |
| 605 | * some debugging code accesses that. |
| 606 | */ |
| 607 | enum iwm_ucode_sec { |
| 608 | IWM_UCODE_SECTION_DATA, |
| 609 | IWM_UCODE_SECTION_INST, |
| 610 | }; |
| 611 | /* |
| 612 | * For 16.0 uCode and above, there is no differentiation between sections, |
| 613 | * just an offset to the HW address. |
| 614 | */ |
| 615 | #define IWM_UCODE_SECTION_MAX 6 |
| 616 | #define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2) |
| 617 | |
| 618 | /* uCode version contains 4 values: Major/Minor/API/Serial */ |
| 619 | #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) |
| 620 | #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) |
| 621 | #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) |
| 622 | #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) |
| 623 | |
| 624 | /* |
| 625 | * Calibration control struct. |
| 626 | * Sent as part of the phy configuration command. |
| 627 | * @flow_trigger: bitmap for which calibrations to perform according to |
| 628 | * flow triggers. |
| 629 | * @event_trigger: bitmap for which calibrations to perform according to |
| 630 | * event triggers. |
| 631 | */ |
| 632 | struct iwm_tlv_calib_ctrl { |
| 633 | uint32_t flow_trigger; |
| 634 | uint32_t event_trigger; |
| 635 | } __packed; |
| 636 | |
| 637 | enum iwm_fw_phy_cfg { |
| 638 | IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, |
| 639 | IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, |
| 640 | IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, |
| 641 | IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, |
| 642 | IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, |
| 643 | IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, |
| 644 | IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, |
| 645 | IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, |
| 646 | IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, |
| 647 | IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, |
| 648 | }; |
| 649 | |
| 650 | #define IWM_UCODE_MAX_CS 1 |
| 651 | |
| 652 | /** |
| 653 | * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. |
| 654 | * @cipher: a cipher suite selector |
| 655 | * @flags: cipher scheme flags (currently reserved for a future use) |
| 656 | * @hdr_len: a size of MPDU security header |
| 657 | * @pn_len: a size of PN |
| 658 | * @pn_off: an offset of pn from the beginning of the security header |
| 659 | * @key_idx_off: an offset of key index byte in the security header |
| 660 | * @key_idx_mask: a bit mask of key_idx bits |
| 661 | * @key_idx_shift: bit shift needed to get key_idx |
| 662 | * @mic_len: mic length in bytes |
| 663 | * @hw_cipher: a HW cipher index used in host commands |
| 664 | */ |
| 665 | struct iwm_fw_cipher_scheme { |
| 666 | uint32_t cipher; |
| 667 | uint8_t flags; |
| 668 | uint8_t hdr_len; |
| 669 | uint8_t pn_len; |
| 670 | uint8_t pn_off; |
| 671 | uint8_t key_idx_off; |
| 672 | uint8_t key_idx_mask; |
| 673 | uint8_t key_idx_shift; |
| 674 | uint8_t mic_len; |
| 675 | uint8_t hw_cipher; |
| 676 | } __packed; |
| 677 | |
| 678 | /** |
| 679 | * struct iwm_fw_cscheme_list - a cipher scheme list |
| 680 | * @size: a number of entries |
| 681 | * @cs: cipher scheme entries |
| 682 | */ |
| 683 | struct iwm_fw_cscheme_list { |
| 684 | uint8_t size; |
| 685 | struct iwm_fw_cipher_scheme cs[]; |
| 686 | } __packed; |
| 687 | |
| 688 | /* |
| 689 | * END iwl-fw.h |
| 690 | */ |
| 691 | |
| 692 | /* |
| 693 | * BEGIN iwl-fw-file.h |
| 694 | */ |
| 695 | |
| 696 | /* v1/v2 uCode file layout */ |
| 697 | struct { |
| 698 | uint32_t ; /* major/minor/API/serial */ |
| 699 | union { |
| 700 | struct { |
| 701 | uint32_t ; /* bytes of runtime code */ |
| 702 | uint32_t ; /* bytes of runtime data */ |
| 703 | uint32_t ; /* bytes of init code */ |
| 704 | uint32_t ; /* bytes of init data */ |
| 705 | uint32_t ; /* bytes of bootstrap code */ |
| 706 | uint8_t [0]; /* in same order as sizes */ |
| 707 | } ; |
| 708 | struct { |
| 709 | uint32_t ; /* build number */ |
| 710 | uint32_t ; /* bytes of runtime code */ |
| 711 | uint32_t ; /* bytes of runtime data */ |
| 712 | uint32_t ; /* bytes of init code */ |
| 713 | uint32_t ; /* bytes of init data */ |
| 714 | uint32_t ; /* bytes of bootstrap code */ |
| 715 | uint8_t [0]; /* in same order as sizes */ |
| 716 | } ; |
| 717 | } ; |
| 718 | }; |
| 719 | |
| 720 | /* |
| 721 | * new TLV uCode file layout |
| 722 | * |
| 723 | * The new TLV file format contains TLVs, that each specify |
| 724 | * some piece of data. |
| 725 | */ |
| 726 | |
| 727 | enum iwm_ucode_tlv_type { |
| 728 | IWM_UCODE_TLV_INVALID = 0, /* unused */ |
| 729 | IWM_UCODE_TLV_INST = 1, |
| 730 | IWM_UCODE_TLV_DATA = 2, |
| 731 | IWM_UCODE_TLV_INIT = 3, |
| 732 | IWM_UCODE_TLV_INIT_DATA = 4, |
| 733 | IWM_UCODE_TLV_BOOT = 5, |
| 734 | IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ |
| 735 | IWM_UCODE_TLV_PAN = 7, |
| 736 | IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, |
| 737 | IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, |
| 738 | IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, |
| 739 | IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, |
| 740 | IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, |
| 741 | IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, |
| 742 | IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, |
| 743 | IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, |
| 744 | IWM_UCODE_TLV_WOWLAN_INST = 16, |
| 745 | IWM_UCODE_TLV_WOWLAN_DATA = 17, |
| 746 | IWM_UCODE_TLV_FLAGS = 18, |
| 747 | IWM_UCODE_TLV_SEC_RT = 19, |
| 748 | IWM_UCODE_TLV_SEC_INIT = 20, |
| 749 | IWM_UCODE_TLV_SEC_WOWLAN = 21, |
| 750 | IWM_UCODE_TLV_DEF_CALIB = 22, |
| 751 | IWM_UCODE_TLV_PHY_SKU = 23, |
| 752 | IWM_UCODE_TLV_SECURE_SEC_RT = 24, |
| 753 | IWM_UCODE_TLV_SECURE_SEC_INIT = 25, |
| 754 | IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, |
| 755 | IWM_UCODE_TLV_NUM_OF_CPU = 27, |
| 756 | IWM_UCODE_TLV_CSCHEME = 28, |
| 757 | |
| 758 | /* |
| 759 | * Following two are not in our base tag, but allow |
| 760 | * handling ucode version 9. |
| 761 | */ |
| 762 | IWM_UCODE_TLV_API_CHANGES_SET = 29, |
| 763 | IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30 |
| 764 | }; |
| 765 | |
| 766 | struct iwm_ucode_tlv { |
| 767 | uint32_t type; /* see above */ |
| 768 | uint32_t length; /* not including type/length fields */ |
| 769 | uint8_t data[0]; |
| 770 | }; |
| 771 | |
| 772 | #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 |
| 773 | |
| 774 | struct { |
| 775 | /* |
| 776 | * The TLV style ucode header is distinguished from |
| 777 | * the v1/v2 style header by first four bytes being |
| 778 | * zero, as such is an invalid combination of |
| 779 | * major/minor/API/serial versions. |
| 780 | */ |
| 781 | uint32_t ; |
| 782 | uint32_t ; |
| 783 | uint8_t [64]; |
| 784 | uint32_t ; /* major/minor/API/serial */ |
| 785 | uint32_t ; |
| 786 | uint64_t ; |
| 787 | /* |
| 788 | * The data contained herein has a TLV layout, |
| 789 | * see above for the TLV header and types. |
| 790 | * Note that each TLV is padded to a length |
| 791 | * that is a multiple of 4 for alignment. |
| 792 | */ |
| 793 | uint8_t [0]; |
| 794 | }; |
| 795 | |
| 796 | /* |
| 797 | * END iwl-fw-file.h |
| 798 | */ |
| 799 | |
| 800 | /* |
| 801 | * BEGIN iwl-prph.h |
| 802 | */ |
| 803 | |
| 804 | /* |
| 805 | * Registers in this file are internal, not PCI bus memory mapped. |
| 806 | * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. |
| 807 | */ |
| 808 | #define IWM_PRPH_BASE (0x00000) |
| 809 | #define IWM_PRPH_END (0xFFFFF) |
| 810 | |
| 811 | /* APMG (power management) constants */ |
| 812 | #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) |
| 813 | #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) |
| 814 | #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) |
| 815 | #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) |
| 816 | #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) |
| 817 | #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) |
| 818 | #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) |
| 819 | #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) |
| 820 | #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) |
| 821 | #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) |
| 822 | #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) |
| 823 | |
| 824 | #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
| 825 | #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
| 826 | #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) |
| 827 | |
| 828 | #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
| 829 | #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) |
| 830 | #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) |
| 831 | #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) |
| 832 | #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
| 833 | #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
| 834 | #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) |
| 835 | |
| 836 | #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
| 837 | |
| 838 | #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) |
| 839 | |
| 840 | /* Device system time */ |
| 841 | #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C |
| 842 | |
| 843 | /* Device NMI register */ |
| 844 | #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 |
| 845 | |
| 846 | /***************************************************************************** |
| 847 | * 7000/3000 series SHR DTS addresses * |
| 848 | *****************************************************************************/ |
| 849 | |
| 850 | #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) |
| 851 | #define IWM_DTSC_CFG_MODE (0x00a10604) |
| 852 | #define IWM_DTSC_VREF_AVG (0x00a10648) |
| 853 | #define IWM_DTSC_VREF5_AVG (0x00a1064c) |
| 854 | #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) |
| 855 | #define IWM_DTSC_PTAT_AVG (0x00a10650) |
| 856 | |
| 857 | |
| 858 | /** |
| 859 | * Tx Scheduler |
| 860 | * |
| 861 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
| 862 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
| 863 | * host DRAM. It steers each frame's Tx command (which contains the frame |
| 864 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the |
| 865 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, |
| 866 | * but one DMA channel may take input from several queues. |
| 867 | * |
| 868 | * Tx DMA FIFOs have dedicated purposes. |
| 869 | * |
| 870 | * For 5000 series and up, they are used differently |
| 871 | * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): |
| 872 | * |
| 873 | * 0 -- EDCA BK (background) frames, lowest priority |
| 874 | * 1 -- EDCA BE (best effort) frames, normal priority |
| 875 | * 2 -- EDCA VI (video) frames, higher priority |
| 876 | * 3 -- EDCA VO (voice) and management frames, highest priority |
| 877 | * 4 -- unused |
| 878 | * 5 -- unused |
| 879 | * 6 -- unused |
| 880 | * 7 -- Commands |
| 881 | * |
| 882 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
| 883 | * In addition, driver can map the remaining queues to Tx DMA/FIFO |
| 884 | * channels 0-3 to support 11n aggregation via EDCA DMA channels. |
| 885 | * |
| 886 | * The driver sets up each queue to work in one of two modes: |
| 887 | * |
| 888 | * 1) Scheduler-Ack, in which the scheduler automatically supports a |
| 889 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue |
| 890 | * contains TFDs for a unique combination of Recipient Address (RA) |
| 891 | * and Traffic Identifier (TID), that is, traffic of a given |
| 892 | * Quality-Of-Service (QOS) priority, destined for a single station. |
| 893 | * |
| 894 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of |
| 895 | * each frame within the BA window, including whether it's been transmitted, |
| 896 | * and whether it's been acknowledged by the receiving station. The device |
| 897 | * automatically processes block-acks received from the receiving STA, |
| 898 | * and reschedules un-acked frames to be retransmitted (successful |
| 899 | * Tx completion may end up being out-of-order). |
| 900 | * |
| 901 | * The driver must maintain the queue's Byte Count table in host DRAM |
| 902 | * for this mode. |
| 903 | * This mode does not support fragmentation. |
| 904 | * |
| 905 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. |
| 906 | * The device may automatically retry Tx, but will retry only one frame |
| 907 | * at a time, until receiving ACK from receiving station, or reaching |
| 908 | * retry limit and giving up. |
| 909 | * |
| 910 | * The command queue (#4/#9) must use this mode! |
| 911 | * This mode does not require use of the Byte Count table in host DRAM. |
| 912 | * |
| 913 | * Driver controls scheduler operation via 3 means: |
| 914 | * 1) Scheduler registers |
| 915 | * 2) Shared scheduler data base in internal SRAM |
| 916 | * 3) Shared data in host DRAM |
| 917 | * |
| 918 | * Initialization: |
| 919 | * |
| 920 | * When loading, driver should allocate memory for: |
| 921 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. |
| 922 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory |
| 923 | * (1024 bytes for each queue). |
| 924 | * |
| 925 | * After receiving "Alive" response from uCode, driver must initialize |
| 926 | * the scheduler (especially for queue #4/#9, the command queue, otherwise |
| 927 | * the driver can't issue commands!): |
| 928 | */ |
| 929 | #define IWM_SCD_MEM_LOWER_BOUND (0x0000) |
| 930 | |
| 931 | /** |
| 932 | * Max Tx window size is the max number of contiguous TFDs that the scheduler |
| 933 | * can keep track of at one time when creating block-ack chains of frames. |
| 934 | * Note that "64" matches the number of ack bits in a block-ack packet. |
| 935 | */ |
| 936 | #define IWM_SCD_WIN_SIZE 64 |
| 937 | #define IWM_SCD_FRAME_LIMIT 64 |
| 938 | |
| 939 | #define IWM_SCD_TXFIFO_POS_TID (0) |
| 940 | #define IWM_SCD_TXFIFO_POS_RA (4) |
| 941 | #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) |
| 942 | |
| 943 | /* agn SCD */ |
| 944 | #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) |
| 945 | #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) |
| 946 | #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) |
| 947 | #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) |
| 948 | #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) |
| 949 | |
| 950 | #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) |
| 951 | #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) |
| 952 | #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) |
| 953 | #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) |
| 954 | #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) |
| 955 | #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) |
| 956 | #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
| 957 | #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) |
| 958 | |
| 959 | /* Context Data */ |
| 960 | #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) |
| 961 | #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) |
| 962 | |
| 963 | /* Tx status */ |
| 964 | #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) |
| 965 | #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) |
| 966 | |
| 967 | /* Translation Data */ |
| 968 | #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) |
| 969 | #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) |
| 970 | |
| 971 | #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ |
| 972 | (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) |
| 973 | |
| 974 | #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ |
| 975 | (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) |
| 976 | |
| 977 | #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ |
| 978 | ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) |
| 979 | |
| 980 | #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) |
| 981 | |
| 982 | #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) |
| 983 | #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) |
| 984 | #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) |
| 985 | #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) |
| 986 | #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) |
| 987 | #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) |
| 988 | #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) |
| 989 | #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) |
| 990 | #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) |
| 991 | |
| 992 | static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) |
| 993 | { |
| 994 | if (chnl < 20) |
| 995 | return IWM_SCD_BASE + 0x18 + chnl * 4; |
| 996 | return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; |
| 997 | } |
| 998 | |
| 999 | static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) |
| 1000 | { |
| 1001 | if (chnl < 20) |
| 1002 | return IWM_SCD_BASE + 0x68 + chnl * 4; |
| 1003 | return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; |
| 1004 | } |
| 1005 | |
| 1006 | static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) |
| 1007 | { |
| 1008 | if (chnl < 20) |
| 1009 | return IWM_SCD_BASE + 0x10c + chnl * 4; |
| 1010 | return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; |
| 1011 | } |
| 1012 | |
| 1013 | /*********************** END TX SCHEDULER *************************************/ |
| 1014 | |
| 1015 | /* Oscillator clock */ |
| 1016 | #define IWM_OSC_CLK (0xa04068) |
| 1017 | #define IWM_OSC_CLK_FORCE_CONTROL (0x8) |
| 1018 | |
| 1019 | /* |
| 1020 | * END iwl-prph.h |
| 1021 | */ |
| 1022 | |
| 1023 | /* |
| 1024 | * BEGIN iwl-fh.h |
| 1025 | */ |
| 1026 | |
| 1027 | /****************************/ |
| 1028 | /* Flow Handler Definitions */ |
| 1029 | /****************************/ |
| 1030 | |
| 1031 | /** |
| 1032 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) |
| 1033 | * Addresses are offsets from device's PCI hardware base address. |
| 1034 | */ |
| 1035 | #define IWM_FH_MEM_LOWER_BOUND (0x1000) |
| 1036 | #define IWM_FH_MEM_UPPER_BOUND (0x2000) |
| 1037 | |
| 1038 | /** |
| 1039 | * Keep-Warm (KW) buffer base address. |
| 1040 | * |
| 1041 | * Driver must allocate a 4KByte buffer that is for keeping the |
| 1042 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency |
| 1043 | * DRAM access when doing Txing or Rxing. The dummy accesses prevent host |
| 1044 | * from going into a power-savings mode that would cause higher DRAM latency, |
| 1045 | * and possible data over/under-runs, before all Tx/Rx is complete. |
| 1046 | * |
| 1047 | * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) |
| 1048 | * of the buffer, which must be 4K aligned. Once this is set up, the device |
| 1049 | * automatically invokes keep-warm accesses when normal accesses might not |
| 1050 | * be sufficient to maintain fast DRAM response. |
| 1051 | * |
| 1052 | * Bit fields: |
| 1053 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned |
| 1054 | */ |
| 1055 | #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) |
| 1056 | |
| 1057 | |
| 1058 | /** |
| 1059 | * TFD Circular Buffers Base (CBBC) addresses |
| 1060 | * |
| 1061 | * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident |
| 1062 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) |
| 1063 | * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 |
| 1064 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte |
| 1065 | * aligned (address bits 0-7 must be 0). |
| 1066 | * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers |
| 1067 | * for them are in different places. |
| 1068 | * |
| 1069 | * Bit fields in each pointer register: |
| 1070 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned |
| 1071 | */ |
| 1072 | #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) |
| 1073 | #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) |
| 1074 | #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) |
| 1075 | #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) |
| 1076 | #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) |
| 1077 | #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) |
| 1078 | |
| 1079 | /* Find TFD CB base pointer for given queue */ |
| 1080 | static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) |
| 1081 | { |
| 1082 | if (chnl < 16) |
| 1083 | return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; |
| 1084 | if (chnl < 20) |
| 1085 | return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); |
| 1086 | return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); |
| 1087 | } |
| 1088 | |
| 1089 | |
| 1090 | /** |
| 1091 | * Rx SRAM Control and Status Registers (RSCSR) |
| 1092 | * |
| 1093 | * These registers provide handshake between driver and device for the Rx queue |
| 1094 | * (this queue handles *all* command responses, notifications, Rx data, etc. |
| 1095 | * sent from uCode to host driver). Unlike Tx, there is only one Rx |
| 1096 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can |
| 1097 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer |
| 1098 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 |
| 1099 | * mapping between RBDs and RBs. |
| 1100 | * |
| 1101 | * Driver must allocate host DRAM memory for the following, and set the |
| 1102 | * physical address of each into device registers: |
| 1103 | * |
| 1104 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 |
| 1105 | * entries (although any power of 2, up to 4096, is selectable by driver). |
| 1106 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size |
| 1107 | * (typically 4K, although 8K or 16K are also selectable by driver). |
| 1108 | * Driver sets up RB size and number of RBDs in the CB via Rx config |
| 1109 | * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. |
| 1110 | * |
| 1111 | * Bit fields within one RBD: |
| 1112 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned |
| 1113 | * |
| 1114 | * Driver sets physical address [35:8] of base of RBD circular buffer |
| 1115 | * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. |
| 1116 | * |
| 1117 | * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers |
| 1118 | * (RBs) have been filled, via a "write pointer", actually the index of |
| 1119 | * the RB's corresponding RBD within the circular buffer. Driver sets |
| 1120 | * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. |
| 1121 | * |
| 1122 | * Bit fields in lower dword of Rx status buffer (upper dword not used |
| 1123 | * by driver: |
| 1124 | * 31-12: Not used by driver |
| 1125 | * 11- 0: Index of last filled Rx buffer descriptor |
| 1126 | * (device writes, driver reads this value) |
| 1127 | * |
| 1128 | * As the driver prepares Receive Buffers (RBs) for device to fill, driver must |
| 1129 | * enter pointers to these RBs into contiguous RBD circular buffer entries, |
| 1130 | * and update the device's "write" index register, |
| 1131 | * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. |
| 1132 | * |
| 1133 | * This "write" index corresponds to the *next* RBD that the driver will make |
| 1134 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within |
| 1135 | * the circular buffer. This value should initially be 0 (before preparing any |
| 1136 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must |
| 1137 | * wrap back to 0 at the end of the circular buffer (but don't wrap before |
| 1138 | * "read" index has advanced past 1! See below). |
| 1139 | * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. |
| 1140 | * |
| 1141 | * As the device fills RBs (referenced from contiguous RBDs within the circular |
| 1142 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, |
| 1143 | * to tell the driver the index of the latest filled RBD. The driver must |
| 1144 | * read this "read" index from DRAM after receiving an Rx interrupt from device |
| 1145 | * |
| 1146 | * The driver must also internally keep track of a third index, which is the |
| 1147 | * next RBD to process. When receiving an Rx interrupt, driver should process |
| 1148 | * all filled but unprocessed RBs up to, but not including, the RB |
| 1149 | * corresponding to the "read" index. For example, if "read" index becomes "1", |
| 1150 | * driver may process the RB pointed to by RBD 0. Depending on volume of |
| 1151 | * traffic, there may be many RBs to process. |
| 1152 | * |
| 1153 | * If read index == write index, device thinks there is no room to put new data. |
| 1154 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To |
| 1155 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" |
| 1156 | * and "read" indexes; that is, make sure that there are no more than 254 |
| 1157 | * buffers waiting to be filled. |
| 1158 | */ |
| 1159 | #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) |
| 1160 | #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) |
| 1161 | #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) |
| 1162 | |
| 1163 | /** |
| 1164 | * Physical base address of 8-byte Rx Status buffer. |
| 1165 | * Bit fields: |
| 1166 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. |
| 1167 | */ |
| 1168 | #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) |
| 1169 | |
| 1170 | /** |
| 1171 | * Physical base address of Rx Buffer Descriptor Circular Buffer. |
| 1172 | * Bit fields: |
| 1173 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. |
| 1174 | */ |
| 1175 | #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) |
| 1176 | |
| 1177 | /** |
| 1178 | * Rx write pointer (index, really!). |
| 1179 | * Bit fields: |
| 1180 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. |
| 1181 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. |
| 1182 | */ |
| 1183 | #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) |
| 1184 | #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) |
| 1185 | |
| 1186 | #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) |
| 1187 | #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG |
| 1188 | |
| 1189 | /** |
| 1190 | * Rx Config/Status Registers (RCSR) |
| 1191 | * Rx Config Reg for channel 0 (only channel used) |
| 1192 | * |
| 1193 | * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for |
| 1194 | * normal operation (see bit fields). |
| 1195 | * |
| 1196 | * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. |
| 1197 | * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for |
| 1198 | * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. |
| 1199 | * |
| 1200 | * Bit fields: |
| 1201 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, |
| 1202 | * '10' operate normally |
| 1203 | * 29-24: reserved |
| 1204 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), |
| 1205 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. |
| 1206 | * 19-18: reserved |
| 1207 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, |
| 1208 | * '10' 12K, '11' 16K. |
| 1209 | * 15-14: reserved |
| 1210 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) |
| 1211 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) |
| 1212 | * typical value 0x10 (about 1/2 msec) |
| 1213 | * 3- 0: reserved |
| 1214 | */ |
| 1215 | #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) |
| 1216 | #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) |
| 1217 | #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) |
| 1218 | |
| 1219 | #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) |
| 1220 | #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) |
| 1221 | #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) |
| 1222 | |
| 1223 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ |
| 1224 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ |
| 1225 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ |
| 1226 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ |
| 1227 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ |
| 1228 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ |
| 1229 | |
| 1230 | #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) |
| 1231 | #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) |
| 1232 | #define IWM_RX_RB_TIMEOUT (0x11) |
| 1233 | |
| 1234 | #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) |
| 1235 | #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) |
| 1236 | #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) |
| 1237 | |
| 1238 | #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) |
| 1239 | #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) |
| 1240 | #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) |
| 1241 | #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) |
| 1242 | |
| 1243 | #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) |
| 1244 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) |
| 1245 | #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) |
| 1246 | |
| 1247 | /** |
| 1248 | * Rx Shared Status Registers (RSSR) |
| 1249 | * |
| 1250 | * After stopping Rx DMA channel (writing 0 to |
| 1251 | * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll |
| 1252 | * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. |
| 1253 | * |
| 1254 | * Bit fields: |
| 1255 | * 24: 1 = Channel 0 is idle |
| 1256 | * |
| 1257 | * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV |
| 1258 | * contain default values that should not be altered by the driver. |
| 1259 | */ |
| 1260 | #define (IWM_FH_MEM_LOWER_BOUND + 0xC40) |
| 1261 | #define (IWM_FH_MEM_LOWER_BOUND + 0xD00) |
| 1262 | |
| 1263 | #define (IWM_FH_MEM_RSSR_LOWER_BOUND) |
| 1264 | #define (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) |
| 1265 | #define \ |
| 1266 | (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) |
| 1267 | |
| 1268 | #define (0x01000000) |
| 1269 | |
| 1270 | #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 |
| 1271 | |
| 1272 | /* TFDB Area - TFDs buffer table */ |
| 1273 | #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) |
| 1274 | #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) |
| 1275 | #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) |
| 1276 | #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) |
| 1277 | #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) |
| 1278 | |
| 1279 | /** |
| 1280 | * Transmit DMA Channel Control/Status Registers (TCSR) |
| 1281 | * |
| 1282 | * Device has one configuration register for each of 8 Tx DMA/FIFO channels |
| 1283 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, |
| 1284 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. |
| 1285 | * |
| 1286 | * To use a Tx DMA channel, driver must initialize its |
| 1287 | * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: |
| 1288 | * |
| 1289 | * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
| 1290 | * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
| 1291 | * |
| 1292 | * All other bits should be 0. |
| 1293 | * |
| 1294 | * Bit fields: |
| 1295 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, |
| 1296 | * '10' operate normally |
| 1297 | * 29- 4: Reserved, set to "0" |
| 1298 | * 3: Enable internal DMA requests (1, normal operation), disable (0) |
| 1299 | * 2- 0: Reserved, set to "0" |
| 1300 | */ |
| 1301 | #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) |
| 1302 | #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) |
| 1303 | |
| 1304 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ |
| 1305 | #define IWM_FH_TCSR_CHNL_NUM (8) |
| 1306 | |
| 1307 | /* TCSR: tx_config register values */ |
| 1308 | #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
| 1309 | (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) |
| 1310 | #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ |
| 1311 | (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) |
| 1312 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ |
| 1313 | (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) |
| 1314 | |
| 1315 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
| 1316 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) |
| 1317 | |
| 1318 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) |
| 1319 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) |
| 1320 | |
| 1321 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) |
| 1322 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) |
| 1323 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) |
| 1324 | |
| 1325 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
| 1326 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) |
| 1327 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) |
| 1328 | |
| 1329 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
| 1330 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) |
| 1331 | #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) |
| 1332 | |
| 1333 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) |
| 1334 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) |
| 1335 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) |
| 1336 | |
| 1337 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) |
| 1338 | #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) |
| 1339 | |
| 1340 | /** |
| 1341 | * Tx Shared Status Registers (TSSR) |
| 1342 | * |
| 1343 | * After stopping Tx DMA channel (writing 0 to |
| 1344 | * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll |
| 1345 | * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle |
| 1346 | * (channel's buffers empty | no pending requests). |
| 1347 | * |
| 1348 | * Bit fields: |
| 1349 | * 31-24: 1 = Channel buffers empty (channel 7:0) |
| 1350 | * 23-16: 1 = No pending requests (channel 7:0) |
| 1351 | */ |
| 1352 | #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) |
| 1353 | #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) |
| 1354 | |
| 1355 | #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) |
| 1356 | |
| 1357 | /** |
| 1358 | * Bit fields for TSSR(Tx Shared Status & Control) error status register: |
| 1359 | * 31: Indicates an address error when accessed to internal memory |
| 1360 | * uCode/driver must write "1" in order to clear this flag |
| 1361 | * 30: Indicates that Host did not send the expected number of dwords to FH |
| 1362 | * uCode/driver must write "1" in order to clear this flag |
| 1363 | * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA |
| 1364 | * command was received from the scheduler while the TRB was already full |
| 1365 | * with previous command |
| 1366 | * uCode/driver must write "1" in order to clear this flag |
| 1367 | * 7-0: Each status bit indicates a channel's TxCredit error. When an error |
| 1368 | * bit is set, it indicates that the FH has received a full indication |
| 1369 | * from the RTC TxFIFO and the current value of the TxCredit counter was |
| 1370 | * not equal to zero. This mean that the credit mechanism was not |
| 1371 | * synchronized to the TxFIFO status |
| 1372 | * uCode/driver must write "1" in order to clear this flag |
| 1373 | */ |
| 1374 | #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) |
| 1375 | #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) |
| 1376 | |
| 1377 | #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) |
| 1378 | |
| 1379 | /* Tx service channels */ |
| 1380 | #define IWM_FH_SRVC_CHNL (9) |
| 1381 | #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) |
| 1382 | #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) |
| 1383 | #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ |
| 1384 | (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) |
| 1385 | |
| 1386 | #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) |
| 1387 | #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ |
| 1388 | (_chan) * 4) |
| 1389 | |
| 1390 | /* Instruct FH to increment the retry count of a packet when |
| 1391 | * it is brought from the memory to TX-FIFO |
| 1392 | */ |
| 1393 | #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) |
| 1394 | |
| 1395 | #define IWM_RX_QUEUE_SIZE 256 |
| 1396 | #define IWM_RX_QUEUE_MASK 255 |
| 1397 | #define IWM_RX_QUEUE_SIZE_LOG 8 |
| 1398 | |
| 1399 | /* |
| 1400 | * RX related structures and functions |
| 1401 | */ |
| 1402 | #define IWM_RX_FREE_BUFFERS 64 |
| 1403 | #define IWM_RX_LOW_WATERMARK 8 |
| 1404 | |
| 1405 | /** |
| 1406 | * struct iwm_rb_status - reseve buffer status |
| 1407 | * host memory mapped FH registers |
| 1408 | * @closed_rb_num [0:11] - Indicates the index of the RB which was closed |
| 1409 | * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed |
| 1410 | * @finished_rb_num [0:11] - Indicates the index of the current RB |
| 1411 | * in which the last frame was written to |
| 1412 | * @finished_fr_num [0:11] - Indicates the index of the RX Frame |
| 1413 | * which was transferred |
| 1414 | */ |
| 1415 | struct iwm_rb_status { |
| 1416 | uint16_t closed_rb_num; |
| 1417 | uint16_t closed_fr_num; |
| 1418 | uint16_t finished_rb_num; |
| 1419 | uint16_t finished_fr_nam; |
| 1420 | uint32_t unused; |
| 1421 | } __packed; |
| 1422 | |
| 1423 | |
| 1424 | #define IWM_TFD_QUEUE_SIZE_MAX (256) |
| 1425 | #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) |
| 1426 | #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ |
| 1427 | IWM_TFD_QUEUE_SIZE_BC_DUP) |
| 1428 | #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) |
| 1429 | #define IWM_NUM_OF_TBS 20 |
| 1430 | |
| 1431 | static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) |
| 1432 | { |
| 1433 | return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; |
| 1434 | } |
| 1435 | /** |
| 1436 | * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor |
| 1437 | * |
| 1438 | * This structure contains dma address and length of transmission address |
| 1439 | * |
| 1440 | * @lo: low [31:0] portion of the dma address of TX buffer |
| 1441 | * every even is unaligned on 16 bit boundary |
| 1442 | * @hi_n_len 0-3 [35:32] portion of dma |
| 1443 | * 4-15 length of the tx buffer |
| 1444 | */ |
| 1445 | struct iwm_tfd_tb { |
| 1446 | uint32_t lo; |
| 1447 | uint16_t hi_n_len; |
| 1448 | } __packed; |
| 1449 | |
| 1450 | /** |
| 1451 | * struct iwm_tfd |
| 1452 | * |
| 1453 | * Transmit Frame Descriptor (TFD) |
| 1454 | * |
| 1455 | * @ __reserved1[3] reserved |
| 1456 | * @ num_tbs 0-4 number of active tbs |
| 1457 | * 5 reserved |
| 1458 | * 6-7 padding (not used) |
| 1459 | * @ tbs[20] transmit frame buffer descriptors |
| 1460 | * @ __pad padding |
| 1461 | * |
| 1462 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. |
| 1463 | * Both driver and device share these circular buffers, each of which must be |
| 1464 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes |
| 1465 | * |
| 1466 | * Driver must indicate the physical address of the base of each |
| 1467 | * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. |
| 1468 | * |
| 1469 | * Each TFD contains pointer/size information for up to 20 data buffers |
| 1470 | * in host DRAM. These buffers collectively contain the (one) frame described |
| 1471 | * by the TFD. Each buffer must be a single contiguous block of memory within |
| 1472 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size |
| 1473 | * of (4K - 4). The concatenates all of a TFD's buffers into a single |
| 1474 | * Tx frame, up to 8 KBytes in size. |
| 1475 | * |
| 1476 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. |
| 1477 | */ |
| 1478 | struct iwm_tfd { |
| 1479 | uint8_t __reserved1[3]; |
| 1480 | uint8_t num_tbs; |
| 1481 | struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; |
| 1482 | uint32_t __pad; |
| 1483 | } __packed; |
| 1484 | |
| 1485 | /* Keep Warm Size */ |
| 1486 | #define IWM_KW_SIZE 0x1000 /* 4k */ |
| 1487 | |
| 1488 | /* Fixed (non-configurable) rx data from phy */ |
| 1489 | |
| 1490 | /** |
| 1491 | * struct iwm_agn_schedq_bc_tbl scheduler byte count table |
| 1492 | * base physical address provided by IWM_SCD_DRAM_BASE_ADDR |
| 1493 | * @tfd_offset 0-12 - tx command byte count |
| 1494 | * 12-16 - station index |
| 1495 | */ |
| 1496 | struct iwm_agn_scd_bc_tbl { |
| 1497 | uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; |
| 1498 | } __packed; |
| 1499 | |
| 1500 | /* |
| 1501 | * END iwl-fh.h |
| 1502 | */ |
| 1503 | |
| 1504 | /* |
| 1505 | * BEGIN mvm/fw-api.h |
| 1506 | */ |
| 1507 | |
| 1508 | /* maximal number of Tx queues in any platform */ |
| 1509 | #define IWM_MVM_MAX_QUEUES 20 |
| 1510 | |
| 1511 | /* Tx queue numbers */ |
| 1512 | enum { |
| 1513 | IWM_MVM_OFFCHANNEL_QUEUE = 8, |
| 1514 | IWM_MVM_CMD_QUEUE = 9, |
| 1515 | }; |
| 1516 | |
| 1517 | #define IWM_MVM_CMD_FIFO 7 |
| 1518 | |
| 1519 | #define IWM_MVM_STATION_COUNT 16 |
| 1520 | |
| 1521 | /* commands */ |
| 1522 | enum { |
| 1523 | IWM_MVM_ALIVE = 0x1, |
| 1524 | IWM_REPLY_ERROR = 0x2, |
| 1525 | |
| 1526 | IWM_INIT_COMPLETE_NOTIF = 0x4, |
| 1527 | |
| 1528 | /* PHY context commands */ |
| 1529 | IWM_PHY_CONTEXT_CMD = 0x8, |
| 1530 | IWM_DBG_CFG = 0x9, |
| 1531 | |
| 1532 | /* station table */ |
| 1533 | IWM_ADD_STA_KEY = 0x17, |
| 1534 | IWM_ADD_STA = 0x18, |
| 1535 | IWM_REMOVE_STA = 0x19, |
| 1536 | |
| 1537 | /* TX */ |
| 1538 | IWM_TX_CMD = 0x1c, |
| 1539 | IWM_TXPATH_FLUSH = 0x1e, |
| 1540 | IWM_MGMT_MCAST_KEY = 0x1f, |
| 1541 | |
| 1542 | /* global key */ |
| 1543 | IWM_WEP_KEY = 0x20, |
| 1544 | |
| 1545 | /* MAC and Binding commands */ |
| 1546 | IWM_MAC_CONTEXT_CMD = 0x28, |
| 1547 | IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ |
| 1548 | IWM_TIME_EVENT_NOTIFICATION = 0x2a, |
| 1549 | IWM_BINDING_CONTEXT_CMD = 0x2b, |
| 1550 | IWM_TIME_QUOTA_CMD = 0x2c, |
| 1551 | IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, |
| 1552 | |
| 1553 | IWM_LQ_CMD = 0x4e, |
| 1554 | |
| 1555 | /* Calibration */ |
| 1556 | IWM_TEMPERATURE_NOTIFICATION = 0x62, |
| 1557 | IWM_CALIBRATION_CFG_CMD = 0x65, |
| 1558 | IWM_CALIBRATION_RES_NOTIFICATION = 0x66, |
| 1559 | IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, |
| 1560 | IWM_RADIO_VERSION_NOTIFICATION = 0x68, |
| 1561 | |
| 1562 | /* Scan offload */ |
| 1563 | IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, |
| 1564 | IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, |
| 1565 | IWM_SCAN_OFFLOAD_COMPLETE = 0x6D, |
| 1566 | IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E, |
| 1567 | IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, |
| 1568 | IWM_MATCH_FOUND_NOTIFICATION = 0xd9, |
| 1569 | |
| 1570 | /* Phy */ |
| 1571 | IWM_PHY_CONFIGURATION_CMD = 0x6a, |
| 1572 | IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, |
| 1573 | /* IWM_PHY_DB_CMD = 0x6c, */ |
| 1574 | |
| 1575 | /* Power - legacy power table command */ |
| 1576 | IWM_POWER_TABLE_CMD = 0x77, |
| 1577 | IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, |
| 1578 | |
| 1579 | /* Thermal Throttling*/ |
| 1580 | IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, |
| 1581 | |
| 1582 | /* Scanning */ |
| 1583 | IWM_SCAN_REQUEST_CMD = 0x80, |
| 1584 | IWM_SCAN_ABORT_CMD = 0x81, |
| 1585 | IWM_SCAN_START_NOTIFICATION = 0x82, |
| 1586 | IWM_SCAN_RESULTS_NOTIFICATION = 0x83, |
| 1587 | IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, |
| 1588 | |
| 1589 | /* NVM */ |
| 1590 | IWM_NVM_ACCESS_CMD = 0x88, |
| 1591 | |
| 1592 | IWM_SET_CALIB_DEFAULT_CMD = 0x8e, |
| 1593 | |
| 1594 | IWM_BEACON_NOTIFICATION = 0x90, |
| 1595 | IWM_BEACON_TEMPLATE_CMD = 0x91, |
| 1596 | IWM_TX_ANT_CONFIGURATION_CMD = 0x98, |
| 1597 | IWM_BT_CONFIG = 0x9b, |
| 1598 | IWM_STATISTICS_NOTIFICATION = 0x9d, |
| 1599 | IWM_REDUCE_TX_POWER_CMD = 0x9f, |
| 1600 | |
| 1601 | /* RF-KILL commands and notifications */ |
| 1602 | IWM_CARD_STATE_CMD = 0xa0, |
| 1603 | IWM_CARD_STATE_NOTIFICATION = 0xa1, |
| 1604 | |
| 1605 | IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, |
| 1606 | |
| 1607 | /* Power - new power table command */ |
| 1608 | IWM_MAC_PM_POWER_TABLE = 0xa9, |
| 1609 | |
| 1610 | IWM_REPLY_RX_PHY_CMD = 0xc0, |
| 1611 | IWM_REPLY_RX_MPDU_CMD = 0xc1, |
| 1612 | IWM_BA_NOTIF = 0xc5, |
| 1613 | |
| 1614 | /* BT Coex */ |
| 1615 | IWM_BT_COEX_PRIO_TABLE = 0xcc, |
| 1616 | IWM_BT_COEX_PROT_ENV = 0xcd, |
| 1617 | IWM_BT_PROFILE_NOTIFICATION = 0xce, |
| 1618 | IWM_BT_COEX_CI = 0x5d, |
| 1619 | |
| 1620 | IWM_REPLY_SF_CFG_CMD = 0xd1, |
| 1621 | IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, |
| 1622 | |
| 1623 | IWM_REPLY_DEBUG_CMD = 0xf0, |
| 1624 | IWM_DEBUG_LOG_MSG = 0xf7, |
| 1625 | |
| 1626 | IWM_MCAST_FILTER_CMD = 0xd0, |
| 1627 | |
| 1628 | /* D3 commands/notifications */ |
| 1629 | IWM_D3_CONFIG_CMD = 0xd3, |
| 1630 | IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, |
| 1631 | IWM_OFFLOADS_QUERY_CMD = 0xd5, |
| 1632 | IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, |
| 1633 | |
| 1634 | /* for WoWLAN in particular */ |
| 1635 | IWM_WOWLAN_PATTERNS = 0xe0, |
| 1636 | IWM_WOWLAN_CONFIGURATION = 0xe1, |
| 1637 | IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, |
| 1638 | IWM_WOWLAN_TKIP_PARAM = 0xe3, |
| 1639 | IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, |
| 1640 | IWM_WOWLAN_GET_STATUSES = 0xe5, |
| 1641 | IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, |
| 1642 | |
| 1643 | /* and for NetDetect */ |
| 1644 | IWM_NET_DETECT_CONFIG_CMD = 0x54, |
| 1645 | IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, |
| 1646 | IWM_NET_DETECT_PROFILES_CMD = 0x57, |
| 1647 | IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, |
| 1648 | IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, |
| 1649 | |
| 1650 | IWM_REPLY_MAX = 0xff, |
| 1651 | }; |
| 1652 | |
| 1653 | /** |
| 1654 | * struct iwm_cmd_response - generic response struct for most commands |
| 1655 | * @status: status of the command asked, changes for each one |
| 1656 | */ |
| 1657 | struct iwm_cmd_response { |
| 1658 | uint32_t status; |
| 1659 | }; |
| 1660 | |
| 1661 | /* |
| 1662 | * struct iwm_tx_ant_cfg_cmd |
| 1663 | * @valid: valid antenna configuration |
| 1664 | */ |
| 1665 | struct iwm_tx_ant_cfg_cmd { |
| 1666 | uint32_t valid; |
| 1667 | } __packed; |
| 1668 | |
| 1669 | /** |
| 1670 | * struct iwm_reduce_tx_power_cmd - TX power reduction command |
| 1671 | * IWM_REDUCE_TX_POWER_CMD = 0x9f |
| 1672 | * @flags: (reserved for future implementation) |
| 1673 | * @mac_context_id: id of the mac ctx for which we are reducing TX power. |
| 1674 | * @pwr_restriction: TX power restriction in dBms. |
| 1675 | */ |
| 1676 | struct iwm_reduce_tx_power_cmd { |
| 1677 | uint8_t flags; |
| 1678 | uint8_t mac_context_id; |
| 1679 | uint16_t pwr_restriction; |
| 1680 | } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ |
| 1681 | |
| 1682 | /* |
| 1683 | * Calibration control struct. |
| 1684 | * Sent as part of the phy configuration command. |
| 1685 | * @flow_trigger: bitmap for which calibrations to perform according to |
| 1686 | * flow triggers. |
| 1687 | * @event_trigger: bitmap for which calibrations to perform according to |
| 1688 | * event triggers. |
| 1689 | */ |
| 1690 | struct iwm_calib_ctrl { |
| 1691 | uint32_t flow_trigger; |
| 1692 | uint32_t event_trigger; |
| 1693 | } __packed; |
| 1694 | |
| 1695 | /* This enum defines the bitmap of various calibrations to enable in both |
| 1696 | * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. |
| 1697 | */ |
| 1698 | enum iwm_calib_cfg { |
| 1699 | IWM_CALIB_CFG_XTAL_IDX = (1 << 0), |
| 1700 | IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), |
| 1701 | IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), |
| 1702 | IWM_CALIB_CFG_PAPD_IDX = (1 << 3), |
| 1703 | IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), |
| 1704 | IWM_CALIB_CFG_DC_IDX = (1 << 5), |
| 1705 | IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), |
| 1706 | IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), |
| 1707 | IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), |
| 1708 | IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), |
| 1709 | IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), |
| 1710 | IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), |
| 1711 | IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), |
| 1712 | IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), |
| 1713 | IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), |
| 1714 | IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), |
| 1715 | IWM_CALIB_CFG_DAC_IDX = (1 << 16), |
| 1716 | IWM_CALIB_CFG_ABS_IDX = (1 << 17), |
| 1717 | IWM_CALIB_CFG_AGC_IDX = (1 << 18), |
| 1718 | }; |
| 1719 | |
| 1720 | /* |
| 1721 | * Phy configuration command. |
| 1722 | */ |
| 1723 | struct iwm_phy_cfg_cmd { |
| 1724 | uint32_t phy_cfg; |
| 1725 | struct iwm_calib_ctrl calib_control; |
| 1726 | } __packed; |
| 1727 | |
| 1728 | #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) |
| 1729 | #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) |
| 1730 | #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) |
| 1731 | #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) |
| 1732 | #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) |
| 1733 | #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) |
| 1734 | #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) |
| 1735 | #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) |
| 1736 | #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) |
| 1737 | #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) |
| 1738 | |
| 1739 | |
| 1740 | /* Target of the IWM_NVM_ACCESS_CMD */ |
| 1741 | enum { |
| 1742 | IWM_NVM_ACCESS_TARGET_CACHE = 0, |
| 1743 | IWM_NVM_ACCESS_TARGET_OTP = 1, |
| 1744 | IWM_NVM_ACCESS_TARGET_EEPROM = 2, |
| 1745 | }; |
| 1746 | |
| 1747 | /* Section types for IWM_NVM_ACCESS_CMD */ |
| 1748 | enum { |
| 1749 | IWM_NVM_SECTION_TYPE_HW = 0, |
| 1750 | IWM_NVM_SECTION_TYPE_SW, |
| 1751 | IWM_NVM_SECTION_TYPE_PAPD, |
| 1752 | IWM_NVM_SECTION_TYPE_BT, |
| 1753 | IWM_NVM_SECTION_TYPE_CALIBRATION, |
| 1754 | IWM_NVM_SECTION_TYPE_PRODUCTION, |
| 1755 | IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, |
| 1756 | IWM_NVM_NUM_OF_SECTIONS, |
| 1757 | }; |
| 1758 | |
| 1759 | /** |
| 1760 | * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section |
| 1761 | * @op_code: 0 - read, 1 - write |
| 1762 | * @target: IWM_NVM_ACCESS_TARGET_* |
| 1763 | * @type: IWM_NVM_SECTION_TYPE_* |
| 1764 | * @offset: offset in bytes into the section |
| 1765 | * @length: in bytes, to read/write |
| 1766 | * @data: if write operation, the data to write. On read its empty |
| 1767 | */ |
| 1768 | struct iwm_nvm_access_cmd { |
| 1769 | uint8_t op_code; |
| 1770 | uint8_t target; |
| 1771 | uint16_t type; |
| 1772 | uint16_t offset; |
| 1773 | uint16_t length; |
| 1774 | uint8_t data[]; |
| 1775 | } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ |
| 1776 | |
| 1777 | /** |
| 1778 | * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD |
| 1779 | * @offset: offset in bytes into the section |
| 1780 | * @length: in bytes, either how much was written or read |
| 1781 | * @type: IWM_NVM_SECTION_TYPE_* |
| 1782 | * @status: 0 for success, fail otherwise |
| 1783 | * @data: if read operation, the data returned. Empty on write. |
| 1784 | */ |
| 1785 | struct iwm_nvm_access_resp { |
| 1786 | uint16_t offset; |
| 1787 | uint16_t length; |
| 1788 | uint16_t type; |
| 1789 | uint16_t status; |
| 1790 | uint8_t data[]; |
| 1791 | } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ |
| 1792 | |
| 1793 | /* IWM_MVM_ALIVE 0x1 */ |
| 1794 | |
| 1795 | /* alive response is_valid values */ |
| 1796 | #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) |
| 1797 | #define IWM_ALIVE_RESP_RFKILL (1 << 1) |
| 1798 | |
| 1799 | /* alive response ver_type values */ |
| 1800 | enum { |
| 1801 | IWM_FW_TYPE_HW = 0, |
| 1802 | IWM_FW_TYPE_PROT = 1, |
| 1803 | IWM_FW_TYPE_AP = 2, |
| 1804 | IWM_FW_TYPE_WOWLAN = 3, |
| 1805 | IWM_FW_TYPE_TIMING = 4, |
| 1806 | IWM_FW_TYPE_WIPAN = 5 |
| 1807 | }; |
| 1808 | |
| 1809 | /* alive response ver_subtype values */ |
| 1810 | enum { |
| 1811 | IWM_FW_SUBTYPE_FULL_FEATURE = 0, |
| 1812 | IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ |
| 1813 | IWM_FW_SUBTYPE_REDUCED = 2, |
| 1814 | IWM_FW_SUBTYPE_ALIVE_ONLY = 3, |
| 1815 | IWM_FW_SUBTYPE_WOWLAN = 4, |
| 1816 | IWM_FW_SUBTYPE_AP_SUBTYPE = 5, |
| 1817 | IWM_FW_SUBTYPE_WIPAN = 6, |
| 1818 | IWM_FW_SUBTYPE_INITIALIZE = 9 |
| 1819 | }; |
| 1820 | |
| 1821 | #define IWM_ALIVE_STATUS_ERR 0xDEAD |
| 1822 | #define IWM_ALIVE_STATUS_OK 0xCAFE |
| 1823 | |
| 1824 | #define IWM_ALIVE_FLG_RFKILL (1 << 0) |
| 1825 | |
| 1826 | struct iwm_mvm_alive_resp { |
| 1827 | uint16_t status; |
| 1828 | uint16_t flags; |
| 1829 | uint8_t ucode_minor; |
| 1830 | uint8_t ucode_major; |
| 1831 | uint16_t id; |
| 1832 | uint8_t api_minor; |
| 1833 | uint8_t api_major; |
| 1834 | uint8_t ver_subtype; |
| 1835 | uint8_t ver_type; |
| 1836 | uint8_t mac; |
| 1837 | uint8_t opt; |
| 1838 | uint16_t reserved2; |
| 1839 | uint32_t timestamp; |
| 1840 | uint32_t error_event_table_ptr; /* SRAM address for error log */ |
| 1841 | uint32_t log_event_table_ptr; /* SRAM address for event log */ |
| 1842 | uint32_t cpu_register_ptr; |
| 1843 | uint32_t dbgm_config_ptr; |
| 1844 | uint32_t alive_counter_ptr; |
| 1845 | uint32_t scd_base_ptr; /* SRAM address for SCD */ |
| 1846 | } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ |
| 1847 | |
| 1848 | /* Error response/notification */ |
| 1849 | enum { |
| 1850 | IWM_FW_ERR_UNKNOWN_CMD = 0x0, |
| 1851 | IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, |
| 1852 | IWM_FW_ERR_SERVICE = 0x2, |
| 1853 | IWM_FW_ERR_ARC_MEMORY = 0x3, |
| 1854 | IWM_FW_ERR_ARC_CODE = 0x4, |
| 1855 | IWM_FW_ERR_WATCH_DOG = 0x5, |
| 1856 | IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, |
| 1857 | IWM_FW_ERR_WEP_KEY_SIZE = 0x11, |
| 1858 | IWM_FW_ERR_OBSOLETE_FUNC = 0x12, |
| 1859 | IWM_FW_ERR_UNEXPECTED = 0xFE, |
| 1860 | IWM_FW_ERR_FATAL = 0xFF |
| 1861 | }; |
| 1862 | |
| 1863 | /** |
| 1864 | * struct iwm_error_resp - FW error indication |
| 1865 | * ( IWM_REPLY_ERROR = 0x2 ) |
| 1866 | * @error_type: one of IWM_FW_ERR_* |
| 1867 | * @cmd_id: the command ID for which the error occured |
| 1868 | * @bad_cmd_seq_num: sequence number of the erroneous command |
| 1869 | * @error_service: which service created the error, applicable only if |
| 1870 | * error_type = 2, otherwise 0 |
| 1871 | * @timestamp: TSF in usecs. |
| 1872 | */ |
| 1873 | struct iwm_error_resp { |
| 1874 | uint32_t error_type; |
| 1875 | uint8_t cmd_id; |
| 1876 | uint8_t reserved1; |
| 1877 | uint16_t bad_cmd_seq_num; |
| 1878 | uint32_t error_service; |
| 1879 | uint64_t timestamp; |
| 1880 | } __packed; |
| 1881 | |
| 1882 | |
| 1883 | /* Common PHY, MAC and Bindings definitions */ |
| 1884 | |
| 1885 | #define IWM_MAX_MACS_IN_BINDING (3) |
| 1886 | #define IWM_MAX_BINDINGS (4) |
| 1887 | #define IWM_AUX_BINDING_INDEX (3) |
| 1888 | #define IWM_MAX_PHYS (4) |
| 1889 | |
| 1890 | /* Used to extract ID and color from the context dword */ |
| 1891 | #define IWM_FW_CTXT_ID_POS (0) |
| 1892 | #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) |
| 1893 | #define IWM_FW_CTXT_COLOR_POS (8) |
| 1894 | #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) |
| 1895 | #define IWM_FW_CTXT_INVALID (0xffffffff) |
| 1896 | |
| 1897 | #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ |
| 1898 | (_color << IWM_FW_CTXT_COLOR_POS)) |
| 1899 | |
| 1900 | /* Possible actions on PHYs, MACs and Bindings */ |
| 1901 | enum { |
| 1902 | IWM_FW_CTXT_ACTION_STUB = 0, |
| 1903 | IWM_FW_CTXT_ACTION_ADD, |
| 1904 | IWM_FW_CTXT_ACTION_MODIFY, |
| 1905 | IWM_FW_CTXT_ACTION_REMOVE, |
| 1906 | IWM_FW_CTXT_ACTION_NUM |
| 1907 | }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ |
| 1908 | |
| 1909 | /* Time Events */ |
| 1910 | |
| 1911 | /* Time Event types, according to MAC type */ |
| 1912 | enum iwm_time_event_type { |
| 1913 | /* BSS Station Events */ |
| 1914 | IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, |
| 1915 | IWM_TE_BSS_STA_ASSOC, |
| 1916 | IWM_TE_BSS_EAP_DHCP_PROT, |
| 1917 | IWM_TE_BSS_QUIET_PERIOD, |
| 1918 | |
| 1919 | /* P2P Device Events */ |
| 1920 | IWM_TE_P2P_DEVICE_DISCOVERABLE, |
| 1921 | IWM_TE_P2P_DEVICE_LISTEN, |
| 1922 | IWM_TE_P2P_DEVICE_ACTION_SCAN, |
| 1923 | IWM_TE_P2P_DEVICE_FULL_SCAN, |
| 1924 | |
| 1925 | /* P2P Client Events */ |
| 1926 | IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, |
| 1927 | IWM_TE_P2P_CLIENT_ASSOC, |
| 1928 | IWM_TE_P2P_CLIENT_QUIET_PERIOD, |
| 1929 | |
| 1930 | /* P2P GO Events */ |
| 1931 | IWM_TE_P2P_GO_ASSOC_PROT, |
| 1932 | IWM_TE_P2P_GO_REPETITIVE_NOA, |
| 1933 | IWM_TE_P2P_GO_CT_WINDOW, |
| 1934 | |
| 1935 | /* WiDi Sync Events */ |
| 1936 | IWM_TE_WIDI_TX_SYNC, |
| 1937 | |
| 1938 | IWM_TE_MAX |
| 1939 | }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ |
| 1940 | |
| 1941 | |
| 1942 | |
| 1943 | /* Time event - defines for command API v1 */ |
| 1944 | |
| 1945 | /* |
| 1946 | * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. |
| 1947 | * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only |
| 1948 | * the first fragment is scheduled. |
| 1949 | * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only |
| 1950 | * the first 2 fragments are scheduled. |
| 1951 | * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any |
| 1952 | * number of fragments are valid. |
| 1953 | * |
| 1954 | * Other than the constant defined above, specifying a fragmentation value 'x' |
| 1955 | * means that the event can be fragmented but only the first 'x' will be |
| 1956 | * scheduled. |
| 1957 | */ |
| 1958 | enum { |
| 1959 | IWM_TE_V1_FRAG_NONE = 0, |
| 1960 | IWM_TE_V1_FRAG_SINGLE = 1, |
| 1961 | IWM_TE_V1_FRAG_DUAL = 2, |
| 1962 | IWM_TE_V1_FRAG_ENDLESS = 0xffffffff |
| 1963 | }; |
| 1964 | |
| 1965 | /* If a Time Event can be fragmented, this is the max number of fragments */ |
| 1966 | #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff |
| 1967 | /* Repeat the time event endlessly (until removed) */ |
| 1968 | #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff |
| 1969 | /* If a Time Event has bounded repetitions, this is the maximal value */ |
| 1970 | #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff |
| 1971 | |
| 1972 | /* Time Event dependencies: none, on another TE, or in a specific time */ |
| 1973 | enum { |
| 1974 | IWM_TE_V1_INDEPENDENT = 0, |
| 1975 | IWM_TE_V1_DEP_OTHER = (1 << 0), |
| 1976 | IWM_TE_V1_DEP_TSF = (1 << 1), |
| 1977 | IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), |
| 1978 | }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ |
| 1979 | |
| 1980 | /* |
| 1981 | * @IWM_TE_V1_NOTIF_NONE: no notifications |
| 1982 | * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start |
| 1983 | * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end |
| 1984 | * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use |
| 1985 | * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. |
| 1986 | * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start |
| 1987 | * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end |
| 1988 | * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. |
| 1989 | * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. |
| 1990 | * |
| 1991 | * Supported Time event notifications configuration. |
| 1992 | * A notification (both event and fragment) includes a status indicating weather |
| 1993 | * the FW was able to schedule the event or not. For fragment start/end |
| 1994 | * notification the status is always success. There is no start/end fragment |
| 1995 | * notification for monolithic events. |
| 1996 | */ |
| 1997 | enum { |
| 1998 | IWM_TE_V1_NOTIF_NONE = 0, |
| 1999 | IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), |
| 2000 | IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), |
| 2001 | IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), |
| 2002 | IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), |
| 2003 | IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), |
| 2004 | IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), |
| 2005 | IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), |
| 2006 | IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), |
| 2007 | }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ |
| 2008 | |
| 2009 | |
| 2010 | /** |
| 2011 | * struct iwm_time_event_cmd_api_v1 - configuring Time Events |
| 2012 | * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also |
| 2013 | * with version 2. determined by IWM_UCODE_TLV_FLAGS) |
| 2014 | * ( IWM_TIME_EVENT_CMD = 0x29 ) |
| 2015 | * @id_and_color: ID and color of the relevant MAC |
| 2016 | * @action: action to perform, one of IWM_FW_CTXT_ACTION_* |
| 2017 | * @id: this field has two meanings, depending on the action: |
| 2018 | * If the action is ADD, then it means the type of event to add. |
| 2019 | * For all other actions it is the unique event ID assigned when the |
| 2020 | * event was added by the FW. |
| 2021 | * @apply_time: When to start the Time Event (in GP2) |
| 2022 | * @max_delay: maximum delay to event's start (apply time), in TU |
| 2023 | * @depends_on: the unique ID of the event we depend on (if any) |
| 2024 | * @interval: interval between repetitions, in TU |
| 2025 | * @interval_reciprocal: 2^32 / interval |
| 2026 | * @duration: duration of event in TU |
| 2027 | * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS |
| 2028 | * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF |
| 2029 | * and IWM_TE_V1_EVENT_SOCIOPATHIC |
| 2030 | * @is_present: 0 or 1, are we present or absent during the Time Event |
| 2031 | * @max_frags: maximal number of fragments the Time Event can be divided to |
| 2032 | * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) |
| 2033 | */ |
| 2034 | struct iwm_time_event_cmd_v1 { |
| 2035 | /* COMMON_INDEX_HDR_API_S_VER_1 */ |
| 2036 | uint32_t id_and_color; |
| 2037 | uint32_t action; |
| 2038 | uint32_t id; |
| 2039 | /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ |
| 2040 | uint32_t apply_time; |
| 2041 | uint32_t max_delay; |
| 2042 | uint32_t dep_policy; |
| 2043 | uint32_t depends_on; |
| 2044 | uint32_t is_present; |
| 2045 | uint32_t max_frags; |
| 2046 | uint32_t interval; |
| 2047 | uint32_t interval_reciprocal; |
| 2048 | uint32_t duration; |
| 2049 | uint32_t repeat; |
| 2050 | uint32_t notify; |
| 2051 | } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ |
| 2052 | |
| 2053 | |
| 2054 | /* Time event - defines for command API v2 */ |
| 2055 | |
| 2056 | /* |
| 2057 | * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. |
| 2058 | * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only |
| 2059 | * the first fragment is scheduled. |
| 2060 | * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only |
| 2061 | * the first 2 fragments are scheduled. |
| 2062 | * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any |
| 2063 | * number of fragments are valid. |
| 2064 | * |
| 2065 | * Other than the constant defined above, specifying a fragmentation value 'x' |
| 2066 | * means that the event can be fragmented but only the first 'x' will be |
| 2067 | * scheduled. |
| 2068 | */ |
| 2069 | enum { |
| 2070 | IWM_TE_V2_FRAG_NONE = 0, |
| 2071 | IWM_TE_V2_FRAG_SINGLE = 1, |
| 2072 | IWM_TE_V2_FRAG_DUAL = 2, |
| 2073 | IWM_TE_V2_FRAG_MAX = 0xfe, |
| 2074 | IWM_TE_V2_FRAG_ENDLESS = 0xff |
| 2075 | }; |
| 2076 | |
| 2077 | /* Repeat the time event endlessly (until removed) */ |
| 2078 | #define IWM_TE_V2_REPEAT_ENDLESS 0xff |
| 2079 | /* If a Time Event has bounded repetitions, this is the maximal value */ |
| 2080 | #define IWM_TE_V2_REPEAT_MAX 0xfe |
| 2081 | |
| 2082 | #define IWM_TE_V2_PLACEMENT_POS 12 |
| 2083 | #define IWM_TE_V2_ABSENCE_POS 15 |
| 2084 | |
| 2085 | /* Time event policy values (for time event cmd api v2) |
| 2086 | * A notification (both event and fragment) includes a status indicating weather |
| 2087 | * the FW was able to schedule the event or not. For fragment start/end |
| 2088 | * notification the status is always success. There is no start/end fragment |
| 2089 | * notification for monolithic events. |
| 2090 | * |
| 2091 | * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable |
| 2092 | * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start |
| 2093 | * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end |
| 2094 | * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use |
| 2095 | * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. |
| 2096 | * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start |
| 2097 | * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end |
| 2098 | * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. |
| 2099 | * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. |
| 2100 | * @IWM_TE_V2_DEP_OTHER: depends on another time event |
| 2101 | * @IWM_TE_V2_DEP_TSF: depends on a specific time |
| 2102 | * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC |
| 2103 | * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. |
| 2104 | */ |
| 2105 | enum { |
| 2106 | IWM_TE_V2_DEFAULT_POLICY = 0x0, |
| 2107 | |
| 2108 | /* notifications (event start/stop, fragment start/stop) */ |
| 2109 | IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), |
| 2110 | IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), |
| 2111 | IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), |
| 2112 | IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), |
| 2113 | |
| 2114 | IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), |
| 2115 | IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), |
| 2116 | IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), |
| 2117 | IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), |
| 2118 | |
| 2119 | IWM_TE_V2_NOTIF_MSK = 0xff, |
| 2120 | |
| 2121 | /* placement characteristics */ |
| 2122 | IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), |
| 2123 | IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), |
| 2124 | IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), |
| 2125 | |
| 2126 | /* are we present or absent during the Time Event. */ |
| 2127 | IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), |
| 2128 | }; |
| 2129 | |
| 2130 | /** |
| 2131 | * struct iwm_time_event_cmd_api_v2 - configuring Time Events |
| 2132 | * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also |
| 2133 | * with version 1. determined by IWM_UCODE_TLV_FLAGS) |
| 2134 | * ( IWM_TIME_EVENT_CMD = 0x29 ) |
| 2135 | * @id_and_color: ID and color of the relevant MAC |
| 2136 | * @action: action to perform, one of IWM_FW_CTXT_ACTION_* |
| 2137 | * @id: this field has two meanings, depending on the action: |
| 2138 | * If the action is ADD, then it means the type of event to add. |
| 2139 | * For all other actions it is the unique event ID assigned when the |
| 2140 | * event was added by the FW. |
| 2141 | * @apply_time: When to start the Time Event (in GP2) |
| 2142 | * @max_delay: maximum delay to event's start (apply time), in TU |
| 2143 | * @depends_on: the unique ID of the event we depend on (if any) |
| 2144 | * @interval: interval between repetitions, in TU |
| 2145 | * @duration: duration of event in TU |
| 2146 | * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS |
| 2147 | * @max_frags: maximal number of fragments the Time Event can be divided to |
| 2148 | * @policy: defines whether uCode shall notify the host or other uCode modules |
| 2149 | * on event and/or fragment start and/or end |
| 2150 | * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF |
| 2151 | * IWM_TE_EVENT_SOCIOPATHIC |
| 2152 | * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* |
| 2153 | */ |
| 2154 | struct iwm_time_event_cmd_v2 { |
| 2155 | /* COMMON_INDEX_HDR_API_S_VER_1 */ |
| 2156 | uint32_t id_and_color; |
| 2157 | uint32_t action; |
| 2158 | uint32_t id; |
| 2159 | /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ |
| 2160 | uint32_t apply_time; |
| 2161 | uint32_t max_delay; |
| 2162 | uint32_t depends_on; |
| 2163 | uint32_t interval; |
| 2164 | uint32_t duration; |
| 2165 | uint8_t repeat; |
| 2166 | uint8_t max_frags; |
| 2167 | uint16_t policy; |
| 2168 | } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ |
| 2169 | |
| 2170 | /** |
| 2171 | * struct iwm_time_event_resp - response structure to iwm_time_event_cmd |
| 2172 | * @status: bit 0 indicates success, all others specify errors |
| 2173 | * @id: the Time Event type |
| 2174 | * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE |
| 2175 | * @id_and_color: ID and color of the relevant MAC |
| 2176 | */ |
| 2177 | struct iwm_time_event_resp { |
| 2178 | uint32_t status; |
| 2179 | uint32_t id; |
| 2180 | uint32_t unique_id; |
| 2181 | uint32_t id_and_color; |
| 2182 | } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ |
| 2183 | |
| 2184 | /** |
| 2185 | * struct iwm_time_event_notif - notifications of time event start/stop |
| 2186 | * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) |
| 2187 | * @timestamp: action timestamp in GP2 |
| 2188 | * @session_id: session's unique id |
| 2189 | * @unique_id: unique id of the Time Event itself |
| 2190 | * @id_and_color: ID and color of the relevant MAC |
| 2191 | * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END |
| 2192 | * @status: true if scheduled, false otherwise (not executed) |
| 2193 | */ |
| 2194 | struct iwm_time_event_notif { |
| 2195 | uint32_t timestamp; |
| 2196 | uint32_t session_id; |
| 2197 | uint32_t unique_id; |
| 2198 | uint32_t id_and_color; |
| 2199 | uint32_t action; |
| 2200 | uint32_t status; |
| 2201 | } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ |
| 2202 | |
| 2203 | |
| 2204 | /* Bindings and Time Quota */ |
| 2205 | |
| 2206 | /** |
| 2207 | * struct iwm_binding_cmd - configuring bindings |
| 2208 | * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) |
| 2209 | * @id_and_color: ID and color of the relevant Binding |
| 2210 | * @action: action to perform, one of IWM_FW_CTXT_ACTION_* |
| 2211 | * @macs: array of MAC id and colors which belong to the binding |
| 2212 | * @phy: PHY id and color which belongs to the binding |
| 2213 | */ |
| 2214 | struct iwm_binding_cmd { |
| 2215 | /* COMMON_INDEX_HDR_API_S_VER_1 */ |
| 2216 | uint32_t id_and_color; |
| 2217 | uint32_t action; |
| 2218 | /* IWM_BINDING_DATA_API_S_VER_1 */ |
| 2219 | uint32_t macs[IWM_MAX_MACS_IN_BINDING]; |
| 2220 | uint32_t phy; |
| 2221 | } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ |
| 2222 | |
| 2223 | /* The maximal number of fragments in the FW's schedule session */ |
| 2224 | #define IWM_MVM_MAX_QUOTA 128 |
| 2225 | |
| 2226 | /** |
| 2227 | * struct iwm_time_quota_data - configuration of time quota per binding |
| 2228 | * @id_and_color: ID and color of the relevant Binding |
| 2229 | * @quota: absolute time quota in TU. The scheduler will try to divide the |
| 2230 | * remainig quota (after Time Events) according to this quota. |
| 2231 | * @max_duration: max uninterrupted context duration in TU |
| 2232 | */ |
| 2233 | struct iwm_time_quota_data { |
| 2234 | uint32_t id_and_color; |
| 2235 | uint32_t quota; |
| 2236 | uint32_t max_duration; |
| 2237 | } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ |
| 2238 | |
| 2239 | /** |
| 2240 | * struct iwm_time_quota_cmd - configuration of time quota between bindings |
| 2241 | * ( IWM_TIME_QUOTA_CMD = 0x2c ) |
| 2242 | * @quotas: allocations per binding |
| 2243 | */ |
| 2244 | struct iwm_time_quota_cmd { |
| 2245 | struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; |
| 2246 | } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ |
| 2247 | |
| 2248 | |
| 2249 | /* PHY context */ |
| 2250 | |
| 2251 | /* Supported bands */ |
| 2252 | #define IWM_PHY_BAND_5 (0) |
| 2253 | #define IWM_PHY_BAND_24 (1) |
| 2254 | |
| 2255 | /* Supported channel width, vary if there is VHT support */ |
| 2256 | #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) |
| 2257 | #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) |
| 2258 | #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) |
| 2259 | #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) |
| 2260 | |
| 2261 | /* |
| 2262 | * Control channel position: |
| 2263 | * For legacy set bit means upper channel, otherwise lower. |
| 2264 | * For VHT - bit-2 marks if the control is lower/upper relative to center-freq |
| 2265 | * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. |
| 2266 | * center_freq |
| 2267 | * | |
| 2268 | * 40Mhz |_______|_______| |
| 2269 | * 80Mhz |_______|_______|_______|_______| |
| 2270 | * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| |
| 2271 | * code 011 010 001 000 | 100 101 110 111 |
| 2272 | */ |
| 2273 | #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) |
| 2274 | #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) |
| 2275 | #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) |
| 2276 | #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) |
| 2277 | #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) |
| 2278 | #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) |
| 2279 | #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) |
| 2280 | #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) |
| 2281 | |
| 2282 | /* |
| 2283 | * @band: IWM_PHY_BAND_* |
| 2284 | * @channel: channel number |
| 2285 | * @width: PHY_[VHT|LEGACY]_CHANNEL_* |
| 2286 | * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* |
| 2287 | */ |
| 2288 | struct iwm_fw_channel_info { |
| 2289 | uint8_t band; |
| 2290 | uint8_t channel; |
| 2291 | uint8_t width; |
| 2292 | uint8_t ctrl_pos; |
| 2293 | } __packed; |
| 2294 | |
| 2295 | #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) |
| 2296 | #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ |
| 2297 | (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) |
| 2298 | #define IWM_PHY_RX_CHAIN_VALID_POS (1) |
| 2299 | #define IWM_PHY_RX_CHAIN_VALID_MSK \ |
| 2300 | (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) |
| 2301 | #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) |
| 2302 | #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ |
| 2303 | (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) |
| 2304 | #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) |
| 2305 | #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ |
| 2306 | (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) |
| 2307 | #define IWM_PHY_RX_CHAIN_CNT_POS (10) |
| 2308 | #define IWM_PHY_RX_CHAIN_CNT_MSK \ |
| 2309 | (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) |
| 2310 | #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) |
| 2311 | #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ |
| 2312 | (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) |
| 2313 | #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) |
| 2314 | #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ |
| 2315 | (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) |
| 2316 | |
| 2317 | /* TODO: fix the value, make it depend on firmware at runtime? */ |
| 2318 | #define IWM_NUM_PHY_CTX 3 |
| 2319 | |
| 2320 | /* TODO: complete missing documentation */ |
| 2321 | /** |
| 2322 | * struct iwm_phy_context_cmd - config of the PHY context |
| 2323 | * ( IWM_PHY_CONTEXT_CMD = 0x8 ) |
| 2324 | * @id_and_color: ID and color of the relevant Binding |
| 2325 | * @action: action to perform, one of IWM_FW_CTXT_ACTION_* |
| 2326 | * @apply_time: 0 means immediate apply and context switch. |
| 2327 | * other value means apply new params after X usecs |
| 2328 | * @tx_param_color: ??? |
| 2329 | * @channel_info: |
| 2330 | * @txchain_info: ??? |
| 2331 | * @rxchain_info: ??? |
| 2332 | * @acquisition_data: ??? |
| 2333 | * @dsp_cfg_flags: set to 0 |
| 2334 | */ |
| 2335 | struct iwm_phy_context_cmd { |
| 2336 | /* COMMON_INDEX_HDR_API_S_VER_1 */ |
| 2337 | uint32_t id_and_color; |
| 2338 | uint32_t action; |
| 2339 | /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ |
| 2340 | uint32_t apply_time; |
| 2341 | uint32_t tx_param_color; |
| 2342 | struct iwm_fw_channel_info ci; |
| 2343 | uint32_t txchain_info; |
| 2344 | uint32_t rxchain_info; |
| 2345 | uint32_t acquisition_data; |
| 2346 | uint32_t dsp_cfg_flags; |
| 2347 | } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ |
| 2348 | |
| 2349 | #define IWM_RX_INFO_PHY_CNT 8 |
| 2350 | #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 |
| 2351 | #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff |
| 2352 | #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 |
| 2353 | #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 |
| 2354 | #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 |
| 2355 | #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 |
| 2356 | #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 |
| 2357 | |
| 2358 | #define IWM_RX_INFO_AGC_IDX 1 |
| 2359 | #define 2 |
| 2360 | #define IWM_OFDM_AGC_A_MSK 0x0000007f |
| 2361 | #define IWM_OFDM_AGC_A_POS 0 |
| 2362 | #define IWM_OFDM_AGC_B_MSK 0x00003f80 |
| 2363 | #define IWM_OFDM_AGC_B_POS 7 |
| 2364 | #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 |
| 2365 | #define IWM_OFDM_AGC_CODE_POS 20 |
| 2366 | #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff |
| 2367 | #define 0 |
| 2368 | #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 |
| 2369 | #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 |
| 2370 | #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 |
| 2371 | #define 16 |
| 2372 | #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 |
| 2373 | #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 |
| 2374 | |
| 2375 | /** |
| 2376 | * struct iwm_rx_phy_info - phy info |
| 2377 | * (IWM_REPLY_RX_PHY_CMD = 0xc0) |
| 2378 | * @non_cfg_phy_cnt: non configurable DSP phy data byte count |
| 2379 | * @cfg_phy_cnt: configurable DSP phy data byte count |
| 2380 | * @stat_id: configurable DSP phy data set ID |
| 2381 | * @reserved1: |
| 2382 | * @system_timestamp: GP2 at on air rise |
| 2383 | * @timestamp: TSF at on air rise |
| 2384 | * @beacon_time_stamp: beacon at on-air rise |
| 2385 | * @phy_flags: general phy flags: band, modulation, ... |
| 2386 | * @channel: channel number |
| 2387 | * @non_cfg_phy_buf: for various implementations of non_cfg_phy |
| 2388 | * @rate_n_flags: IWM_RATE_MCS_* |
| 2389 | * @byte_count: frame's byte-count |
| 2390 | * @frame_time: frame's time on the air, based on byte count and frame rate |
| 2391 | * calculation |
| 2392 | * @mac_active_msk: what MACs were active when the frame was received |
| 2393 | * |
| 2394 | * Before each Rx, the device sends this data. It contains PHY information |
| 2395 | * about the reception of the packet. |
| 2396 | */ |
| 2397 | struct iwm_rx_phy_info { |
| 2398 | uint8_t non_cfg_phy_cnt; |
| 2399 | uint8_t cfg_phy_cnt; |
| 2400 | uint8_t stat_id; |
| 2401 | uint8_t reserved1; |
| 2402 | uint32_t system_timestamp; |
| 2403 | uint64_t timestamp; |
| 2404 | uint32_t beacon_time_stamp; |
| 2405 | uint16_t phy_flags; |
| 2406 | #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) |
| 2407 | uint16_t channel; |
| 2408 | uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; |
| 2409 | uint8_t rate; |
| 2410 | uint8_t rflags; |
| 2411 | uint16_t xrflags; |
| 2412 | uint32_t byte_count; |
| 2413 | uint16_t mac_active_msk; |
| 2414 | uint16_t frame_time; |
| 2415 | } __packed; |
| 2416 | |
| 2417 | struct iwm_rx_mpdu_res_start { |
| 2418 | uint16_t byte_count; |
| 2419 | uint16_t reserved; |
| 2420 | } __packed; |
| 2421 | |
| 2422 | /** |
| 2423 | * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags |
| 2424 | * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band |
| 2425 | * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: |
| 2426 | * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short |
| 2427 | * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: |
| 2428 | * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received |
| 2429 | * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU |
| 2430 | * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame |
| 2431 | * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble |
| 2432 | * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame |
| 2433 | */ |
| 2434 | enum iwm_rx_phy_flags { |
| 2435 | IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), |
| 2436 | IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), |
| 2437 | IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), |
| 2438 | IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), |
| 2439 | IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), |
| 2440 | IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, |
| 2441 | IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), |
| 2442 | IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), |
| 2443 | IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), |
| 2444 | IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), |
| 2445 | }; |
| 2446 | |
| 2447 | /** |
| 2448 | * enum iwm_mvm_rx_status - written by fw for each Rx packet |
| 2449 | * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine |
| 2450 | * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow |
| 2451 | * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: |
| 2452 | * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: |
| 2453 | * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: |
| 2454 | * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed |
| 2455 | * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked |
| 2456 | * in the driver. |
| 2457 | * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine |
| 2458 | * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or |
| 2459 | * alg = CCM only. Checks replay attack for 11w frames. Relevant only if |
| 2460 | * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. |
| 2461 | * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted |
| 2462 | * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP |
| 2463 | * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM |
| 2464 | * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP |
| 2465 | * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC |
| 2466 | * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted |
| 2467 | * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm |
| 2468 | * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted |
| 2469 | * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: |
| 2470 | * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: |
| 2471 | * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: |
| 2472 | * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame |
| 2473 | * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: |
| 2474 | * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: |
| 2475 | * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: |
| 2476 | * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: |
| 2477 | * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: |
| 2478 | */ |
| 2479 | enum iwm_mvm_rx_status { |
| 2480 | IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), |
| 2481 | IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), |
| 2482 | IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), |
| 2483 | IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), |
| 2484 | IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), |
| 2485 | IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), |
| 2486 | IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), |
| 2487 | IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), |
| 2488 | IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), |
| 2489 | IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), |
| 2490 | IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), |
| 2491 | IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), |
| 2492 | IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), |
| 2493 | IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), |
| 2494 | IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), |
| 2495 | IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), |
| 2496 | IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), |
| 2497 | IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), |
| 2498 | IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), |
| 2499 | IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), |
| 2500 | IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), |
| 2501 | IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), |
| 2502 | IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), |
| 2503 | IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), |
| 2504 | IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), |
| 2505 | IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), |
| 2506 | IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), |
| 2507 | }; |
| 2508 | |
| 2509 | /** |
| 2510 | * struct iwm_radio_version_notif - information on the radio version |
| 2511 | * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) |
| 2512 | * @radio_flavor: |
| 2513 | * @radio_step: |
| 2514 | * @radio_dash: |
| 2515 | */ |
| 2516 | struct iwm_radio_version_notif { |
| 2517 | uint32_t radio_flavor; |
| 2518 | uint32_t radio_step; |
| 2519 | uint32_t radio_dash; |
| 2520 | } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ |
| 2521 | |
| 2522 | enum iwm_card_state_flags { |
| 2523 | IWM_CARD_ENABLED = 0x00, |
| 2524 | IWM_HW_CARD_DISABLED = 0x01, |
| 2525 | IWM_SW_CARD_DISABLED = 0x02, |
| 2526 | IWM_CT_KILL_CARD_DISABLED = 0x04, |
| 2527 | IWM_HALT_CARD_DISABLED = 0x08, |
| 2528 | IWM_CARD_DISABLED_MSK = 0x0f, |
| 2529 | IWM_CARD_IS_RX_ON = 0x10, |
| 2530 | }; |
| 2531 | |
| 2532 | /** |
| 2533 | * struct iwm_radio_version_notif - information on the radio version |
| 2534 | * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) |
| 2535 | * @flags: %iwm_card_state_flags |
| 2536 | */ |
| 2537 | struct iwm_card_state_notif { |
| 2538 | uint32_t flags; |
| 2539 | } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ |
| 2540 | |
| 2541 | /** |
| 2542 | * struct iwm_missed_beacons_notif - information on missed beacons |
| 2543 | * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) |
| 2544 | * @mac_id: interface ID |
| 2545 | * @consec_missed_beacons_since_last_rx: number of consecutive missed |
| 2546 | * beacons since last RX. |
| 2547 | * @consec_missed_beacons: number of consecutive missed beacons |
| 2548 | * @num_expected_beacons: |
| 2549 | * @num_recvd_beacons: |
| 2550 | */ |
| 2551 | struct iwm_missed_beacons_notif { |
| 2552 | uint32_t mac_id; |
| 2553 | uint32_t consec_missed_beacons_since_last_rx; |
| 2554 | uint32_t consec_missed_beacons; |
| 2555 | uint32_t num_expected_beacons; |
| 2556 | uint32_t num_recvd_beacons; |
| 2557 | } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ |
| 2558 | |
| 2559 | /** |
| 2560 | * struct iwm_set_calib_default_cmd - set default value for calibration. |
| 2561 | * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) |
| 2562 | * @calib_index: the calibration to set value for |
| 2563 | * @length: of data |
| 2564 | * @data: the value to set for the calibration result |
| 2565 | */ |
| 2566 | struct iwm_set_calib_default_cmd { |
| 2567 | uint16_t calib_index; |
| 2568 | uint16_t length; |
| 2569 | uint8_t data[0]; |
| 2570 | } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ |
| 2571 | |
| 2572 | #define IWM_MAX_PORT_ID_NUM 2 |
| 2573 | #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 |
| 2574 | |
| 2575 | /** |
| 2576 | * struct iwm_mcast_filter_cmd - configure multicast filter. |
| 2577 | * @filter_own: Set 1 to filter out multicast packets sent by station itself |
| 2578 | * @port_id: Multicast MAC addresses array specifier. This is a strange way |
| 2579 | * to identify network interface adopted in host-device IF. |
| 2580 | * It is used by FW as index in array of addresses. This array has |
| 2581 | * IWM_MAX_PORT_ID_NUM members. |
| 2582 | * @count: Number of MAC addresses in the array |
| 2583 | * @pass_all: Set 1 to pass all multicast packets. |
| 2584 | * @bssid: current association BSSID. |
| 2585 | * @addr_list: Place holder for array of MAC addresses. |
| 2586 | * IMPORTANT: add padding if necessary to ensure DWORD alignment. |
| 2587 | */ |
| 2588 | struct iwm_mcast_filter_cmd { |
| 2589 | uint8_t filter_own; |
| 2590 | uint8_t port_id; |
| 2591 | uint8_t count; |
| 2592 | uint8_t pass_all; |
| 2593 | uint8_t bssid[6]; |
| 2594 | uint8_t reserved[2]; |
| 2595 | uint8_t addr_list[0]; |
| 2596 | } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ |
| 2597 | |
| 2598 | struct iwm_mvm_statistics_dbg { |
| 2599 | uint32_t burst_check; |
| 2600 | uint32_t burst_count; |
| 2601 | uint32_t wait_for_silence_timeout_cnt; |
| 2602 | uint32_t reserved[3]; |
| 2603 | } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ |
| 2604 | |
| 2605 | struct iwm_mvm_statistics_div { |
| 2606 | uint32_t tx_on_a; |
| 2607 | uint32_t tx_on_b; |
| 2608 | uint32_t exec_time; |
| 2609 | uint32_t probe_time; |
| 2610 | uint32_t ; |
| 2611 | uint32_t reserved2; |
| 2612 | } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ |
| 2613 | |
| 2614 | struct iwm_mvm_statistics_general_common { |
| 2615 | uint32_t temperature; /* radio temperature */ |
| 2616 | uint32_t temperature_m; /* radio voltage */ |
| 2617 | struct iwm_mvm_statistics_dbg dbg; |
| 2618 | uint32_t sleep_time; |
| 2619 | uint32_t slots_out; |
| 2620 | uint32_t slots_idle; |
| 2621 | uint32_t ttl_timestamp; |
| 2622 | struct iwm_mvm_statistics_div div; |
| 2623 | uint32_t rx_enable_counter; |
| 2624 | /* |
| 2625 | * num_of_sos_states: |
| 2626 | * count the number of times we have to re-tune |
| 2627 | * in order to get out of bad PHY status |
| 2628 | */ |
| 2629 | uint32_t num_of_sos_states; |
| 2630 | } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ |
| 2631 | |
| 2632 | struct iwm_mvm_statistics_rx_non_phy { |
| 2633 | uint32_t bogus_cts; /* CTS received when not expecting CTS */ |
| 2634 | uint32_t bogus_ack; /* ACK received when not expecting ACK */ |
| 2635 | uint32_t non_bssid_frames; /* number of frames with BSSID that |
| 2636 | * doesn't belong to the STA BSSID */ |
| 2637 | uint32_t filtered_frames; /* count frames that were dumped in the |
| 2638 | * filtering process */ |
| 2639 | uint32_t non_channel_beacons; /* beacons with our bss id but not on |
| 2640 | * our serving channel */ |
| 2641 | uint32_t channel_beacons; /* beacons with our bss id and in our |
| 2642 | * serving channel */ |
| 2643 | uint32_t num_missed_bcon; /* number of missed beacons */ |
| 2644 | uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the |
| 2645 | * ADC was in saturation */ |
| 2646 | uint32_t ina_detection_search_time;/* total time (in 0.8us) searched |
| 2647 | * for INA */ |
| 2648 | uint32_t [3];/* RSSI silence after beacon frame */ |
| 2649 | uint32_t interference_data_flag; /* flag for interference data |
| 2650 | * availability. 1 when data is |
| 2651 | * available. */ |
| 2652 | uint32_t channel_load; /* counts RX Enable time in uSec */ |
| 2653 | uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM |
| 2654 | * and CCK) counter */ |
| 2655 | uint32_t ; |
| 2656 | uint32_t ; |
| 2657 | uint32_t ; |
| 2658 | uint32_t beacon_energy_a; |
| 2659 | uint32_t beacon_energy_b; |
| 2660 | uint32_t beacon_energy_c; |
| 2661 | uint32_t num_bt_kills; |
| 2662 | uint32_t mac_id; |
| 2663 | uint32_t directed_data_mpdu; |
| 2664 | } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ |
| 2665 | |
| 2666 | struct iwm_mvm_statistics_rx_phy { |
| 2667 | uint32_t ina_cnt; |
| 2668 | uint32_t fina_cnt; |
| 2669 | uint32_t plcp_err; |
| 2670 | uint32_t crc32_err; |
| 2671 | uint32_t overrun_err; |
| 2672 | uint32_t early_overrun_err; |
| 2673 | uint32_t crc32_good; |
| 2674 | uint32_t false_alarm_cnt; |
| 2675 | uint32_t fina_sync_err_cnt; |
| 2676 | uint32_t sfd_timeout; |
| 2677 | uint32_t fina_timeout; |
| 2678 | uint32_t unresponded_rts; |
| 2679 | uint32_t rxe_frame_limit_overrun; |
| 2680 | uint32_t sent_ack_cnt; |
| 2681 | uint32_t sent_cts_cnt; |
| 2682 | uint32_t sent_ba_rsp_cnt; |
| 2683 | uint32_t dsp_self_kill; |
| 2684 | uint32_t mh_format_err; |
| 2685 | uint32_t re_acq_main_rssi_sum; |
| 2686 | uint32_t reserved; |
| 2687 | } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ |
| 2688 | |
| 2689 | struct iwm_mvm_statistics_rx_ht_phy { |
| 2690 | uint32_t plcp_err; |
| 2691 | uint32_t overrun_err; |
| 2692 | uint32_t early_overrun_err; |
| 2693 | uint32_t crc32_good; |
| 2694 | uint32_t crc32_err; |
| 2695 | uint32_t mh_format_err; |
| 2696 | uint32_t agg_crc32_good; |
| 2697 | uint32_t agg_mpdu_cnt; |
| 2698 | uint32_t agg_cnt; |
| 2699 | uint32_t unsupport_mcs; |
| 2700 | } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ |
| 2701 | |
| 2702 | #define IWM_MAX_CHAINS 3 |
| 2703 | |
| 2704 | struct iwm_mvm_statistics_tx_non_phy_agg { |
| 2705 | uint32_t ba_timeout; |
| 2706 | uint32_t ba_reschedule_frames; |
| 2707 | uint32_t scd_query_agg_frame_cnt; |
| 2708 | uint32_t scd_query_no_agg; |
| 2709 | uint32_t scd_query_agg; |
| 2710 | uint32_t scd_query_mismatch; |
| 2711 | uint32_t frame_not_ready; |
| 2712 | uint32_t underrun; |
| 2713 | uint32_t bt_prio_kill; |
| 2714 | uint32_t rx_ba_rsp_cnt; |
| 2715 | int8_t txpower[IWM_MAX_CHAINS]; |
| 2716 | int8_t reserved; |
| 2717 | uint32_t reserved2; |
| 2718 | } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ |
| 2719 | |
| 2720 | struct iwm_mvm_statistics_tx_channel_width { |
| 2721 | uint32_t ext_cca_narrow_ch20[1]; |
| 2722 | uint32_t ext_cca_narrow_ch40[2]; |
| 2723 | uint32_t ext_cca_narrow_ch80[3]; |
| 2724 | uint32_t ext_cca_narrow_ch160[4]; |
| 2725 | uint32_t last_tx_ch_width_indx; |
| 2726 | uint32_t rx_detected_per_ch_width[4]; |
| 2727 | uint32_t success_per_ch_width[4]; |
| 2728 | uint32_t fail_per_ch_width[4]; |
| 2729 | }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ |
| 2730 | |
| 2731 | struct iwm_mvm_statistics_tx { |
| 2732 | uint32_t preamble_cnt; |
| 2733 | uint32_t rx_detected_cnt; |
| 2734 | uint32_t bt_prio_defer_cnt; |
| 2735 | uint32_t bt_prio_kill_cnt; |
| 2736 | uint32_t few_bytes_cnt; |
| 2737 | uint32_t cts_timeout; |
| 2738 | uint32_t ack_timeout; |
| 2739 | uint32_t expected_ack_cnt; |
| 2740 | uint32_t actual_ack_cnt; |
| 2741 | uint32_t dump_msdu_cnt; |
| 2742 | uint32_t burst_abort_next_frame_mismatch_cnt; |
| 2743 | uint32_t burst_abort_missing_next_frame_cnt; |
| 2744 | uint32_t cts_timeout_collision; |
| 2745 | uint32_t ack_or_ba_timeout_collision; |
| 2746 | struct iwm_mvm_statistics_tx_non_phy_agg agg; |
| 2747 | struct iwm_mvm_statistics_tx_channel_width channel_width; |
| 2748 | } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ |
| 2749 | |
| 2750 | |
| 2751 | struct iwm_mvm_statistics_bt_activity { |
| 2752 | uint32_t hi_priority_tx_req_cnt; |
| 2753 | uint32_t hi_priority_tx_denied_cnt; |
| 2754 | uint32_t lo_priority_tx_req_cnt; |
| 2755 | uint32_t lo_priority_tx_denied_cnt; |
| 2756 | uint32_t hi_priority_rx_req_cnt; |
| 2757 | uint32_t hi_priority_rx_denied_cnt; |
| 2758 | uint32_t lo_priority_rx_req_cnt; |
| 2759 | uint32_t lo_priority_rx_denied_cnt; |
| 2760 | } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ |
| 2761 | |
| 2762 | struct iwm_mvm_statistics_general { |
| 2763 | struct iwm_mvm_statistics_general_common common; |
| 2764 | uint32_t beacon_filtered; |
| 2765 | uint32_t missed_beacons; |
| 2766 | int8_t beacon_filter_average_energy; |
| 2767 | int8_t beacon_filter_reason; |
| 2768 | int8_t beacon_filter_current_energy; |
| 2769 | int8_t beacon_filter_reserved; |
| 2770 | uint32_t beacon_filter_delta_time; |
| 2771 | struct iwm_mvm_statistics_bt_activity bt_activity; |
| 2772 | } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ |
| 2773 | |
| 2774 | struct iwm_mvm_statistics_rx { |
| 2775 | struct iwm_mvm_statistics_rx_phy ofdm; |
| 2776 | struct iwm_mvm_statistics_rx_phy cck; |
| 2777 | struct iwm_mvm_statistics_rx_non_phy general; |
| 2778 | struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; |
| 2779 | } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ |
| 2780 | |
| 2781 | /* |
| 2782 | * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) |
| 2783 | * |
| 2784 | * By default, uCode issues this notification after receiving a beacon |
| 2785 | * while associated. To disable this behavior, set DISABLE_NOTIF flag in the |
| 2786 | * IWM_REPLY_STATISTICS_CMD 0x9c, above. |
| 2787 | * |
| 2788 | * Statistics counters continue to increment beacon after beacon, but are |
| 2789 | * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD |
| 2790 | * 0x9c with CLEAR_STATS bit set (see above). |
| 2791 | * |
| 2792 | * uCode also issues this notification during scans. uCode clears statistics |
| 2793 | * appropriately so that each notification contains statistics for only the |
| 2794 | * one channel that has just been scanned. |
| 2795 | */ |
| 2796 | |
| 2797 | struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ |
| 2798 | uint32_t flag; |
| 2799 | struct iwm_mvm_statistics_rx rx; |
| 2800 | struct iwm_mvm_statistics_tx tx; |
| 2801 | struct iwm_mvm_statistics_general general; |
| 2802 | } __packed; |
| 2803 | |
| 2804 | /*********************************** |
| 2805 | * Smart Fifo API |
| 2806 | ***********************************/ |
| 2807 | /* Smart Fifo state */ |
| 2808 | enum iwm_sf_state { |
| 2809 | IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ |
| 2810 | IWM_SF_FULL_ON, |
| 2811 | IWM_SF_UNINIT, |
| 2812 | IWM_SF_INIT_OFF, |
| 2813 | IWM_SF_HW_NUM_STATES |
| 2814 | }; |
| 2815 | |
| 2816 | /* Smart Fifo possible scenario */ |
| 2817 | enum iwm_sf_scenario { |
| 2818 | IWM_SF_SCENARIO_SINGLE_UNICAST, |
| 2819 | IWM_SF_SCENARIO_AGG_UNICAST, |
| 2820 | IWM_SF_SCENARIO_MULTICAST, |
| 2821 | IWM_SF_SCENARIO_BA_RESP, |
| 2822 | IWM_SF_SCENARIO_TX_RESP, |
| 2823 | IWM_SF_NUM_SCENARIO |
| 2824 | }; |
| 2825 | |
| 2826 | #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ |
| 2827 | #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ |
| 2828 | |
| 2829 | /* smart FIFO default values */ |
| 2830 | #define IWM_SF_W_MARK_SISO 4096 |
| 2831 | #define IWM_SF_W_MARK_MIMO2 8192 |
| 2832 | #define IWM_SF_W_MARK_MIMO3 6144 |
| 2833 | #define IWM_SF_W_MARK_LEGACY 4096 |
| 2834 | #define IWM_SF_W_MARK_SCAN 4096 |
| 2835 | |
| 2836 | /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ |
| 2837 | #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ |
| 2838 | #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ |
| 2839 | #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ |
| 2840 | #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ |
| 2841 | #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ |
| 2842 | #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ |
| 2843 | #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ |
| 2844 | #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ |
| 2845 | #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ |
| 2846 | #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ |
| 2847 | |
| 2848 | #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ |
| 2849 | |
| 2850 | /** |
| 2851 | * Smart Fifo configuration command. |
| 2852 | * @state: smart fifo state, types listed in iwm_sf_sate. |
| 2853 | * @watermark: Minimum allowed availabe free space in RXF for transient state. |
| 2854 | * @long_delay_timeouts: aging and idle timer values for each scenario |
| 2855 | * in long delay state. |
| 2856 | * @full_on_timeouts: timer values for each scenario in full on state. |
| 2857 | */ |
| 2858 | struct iwm_sf_cfg_cmd { |
| 2859 | enum iwm_sf_state state; |
| 2860 | uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; |
| 2861 | uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; |
| 2862 | uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; |
| 2863 | } __packed; /* IWM_SF_CFG_API_S_VER_2 */ |
| 2864 | |
| 2865 | /* |
| 2866 | * END mvm/fw-api.h |
| 2867 | */ |
| 2868 | |
| 2869 | /* |
| 2870 | * BEGIN mvm/fw-api-mac.h |
| 2871 | */ |
| 2872 | |
| 2873 | /* |
| 2874 | * The first MAC indices (starting from 0) |
| 2875 | * are available to the driver, AUX follows |
| 2876 | */ |
| 2877 | #define IWM_MAC_INDEX_AUX 4 |
| 2878 | #define IWM_MAC_INDEX_MIN_DRIVER 0 |
| 2879 | #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX |
| 2880 | |
| 2881 | enum iwm_ac { |
| 2882 | IWM_AC_BK, |
| 2883 | IWM_AC_BE, |
| 2884 | IWM_AC_VI, |
| 2885 | IWM_AC_VO, |
| 2886 | IWM_AC_NUM, |
| 2887 | }; |
| 2888 | |
| 2889 | /** |
| 2890 | * enum iwm_mac_protection_flags - MAC context flags |
| 2891 | * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, |
| 2892 | * this will require CCK RTS/CTS2self. |
| 2893 | * RTS/CTS will protect full burst time. |
| 2894 | * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection |
| 2895 | * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions |
| 2896 | * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self |
| 2897 | */ |
| 2898 | enum iwm_mac_protection_flags { |
| 2899 | IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), |
| 2900 | IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), |
| 2901 | IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), |
| 2902 | IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), |
| 2903 | }; |
| 2904 | |
| 2905 | #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) |
| 2906 | #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) |
| 2907 | |
| 2908 | /** |
| 2909 | * enum iwm_mac_types - Supported MAC types |
| 2910 | * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type |
| 2911 | * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) |
| 2912 | * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) |
| 2913 | * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS |
| 2914 | * @IWM_FW_MAC_TYPE_IBSS: IBSS |
| 2915 | * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station |
| 2916 | * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device |
| 2917 | * @IWM_FW_MAC_TYPE_P2P_STA: P2P client |
| 2918 | * @IWM_FW_MAC_TYPE_GO: P2P GO |
| 2919 | * @IWM_FW_MAC_TYPE_TEST: ? |
| 2920 | * @IWM_FW_MAC_TYPE_MAX: highest support MAC type |
| 2921 | */ |
| 2922 | enum iwm_mac_types { |
| 2923 | IWM_FW_MAC_TYPE_FIRST = 1, |
| 2924 | IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, |
| 2925 | IWM_FW_MAC_TYPE_LISTENER, |
| 2926 | IWM_FW_MAC_TYPE_PIBSS, |
| 2927 | IWM_FW_MAC_TYPE_IBSS, |
| 2928 | IWM_FW_MAC_TYPE_BSS_STA, |
| 2929 | IWM_FW_MAC_TYPE_P2P_DEVICE, |
| 2930 | IWM_FW_MAC_TYPE_P2P_STA, |
| 2931 | IWM_FW_MAC_TYPE_GO, |
| 2932 | IWM_FW_MAC_TYPE_TEST, |
| 2933 | IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST |
| 2934 | }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ |
| 2935 | |
| 2936 | /** |
| 2937 | * enum iwm_tsf_id - TSF hw timer ID |
| 2938 | * @IWM_TSF_ID_A: use TSF A |
| 2939 | * @IWM_TSF_ID_B: use TSF B |
| 2940 | * @IWM_TSF_ID_C: use TSF C |
| 2941 | * @IWM_TSF_ID_D: use TSF D |
| 2942 | * @IWM_NUM_TSF_IDS: number of TSF timers available |
| 2943 | */ |
| 2944 | enum iwm_tsf_id { |
| 2945 | IWM_TSF_ID_A = 0, |
| 2946 | IWM_TSF_ID_B = 1, |
| 2947 | IWM_TSF_ID_C = 2, |
| 2948 | IWM_TSF_ID_D = 3, |
| 2949 | IWM_NUM_TSF_IDS = 4, |
| 2950 | }; /* IWM_TSF_ID_API_E_VER_1 */ |
| 2951 | |
| 2952 | /** |
| 2953 | * struct iwm_mac_data_ap - configuration data for AP MAC context |
| 2954 | * @beacon_time: beacon transmit time in system time |
| 2955 | * @beacon_tsf: beacon transmit time in TSF |
| 2956 | * @bi: beacon interval in TU |
| 2957 | * @bi_reciprocal: 2^32 / bi |
| 2958 | * @dtim_interval: dtim transmit time in TU |
| 2959 | * @dtim_reciprocal: 2^32 / dtim_interval |
| 2960 | * @mcast_qid: queue ID for multicast traffic |
| 2961 | * @beacon_template: beacon template ID |
| 2962 | */ |
| 2963 | struct iwm_mac_data_ap { |
| 2964 | uint32_t beacon_time; |
| 2965 | uint64_t beacon_tsf; |
| 2966 | uint32_t bi; |
| 2967 | uint32_t bi_reciprocal; |
| 2968 | uint32_t dtim_interval; |
| 2969 | uint32_t dtim_reciprocal; |
| 2970 | uint32_t mcast_qid; |
| 2971 | uint32_t beacon_template; |
| 2972 | } __packed; /* AP_MAC_DATA_API_S_VER_1 */ |
| 2973 | |
| 2974 | /** |
| 2975 | * struct iwm_mac_data_ibss - configuration data for IBSS MAC context |
| 2976 | * @beacon_time: beacon transmit time in system time |
| 2977 | * @beacon_tsf: beacon transmit time in TSF |
| 2978 | * @bi: beacon interval in TU |
| 2979 | * @bi_reciprocal: 2^32 / bi |
| 2980 | * @beacon_template: beacon template ID |
| 2981 | */ |
| 2982 | struct iwm_mac_data_ibss { |
| 2983 | uint32_t beacon_time; |
| 2984 | uint64_t beacon_tsf; |
| 2985 | uint32_t bi; |
| 2986 | uint32_t bi_reciprocal; |
| 2987 | uint32_t beacon_template; |
| 2988 | } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ |
| 2989 | |
| 2990 | /** |
| 2991 | * struct iwm_mac_data_sta - configuration data for station MAC context |
| 2992 | * @is_assoc: 1 for associated state, 0 otherwise |
| 2993 | * @dtim_time: DTIM arrival time in system time |
| 2994 | * @dtim_tsf: DTIM arrival time in TSF |
| 2995 | * @bi: beacon interval in TU, applicable only when associated |
| 2996 | * @bi_reciprocal: 2^32 / bi , applicable only when associated |
| 2997 | * @dtim_interval: DTIM interval in TU, applicable only when associated |
| 2998 | * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated |
| 2999 | * @listen_interval: in beacon intervals, applicable only when associated |
| 3000 | * @assoc_id: unique ID assigned by the AP during association |
| 3001 | */ |
| 3002 | struct iwm_mac_data_sta { |
| 3003 | uint32_t is_assoc; |
| 3004 | uint32_t dtim_time; |
| 3005 | uint64_t dtim_tsf; |
| 3006 | uint32_t bi; |
| 3007 | uint32_t bi_reciprocal; |
| 3008 | uint32_t dtim_interval; |
| 3009 | uint32_t dtim_reciprocal; |
| 3010 | uint32_t listen_interval; |
| 3011 | uint32_t assoc_id; |
| 3012 | uint32_t assoc_beacon_arrive_time; |
| 3013 | } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ |
| 3014 | |
| 3015 | /** |
| 3016 | * struct iwm_mac_data_go - configuration data for P2P GO MAC context |
| 3017 | * @ap: iwm_mac_data_ap struct with most config data |
| 3018 | * @ctwin: client traffic window in TU (period after TBTT when GO is present). |
| 3019 | * 0 indicates that there is no CT window. |
| 3020 | * @opp_ps_enabled: indicate that opportunistic PS allowed |
| 3021 | */ |
| 3022 | struct iwm_mac_data_go { |
| 3023 | struct iwm_mac_data_ap ap; |
| 3024 | uint32_t ctwin; |
| 3025 | uint32_t opp_ps_enabled; |
| 3026 | } __packed; /* GO_MAC_DATA_API_S_VER_1 */ |
| 3027 | |
| 3028 | /** |
| 3029 | * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context |
| 3030 | * @sta: iwm_mac_data_sta struct with most config data |
| 3031 | * @ctwin: client traffic window in TU (period after TBTT when GO is present). |
| 3032 | * 0 indicates that there is no CT window. |
| 3033 | */ |
| 3034 | struct iwm_mac_data_p2p_sta { |
| 3035 | struct iwm_mac_data_sta sta; |
| 3036 | uint32_t ctwin; |
| 3037 | } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ |
| 3038 | |
| 3039 | /** |
| 3040 | * struct iwm_mac_data_pibss - Pseudo IBSS config data |
| 3041 | * @stats_interval: interval in TU between statistics notifications to host. |
| 3042 | */ |
| 3043 | struct iwm_mac_data_pibss { |
| 3044 | uint32_t stats_interval; |
| 3045 | } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ |
| 3046 | |
| 3047 | /* |
| 3048 | * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC |
| 3049 | * context. |
| 3050 | * @is_disc_extended: if set to true, P2P Device discoverability is enabled on |
| 3051 | * other channels as well. This should be to true only in case that the |
| 3052 | * device is discoverable and there is an active GO. Note that setting this |
| 3053 | * field when not needed, will increase the number of interrupts and have |
| 3054 | * effect on the platform power, as this setting opens the Rx filters on |
| 3055 | * all macs. |
| 3056 | */ |
| 3057 | struct iwm_mac_data_p2p_dev { |
| 3058 | uint32_t is_disc_extended; |
| 3059 | } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ |
| 3060 | |
| 3061 | /** |
| 3062 | * enum iwm_mac_filter_flags - MAC context filter flags |
| 3063 | * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames |
| 3064 | * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and |
| 3065 | * control frames to the host |
| 3066 | * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames |
| 3067 | * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames |
| 3068 | * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames |
| 3069 | * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host |
| 3070 | * (in station mode when associated) |
| 3071 | * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames |
| 3072 | * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames |
| 3073 | * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host |
| 3074 | */ |
| 3075 | enum iwm_mac_filter_flags { |
| 3076 | IWM_MAC_FILTER_IN_PROMISC = (1 << 0), |
| 3077 | IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), |
| 3078 | IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), |
| 3079 | IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), |
| 3080 | IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), |
| 3081 | IWM_MAC_FILTER_IN_BEACON = (1 << 6), |
| 3082 | IWM_MAC_FILTER_OUT_BCAST = (1 << 8), |
| 3083 | IWM_MAC_FILTER_IN_CRC32 = (1 << 11), |
| 3084 | IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), |
| 3085 | }; |
| 3086 | |
| 3087 | /** |
| 3088 | * enum iwm_mac_qos_flags - QoS flags |
| 3089 | * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? |
| 3090 | * @IWM_MAC_QOS_FLG_TGN: HT is enabled |
| 3091 | * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? |
| 3092 | * |
| 3093 | */ |
| 3094 | enum iwm_mac_qos_flags { |
| 3095 | IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), |
| 3096 | IWM_MAC_QOS_FLG_TGN = (1 << 1), |
| 3097 | IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), |
| 3098 | }; |
| 3099 | |
| 3100 | /** |
| 3101 | * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD |
| 3102 | * @cw_min: Contention window, start value in numbers of slots. |
| 3103 | * Should be a power-of-2, minus 1. Device's default is 0x0f. |
| 3104 | * @cw_max: Contention window, max value in numbers of slots. |
| 3105 | * Should be a power-of-2, minus 1. Device's default is 0x3f. |
| 3106 | * @aifsn: Number of slots in Arbitration Interframe Space (before |
| 3107 | * performing random backoff timing prior to Tx). Device default 1. |
| 3108 | * @fifos_mask: FIFOs used by this MAC for this AC |
| 3109 | * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. |
| 3110 | * |
| 3111 | * One instance of this config struct for each of 4 EDCA access categories |
| 3112 | * in struct iwm_qosparam_cmd. |
| 3113 | * |
| 3114 | * Device will automatically increase contention window by (2*CW) + 1 for each |
| 3115 | * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW |
| 3116 | * value, to cap the CW value. |
| 3117 | */ |
| 3118 | struct iwm_ac_qos { |
| 3119 | uint16_t cw_min; |
| 3120 | uint16_t cw_max; |
| 3121 | uint8_t aifsn; |
| 3122 | uint8_t fifos_mask; |
| 3123 | uint16_t edca_txop; |
| 3124 | } __packed; /* IWM_AC_QOS_API_S_VER_2 */ |
| 3125 | |
| 3126 | /** |
| 3127 | * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts |
| 3128 | * ( IWM_MAC_CONTEXT_CMD = 0x28 ) |
| 3129 | * @id_and_color: ID and color of the MAC |
| 3130 | * @action: action to perform, one of IWM_FW_CTXT_ACTION_* |
| 3131 | * @mac_type: one of IWM_FW_MAC_TYPE_* |
| 3132 | * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* |
| 3133 | * @node_addr: MAC address |
| 3134 | * @bssid_addr: BSSID |
| 3135 | * @cck_rates: basic rates available for CCK |
| 3136 | * @ofdm_rates: basic rates available for OFDM |
| 3137 | * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* |
| 3138 | * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise |
| 3139 | * @short_slot: 0x10 for enabling short slots, 0 otherwise |
| 3140 | * @filter_flags: combination of IWM_MAC_FILTER_* |
| 3141 | * @qos_flags: from IWM_MAC_QOS_FLG_* |
| 3142 | * @ac: one iwm_mac_qos configuration for each AC |
| 3143 | * @mac_specific: one of struct iwm_mac_data_*, according to mac_type |
| 3144 | */ |
| 3145 | struct iwm_mac_ctx_cmd { |
| 3146 | /* COMMON_INDEX_HDR_API_S_VER_1 */ |
| 3147 | uint32_t id_and_color; |
| 3148 | uint32_t action; |
| 3149 | /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ |
| 3150 | uint32_t mac_type; |
| 3151 | uint32_t tsf_id; |
| 3152 | uint8_t node_addr[6]; |
| 3153 | uint16_t reserved_for_node_addr; |
| 3154 | uint8_t bssid_addr[6]; |
| 3155 | uint16_t reserved_for_bssid_addr; |
| 3156 | uint32_t cck_rates; |
| 3157 | uint32_t ofdm_rates; |
| 3158 | uint32_t protection_flags; |
| 3159 | uint32_t cck_short_preamble; |
| 3160 | uint32_t short_slot; |
| 3161 | uint32_t filter_flags; |
| 3162 | /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ |
| 3163 | uint32_t qos_flags; |
| 3164 | struct iwm_ac_qos ac[IWM_AC_NUM+1]; |
| 3165 | /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ |
| 3166 | union { |
| 3167 | struct iwm_mac_data_ap ap; |
| 3168 | struct iwm_mac_data_go go; |
| 3169 | struct iwm_mac_data_sta sta; |
| 3170 | struct iwm_mac_data_p2p_sta p2p_sta; |
| 3171 | struct iwm_mac_data_p2p_dev p2p_dev; |
| 3172 | struct iwm_mac_data_pibss pibss; |
| 3173 | struct iwm_mac_data_ibss ibss; |
| 3174 | }; |
| 3175 | } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ |
| 3176 | |
| 3177 | static inline uint32_t iwm_mvm_reciprocal(uint32_t v) |
| 3178 | { |
| 3179 | if (!v) |
| 3180 | return 0; |
| 3181 | return 0xFFFFFFFF / v; |
| 3182 | } |
| 3183 | |
| 3184 | #define IWM_NONQOS_SEQ_GET 0x1 |
| 3185 | #define IWM_NONQOS_SEQ_SET 0x2 |
| 3186 | struct iwm_nonqos_seq_query_cmd { |
| 3187 | uint32_t get_set_flag; |
| 3188 | uint32_t mac_id_n_color; |
| 3189 | uint16_t value; |
| 3190 | uint16_t reserved; |
| 3191 | } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ |
| 3192 | |
| 3193 | /* |
| 3194 | * END mvm/fw-api-mac.h |
| 3195 | */ |
| 3196 | |
| 3197 | /* |
| 3198 | * BEGIN mvm/fw-api-power.h |
| 3199 | */ |
| 3200 | |
| 3201 | /* Power Management Commands, Responses, Notifications */ |
| 3202 | |
| 3203 | /* Radio LP RX Energy Threshold measured in dBm */ |
| 3204 | #define 75 |
| 3205 | #define 94 |
| 3206 | #define 30 |
| 3207 | |
| 3208 | /** |
| 3209 | * enum iwm_scan_flags - masks for power table command flags |
| 3210 | * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off |
| 3211 | * receiver and transmitter. '0' - does not allow. |
| 3212 | * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, |
| 3213 | * '1' Driver enables PM (use rest of parameters) |
| 3214 | * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, |
| 3215 | * '1' PM could sleep over DTIM till listen Interval. |
| 3216 | * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all |
| 3217 | * access categories are both delivery and trigger enabled. |
| 3218 | * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and |
| 3219 | * PBW Snoozing enabled |
| 3220 | * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask |
| 3221 | * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. |
| 3222 | * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving |
| 3223 | * detection enablement |
| 3224 | */ |
| 3225 | enum iwm_power_flags { |
| 3226 | IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), |
| 3227 | IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), |
| 3228 | IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), |
| 3229 | IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), |
| 3230 | IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), |
| 3231 | IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), |
| 3232 | IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), |
| 3233 | IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), |
| 3234 | }; |
| 3235 | |
| 3236 | #define IWM_POWER_VEC_SIZE 5 |
| 3237 | |
| 3238 | /** |
| 3239 | * struct iwm_powertable_cmd - legacy power command. Beside old API support this |
| 3240 | * is used also with a new power API for device wide power settings. |
| 3241 | * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) |
| 3242 | * |
| 3243 | * @flags: Power table command flags from IWM_POWER_FLAGS_* |
| 3244 | * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. |
| 3245 | * Minimum allowed:- 3 * DTIM. Keep alive period must be |
| 3246 | * set regardless of power scheme or current power state. |
| 3247 | * FW use this value also when PM is disabled. |
| 3248 | * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to |
| 3249 | * PSM transition - legacy PM |
| 3250 | * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to |
| 3251 | * PSM transition - legacy PM |
| 3252 | * @sleep_interval: not in use |
| 3253 | * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag |
| 3254 | * is set. For example, if it is required to skip over |
| 3255 | * one DTIM, this value need to be set to 2 (DTIM periods). |
| 3256 | * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. |
| 3257 | * Default: 80dbm |
| 3258 | */ |
| 3259 | struct iwm_powertable_cmd { |
| 3260 | /* PM_POWER_TABLE_CMD_API_S_VER_6 */ |
| 3261 | uint16_t flags; |
| 3262 | uint8_t keep_alive_seconds; |
| 3263 | uint8_t debug_flags; |
| 3264 | uint32_t rx_data_timeout; |
| 3265 | uint32_t tx_data_timeout; |
| 3266 | uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; |
| 3267 | uint32_t skip_dtim_periods; |
| 3268 | uint32_t ; |
| 3269 | } __packed; |
| 3270 | |
| 3271 | /** |
| 3272 | * enum iwm_device_power_flags - masks for device power command flags |
| 3273 | * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off |
| 3274 | * receiver and transmitter. '0' - does not allow. This flag should be |
| 3275 | * always set to '1' unless one need to disable actual power down for debug |
| 3276 | * purposes. |
| 3277 | * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning |
| 3278 | * that power management is disabled. '0' Power management is enabled, one |
| 3279 | * of power schemes is applied. |
| 3280 | */ |
| 3281 | enum iwm_device_power_flags { |
| 3282 | IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), |
| 3283 | IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), |
| 3284 | }; |
| 3285 | |
| 3286 | /** |
| 3287 | * struct iwm_device_power_cmd - device wide power command. |
| 3288 | * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) |
| 3289 | * |
| 3290 | * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* |
| 3291 | */ |
| 3292 | struct iwm_device_power_cmd { |
| 3293 | /* PM_POWER_TABLE_CMD_API_S_VER_6 */ |
| 3294 | uint16_t flags; |
| 3295 | uint16_t reserved; |
| 3296 | } __packed; |
| 3297 | |
| 3298 | /** |
| 3299 | * struct iwm_mac_power_cmd - New power command containing uAPSD support |
| 3300 | * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) |
| 3301 | * @id_and_color: MAC contex identifier |
| 3302 | * @flags: Power table command flags from POWER_FLAGS_* |
| 3303 | * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. |
| 3304 | * Minimum allowed:- 3 * DTIM. Keep alive period must be |
| 3305 | * set regardless of power scheme or current power state. |
| 3306 | * FW use this value also when PM is disabled. |
| 3307 | * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to |
| 3308 | * PSM transition - legacy PM |
| 3309 | * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to |
| 3310 | * PSM transition - legacy PM |
| 3311 | * @sleep_interval: not in use |
| 3312 | * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag |
| 3313 | * is set. For example, if it is required to skip over |
| 3314 | * one DTIM, this value need to be set to 2 (DTIM periods). |
| 3315 | * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to |
| 3316 | * PSM transition - uAPSD |
| 3317 | * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to |
| 3318 | * PSM transition - uAPSD |
| 3319 | * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. |
| 3320 | * Default: 80dbm |
| 3321 | * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set |
| 3322 | * @snooze_interval: Maximum time between attempts to retrieve buffered data |
| 3323 | * from the AP [msec] |
| 3324 | * @snooze_window: A window of time in which PBW snoozing insures that all |
| 3325 | * packets received. It is also the minimum time from last |
| 3326 | * received unicast RX packet, before client stops snoozing |
| 3327 | * for data. [msec] |
| 3328 | * @snooze_step: TBD |
| 3329 | * @qndp_tid: TID client shall use for uAPSD QNDP triggers |
| 3330 | * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for |
| 3331 | * each corresponding AC. |
| 3332 | * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. |
| 3333 | * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct |
| 3334 | * values. |
| 3335 | * @heavy_tx_thld_packets: TX threshold measured in number of packets |
| 3336 | * @heavy_rx_thld_packets: RX threshold measured in number of packets |
| 3337 | * @heavy_tx_thld_percentage: TX threshold measured in load's percentage |
| 3338 | * @heavy_rx_thld_percentage: RX threshold measured in load's percentage |
| 3339 | * @limited_ps_threshold: |
| 3340 | */ |
| 3341 | struct iwm_mac_power_cmd { |
| 3342 | /* CONTEXT_DESC_API_T_VER_1 */ |
| 3343 | uint32_t id_and_color; |
| 3344 | |
| 3345 | /* CLIENT_PM_POWER_TABLE_S_VER_1 */ |
| 3346 | uint16_t flags; |
| 3347 | uint16_t keep_alive_seconds; |
| 3348 | uint32_t rx_data_timeout; |
| 3349 | uint32_t tx_data_timeout; |
| 3350 | uint32_t rx_data_timeout_uapsd; |
| 3351 | uint32_t tx_data_timeout_uapsd; |
| 3352 | uint8_t ; |
| 3353 | uint8_t skip_dtim_periods; |
| 3354 | uint16_t snooze_interval; |
| 3355 | uint16_t snooze_window; |
| 3356 | uint8_t snooze_step; |
| 3357 | uint8_t qndp_tid; |
| 3358 | uint8_t uapsd_ac_flags; |
| 3359 | uint8_t uapsd_max_sp; |
| 3360 | uint8_t heavy_tx_thld_packets; |
| 3361 | uint8_t heavy_rx_thld_packets; |
| 3362 | uint8_t heavy_tx_thld_percentage; |
| 3363 | uint8_t heavy_rx_thld_percentage; |
| 3364 | uint8_t limited_ps_threshold; |
| 3365 | uint8_t reserved; |
| 3366 | } __packed; |
| 3367 | |
| 3368 | /* |
| 3369 | * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when |
| 3370 | * associated AP is identified as improperly implementing uAPSD protocol. |
| 3371 | * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 |
| 3372 | * @sta_id: index of station in uCode's station table - associated AP ID in |
| 3373 | * this context. |
| 3374 | */ |
| 3375 | struct iwm_uapsd_misbehaving_ap_notif { |
| 3376 | uint32_t sta_id; |
| 3377 | uint8_t mac_id; |
| 3378 | uint8_t reserved[3]; |
| 3379 | } __packed; |
| 3380 | |
| 3381 | /** |
| 3382 | * struct iwm_beacon_filter_cmd |
| 3383 | * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) |
| 3384 | * @id_and_color: MAC contex identifier |
| 3385 | * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon |
| 3386 | * to driver if delta in Energy values calculated for this and last |
| 3387 | * passed beacon is greater than this threshold. Zero value means that |
| 3388 | * the Energy change is ignored for beacon filtering, and beacon will |
| 3389 | * not be forced to be sent to driver regardless of this delta. Typical |
| 3390 | * energy delta 5dB. |
| 3391 | * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. |
| 3392 | * Send beacon to driver if delta in Energy values calculated for this |
| 3393 | * and last passed beacon is greater than this threshold. Zero value |
| 3394 | * means that the Energy change is ignored for beacon filtering while in |
| 3395 | * Roaming state, typical energy delta 1dB. |
| 3396 | * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values |
| 3397 | * calculated for current beacon is less than the threshold, use |
| 3398 | * Roaming Energy Delta Threshold, otherwise use normal Energy Delta |
| 3399 | * Threshold. Typical energy threshold is -72dBm. |
| 3400 | * @bf_temp_threshold: This threshold determines the type of temperature |
| 3401 | * filtering (Slow or Fast) that is selected (Units are in Celsuis): |
| 3402 | * If the current temperature is above this threshold - Fast filter |
| 3403 | * will be used, If the current temperature is below this threshold - |
| 3404 | * Slow filter will be used. |
| 3405 | * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values |
| 3406 | * calculated for this and the last passed beacon is greater than this |
| 3407 | * threshold. Zero value means that the temperature change is ignored for |
| 3408 | * beacon filtering; beacons will not be forced to be sent to driver |
| 3409 | * regardless of whether its temerature has been changed. |
| 3410 | * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values |
| 3411 | * calculated for this and the last passed beacon is greater than this |
| 3412 | * threshold. Zero value means that the temperature change is ignored for |
| 3413 | * beacon filtering; beacons will not be forced to be sent to driver |
| 3414 | * regardless of whether its temerature has been changed. |
| 3415 | * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. |
| 3416 | * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed |
| 3417 | * for a specific period of time. Units: Beacons. |
| 3418 | * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed |
| 3419 | * for a longer period of time then this escape-timeout. Units: Beacons. |
| 3420 | * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. |
| 3421 | */ |
| 3422 | struct iwm_beacon_filter_cmd { |
| 3423 | uint32_t bf_energy_delta; |
| 3424 | uint32_t bf_roaming_energy_delta; |
| 3425 | uint32_t bf_roaming_state; |
| 3426 | uint32_t bf_temp_threshold; |
| 3427 | uint32_t bf_temp_fast_filter; |
| 3428 | uint32_t bf_temp_slow_filter; |
| 3429 | uint32_t bf_enable_beacon_filter; |
| 3430 | uint32_t bf_debug_flag; |
| 3431 | uint32_t bf_escape_timer; |
| 3432 | uint32_t ba_escape_timer; |
| 3433 | uint32_t ba_enable_beacon_abort; |
| 3434 | } __packed; |
| 3435 | |
| 3436 | /* Beacon filtering and beacon abort */ |
| 3437 | #define IWM_BF_ENERGY_DELTA_DEFAULT 5 |
| 3438 | #define IWM_BF_ENERGY_DELTA_MAX 255 |
| 3439 | #define IWM_BF_ENERGY_DELTA_MIN 0 |
| 3440 | |
| 3441 | #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 |
| 3442 | #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 |
| 3443 | #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 |
| 3444 | |
| 3445 | #define IWM_BF_ROAMING_STATE_DEFAULT 72 |
| 3446 | #define IWM_BF_ROAMING_STATE_MAX 255 |
| 3447 | #define IWM_BF_ROAMING_STATE_MIN 0 |
| 3448 | |
| 3449 | #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 |
| 3450 | #define IWM_BF_TEMP_THRESHOLD_MAX 255 |
| 3451 | #define IWM_BF_TEMP_THRESHOLD_MIN 0 |
| 3452 | |
| 3453 | #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 |
| 3454 | #define IWM_BF_TEMP_FAST_FILTER_MAX 255 |
| 3455 | #define IWM_BF_TEMP_FAST_FILTER_MIN 0 |
| 3456 | |
| 3457 | #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 |
| 3458 | #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 |
| 3459 | #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 |
| 3460 | |
| 3461 | #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 |
| 3462 | |
| 3463 | #define IWM_BF_DEBUG_FLAG_DEFAULT 0 |
| 3464 | |
| 3465 | #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 |
| 3466 | #define IWM_BF_ESCAPE_TIMER_MAX 1024 |
| 3467 | #define IWM_BF_ESCAPE_TIMER_MIN 0 |
| 3468 | |
| 3469 | #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 |
| 3470 | #define IWM_BA_ESCAPE_TIMER_D3 9 |
| 3471 | #define IWM_BA_ESCAPE_TIMER_MAX 1024 |
| 3472 | #define IWM_BA_ESCAPE_TIMER_MIN 0 |
| 3473 | |
| 3474 | #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 |
| 3475 | |
| 3476 | #define IWM_BF_CMD_CONFIG_DEFAULTS \ |
| 3477 | .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ |
| 3478 | .bf_roaming_energy_delta = \ |
| 3479 | htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ |
| 3480 | .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ |
| 3481 | .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ |
| 3482 | .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ |
| 3483 | .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ |
| 3484 | .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ |
| 3485 | .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ |
| 3486 | .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) |
| 3487 | |
| 3488 | /* |
| 3489 | * END mvm/fw-api-power.h |
| 3490 | */ |
| 3491 | |
| 3492 | /* |
| 3493 | * BEGIN mvm/fw-api-rs.h |
| 3494 | */ |
| 3495 | |
| 3496 | /* |
| 3497 | * These serve as indexes into |
| 3498 | * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; |
| 3499 | * TODO: avoid overlap between legacy and HT rates |
| 3500 | */ |
| 3501 | enum { |
| 3502 | IWM_RATE_1M_INDEX = 0, |
| 3503 | IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, |
| 3504 | IWM_RATE_2M_INDEX, |
| 3505 | IWM_RATE_5M_INDEX, |
| 3506 | IWM_RATE_11M_INDEX, |
| 3507 | IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, |
| 3508 | IWM_RATE_6M_INDEX, |
| 3509 | IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, |
| 3510 | IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, |
| 3511 | IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, |
| 3512 | IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, |
| 3513 | IWM_RATE_9M_INDEX, |
| 3514 | IWM_RATE_12M_INDEX, |
| 3515 | IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, |
| 3516 | IWM_RATE_18M_INDEX, |
| 3517 | IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, |
| 3518 | IWM_RATE_24M_INDEX, |
| 3519 | IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, |
| 3520 | IWM_RATE_36M_INDEX, |
| 3521 | IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, |
| 3522 | IWM_RATE_48M_INDEX, |
| 3523 | IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, |
| 3524 | IWM_RATE_54M_INDEX, |
| 3525 | IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, |
| 3526 | IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, |
| 3527 | IWM_RATE_60M_INDEX, |
| 3528 | IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, |
| 3529 | IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, |
| 3530 | IWM_RATE_MCS_8_INDEX, |
| 3531 | IWM_RATE_MCS_9_INDEX, |
| 3532 | IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, |
| 3533 | IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, |
| 3534 | IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, |
| 3535 | }; |
| 3536 | |
| 3537 | #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) |
| 3538 | |
| 3539 | /* fw API values for legacy bit rates, both OFDM and CCK */ |
| 3540 | enum { |
| 3541 | IWM_RATE_6M_PLCP = 13, |
| 3542 | IWM_RATE_9M_PLCP = 15, |
| 3543 | IWM_RATE_12M_PLCP = 5, |
| 3544 | IWM_RATE_18M_PLCP = 7, |
| 3545 | IWM_RATE_24M_PLCP = 9, |
| 3546 | IWM_RATE_36M_PLCP = 11, |
| 3547 | IWM_RATE_48M_PLCP = 1, |
| 3548 | IWM_RATE_54M_PLCP = 3, |
| 3549 | IWM_RATE_1M_PLCP = 10, |
| 3550 | IWM_RATE_2M_PLCP = 20, |
| 3551 | IWM_RATE_5M_PLCP = 55, |
| 3552 | IWM_RATE_11M_PLCP = 110, |
| 3553 | IWM_RATE_INVM_PLCP = -1, |
| 3554 | }; |
| 3555 | |
| 3556 | /* |
| 3557 | * rate_n_flags bit fields |
| 3558 | * |
| 3559 | * The 32-bit value has different layouts in the low 8 bites depending on the |
| 3560 | * format. There are three formats, HT, VHT and legacy (11abg, with subformats |
| 3561 | * for CCK and OFDM). |
| 3562 | * |
| 3563 | * High-throughput (HT) rate format |
| 3564 | * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) |
| 3565 | * Very High-throughput (VHT) rate format |
| 3566 | * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) |
| 3567 | * Legacy OFDM rate format for bits 7:0 |
| 3568 | * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) |
| 3569 | * Legacy CCK rate format for bits 7:0: |
| 3570 | * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) |
| 3571 | */ |
| 3572 | |
| 3573 | /* Bit 8: (1) HT format, (0) legacy or VHT format */ |
| 3574 | #define IWM_RATE_MCS_HT_POS 8 |
| 3575 | #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) |
| 3576 | |
| 3577 | /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ |
| 3578 | #define IWM_RATE_MCS_CCK_POS 9 |
| 3579 | #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) |
| 3580 | |
| 3581 | /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ |
| 3582 | #define IWM_RATE_MCS_VHT_POS 26 |
| 3583 | #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) |
| 3584 | |
| 3585 | |
| 3586 | /* |
| 3587 | * High-throughput (HT) rate format for bits 7:0 |
| 3588 | * |
| 3589 | * 2-0: MCS rate base |
| 3590 | * 0) 6 Mbps |
| 3591 | * 1) 12 Mbps |
| 3592 | * 2) 18 Mbps |
| 3593 | * 3) 24 Mbps |
| 3594 | * 4) 36 Mbps |
| 3595 | * 5) 48 Mbps |
| 3596 | * 6) 54 Mbps |
| 3597 | * 7) 60 Mbps |
| 3598 | * 4-3: 0) Single stream (SISO) |
| 3599 | * 1) Dual stream (MIMO) |
| 3600 | * 2) Triple stream (MIMO) |
| 3601 | * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data |
| 3602 | * (bits 7-6 are zero) |
| 3603 | * |
| 3604 | * Together the low 5 bits work out to the MCS index because we don't |
| 3605 | * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two |
| 3606 | * streams and 16-23 have three streams. We could also support MCS 32 |
| 3607 | * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) |
| 3608 | */ |
| 3609 | #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 |
| 3610 | #define IWM_RATE_HT_MCS_NSS_POS 3 |
| 3611 | #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) |
| 3612 | |
| 3613 | /* Bit 10: (1) Use Green Field preamble */ |
| 3614 | #define IWM_RATE_HT_MCS_GF_POS 10 |
| 3615 | #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) |
| 3616 | |
| 3617 | #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f |
| 3618 | |
| 3619 | /* |
| 3620 | * Very High-throughput (VHT) rate format for bits 7:0 |
| 3621 | * |
| 3622 | * 3-0: VHT MCS (0-9) |
| 3623 | * 5-4: number of streams - 1: |
| 3624 | * 0) Single stream (SISO) |
| 3625 | * 1) Dual stream (MIMO) |
| 3626 | * 2) Triple stream (MIMO) |
| 3627 | */ |
| 3628 | |
| 3629 | /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ |
| 3630 | #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf |
| 3631 | #define IWM_RATE_VHT_MCS_NSS_POS 4 |
| 3632 | #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) |
| 3633 | |
| 3634 | /* |
| 3635 | * Legacy OFDM rate format for bits 7:0 |
| 3636 | * |
| 3637 | * 3-0: 0xD) 6 Mbps |
| 3638 | * 0xF) 9 Mbps |
| 3639 | * 0x5) 12 Mbps |
| 3640 | * 0x7) 18 Mbps |
| 3641 | * 0x9) 24 Mbps |
| 3642 | * 0xB) 36 Mbps |
| 3643 | * 0x1) 48 Mbps |
| 3644 | * 0x3) 54 Mbps |
| 3645 | * (bits 7-4 are 0) |
| 3646 | * |
| 3647 | * Legacy CCK rate format for bits 7:0: |
| 3648 | * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): |
| 3649 | * |
| 3650 | * 6-0: 10) 1 Mbps |
| 3651 | * 20) 2 Mbps |
| 3652 | * 55) 5.5 Mbps |
| 3653 | * 110) 11 Mbps |
| 3654 | * (bit 7 is 0) |
| 3655 | */ |
| 3656 | #define IWM_RATE_LEGACY_RATE_MSK 0xff |
| 3657 | |
| 3658 | |
| 3659 | /* |
| 3660 | * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz |
| 3661 | * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT |
| 3662 | */ |
| 3663 | #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 |
| 3664 | #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) |
| 3665 | #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) |
| 3666 | #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) |
| 3667 | #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) |
| 3668 | #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) |
| 3669 | |
| 3670 | /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ |
| 3671 | #define IWM_RATE_MCS_SGI_POS 13 |
| 3672 | #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) |
| 3673 | |
| 3674 | /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ |
| 3675 | #define IWM_RATE_MCS_ANT_POS 14 |
| 3676 | #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) |
| 3677 | #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) |
| 3678 | #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) |
| 3679 | #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ |
| 3680 | IWM_RATE_MCS_ANT_B_MSK) |
| 3681 | #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ |
| 3682 | IWM_RATE_MCS_ANT_C_MSK) |
| 3683 | #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK |
| 3684 | #define IWM_RATE_MCS_ANT_NUM 3 |
| 3685 | |
| 3686 | /* Bit 17-18: (0) SS, (1) SS*2 */ |
| 3687 | #define IWM_RATE_MCS_STBC_POS 17 |
| 3688 | #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) |
| 3689 | |
| 3690 | /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ |
| 3691 | #define IWM_RATE_MCS_BF_POS 19 |
| 3692 | #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) |
| 3693 | |
| 3694 | /* Bit 20: (0) ZLF is off, (1) ZLF is on */ |
| 3695 | #define IWM_RATE_MCS_ZLF_POS 20 |
| 3696 | #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) |
| 3697 | |
| 3698 | /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ |
| 3699 | #define IWM_RATE_MCS_DUP_POS 24 |
| 3700 | #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) |
| 3701 | |
| 3702 | /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ |
| 3703 | #define IWM_RATE_MCS_LDPC_POS 27 |
| 3704 | #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) |
| 3705 | |
| 3706 | |
| 3707 | /* Link Quality definitions */ |
| 3708 | |
| 3709 | /* # entries in rate scale table to support Tx retries */ |
| 3710 | #define IWM_LQ_MAX_RETRY_NUM 16 |
| 3711 | |
| 3712 | /* Link quality command flags bit fields */ |
| 3713 | |
| 3714 | /* Bit 0: (0) Don't use RTS (1) Use RTS */ |
| 3715 | #define IWM_LQ_FLAG_USE_RTS_POS 0 |
| 3716 | #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) |
| 3717 | |
| 3718 | /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ |
| 3719 | #define IWM_LQ_FLAG_COLOR_POS 1 |
| 3720 | #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) |
| 3721 | |
| 3722 | /* Bit 4-5: Tx RTS BW Signalling |
| 3723 | * (0) No RTS BW signalling |
| 3724 | * (1) Static BW signalling |
| 3725 | * (2) Dynamic BW signalling |
| 3726 | */ |
| 3727 | #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 |
| 3728 | #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) |
| 3729 | #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) |
| 3730 | #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) |
| 3731 | |
| 3732 | /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection |
| 3733 | * Dyanmic BW selection allows Tx with narrower BW then requested in rates |
| 3734 | */ |
| 3735 | #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 |
| 3736 | #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) |
| 3737 | |
| 3738 | /** |
| 3739 | * struct iwm_lq_cmd - link quality command |
| 3740 | * @sta_id: station to update |
| 3741 | * @control: not used |
| 3742 | * @flags: combination of IWM_LQ_FLAG_* |
| 3743 | * @mimo_delim: the first SISO index in rs_table, which separates MIMO |
| 3744 | * and SISO rates |
| 3745 | * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). |
| 3746 | * Should be ANT_[ABC] |
| 3747 | * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] |
| 3748 | * @initial_rate_index: first index from rs_table per AC category |
| 3749 | * @agg_time_limit: aggregation max time threshold in usec/100, meaning |
| 3750 | * value of 100 is one usec. Range is 100 to 8000 |
| 3751 | * @agg_disable_start_th: try-count threshold for starting aggregation. |
| 3752 | * If a frame has higher try-count, it should not be selected for |
| 3753 | * starting an aggregation sequence. |
| 3754 | * @agg_frame_cnt_limit: max frame count in an aggregation. |
| 3755 | * 0: no limit |
| 3756 | * 1: no aggregation (one frame per aggregation) |
| 3757 | * 2 - 0x3f: maximal number of frames (up to 3f == 63) |
| 3758 | * @rs_table: array of rates for each TX try, each is rate_n_flags, |
| 3759 | * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP |
| 3760 | * @bf_params: beam forming params, currently not used |
| 3761 | */ |
| 3762 | struct iwm_lq_cmd { |
| 3763 | uint8_t sta_id; |
| 3764 | uint8_t reserved1; |
| 3765 | uint16_t control; |
| 3766 | /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ |
| 3767 | uint8_t flags; |
| 3768 | uint8_t mimo_delim; |
| 3769 | uint8_t single_stream_ant_msk; |
| 3770 | uint8_t dual_stream_ant_msk; |
| 3771 | uint8_t initial_rate_index[IWM_AC_NUM]; |
| 3772 | /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ |
| 3773 | uint16_t agg_time_limit; |
| 3774 | uint8_t agg_disable_start_th; |
| 3775 | uint8_t agg_frame_cnt_limit; |
| 3776 | uint32_t reserved2; |
| 3777 | uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; |
| 3778 | uint32_t bf_params; |
| 3779 | }; /* LINK_QUALITY_CMD_API_S_VER_1 */ |
| 3780 | |
| 3781 | /* |
| 3782 | * END mvm/fw-api-rs.h |
| 3783 | */ |
| 3784 | |
| 3785 | /* |
| 3786 | * BEGIN mvm/fw-api-tx.h |
| 3787 | */ |
| 3788 | |
| 3789 | /** |
| 3790 | * enum iwm_tx_flags - bitmasks for tx_flags in TX command |
| 3791 | * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame |
| 3792 | * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station |
| 3793 | * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. |
| 3794 | * Otherwise, use rate_n_flags from the TX command |
| 3795 | * @IWM_TX_CMD_FLG_BA: this frame is a block ack |
| 3796 | * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected |
| 3797 | * Must set IWM_TX_CMD_FLG_ACK with this flag. |
| 3798 | * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection |
| 3799 | * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence |
| 3800 | * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence |
| 3801 | * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) |
| 3802 | * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame |
| 3803 | * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. |
| 3804 | * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command |
| 3805 | * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU |
| 3806 | * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame |
| 3807 | * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame |
| 3808 | * Should be set for beacons and probe responses |
| 3809 | * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations |
| 3810 | * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count |
| 3811 | * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation |
| 3812 | * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. |
| 3813 | * Should be set for 26/30 length MAC headers |
| 3814 | * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW |
| 3815 | * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration |
| 3816 | * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation |
| 3817 | * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id |
| 3818 | * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped |
| 3819 | * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD |
| 3820 | * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power |
| 3821 | * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk |
| 3822 | */ |
| 3823 | enum iwm_tx_flags { |
| 3824 | IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), |
| 3825 | IWM_TX_CMD_FLG_ACK = (1 << 3), |
| 3826 | IWM_TX_CMD_FLG_STA_RATE = (1 << 4), |
| 3827 | IWM_TX_CMD_FLG_BA = (1 << 5), |
| 3828 | IWM_TX_CMD_FLG_BAR = (1 << 6), |
| 3829 | IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), |
| 3830 | IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), |
| 3831 | IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), |
| 3832 | IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), |
| 3833 | IWM_TX_CMD_FLG_BT_DIS = (1 << 12), |
| 3834 | IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), |
| 3835 | IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), |
| 3836 | IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), |
| 3837 | IWM_TX_CMD_FLG_TSF = (1 << 16), |
| 3838 | IWM_TX_CMD_FLG_CALIB = (1 << 17), |
| 3839 | IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), |
| 3840 | IWM_TX_CMD_FLG_AGG_START = (1 << 19), |
| 3841 | IWM_TX_CMD_FLG_MH_PAD = (1 << 20), |
| 3842 | IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), |
| 3843 | IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), |
| 3844 | IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), |
| 3845 | IWM_TX_CMD_FLG_DUR = (1 << 25), |
| 3846 | IWM_TX_CMD_FLG_FW_DROP = (1 << 26), |
| 3847 | IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), |
| 3848 | IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), |
| 3849 | IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) |
| 3850 | }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ |
| 3851 | |
| 3852 | /* |
| 3853 | * TX command security control |
| 3854 | */ |
| 3855 | #define IWM_TX_CMD_SEC_WEP 0x01 |
| 3856 | #define IWM_TX_CMD_SEC_CCM 0x02 |
| 3857 | #define IWM_TX_CMD_SEC_TKIP 0x03 |
| 3858 | #define IWM_TX_CMD_SEC_EXT 0x04 |
| 3859 | #define IWM_TX_CMD_SEC_MSK 0x07 |
| 3860 | #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 |
| 3861 | #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 |
| 3862 | #define IWM_TX_CMD_SEC_KEY128 0x08 |
| 3863 | |
| 3864 | /* TODO: how does these values are OK with only 16 bit variable??? */ |
| 3865 | /* |
| 3866 | * TX command next frame info |
| 3867 | * |
| 3868 | * bits 0:2 - security control (IWM_TX_CMD_SEC_*) |
| 3869 | * bit 3 - immediate ACK required |
| 3870 | * bit 4 - rate is taken from STA table |
| 3871 | * bit 5 - frame belongs to BA stream |
| 3872 | * bit 6 - immediate BA response expected |
| 3873 | * bit 7 - unused |
| 3874 | * bits 8:15 - Station ID |
| 3875 | * bits 16:31 - rate |
| 3876 | */ |
| 3877 | #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) |
| 3878 | #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) |
| 3879 | #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) |
| 3880 | #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) |
| 3881 | #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) |
| 3882 | #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) |
| 3883 | #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) |
| 3884 | #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) |
| 3885 | #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) |
| 3886 | |
| 3887 | /* |
| 3888 | * TX command Frame life time in us - to be written in pm_frame_timeout |
| 3889 | */ |
| 3890 | #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF |
| 3891 | #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ |
| 3892 | #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ |
| 3893 | #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 |
| 3894 | |
| 3895 | /* |
| 3896 | * TID for non QoS frames - to be written in tid_tspec |
| 3897 | */ |
| 3898 | #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT |
| 3899 | |
| 3900 | /* |
| 3901 | * Limits on the retransmissions - to be written in {data,rts}_retry_limit |
| 3902 | */ |
| 3903 | #define IWM_DEFAULT_TX_RETRY 15 |
| 3904 | #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 |
| 3905 | #define IWM_RTS_DFAULT_RETRY_LIMIT 60 |
| 3906 | #define IWM_BAR_DFAULT_RETRY_LIMIT 60 |
| 3907 | #define IWM_LOW_RETRY_LIMIT 7 |
| 3908 | |
| 3909 | /* TODO: complete documentation for try_cnt and btkill_cnt */ |
| 3910 | /** |
| 3911 | * struct iwm_tx_cmd - TX command struct to FW |
| 3912 | * ( IWM_TX_CMD = 0x1c ) |
| 3913 | * @len: in bytes of the payload, see below for details |
| 3914 | * @next_frame_len: same as len, but for next frame (0 if not applicable) |
| 3915 | * Used for fragmentation and bursting, but not in 11n aggregation. |
| 3916 | * @tx_flags: combination of IWM_TX_CMD_FLG_* |
| 3917 | * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is |
| 3918 | * cleared. Combination of IWM_RATE_MCS_* |
| 3919 | * @sta_id: index of destination station in FW station table |
| 3920 | * @sec_ctl: security control, IWM_TX_CMD_SEC_* |
| 3921 | * @initial_rate_index: index into the the rate table for initial TX attempt. |
| 3922 | * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. |
| 3923 | * @key: security key |
| 3924 | * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* |
| 3925 | * @life_time: frame life time (usecs??) |
| 3926 | * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + |
| 3927 | * btkill_cnd + reserved), first 32 bits. "0" disables usage. |
| 3928 | * @dram_msb_ptr: upper bits of the scratch physical address |
| 3929 | * @rts_retry_limit: max attempts for RTS |
| 3930 | * @data_retry_limit: max attempts to send the data packet |
| 3931 | * @tid_spec: TID/tspec |
| 3932 | * @pm_frame_timeout: PM TX frame timeout |
| 3933 | * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not |
| 3934 | * specified by HCCA protocol |
| 3935 | * |
| 3936 | * The byte count (both len and next_frame_len) includes MAC header |
| 3937 | * (24/26/30/32 bytes) |
| 3938 | * + 2 bytes pad if 26/30 header size |
| 3939 | * + 8 byte IV for CCM or TKIP (not used for WEP) |
| 3940 | * + Data payload |
| 3941 | * + 8-byte MIC (not used for CCM/WEP) |
| 3942 | * It does not include post-MAC padding, i.e., |
| 3943 | * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. |
| 3944 | * Range of len: 14-2342 bytes. |
| 3945 | * |
| 3946 | * After the struct fields the MAC header is placed, plus any padding, |
| 3947 | * and then the actial payload. |
| 3948 | */ |
| 3949 | struct iwm_tx_cmd { |
| 3950 | uint16_t len; |
| 3951 | uint16_t next_frame_len; |
| 3952 | uint32_t tx_flags; |
| 3953 | struct { |
| 3954 | uint8_t try_cnt; |
| 3955 | uint8_t btkill_cnt; |
| 3956 | uint16_t reserved; |
| 3957 | } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ |
| 3958 | uint32_t rate_n_flags; |
| 3959 | uint8_t sta_id; |
| 3960 | uint8_t sec_ctl; |
| 3961 | uint8_t initial_rate_index; |
| 3962 | uint8_t reserved2; |
| 3963 | uint8_t key[16]; |
| 3964 | uint16_t next_frame_flags; |
| 3965 | uint16_t reserved3; |
| 3966 | uint32_t life_time; |
| 3967 | uint32_t dram_lsb_ptr; |
| 3968 | uint8_t dram_msb_ptr; |
| 3969 | uint8_t rts_retry_limit; |
| 3970 | uint8_t data_retry_limit; |
| 3971 | uint8_t tid_tspec; |
| 3972 | uint16_t pm_frame_timeout; |
| 3973 | uint16_t driver_txop; |
| 3974 | uint8_t payload[0]; |
| 3975 | struct ieee80211_frame hdr[0]; |
| 3976 | } __packed; /* IWM_TX_CMD_API_S_VER_3 */ |
| 3977 | |
| 3978 | /* |
| 3979 | * TX response related data |
| 3980 | */ |
| 3981 | |
| 3982 | /* |
| 3983 | * enum iwm_tx_status - status that is returned by the fw after attempts to Tx |
| 3984 | * @IWM_TX_STATUS_SUCCESS: |
| 3985 | * @IWM_TX_STATUS_DIRECT_DONE: |
| 3986 | * @IWM_TX_STATUS_POSTPONE_DELAY: |
| 3987 | * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: |
| 3988 | * @IWM_TX_STATUS_POSTPONE_BT_PRIO: |
| 3989 | * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: |
| 3990 | * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: |
| 3991 | * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: |
| 3992 | * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: |
| 3993 | * @IWM_TX_STATUS_FAIL_LONG_LIMIT: |
| 3994 | * @IWM_TX_STATUS_FAIL_UNDERRUN: |
| 3995 | * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: |
| 3996 | * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: |
| 3997 | * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: |
| 3998 | * @IWM_TX_STATUS_FAIL_DEST_PS: |
| 3999 | * @IWM_TX_STATUS_FAIL_HOST_ABORTED: |
| 4000 | * @IWM_TX_STATUS_FAIL_BT_RETRY: |
| 4001 | * @IWM_TX_STATUS_FAIL_STA_INVALID: |
| 4002 | * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: |
| 4003 | * @IWM_TX_STATUS_FAIL_TID_DISABLE: |
| 4004 | * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: |
| 4005 | * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: |
| 4006 | * @IWM_TX_STATUS_FAIL_FW_DROP: |
| 4007 | * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and |
| 4008 | * STA table |
| 4009 | * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: |
| 4010 | * @IWM_TX_MODE_MSK: |
| 4011 | * @IWM_TX_MODE_NO_BURST: |
| 4012 | * @IWM_TX_MODE_IN_BURST_SEQ: |
| 4013 | * @IWM_TX_MODE_FIRST_IN_BURST: |
| 4014 | * @IWM_TX_QUEUE_NUM_MSK: |
| 4015 | * |
| 4016 | * Valid only if frame_count =1 |
| 4017 | * TODO: complete documentation |
| 4018 | */ |
| 4019 | enum iwm_tx_status { |
| 4020 | IWM_TX_STATUS_MSK = 0x000000ff, |
| 4021 | IWM_TX_STATUS_SUCCESS = 0x01, |
| 4022 | IWM_TX_STATUS_DIRECT_DONE = 0x02, |
| 4023 | /* postpone TX */ |
| 4024 | IWM_TX_STATUS_POSTPONE_DELAY = 0x40, |
| 4025 | IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, |
| 4026 | IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, |
| 4027 | IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, |
| 4028 | IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, |
| 4029 | /* abort TX */ |
| 4030 | IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, |
| 4031 | IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, |
| 4032 | IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, |
| 4033 | IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, |
| 4034 | IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, |
| 4035 | IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, |
| 4036 | IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, |
| 4037 | IWM_TX_STATUS_FAIL_DEST_PS = 0x88, |
| 4038 | IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, |
| 4039 | IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, |
| 4040 | IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, |
| 4041 | IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, |
| 4042 | IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, |
| 4043 | IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, |
| 4044 | IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, |
| 4045 | IWM_TX_STATUS_FAIL_FW_DROP = 0x90, |
| 4046 | IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, |
| 4047 | IWM_TX_STATUS_INTERNAL_ABORT = 0x92, |
| 4048 | IWM_TX_MODE_MSK = 0x00000f00, |
| 4049 | IWM_TX_MODE_NO_BURST = 0x00000000, |
| 4050 | IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, |
| 4051 | IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, |
| 4052 | IWM_TX_QUEUE_NUM_MSK = 0x0001f000, |
| 4053 | IWM_TX_NARROW_BW_MSK = 0x00060000, |
| 4054 | IWM_TX_NARROW_BW_1DIV2 = 0x00020000, |
| 4055 | IWM_TX_NARROW_BW_1DIV4 = 0x00040000, |
| 4056 | IWM_TX_NARROW_BW_1DIV8 = 0x00060000, |
| 4057 | }; |
| 4058 | |
| 4059 | /* |
| 4060 | * enum iwm_tx_agg_status - TX aggregation status |
| 4061 | * @IWM_AGG_TX_STATE_STATUS_MSK: |
| 4062 | * @IWM_AGG_TX_STATE_TRANSMITTED: |
| 4063 | * @IWM_AGG_TX_STATE_UNDERRUN: |
| 4064 | * @IWM_AGG_TX_STATE_BT_PRIO: |
| 4065 | * @IWM_AGG_TX_STATE_FEW_BYTES: |
| 4066 | * @IWM_AGG_TX_STATE_ABORT: |
| 4067 | * @IWM_AGG_TX_STATE_LAST_SENT_TTL: |
| 4068 | * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: |
| 4069 | * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: |
| 4070 | * @IWM_AGG_TX_STATE_SCD_QUERY: |
| 4071 | * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: |
| 4072 | * @IWM_AGG_TX_STATE_RESPONSE: |
| 4073 | * @IWM_AGG_TX_STATE_DUMP_TX: |
| 4074 | * @IWM_AGG_TX_STATE_DELAY_TX: |
| 4075 | * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries |
| 4076 | * occur if tx failed for this frame when it was a member of a previous |
| 4077 | * aggregation block). If rate scaling is used, retry count indicates the |
| 4078 | * rate table entry used for all frames in the new agg. |
| 4079 | *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for |
| 4080 | * this frame |
| 4081 | * |
| 4082 | * TODO: complete documentation |
| 4083 | */ |
| 4084 | enum iwm_tx_agg_status { |
| 4085 | IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, |
| 4086 | IWM_AGG_TX_STATE_TRANSMITTED = 0x000, |
| 4087 | IWM_AGG_TX_STATE_UNDERRUN = 0x001, |
| 4088 | IWM_AGG_TX_STATE_BT_PRIO = 0x002, |
| 4089 | IWM_AGG_TX_STATE_FEW_BYTES = 0x004, |
| 4090 | IWM_AGG_TX_STATE_ABORT = 0x008, |
| 4091 | IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, |
| 4092 | IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, |
| 4093 | IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, |
| 4094 | IWM_AGG_TX_STATE_SCD_QUERY = 0x080, |
| 4095 | IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, |
| 4096 | IWM_AGG_TX_STATE_RESPONSE = 0x1ff, |
| 4097 | IWM_AGG_TX_STATE_DUMP_TX = 0x200, |
| 4098 | IWM_AGG_TX_STATE_DELAY_TX = 0x400, |
| 4099 | IWM_AGG_TX_STATE_TRY_CNT_POS = 12, |
| 4100 | IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, |
| 4101 | }; |
| 4102 | |
| 4103 | #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ |
| 4104 | IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ |
| 4105 | IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) |
| 4106 | |
| 4107 | /* |
| 4108 | * The mask below describes a status where we are absolutely sure that the MPDU |
| 4109 | * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've |
| 4110 | * written the bytes to the TXE, but we know nothing about what the DSP did. |
| 4111 | */ |
| 4112 | #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ |
| 4113 | IWM_AGG_TX_STATE_ABORT | \ |
| 4114 | IWM_AGG_TX_STATE_SCD_QUERY) |
| 4115 | |
| 4116 | /* |
| 4117 | * IWM_REPLY_TX = 0x1c (response) |
| 4118 | * |
| 4119 | * This response may be in one of two slightly different formats, indicated |
| 4120 | * by the frame_count field: |
| 4121 | * |
| 4122 | * 1) No aggregation (frame_count == 1). This reports Tx results for a single |
| 4123 | * frame. Multiple attempts, at various bit rates, may have been made for |
| 4124 | * this frame. |
| 4125 | * |
| 4126 | * 2) Aggregation (frame_count > 1). This reports Tx results for two or more |
| 4127 | * frames that used block-acknowledge. All frames were transmitted at |
| 4128 | * same rate. Rate scaling may have been used if first frame in this new |
| 4129 | * agg block failed in previous agg block(s). |
| 4130 | * |
| 4131 | * Note that, for aggregation, ACK (block-ack) status is not delivered |
| 4132 | * here; block-ack has not been received by the time the device records |
| 4133 | * this status. |
| 4134 | * This status relates to reasons the tx might have been blocked or aborted |
| 4135 | * within the device, rather than whether it was received successfully by |
| 4136 | * the destination station. |
| 4137 | */ |
| 4138 | |
| 4139 | /** |
| 4140 | * struct iwm_agg_tx_status - per packet TX aggregation status |
| 4141 | * @status: enum iwm_tx_agg_status |
| 4142 | * @sequence: Sequence # for this frame's Tx cmd (not SSN!) |
| 4143 | */ |
| 4144 | struct iwm_agg_tx_status { |
| 4145 | uint16_t status; |
| 4146 | uint16_t sequence; |
| 4147 | } __packed; |
| 4148 | |
| 4149 | /* |
| 4150 | * definitions for initial rate index field |
| 4151 | * bits [3:0] initial rate index |
| 4152 | * bits [6:4] rate table color, used for the initial rate |
| 4153 | * bit-7 invalid rate indication |
| 4154 | */ |
| 4155 | #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f |
| 4156 | #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 |
| 4157 | #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 |
| 4158 | |
| 4159 | #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) |
| 4160 | #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) |
| 4161 | |
| 4162 | /** |
| 4163 | * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet |
| 4164 | * ( IWM_REPLY_TX = 0x1c ) |
| 4165 | * @frame_count: 1 no aggregation, >1 aggregation |
| 4166 | * @bt_kill_count: num of times blocked by bluetooth (unused for agg) |
| 4167 | * @failure_rts: num of failures due to unsuccessful RTS |
| 4168 | * @failure_frame: num failures due to no ACK (unused for agg) |
| 4169 | * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the |
| 4170 | * Tx of all the batch. IWM_RATE_MCS_* |
| 4171 | * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. |
| 4172 | * for agg: RTS + CTS + aggregation tx time + block-ack time. |
| 4173 | * in usec. |
| 4174 | * @pa_status: tx power info |
| 4175 | * @pa_integ_res_a: tx power info |
| 4176 | * @pa_integ_res_b: tx power info |
| 4177 | * @pa_integ_res_c: tx power info |
| 4178 | * @measurement_req_id: tx power info |
| 4179 | * @tfd_info: TFD information set by the FH |
| 4180 | * @seq_ctl: sequence control from the Tx cmd |
| 4181 | * @byte_cnt: byte count from the Tx cmd |
| 4182 | * @tlc_info: TLC rate info |
| 4183 | * @ra_tid: bits [3:0] = ra, bits [7:4] = tid |
| 4184 | * @frame_ctrl: frame control |
| 4185 | * @status: for non-agg: frame status IWM_TX_STATUS_* |
| 4186 | * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields |
| 4187 | * follow this one, up to frame_count. |
| 4188 | * |
| 4189 | * After the array of statuses comes the SSN of the SCD. Look at |
| 4190 | * %iwm_mvm_get_scd_ssn for more details. |
| 4191 | */ |
| 4192 | struct iwm_mvm_tx_resp { |
| 4193 | uint8_t frame_count; |
| 4194 | uint8_t bt_kill_count; |
| 4195 | uint8_t failure_rts; |
| 4196 | uint8_t failure_frame; |
| 4197 | uint32_t initial_rate; |
| 4198 | uint16_t wireless_media_time; |
| 4199 | |
| 4200 | uint8_t pa_status; |
| 4201 | uint8_t pa_integ_res_a[3]; |
| 4202 | uint8_t pa_integ_res_b[3]; |
| 4203 | uint8_t pa_integ_res_c[3]; |
| 4204 | uint16_t measurement_req_id; |
| 4205 | uint16_t reserved; |
| 4206 | |
| 4207 | uint32_t tfd_info; |
| 4208 | uint16_t seq_ctl; |
| 4209 | uint16_t byte_cnt; |
| 4210 | uint8_t tlc_info; |
| 4211 | uint8_t ra_tid; |
| 4212 | uint16_t frame_ctrl; |
| 4213 | |
| 4214 | struct iwm_agg_tx_status status; |
| 4215 | } __packed; /* IWM_TX_RSP_API_S_VER_3 */ |
| 4216 | |
| 4217 | /** |
| 4218 | * struct iwm_mvm_ba_notif - notifies about reception of BA |
| 4219 | * ( IWM_BA_NOTIF = 0xc5 ) |
| 4220 | * @sta_addr_lo32: lower 32 bits of the MAC address |
| 4221 | * @sta_addr_hi16: upper 16 bits of the MAC address |
| 4222 | * @sta_id: Index of recipient (BA-sending) station in fw's station table |
| 4223 | * @tid: tid of the session |
| 4224 | * @seq_ctl: |
| 4225 | * @bitmap: the bitmap of the BA notification as seen in the air |
| 4226 | * @scd_flow: the tx queue this BA relates to |
| 4227 | * @scd_ssn: the index of the last contiguously sent packet |
| 4228 | * @txed: number of Txed frames in this batch |
| 4229 | * @txed_2_done: number of Acked frames in this batch |
| 4230 | */ |
| 4231 | struct iwm_mvm_ba_notif { |
| 4232 | uint32_t sta_addr_lo32; |
| 4233 | uint16_t sta_addr_hi16; |
| 4234 | uint16_t reserved; |
| 4235 | |
| 4236 | uint8_t sta_id; |
| 4237 | uint8_t tid; |
| 4238 | uint16_t seq_ctl; |
| 4239 | uint64_t bitmap; |
| 4240 | uint16_t scd_flow; |
| 4241 | uint16_t scd_ssn; |
| 4242 | uint8_t txed; |
| 4243 | uint8_t txed_2_done; |
| 4244 | uint16_t reserved1; |
| 4245 | } __packed; |
| 4246 | |
| 4247 | /* |
| 4248 | * struct iwm_mac_beacon_cmd - beacon template command |
| 4249 | * @tx: the tx commands associated with the beacon frame |
| 4250 | * @template_id: currently equal to the mac context id of the coresponding |
| 4251 | * mac. |
| 4252 | * @tim_idx: the offset of the tim IE in the beacon |
| 4253 | * @tim_size: the length of the tim IE |
| 4254 | * @frame: the template of the beacon frame |
| 4255 | */ |
| 4256 | struct iwm_mac_beacon_cmd { |
| 4257 | struct iwm_tx_cmd tx; |
| 4258 | uint32_t template_id; |
| 4259 | uint32_t tim_idx; |
| 4260 | uint32_t tim_size; |
| 4261 | struct ieee80211_frame frame[0]; |
| 4262 | } __packed; |
| 4263 | |
| 4264 | struct iwm_beacon_notif { |
| 4265 | struct iwm_mvm_tx_resp beacon_notify_hdr; |
| 4266 | uint64_t tsf; |
| 4267 | uint32_t ibss_mgr_status; |
| 4268 | } __packed; |
| 4269 | |
| 4270 | /** |
| 4271 | * enum iwm_dump_control - dump (flush) control flags |
| 4272 | * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the the FIFO is empty |
| 4273 | * and the TFD queues are empty. |
| 4274 | */ |
| 4275 | enum iwm_dump_control { |
| 4276 | IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), |
| 4277 | }; |
| 4278 | |
| 4279 | /** |
| 4280 | * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command |
| 4281 | * @queues_ctl: bitmap of queues to flush |
| 4282 | * @flush_ctl: control flags |
| 4283 | * @reserved: reserved |
| 4284 | */ |
| 4285 | struct iwm_tx_path_flush_cmd { |
| 4286 | uint32_t queues_ctl; |
| 4287 | uint16_t flush_ctl; |
| 4288 | uint16_t reserved; |
| 4289 | } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ |
| 4290 | |
| 4291 | /** |
| 4292 | * iwm_mvm_get_scd_ssn - returns the SSN of the SCD |
| 4293 | * @tx_resp: the Tx response from the fw (agg or non-agg) |
| 4294 | * |
| 4295 | * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since |
| 4296 | * it can't know that everything will go well until the end of the AMPDU, it |
| 4297 | * can't know in advance the number of MPDUs that will be sent in the current |
| 4298 | * batch. This is why it writes the agg Tx response while it fetches the MPDUs. |
| 4299 | * Hence, it can't know in advance what the SSN of the SCD will be at the end |
| 4300 | * of the batch. This is why the SSN of the SCD is written at the end of the |
| 4301 | * whole struct at a variable offset. This function knows how to cope with the |
| 4302 | * variable offset and returns the SSN of the SCD. |
| 4303 | */ |
| 4304 | static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) |
| 4305 | { |
| 4306 | return le32_to_cpup((uint32_t *)&tx_resp->status + |
| 4307 | tx_resp->frame_count) & 0xfff; |
| 4308 | } |
| 4309 | |
| 4310 | /* |
| 4311 | * END mvm/fw-api-tx.h |
| 4312 | */ |
| 4313 | |
| 4314 | /* |
| 4315 | * BEGIN mvm/fw-api-scan.h |
| 4316 | */ |
| 4317 | |
| 4318 | /* Scan Commands, Responses, Notifications */ |
| 4319 | |
| 4320 | /* Masks for iwm_scan_channel.type flags */ |
| 4321 | #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) |
| 4322 | #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) |
| 4323 | |
| 4324 | /* Max number of IEs for direct SSID scans in a command */ |
| 4325 | #define IWM_PROBE_OPTION_MAX 20 |
| 4326 | |
| 4327 | /** |
| 4328 | * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table |
| 4329 | * @channel: band is selected by iwm_scan_cmd "flags" field |
| 4330 | * @tx_gain: gain for analog radio |
| 4331 | * @dsp_atten: gain for DSP |
| 4332 | * @active_dwell: dwell time for active scan in TU, typically 5-50 |
| 4333 | * @passive_dwell: dwell time for passive scan in TU, typically 20-500 |
| 4334 | * @type: type is broken down to these bits: |
| 4335 | * bit 0: 0 = passive, 1 = active |
| 4336 | * bits 1-20: SSID direct bit map. If any of these bits is set then |
| 4337 | * the corresponding SSID IE is transmitted in probe request |
| 4338 | * (bit i adds IE in position i to the probe request) |
| 4339 | * bit 22: channel width, 0 = regular, 1 = TGj narrow channel |
| 4340 | * |
| 4341 | * @iteration_count: |
| 4342 | * @iteration_interval: |
| 4343 | * This struct is used once for each channel in the scan list. |
| 4344 | * Each channel can independently select: |
| 4345 | * 1) SSID for directed active scans |
| 4346 | * 2) Txpower setting (for rate specified within Tx command) |
| 4347 | * 3) How long to stay on-channel (behavior may be modified by quiet_time, |
| 4348 | * quiet_plcp_th, good_CRC_th) |
| 4349 | * |
| 4350 | * To avoid uCode errors, make sure the following are true (see comments |
| 4351 | * under struct iwm_scan_cmd about max_out_time and quiet_time): |
| 4352 | * 1) If using passive_dwell (i.e. passive_dwell != 0): |
| 4353 | * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) |
| 4354 | * 2) quiet_time <= active_dwell |
| 4355 | * 3) If restricting off-channel time (i.e. max_out_time !=0): |
| 4356 | * passive_dwell < max_out_time |
| 4357 | * active_dwell < max_out_time |
| 4358 | */ |
| 4359 | struct iwm_scan_channel { |
| 4360 | uint32_t type; |
| 4361 | uint16_t channel; |
| 4362 | uint16_t iteration_count; |
| 4363 | uint32_t iteration_interval; |
| 4364 | uint16_t active_dwell; |
| 4365 | uint16_t passive_dwell; |
| 4366 | } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ |
| 4367 | |
| 4368 | /** |
| 4369 | * struct iwm_ssid_ie - directed scan network information element |
| 4370 | * |
| 4371 | * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, |
| 4372 | * selected by "type" bit field in struct iwm_scan_channel; |
| 4373 | * each channel may select different ssids from among the 20 entries. |
| 4374 | * SSID IEs get transmitted in reverse order of entry. |
| 4375 | */ |
| 4376 | struct iwm_ssid_ie { |
| 4377 | uint8_t id; |
| 4378 | uint8_t len; |
| 4379 | uint8_t ssid[IEEE80211_NWID_LEN]; |
| 4380 | } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ |
| 4381 | |
| 4382 | /** |
| 4383 | * iwm_scan_flags - masks for scan command flags |
| 4384 | *@IWM_SCAN_FLAGS_PERIODIC_SCAN: |
| 4385 | *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: |
| 4386 | *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: |
| 4387 | *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: |
| 4388 | *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: |
| 4389 | *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active |
| 4390 | * in the past hour, even if they are marked as passive. |
| 4391 | */ |
| 4392 | enum iwm_scan_flags { |
| 4393 | IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), |
| 4394 | IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), |
| 4395 | IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), |
| 4396 | IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), |
| 4397 | IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), |
| 4398 | IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), |
| 4399 | }; |
| 4400 | |
| 4401 | /** |
| 4402 | * enum iwm_scan_type - Scan types for scan command |
| 4403 | * @IWM_SCAN_TYPE_FORCED: |
| 4404 | * @IWM_SCAN_TYPE_BACKGROUND: |
| 4405 | * @IWM_SCAN_TYPE_OS: |
| 4406 | * @IWM_SCAN_TYPE_ROAMING: |
| 4407 | * @IWM_SCAN_TYPE_ACTION: |
| 4408 | * @IWM_SCAN_TYPE_DISCOVERY: |
| 4409 | * @IWM_SCAN_TYPE_DISCOVERY_FORCED: |
| 4410 | */ |
| 4411 | enum iwm_scan_type { |
| 4412 | IWM_SCAN_TYPE_FORCED = 0, |
| 4413 | IWM_SCAN_TYPE_BACKGROUND = 1, |
| 4414 | IWM_SCAN_TYPE_OS = 2, |
| 4415 | IWM_SCAN_TYPE_ROAMING = 3, |
| 4416 | IWM_SCAN_TYPE_ACTION = 4, |
| 4417 | IWM_SCAN_TYPE_DISCOVERY = 5, |
| 4418 | IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, |
| 4419 | }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ |
| 4420 | |
| 4421 | /* Maximal number of channels to scan */ |
| 4422 | #define IWM_MAX_NUM_SCAN_CHANNELS 0x24 |
| 4423 | |
| 4424 | /** |
| 4425 | * struct iwm_scan_cmd - scan request command |
| 4426 | * ( IWM_SCAN_REQUEST_CMD = 0x80 ) |
| 4427 | * @len: command length in bytes |
| 4428 | * @scan_flags: scan flags from IWM_SCAN_FLAGS_* |
| 4429 | * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS) |
| 4430 | * @quiet_time: in msecs, dwell this time for active scan on quiet channels |
| 4431 | * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than |
| 4432 | * this number of packets were received (typically 1) |
| 4433 | * @passive2active: is auto switching from passive to active during scan allowed |
| 4434 | * @rxchain_sel_flags: RXON_RX_CHAIN_* |
| 4435 | * @max_out_time: in usecs, max out of serving channel time |
| 4436 | * @suspend_time: how long to pause scan when returning to service channel: |
| 4437 | * bits 0-19: beacon interal in usecs (suspend before executing) |
| 4438 | * bits 20-23: reserved |
| 4439 | * bits 24-31: number of beacons (suspend between channels) |
| 4440 | * @rxon_flags: RXON_FLG_* |
| 4441 | * @filter_flags: RXON_FILTER_* |
| 4442 | * @tx_cmd: for active scans (zero for passive), w/o payload, |
| 4443 | * no RS so specify TX rate |
| 4444 | * @direct_scan: direct scan SSIDs |
| 4445 | * @type: one of IWM_SCAN_TYPE_* |
| 4446 | * @repeats: how many time to repeat the scan |
| 4447 | */ |
| 4448 | struct iwm_scan_cmd { |
| 4449 | uint16_t len; |
| 4450 | uint8_t scan_flags; |
| 4451 | uint8_t channel_count; |
| 4452 | uint16_t quiet_time; |
| 4453 | uint16_t quiet_plcp_th; |
| 4454 | uint16_t passive2active; |
| 4455 | uint16_t rxchain_sel_flags; |
| 4456 | uint32_t max_out_time; |
| 4457 | uint32_t suspend_time; |
| 4458 | /* IWM_RX_ON_FLAGS_API_S_VER_1 */ |
| 4459 | uint32_t rxon_flags; |
| 4460 | uint32_t filter_flags; |
| 4461 | struct iwm_tx_cmd tx_cmd; |
| 4462 | struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; |
| 4463 | uint32_t type; |
| 4464 | uint32_t repeats; |
| 4465 | |
| 4466 | /* |
| 4467 | * Probe request frame, followed by channel list. |
| 4468 | * |
| 4469 | * Size of probe request frame is specified by byte count in tx_cmd. |
| 4470 | * Channel list follows immediately after probe request frame. |
| 4471 | * Number of channels in list is specified by channel_count. |
| 4472 | * Each channel in list is of type: |
| 4473 | * |
| 4474 | * struct iwm_scan_channel channels[0]; |
| 4475 | * |
| 4476 | * NOTE: Only one band of channels can be scanned per pass. You |
| 4477 | * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait |
| 4478 | * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION) |
| 4479 | * before requesting another scan. |
| 4480 | */ |
| 4481 | uint8_t data[0]; |
| 4482 | } __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */ |
| 4483 | |
| 4484 | /* Response to scan request contains only status with one of these values */ |
| 4485 | #define IWM_SCAN_RESPONSE_OK 0x1 |
| 4486 | #define IWM_SCAN_RESPONSE_ERROR 0x2 |
| 4487 | |
| 4488 | /* |
| 4489 | * IWM_SCAN_ABORT_CMD = 0x81 |
| 4490 | * When scan abort is requested, the command has no fields except the common |
| 4491 | * header. The response contains only a status with one of these values. |
| 4492 | */ |
| 4493 | #define IWM_SCAN_ABORT_POSSIBLE 0x1 |
| 4494 | #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ |
| 4495 | |
| 4496 | /* TODO: complete documentation */ |
| 4497 | #define IWM_SCAN_OWNER_STATUS 0x1 |
| 4498 | #define IWM_MEASURE_OWNER_STATUS 0x2 |
| 4499 | |
| 4500 | /** |
| 4501 | * struct iwm_scan_start_notif - notifies start of scan in the device |
| 4502 | * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) |
| 4503 | * @tsf_low: TSF timer (lower half) in usecs |
| 4504 | * @tsf_high: TSF timer (higher half) in usecs |
| 4505 | * @beacon_timer: structured as follows: |
| 4506 | * bits 0:19 - beacon interval in usecs |
| 4507 | * bits 20:23 - reserved (0) |
| 4508 | * bits 24:31 - number of beacons |
| 4509 | * @channel: which channel is scanned |
| 4510 | * @band: 0 for 5.2 GHz, 1 for 2.4 GHz |
| 4511 | * @status: one of *_OWNER_STATUS |
| 4512 | */ |
| 4513 | struct iwm_scan_start_notif { |
| 4514 | uint32_t tsf_low; |
| 4515 | uint32_t tsf_high; |
| 4516 | uint32_t beacon_timer; |
| 4517 | uint8_t channel; |
| 4518 | uint8_t band; |
| 4519 | uint8_t reserved[2]; |
| 4520 | uint32_t status; |
| 4521 | } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ |
| 4522 | |
| 4523 | /* scan results probe_status first bit indicates success */ |
| 4524 | #define IWM_SCAN_PROBE_STATUS_OK 0 |
| 4525 | #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) |
| 4526 | /* error statuses combined with TX_FAILED */ |
| 4527 | #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) |
| 4528 | #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) |
| 4529 | |
| 4530 | /* How many statistics are gathered for each channel */ |
| 4531 | #define IWM_SCAN_RESULTS_STATISTICS 1 |
| 4532 | |
| 4533 | /** |
| 4534 | * enum iwm_scan_complete_status - status codes for scan complete notifications |
| 4535 | * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully |
| 4536 | * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user |
| 4537 | * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed |
| 4538 | * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready |
| 4539 | * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed |
| 4540 | * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed |
| 4541 | * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command |
| 4542 | * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort |
| 4543 | * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax |
| 4544 | * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful |
| 4545 | * (not an error!) |
| 4546 | * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver |
| 4547 | * asked for |
| 4548 | * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events |
| 4549 | */ |
| 4550 | enum iwm_scan_complete_status { |
| 4551 | IWM_SCAN_COMP_STATUS_OK = 0x1, |
| 4552 | IWM_SCAN_COMP_STATUS_ABORT = 0x2, |
| 4553 | IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, |
| 4554 | IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, |
| 4555 | IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, |
| 4556 | IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, |
| 4557 | IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, |
| 4558 | IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, |
| 4559 | IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, |
| 4560 | IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, |
| 4561 | IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, |
| 4562 | IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, |
| 4563 | }; |
| 4564 | |
| 4565 | /** |
| 4566 | * struct iwm_scan_results_notif - scan results for one channel |
| 4567 | * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) |
| 4568 | * @channel: which channel the results are from |
| 4569 | * @band: 0 for 5.2 GHz, 1 for 2.4 GHz |
| 4570 | * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request |
| 4571 | * @num_probe_not_sent: # of request that weren't sent due to not enough time |
| 4572 | * @duration: duration spent in channel, in usecs |
| 4573 | * @statistics: statistics gathered for this channel |
| 4574 | */ |
| 4575 | struct iwm_scan_results_notif { |
| 4576 | uint8_t channel; |
| 4577 | uint8_t band; |
| 4578 | uint8_t probe_status; |
| 4579 | uint8_t num_probe_not_sent; |
| 4580 | uint32_t duration; |
| 4581 | uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; |
| 4582 | } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ |
| 4583 | |
| 4584 | /** |
| 4585 | * struct iwm_scan_complete_notif - notifies end of scanning (all channels) |
| 4586 | * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) |
| 4587 | * @scanned_channels: number of channels scanned (and number of valid results) |
| 4588 | * @status: one of IWM_SCAN_COMP_STATUS_* |
| 4589 | * @bt_status: BT on/off status |
| 4590 | * @last_channel: last channel that was scanned |
| 4591 | * @tsf_low: TSF timer (lower half) in usecs |
| 4592 | * @tsf_high: TSF timer (higher half) in usecs |
| 4593 | * @results: all scan results, only "scanned_channels" of them are valid |
| 4594 | */ |
| 4595 | struct iwm_scan_complete_notif { |
| 4596 | uint8_t scanned_channels; |
| 4597 | uint8_t status; |
| 4598 | uint8_t bt_status; |
| 4599 | uint8_t last_channel; |
| 4600 | uint32_t tsf_low; |
| 4601 | uint32_t tsf_high; |
| 4602 | struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; |
| 4603 | } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ |
| 4604 | |
| 4605 | /* scan offload */ |
| 4606 | #define IWM_MAX_SCAN_CHANNELS 40 |
| 4607 | #define IWM_SCAN_MAX_BLACKLIST_LEN 64 |
| 4608 | #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 |
| 4609 | #define IWM_SCAN_MAX_PROFILES 11 |
| 4610 | #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 |
| 4611 | |
| 4612 | /* Default watchdog (in MS) for scheduled scan iteration */ |
| 4613 | #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) |
| 4614 | |
| 4615 | #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) |
| 4616 | #define IWM_CAN_ABORT_STATUS 1 |
| 4617 | |
| 4618 | #define IWM_FULL_SCAN_MULTIPLIER 5 |
| 4619 | #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 |
| 4620 | |
| 4621 | enum iwm_scan_framework_client { |
| 4622 | IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), |
| 4623 | IWM_SCAN_CLIENT_NETDETECT = (1 << 1), |
| 4624 | IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), |
| 4625 | }; |
| 4626 | |
| 4627 | /** |
| 4628 | * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 |
| 4629 | * @scan_flags: see enum iwm_scan_flags |
| 4630 | * @channel_count: channels in channel list |
| 4631 | * @quiet_time: dwell time, in milisiconds, on quiet channel |
| 4632 | * @quiet_plcp_th: quiet channel num of packets threshold |
| 4633 | * @good_CRC_th: passive to active promotion threshold |
| 4634 | * @rx_chain: RXON rx chain. |
| 4635 | * @max_out_time: max uSec to be out of assoceated channel |
| 4636 | * @suspend_time: pause scan this long when returning to service channel |
| 4637 | * @flags: RXON flags |
| 4638 | * @filter_flags: RXONfilter |
| 4639 | * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. |
| 4640 | * @direct_scan: list of SSIDs for directed active scan |
| 4641 | * @scan_type: see enum iwm_scan_type. |
| 4642 | * @rep_count: repetition count for each scheduled scan iteration. |
| 4643 | */ |
| 4644 | struct iwm_scan_offload_cmd { |
| 4645 | uint16_t len; |
| 4646 | uint8_t scan_flags; |
| 4647 | uint8_t channel_count; |
| 4648 | uint16_t quiet_time; |
| 4649 | uint16_t quiet_plcp_th; |
| 4650 | uint16_t good_CRC_th; |
| 4651 | uint16_t rx_chain; |
| 4652 | uint32_t max_out_time; |
| 4653 | uint32_t suspend_time; |
| 4654 | /* IWM_RX_ON_FLAGS_API_S_VER_1 */ |
| 4655 | uint32_t flags; |
| 4656 | uint32_t filter_flags; |
| 4657 | struct iwm_tx_cmd tx_cmd[2]; |
| 4658 | /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ |
| 4659 | struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; |
| 4660 | uint32_t scan_type; |
| 4661 | uint32_t rep_count; |
| 4662 | } __packed; |
| 4663 | |
| 4664 | enum iwm_scan_offload_channel_flags { |
| 4665 | IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), |
| 4666 | IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), |
| 4667 | IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), |
| 4668 | IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), |
| 4669 | }; |
| 4670 | |
| 4671 | /** |
| 4672 | * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S |
| 4673 | * @type: bitmap - see enum iwm_scan_offload_channel_flags. |
| 4674 | * 0: passive (0) or active (1) scan. |
| 4675 | * 1-20: directed scan to i'th ssid. |
| 4676 | * 22: channel width configuation - 1 for narrow. |
| 4677 | * 24: full scan. |
| 4678 | * 25: partial scan. |
| 4679 | * @channel_number: channel number 1-13 etc. |
| 4680 | * @iter_count: repetition count for the channel. |
| 4681 | * @iter_interval: interval between two innteration on one channel. |
| 4682 | * @dwell_time: entry 0 - active scan, entry 1 - passive scan. |
| 4683 | */ |
| 4684 | struct iwm_scan_channel_cfg { |
| 4685 | uint32_t type[IWM_MAX_SCAN_CHANNELS]; |
| 4686 | uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; |
| 4687 | uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; |
| 4688 | uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; |
| 4689 | uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; |
| 4690 | } __packed; |
| 4691 | |
| 4692 | /** |
| 4693 | * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S |
| 4694 | * @scan_cmd: scan command fixed part |
| 4695 | * @channel_cfg: scan channel configuration |
| 4696 | * @data: probe request frames (one per band) |
| 4697 | */ |
| 4698 | struct iwm_scan_offload_cfg { |
| 4699 | struct iwm_scan_offload_cmd scan_cmd; |
| 4700 | struct iwm_scan_channel_cfg channel_cfg; |
| 4701 | uint8_t data[0]; |
| 4702 | } __packed; |
| 4703 | |
| 4704 | /** |
| 4705 | * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S |
| 4706 | * @ssid: MAC address to filter out |
| 4707 | * @reported_rssi: AP rssi reported to the host |
| 4708 | * @client_bitmap: clients ignore this entry - enum scan_framework_client |
| 4709 | */ |
| 4710 | struct iwm_scan_offload_blacklist { |
| 4711 | uint8_t ssid[ETHER_ADDR_LEN]; |
| 4712 | uint8_t ; |
| 4713 | uint8_t client_bitmap; |
| 4714 | } __packed; |
| 4715 | |
| 4716 | enum iwm_scan_offload_network_type { |
| 4717 | IWM_NETWORK_TYPE_BSS = 1, |
| 4718 | IWM_NETWORK_TYPE_IBSS = 2, |
| 4719 | IWM_NETWORK_TYPE_ANY = 3, |
| 4720 | }; |
| 4721 | |
| 4722 | enum iwm_scan_offload_band_selection { |
| 4723 | IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, |
| 4724 | IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, |
| 4725 | IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, |
| 4726 | }; |
| 4727 | |
| 4728 | /** |
| 4729 | * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S |
| 4730 | * @ssid_index: index to ssid list in fixed part |
| 4731 | * @unicast_cipher: encryption olgorithm to match - bitmap |
| 4732 | * @aut_alg: authentication olgorithm to match - bitmap |
| 4733 | * @network_type: enum iwm_scan_offload_network_type |
| 4734 | * @band_selection: enum iwm_scan_offload_band_selection |
| 4735 | * @client_bitmap: clients waiting for match - enum scan_framework_client |
| 4736 | */ |
| 4737 | struct iwm_scan_offload_profile { |
| 4738 | uint8_t ssid_index; |
| 4739 | uint8_t unicast_cipher; |
| 4740 | uint8_t auth_alg; |
| 4741 | uint8_t network_type; |
| 4742 | uint8_t band_selection; |
| 4743 | uint8_t client_bitmap; |
| 4744 | uint8_t reserved[2]; |
| 4745 | } __packed; |
| 4746 | |
| 4747 | /** |
| 4748 | * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 |
| 4749 | * @blaclist: AP list to filter off from scan results |
| 4750 | * @profiles: profiles to search for match |
| 4751 | * @blacklist_len: length of blacklist |
| 4752 | * @num_profiles: num of profiles in the list |
| 4753 | * @match_notify: clients waiting for match found notification |
| 4754 | * @pass_match: clients waiting for the results |
| 4755 | * @active_clients: active clients bitmap - enum scan_framework_client |
| 4756 | * @any_beacon_notify: clients waiting for match notification without match |
| 4757 | */ |
| 4758 | struct iwm_scan_offload_profile_cfg { |
| 4759 | struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; |
| 4760 | uint8_t blacklist_len; |
| 4761 | uint8_t num_profiles; |
| 4762 | uint8_t match_notify; |
| 4763 | uint8_t pass_match; |
| 4764 | uint8_t active_clients; |
| 4765 | uint8_t any_beacon_notify; |
| 4766 | uint8_t reserved[2]; |
| 4767 | } __packed; |
| 4768 | |
| 4769 | /** |
| 4770 | * iwm_scan_offload_schedule - schedule of scan offload |
| 4771 | * @delay: delay between iterations, in seconds. |
| 4772 | * @iterations: num of scan iterations |
| 4773 | * @full_scan_mul: number of partial scans before each full scan |
| 4774 | */ |
| 4775 | struct iwm_scan_offload_schedule { |
| 4776 | uint16_t delay; |
| 4777 | uint8_t iterations; |
| 4778 | uint8_t full_scan_mul; |
| 4779 | } __packed; |
| 4780 | |
| 4781 | /* |
| 4782 | * iwm_scan_offload_flags |
| 4783 | * |
| 4784 | * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. |
| 4785 | * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. |
| 4786 | * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan |
| 4787 | * on A band. |
| 4788 | */ |
| 4789 | enum iwm_scan_offload_flags { |
| 4790 | IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), |
| 4791 | IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), |
| 4792 | IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), |
| 4793 | }; |
| 4794 | |
| 4795 | /** |
| 4796 | * iwm_scan_offload_req - scan offload request command |
| 4797 | * @flags: bitmap - enum iwm_scan_offload_flags. |
| 4798 | * @watchdog: maximum scan duration in TU. |
| 4799 | * @delay: delay in seconds before first iteration. |
| 4800 | * @schedule_line: scan offload schedule, for fast and regular scan. |
| 4801 | */ |
| 4802 | struct iwm_scan_offload_req { |
| 4803 | uint16_t flags; |
| 4804 | uint16_t watchdog; |
| 4805 | uint16_t delay; |
| 4806 | uint16_t reserved; |
| 4807 | struct iwm_scan_offload_schedule schedule_line[2]; |
| 4808 | } __packed; |
| 4809 | |
| 4810 | enum iwm_scan_offload_compleate_status { |
| 4811 | IWM_SCAN_OFFLOAD_COMPLETED = 1, |
| 4812 | IWM_SCAN_OFFLOAD_ABORTED = 2, |
| 4813 | }; |
| 4814 | |
| 4815 | /** |
| 4816 | * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 |
| 4817 | * @last_schedule_line: last schedule line executed (fast or regular) |
| 4818 | * @last_schedule_iteration: last scan iteration executed before scan abort |
| 4819 | * @status: enum iwm_scan_offload_compleate_status |
| 4820 | */ |
| 4821 | struct iwm_scan_offload_complete { |
| 4822 | uint8_t last_schedule_line; |
| 4823 | uint8_t last_schedule_iteration; |
| 4824 | uint8_t status; |
| 4825 | uint8_t reserved; |
| 4826 | } __packed; |
| 4827 | |
| 4828 | /** |
| 4829 | * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 |
| 4830 | * @ssid_bitmap: SSIDs indexes found in this iteration |
| 4831 | * @client_bitmap: clients that are active and wait for this notification |
| 4832 | */ |
| 4833 | struct iwm_sched_scan_results { |
| 4834 | uint16_t ssid_bitmap; |
| 4835 | uint8_t client_bitmap; |
| 4836 | uint8_t reserved; |
| 4837 | }; |
| 4838 | |
| 4839 | /* |
| 4840 | * END mvm/fw-api-scan.h |
| 4841 | */ |
| 4842 | |
| 4843 | /* |
| 4844 | * BEGIN mvm/fw-api-sta.h |
| 4845 | */ |
| 4846 | |
| 4847 | /** |
| 4848 | * enum iwm_sta_flags - flags for the ADD_STA host command |
| 4849 | * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: |
| 4850 | * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: |
| 4851 | * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection |
| 4852 | * @IWM_STA_FLG_PS: set if STA is in Power Save |
| 4853 | * @IWM_STA_FLG_INVALID: set if STA is invalid |
| 4854 | * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled |
| 4855 | * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs |
| 4856 | * @IWM_STA_FLG_DRAIN_FLOW: drain flow |
| 4857 | * @IWM_STA_FLG_PAN: STA is for PAN interface |
| 4858 | * @IWM_STA_FLG_CLASS_AUTH: |
| 4859 | * @IWM_STA_FLG_CLASS_ASSOC: |
| 4860 | * @IWM_STA_FLG_CLASS_MIMO_PROT: |
| 4861 | * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU |
| 4862 | * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation |
| 4863 | * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is |
| 4864 | * initialised by driver and can be updated by fw upon reception of |
| 4865 | * action frames that can change the channel width. When cleared the fw |
| 4866 | * will send all the frames in 20MHz even when FAT channel is requested. |
| 4867 | * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the |
| 4868 | * driver and can be updated by fw upon reception of action frames. |
| 4869 | * @IWM_STA_FLG_MFP_EN: Management Frame Protection |
| 4870 | */ |
| 4871 | enum iwm_sta_flags { |
| 4872 | IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), |
| 4873 | IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), |
| 4874 | |
| 4875 | IWM_STA_FLG_FLG_ANT_A = (1 << 4), |
| 4876 | IWM_STA_FLG_FLG_ANT_B = (2 << 4), |
| 4877 | IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A | |
| 4878 | IWM_STA_FLG_FLG_ANT_B), |
| 4879 | |
| 4880 | IWM_STA_FLG_PS = (1 << 8), |
| 4881 | IWM_STA_FLG_DRAIN_FLOW = (1 << 12), |
| 4882 | IWM_STA_FLG_PAN = (1 << 13), |
| 4883 | IWM_STA_FLG_CLASS_AUTH = (1 << 14), |
| 4884 | IWM_STA_FLG_CLASS_ASSOC = (1 << 15), |
| 4885 | IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), |
| 4886 | |
| 4887 | IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, |
| 4888 | IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4889 | IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4890 | IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4891 | IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4892 | IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4893 | IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4894 | IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4895 | IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4896 | IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), |
| 4897 | |
| 4898 | IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, |
| 4899 | IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), |
| 4900 | IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), |
| 4901 | IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), |
| 4902 | IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), |
| 4903 | IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), |
| 4904 | |
| 4905 | IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), |
| 4906 | IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), |
| 4907 | IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), |
| 4908 | IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), |
| 4909 | IWM_STA_FLG_FAT_EN_MSK = (3 << 26), |
| 4910 | |
| 4911 | IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), |
| 4912 | IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), |
| 4913 | IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), |
| 4914 | IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), |
| 4915 | }; |
| 4916 | |
| 4917 | /** |
| 4918 | * enum iwm_sta_key_flag - key flags for the ADD_STA host command |
| 4919 | * @IWM_STA_KEY_FLG_NO_ENC: no encryption |
| 4920 | * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm |
| 4921 | * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm |
| 4922 | * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm |
| 4923 | * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) |
| 4924 | * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm |
| 4925 | * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm |
| 4926 | * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value |
| 4927 | * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from |
| 4928 | * station info array (1 - n 1X mode) |
| 4929 | * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key |
| 4930 | * @IWM_STA_KEY_NOT_VALID: key is invalid |
| 4931 | * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key |
| 4932 | * @IWM_STA_KEY_MULTICAST: set for multical key |
| 4933 | * @IWM_STA_KEY_MFP: key is used for Management Frame Protection |
| 4934 | */ |
| 4935 | enum iwm_sta_key_flag { |
| 4936 | IWM_STA_KEY_FLG_NO_ENC = (0 << 0), |
| 4937 | IWM_STA_KEY_FLG_WEP = (1 << 0), |
| 4938 | IWM_STA_KEY_FLG_CCM = (2 << 0), |
| 4939 | IWM_STA_KEY_FLG_TKIP = (3 << 0), |
| 4940 | IWM_STA_KEY_FLG_EXT = (4 << 0), |
| 4941 | IWM_STA_KEY_FLG_CMAC = (6 << 0), |
| 4942 | IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), |
| 4943 | IWM_STA_KEY_FLG_EN_MSK = (7 << 0), |
| 4944 | |
| 4945 | IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), |
| 4946 | IWM_STA_KEY_FLG_KEYID_POS = 8, |
| 4947 | IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), |
| 4948 | IWM_STA_KEY_NOT_VALID = (1 << 11), |
| 4949 | IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), |
| 4950 | IWM_STA_KEY_MULTICAST = (1 << 14), |
| 4951 | IWM_STA_KEY_MFP = (1 << 15), |
| 4952 | }; |
| 4953 | |
| 4954 | /** |
| 4955 | * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed |
| 4956 | * @IWM_STA_MODIFY_KEY: this command modifies %key |
| 4957 | * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx |
| 4958 | * @IWM_STA_MODIFY_TX_RATE: unused |
| 4959 | * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid |
| 4960 | * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid |
| 4961 | * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count |
| 4962 | * @IWM_STA_MODIFY_PROT_TH: |
| 4963 | * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station |
| 4964 | */ |
| 4965 | enum iwm_sta_modify_flag { |
| 4966 | IWM_STA_MODIFY_KEY = (1 << 0), |
| 4967 | IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), |
| 4968 | IWM_STA_MODIFY_TX_RATE = (1 << 2), |
| 4969 | IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), |
| 4970 | IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), |
| 4971 | IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), |
| 4972 | IWM_STA_MODIFY_PROT_TH = (1 << 6), |
| 4973 | IWM_STA_MODIFY_QUEUES = (1 << 7), |
| 4974 | }; |
| 4975 | |
| 4976 | #define IWM_STA_MODE_MODIFY 1 |
| 4977 | |
| 4978 | /** |
| 4979 | * enum iwm_sta_sleep_flag - type of sleep of the station |
| 4980 | * @IWM_STA_SLEEP_STATE_AWAKE: |
| 4981 | * @IWM_STA_SLEEP_STATE_PS_POLL: |
| 4982 | * @IWM_STA_SLEEP_STATE_UAPSD: |
| 4983 | */ |
| 4984 | enum iwm_sta_sleep_flag { |
| 4985 | IWM_STA_SLEEP_STATE_AWAKE = 0, |
| 4986 | IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), |
| 4987 | IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), |
| 4988 | }; |
| 4989 | |
| 4990 | /* STA ID and color bits definitions */ |
| 4991 | #define IWM_STA_ID_SEED (0x0f) |
| 4992 | #define IWM_STA_ID_POS (0) |
| 4993 | #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) |
| 4994 | |
| 4995 | #define IWM_STA_COLOR_SEED (0x7) |
| 4996 | #define IWM_STA_COLOR_POS (4) |
| 4997 | #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) |
| 4998 | |
| 4999 | #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ |
| 5000 | (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) |
| 5001 | #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ |
| 5002 | (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) |
| 5003 | |
| 5004 | #define IWM_STA_KEY_MAX_NUM (16) |
| 5005 | #define IWM_STA_KEY_IDX_INVALID (0xff) |
| 5006 | #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) |
| 5007 | #define IWM_MAX_GLOBAL_KEYS (4) |
| 5008 | #define IWM_STA_KEY_LEN_WEP40 (5) |
| 5009 | #define IWM_STA_KEY_LEN_WEP104 (13) |
| 5010 | |
| 5011 | /** |
| 5012 | * struct iwm_mvm_keyinfo - key information |
| 5013 | * @key_flags: type %iwm_sta_key_flag |
| 5014 | * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection |
| 5015 | * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx |
| 5016 | * @key_offset: key offset in the fw's key table |
| 5017 | * @key: 16-byte unicast decryption key |
| 5018 | * @tx_secur_seq_cnt: initial RSC / PN needed for replay check |
| 5019 | * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only |
| 5020 | * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only |
| 5021 | */ |
| 5022 | struct iwm_mvm_keyinfo { |
| 5023 | uint16_t key_flags; |
| 5024 | uint8_t tkip_rx_tsc_byte2; |
| 5025 | uint8_t reserved1; |
| 5026 | uint16_t tkip_rx_ttak[5]; |
| 5027 | uint8_t key_offset; |
| 5028 | uint8_t reserved2; |
| 5029 | uint8_t key[16]; |
| 5030 | uint64_t tx_secur_seq_cnt; |
| 5031 | uint64_t hw_tkip_mic_rx_key; |
| 5032 | uint64_t hw_tkip_mic_tx_key; |
| 5033 | } __packed; |
| 5034 | |
| 5035 | /** |
| 5036 | * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table. |
| 5037 | * ( IWM_REPLY_ADD_STA = 0x18 ) |
| 5038 | * @add_modify: 1: modify existing, 0: add new station |
| 5039 | * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent |
| 5040 | * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key |
| 5041 | * sent |
| 5042 | * @mac_id_n_color: the Mac context this station belongs to |
| 5043 | * @addr[ETHER_ADDR_LEN]: station's MAC address |
| 5044 | * @sta_id: index of station in uCode's station table |
| 5045 | * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave |
| 5046 | * alone. 1 - modify, 0 - don't change. |
| 5047 | * @key: look at %iwm_mvm_keyinfo |
| 5048 | * @station_flags: look at %iwm_sta_flags |
| 5049 | * @station_flags_msk: what of %station_flags have changed |
| 5050 | * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable |
| 5051 | * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. |
| 5052 | * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) |
| 5053 | * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set |
| 5054 | * add_immediate_ba_ssn. |
| 5055 | * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) |
| 5056 | * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field |
| 5057 | * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with |
| 5058 | * add_immediate_ba_tid. |
| 5059 | * @sleep_tx_count: number of packets to transmit to station even though it is |
| 5060 | * asleep. Used to synchronise PS-poll and u-APSD responses while ucode |
| 5061 | * keeps track of STA sleep state. |
| 5062 | * @sleep_state_flags: Look at %iwm_sta_sleep_flag. |
| 5063 | * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP |
| 5064 | * mac-addr. |
| 5065 | * @beamform_flags: beam forming controls |
| 5066 | * @tfd_queue_msk: tfd queues used by this station |
| 5067 | * |
| 5068 | * The device contains an internal table of per-station information, with info |
| 5069 | * on security keys, aggregation parameters, and Tx rates for initial Tx |
| 5070 | * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). |
| 5071 | * |
| 5072 | * ADD_STA sets up the table entry for one station, either creating a new |
| 5073 | * entry, or modifying a pre-existing one. |
| 5074 | */ |
| 5075 | struct iwm_mvm_add_sta_cmd_v5 { |
| 5076 | uint8_t add_modify; |
| 5077 | uint8_t unicast_tx_key_id; |
| 5078 | uint8_t multicast_tx_key_id; |
| 5079 | uint8_t reserved1; |
| 5080 | uint32_t mac_id_n_color; |
| 5081 | uint8_t addr[ETHER_ADDR_LEN]; |
| 5082 | uint16_t reserved2; |
| 5083 | uint8_t sta_id; |
| 5084 | uint8_t modify_mask; |
| 5085 | uint16_t reserved3; |
| 5086 | struct iwm_mvm_keyinfo key; |
| 5087 | uint32_t station_flags; |
| 5088 | uint32_t station_flags_msk; |
| 5089 | uint16_t tid_disable_tx; |
| 5090 | uint16_t reserved4; |
| 5091 | uint8_t add_immediate_ba_tid; |
| 5092 | uint8_t remove_immediate_ba_tid; |
| 5093 | uint16_t add_immediate_ba_ssn; |
| 5094 | uint16_t sleep_tx_count; |
| 5095 | uint16_t sleep_state_flags; |
| 5096 | uint16_t assoc_id; |
| 5097 | uint16_t beamform_flags; |
| 5098 | uint32_t tfd_queue_msk; |
| 5099 | } __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */ |
| 5100 | |
| 5101 | /** |
| 5102 | * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station |
| 5103 | * VER_6 of this command is quite similar to VER_5 except |
| 5104 | * exclusion of all fields related to the security key installation. |
| 5105 | */ |
| 5106 | struct iwm_mvm_add_sta_cmd_v6 { |
| 5107 | uint8_t add_modify; |
| 5108 | uint8_t reserved1; |
| 5109 | uint16_t tid_disable_tx; |
| 5110 | uint32_t mac_id_n_color; |
| 5111 | uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ |
| 5112 | uint16_t reserved2; |
| 5113 | uint8_t sta_id; |
| 5114 | uint8_t modify_mask; |
| 5115 | uint16_t reserved3; |
| 5116 | uint32_t station_flags; |
| 5117 | uint32_t station_flags_msk; |
| 5118 | uint8_t add_immediate_ba_tid; |
| 5119 | uint8_t remove_immediate_ba_tid; |
| 5120 | uint16_t add_immediate_ba_ssn; |
| 5121 | uint16_t sleep_tx_count; |
| 5122 | uint16_t sleep_state_flags; |
| 5123 | uint16_t assoc_id; |
| 5124 | uint16_t beamform_flags; |
| 5125 | uint32_t tfd_queue_msk; |
| 5126 | } __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */ |
| 5127 | |
| 5128 | /** |
| 5129 | * struct iwm_mvm_add_sta_key_cmd - add/modify sta key |
| 5130 | * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) |
| 5131 | * @sta_id: index of station in uCode's station table |
| 5132 | * @key_offset: key offset in key storage |
| 5133 | * @key_flags: type %iwm_sta_key_flag |
| 5134 | * @key: key material data |
| 5135 | * @key2: key material data |
| 5136 | * @rx_secur_seq_cnt: RX security sequence counter for the key |
| 5137 | * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection |
| 5138 | * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx |
| 5139 | */ |
| 5140 | struct iwm_mvm_add_sta_key_cmd { |
| 5141 | uint8_t sta_id; |
| 5142 | uint8_t key_offset; |
| 5143 | uint16_t key_flags; |
| 5144 | uint8_t key[16]; |
| 5145 | uint8_t key2[16]; |
| 5146 | uint8_t rx_secur_seq_cnt[16]; |
| 5147 | uint8_t tkip_rx_tsc_byte2; |
| 5148 | uint8_t reserved; |
| 5149 | uint16_t tkip_rx_ttak[5]; |
| 5150 | } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ |
| 5151 | |
| 5152 | /** |
| 5153 | * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command |
| 5154 | * @IWM_ADD_STA_SUCCESS: operation was executed successfully |
| 5155 | * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table |
| 5156 | * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session |
| 5157 | * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station |
| 5158 | * that doesn't exist. |
| 5159 | */ |
| 5160 | enum iwm_mvm_add_sta_rsp_status { |
| 5161 | IWM_ADD_STA_SUCCESS = 0x1, |
| 5162 | IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, |
| 5163 | IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, |
| 5164 | IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, |
| 5165 | }; |
| 5166 | |
| 5167 | /** |
| 5168 | * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table |
| 5169 | * ( IWM_REMOVE_STA = 0x19 ) |
| 5170 | * @sta_id: the station id of the station to be removed |
| 5171 | */ |
| 5172 | struct iwm_mvm_rm_sta_cmd { |
| 5173 | uint8_t sta_id; |
| 5174 | uint8_t reserved[3]; |
| 5175 | } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ |
| 5176 | |
| 5177 | /** |
| 5178 | * struct iwm_mvm_mgmt_mcast_key_cmd |
| 5179 | * ( IWM_MGMT_MCAST_KEY = 0x1f ) |
| 5180 | * @ctrl_flags: %iwm_sta_key_flag |
| 5181 | * @IGTK: |
| 5182 | * @K1: IGTK master key |
| 5183 | * @K2: IGTK sub key |
| 5184 | * @sta_id: station ID that support IGTK |
| 5185 | * @key_id: |
| 5186 | * @receive_seq_cnt: initial RSC/PN needed for replay check |
| 5187 | */ |
| 5188 | struct iwm_mvm_mgmt_mcast_key_cmd { |
| 5189 | uint32_t ctrl_flags; |
| 5190 | uint8_t IGTK[16]; |
| 5191 | uint8_t K1[16]; |
| 5192 | uint8_t K2[16]; |
| 5193 | uint32_t key_id; |
| 5194 | uint32_t sta_id; |
| 5195 | uint64_t receive_seq_cnt; |
| 5196 | } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ |
| 5197 | |
| 5198 | struct iwm_mvm_wep_key { |
| 5199 | uint8_t key_index; |
| 5200 | uint8_t key_offset; |
| 5201 | uint16_t reserved1; |
| 5202 | uint8_t key_size; |
| 5203 | uint8_t reserved2[3]; |
| 5204 | uint8_t key[16]; |
| 5205 | } __packed; |
| 5206 | |
| 5207 | struct iwm_mvm_wep_key_cmd { |
| 5208 | uint32_t mac_id_n_color; |
| 5209 | uint8_t num_keys; |
| 5210 | uint8_t decryption_type; |
| 5211 | uint8_t flags; |
| 5212 | uint8_t reserved; |
| 5213 | struct iwm_mvm_wep_key wep_key[0]; |
| 5214 | } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ |
| 5215 | |
| 5216 | |
| 5217 | /* |
| 5218 | * END mvm/fw-api-sta.h |
| 5219 | */ |
| 5220 | |
| 5221 | /* |
| 5222 | * Some cherry-picked definitions |
| 5223 | */ |
| 5224 | |
| 5225 | #define IWM_FRAME_LIMIT 64 |
| 5226 | |
| 5227 | struct { |
| 5228 | uint8_t ; |
| 5229 | uint8_t ; |
| 5230 | uint8_t ; |
| 5231 | uint8_t ; |
| 5232 | } __packed; |
| 5233 | |
| 5234 | enum iwm_power_scheme { |
| 5235 | IWM_POWER_SCHEME_CAM = 1, |
| 5236 | IWM_POWER_SCHEME_BPS, |
| 5237 | IWM_POWER_SCHEME_LP |
| 5238 | }; |
| 5239 | |
| 5240 | #define IWM_DEF_CMD_PAYLOAD_SIZE 320 |
| 5241 | #define IWM_CMD_FAILED_MSK 0x40 |
| 5242 | |
| 5243 | struct iwm_device_cmd { |
| 5244 | struct iwm_cmd_header hdr; |
| 5245 | |
| 5246 | uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; |
| 5247 | } __packed; |
| 5248 | |
| 5249 | struct iwm_rx_packet { |
| 5250 | /* |
| 5251 | * The first 4 bytes of the RX frame header contain both the RX frame |
| 5252 | * size and some flags. |
| 5253 | * Bit fields: |
| 5254 | * 31: flag flush RB request |
| 5255 | * 30: flag ignore TC (terminal counter) request |
| 5256 | * 29: flag fast IRQ request |
| 5257 | * 28-14: Reserved |
| 5258 | * 13-00: RX frame size |
| 5259 | */ |
| 5260 | uint32_t len_n_flags; |
| 5261 | struct iwm_cmd_header hdr; |
| 5262 | uint8_t data[]; |
| 5263 | } __packed; |
| 5264 | |
| 5265 | #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff |
| 5266 | |
| 5267 | static uint32_t |
| 5268 | iwm_rx_packet_len(const struct iwm_rx_packet *pkt) |
| 5269 | { |
| 5270 | |
| 5271 | return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; |
| 5272 | } |
| 5273 | |
| 5274 | static uint32_t |
| 5275 | iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) |
| 5276 | { |
| 5277 | |
| 5278 | return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); |
| 5279 | } |
| 5280 | |
| 5281 | |
| 5282 | #define IWM_MIN_DBM -100 |
| 5283 | #define IWM_MAX_DBM -33 /* realistic guess */ |
| 5284 | |
| 5285 | #define IWM_READ(sc, reg) \ |
| 5286 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
| 5287 | |
| 5288 | #define IWM_WRITE(sc, reg, val) \ |
| 5289 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 5290 | |
| 5291 | #define IWM_WRITE_1(sc, reg, val) \ |
| 5292 | bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 5293 | |
| 5294 | #define IWM_SETBITS(sc, reg, mask) \ |
| 5295 | IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) |
| 5296 | |
| 5297 | #define IWM_CLRBITS(sc, reg, mask) \ |
| 5298 | IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) |
| 5299 | |
| 5300 | #define IWM_BARRIER_WRITE(sc) \ |
| 5301 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ |
| 5302 | BUS_SPACE_BARRIER_WRITE) |
| 5303 | |
| 5304 | #define IWM_BARRIER_READ_WRITE(sc) \ |
| 5305 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ |
| 5306 | BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) |
| 5307 | |