| 1 | /* $NetBSD: if_alereg.h,v 1.2 2009/04/25 17:04:40 tsutsui Exp $ */ |
| 2 | /* $OpenBSD: if_alereg.h,v 1.1 2009/02/25 03:05:32 kevlo Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice unmodified, this list of conditions, and the following |
| 13 | * disclaimer. |
| 14 | * 2. Redistributions in binary form must reproduce the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer in the |
| 16 | * documentation and/or other materials provided with the distribution. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMATE. |
| 29 | * |
| 30 | * $FreeBSD: src/sys/dev/ale/if_alereg.h,v 1.1 2008/11/12 09:52:06 yongari Exp $ |
| 31 | */ |
| 32 | |
| 33 | #ifndef _IF_ALEREG_H |
| 34 | #define _IF_ALEREG_H |
| 35 | |
| 36 | #define ALE_PCIR_BAR 0x10 |
| 37 | |
| 38 | #define ALE_SPI_CTRL 0x200 |
| 39 | #define SPI_VPD_ENB 0x00002000 |
| 40 | |
| 41 | #define ALE_SPI_ADDR 0x204 /* 16bits */ |
| 42 | |
| 43 | #define ALE_SPI_DATA 0x208 |
| 44 | |
| 45 | #define ALE_SPI_CONFIG 0x20C |
| 46 | |
| 47 | #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ |
| 48 | |
| 49 | #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ |
| 50 | |
| 51 | #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ |
| 52 | |
| 53 | #define ALE_SPI_OP_RDID 0x213 /* 8bits */ |
| 54 | |
| 55 | #define ALE_SPI_OP_WREN 0x214 /* 8bits */ |
| 56 | |
| 57 | #define ALE_SPI_OP_RDSR 0x215 /* 8bits */ |
| 58 | |
| 59 | #define ALE_SPI_OP_WRSR 0x216 /* 8bits */ |
| 60 | |
| 61 | #define ALE_SPI_OP_READ 0x217 /* 8bits */ |
| 62 | |
| 63 | #define ALE_TWSI_CTRL 0x218 |
| 64 | #define TWSI_CTRL_SW_LD_START 0x00000800 |
| 65 | #define TWSI_CTRL_HW_LD_START 0x00001000 |
| 66 | #define TWSI_CTRL_LD_EXIST 0x00400000 |
| 67 | |
| 68 | #define ALE_DEV_MISC_CTRL 0x21C |
| 69 | |
| 70 | #define ALE_PCIE_PHYMISC 0x1000 |
| 71 | #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 |
| 72 | |
| 73 | #define ALE_MASTER_CFG 0x1400 |
| 74 | #define MASTER_RESET 0x00000001 |
| 75 | #define MASTER_MTIMER_ENB 0x00000002 |
| 76 | #define MASTER_IM_TX_TIMER_ENB 0x00000004 |
| 77 | #define MASTER_MANUAL_INT_ENB 0x00000008 |
| 78 | #define MASTER_IM_RX_TIMER_ENB 0x00000020 |
| 79 | #define MASTER_INT_RDCLR 0x00000040 |
| 80 | #define MASTER_LED_MODE 0x00000200 |
| 81 | #define MASTER_CHIP_REV_MASK 0x00FF0000 |
| 82 | #define MASTER_CHIP_ID_MASK 0xFF000000 |
| 83 | #define MASTER_CHIP_REV_SHIFT 16 |
| 84 | #define MASTER_CHIP_ID_SHIFT 24 |
| 85 | |
| 86 | /* Number of ticks per usec for AR81xx. */ |
| 87 | #define ALE_TICK_USECS 2 |
| 88 | #define ALE_USECS(x) ((x) / ALE_TICK_USECS) |
| 89 | |
| 90 | #define ALE_MANUAL_TIMER 0x1404 |
| 91 | |
| 92 | #define ALE_IM_TIMER 0x1408 |
| 93 | #define IM_TIMER_TX_MASK 0x0000FFFF |
| 94 | #define IM_TIMER_RX_MASK 0xFFFF0000 |
| 95 | #define IM_TIMER_TX_SHIFT 0 |
| 96 | #define IM_TIMER_RX_SHIFT 16 |
| 97 | #define ALE_IM_TIMER_MIN 0 |
| 98 | #define ALE_IM_TIMER_MAX 130000 /* 130ms */ |
| 99 | #define ALE_IM_RX_TIMER_DEFAULT 30 |
| 100 | #define ALE_IM_TX_TIMER_DEFAULT 1000 |
| 101 | |
| 102 | #define ALE_GPHY_CTRL 0x140C /* 16bits */ |
| 103 | #define GPHY_CTRL_EXT_RESET 0x0001 |
| 104 | #define GPHY_CTRL_PIPE_MOD 0x0002 |
| 105 | #define GPHY_CTRL_BERT_START 0x0010 |
| 106 | #define GPHY_CTRL_GALE_25M_ENB 0x0020 |
| 107 | #define GPHY_CTRL_LPW_EXIT 0x0040 |
| 108 | #define GPHY_CTRL_PHY_IDDQ 0x0080 |
| 109 | #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 |
| 110 | #define GPHY_CTRL_PCLK_SEL_DIS 0x0200 |
| 111 | #define GPHY_CTRL_HIB_EN 0x0400 |
| 112 | #define GPHY_CTRL_HIB_PULSE 0x0800 |
| 113 | #define GPHY_CTRL_SEL_ANA_RESET 0x1000 |
| 114 | #define GPHY_CTRL_PHY_PLL_ON 0x2000 |
| 115 | #define GPHY_CTRL_PWDOWN_HW 0x4000 |
| 116 | |
| 117 | #define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ |
| 118 | |
| 119 | #define ALE_IDLE_STATUS 0x1410 |
| 120 | #define IDLE_STATUS_RXMAC 0x00000001 |
| 121 | #define IDLE_STATUS_TXMAC 0x00000002 |
| 122 | #define IDLE_STATUS_RXQ 0x00000004 |
| 123 | #define IDLE_STATUS_TXQ 0x00000008 |
| 124 | #define IDLE_STATUS_DMARD 0x00000010 |
| 125 | #define IDLE_STATUS_DMAWR 0x00000020 |
| 126 | #define IDLE_STATUS_SMB 0x00000040 |
| 127 | #define IDLE_STATUS_CMB 0x00000080 |
| 128 | |
| 129 | #define ALE_MDIO 0x1414 |
| 130 | #define MDIO_DATA_MASK 0x0000FFFF |
| 131 | #define MDIO_REG_ADDR_MASK 0x001F0000 |
| 132 | #define MDIO_OP_READ 0x00200000 |
| 133 | #define MDIO_OP_WRITE 0x00000000 |
| 134 | #define MDIO_SUP_PREAMBLE 0x00400000 |
| 135 | #define MDIO_OP_EXECUTE 0x00800000 |
| 136 | #define MDIO_CLK_25_4 0x00000000 |
| 137 | #define MDIO_CLK_25_6 0x02000000 |
| 138 | #define MDIO_CLK_25_8 0x03000000 |
| 139 | #define MDIO_CLK_25_10 0x04000000 |
| 140 | #define MDIO_CLK_25_14 0x05000000 |
| 141 | #define MDIO_CLK_25_20 0x06000000 |
| 142 | #define MDIO_CLK_25_28 0x07000000 |
| 143 | #define MDIO_OP_BUSY 0x08000000 |
| 144 | #define MDIO_DATA_SHIFT 0 |
| 145 | #define MDIO_REG_ADDR_SHIFT 16 |
| 146 | |
| 147 | #define MDIO_REG_ADDR(x) \ |
| 148 | (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) |
| 149 | /* Default PHY address. */ |
| 150 | #define ALE_PHY_ADDR 0 |
| 151 | |
| 152 | #define ALE_PHY_STATUS 0x1418 |
| 153 | #define PHY_STATUS_100M 0x00020000 |
| 154 | |
| 155 | /* Packet memory BIST. */ |
| 156 | #define ALE_BIST0 0x141C |
| 157 | #define BIST0_ENB 0x00000001 |
| 158 | #define BIST0_SRAM_FAIL 0x00000002 |
| 159 | #define BIST0_FUSE_FLAG 0x00000004 |
| 160 | |
| 161 | /* PCIe retry buffer BIST. */ |
| 162 | #define ALE_BIST1 0x1420 |
| 163 | #define BIST1_ENB 0x00000001 |
| 164 | #define BIST1_SRAM_FAIL 0x00000002 |
| 165 | #define BIST1_FUSE_FLAG 0x00000004 |
| 166 | |
| 167 | #define ALE_SERDES_LOCK 0x1424 |
| 168 | #define SERDES_LOCK_DET 0x00000001 |
| 169 | #define SERDES_LOCK_DET_ENB 0x00000002 |
| 170 | |
| 171 | #define ALE_MAC_CFG 0x1480 |
| 172 | #define MAC_CFG_TX_ENB 0x00000001 |
| 173 | #define MAC_CFG_RX_ENB 0x00000002 |
| 174 | #define MAC_CFG_TX_FC 0x00000004 |
| 175 | #define MAC_CFG_RX_FC 0x00000008 |
| 176 | #define MAC_CFG_LOOP 0x00000010 |
| 177 | #define MAC_CFG_FULL_DUPLEX 0x00000020 |
| 178 | #define MAC_CFG_TX_CRC_ENB 0x00000040 |
| 179 | #define MAC_CFG_TX_AUTO_PAD 0x00000080 |
| 180 | #define MAC_CFG_TX_LENCHK 0x00000100 |
| 181 | #define MAC_CFG_RX_JUMBO_ENB 0x00000200 |
| 182 | #define MAC_CFG_PREAMBLE_MASK 0x00003C00 |
| 183 | #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 |
| 184 | #define MAC_CFG_PROMISC 0x00008000 |
| 185 | #define MAC_CFG_TX_PAUSE 0x00010000 |
| 186 | #define MAC_CFG_SCNT 0x00020000 |
| 187 | #define MAC_CFG_SYNC_RST_TX 0x00040000 |
| 188 | #define MAC_CFG_SPEED_MASK 0x00300000 |
| 189 | #define MAC_CFG_SPEED_10_100 0x00100000 |
| 190 | #define MAC_CFG_SPEED_1000 0x00200000 |
| 191 | #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 |
| 192 | #define MAC_CFG_TX_JUMBO_ENB 0x00800000 |
| 193 | #define MAC_CFG_RXCSUM_ENB 0x01000000 |
| 194 | #define MAC_CFG_ALLMULTI 0x02000000 |
| 195 | #define MAC_CFG_BCAST 0x04000000 |
| 196 | #define MAC_CFG_DBG 0x08000000 |
| 197 | #define MAC_CFG_PREAMBLE_SHIFT 10 |
| 198 | #define MAC_CFG_PREAMBLE_DEFAULT 7 |
| 199 | |
| 200 | #define ALE_IPG_IFG_CFG 0x1484 |
| 201 | #define IPG_IFG_IPGT_MASK 0x0000007F |
| 202 | #define IPG_IFG_MIFG_MASK 0x0000FF00 |
| 203 | #define IPG_IFG_IPG1_MASK 0x007F0000 |
| 204 | #define IPG_IFG_IPG2_MASK 0x7F000000 |
| 205 | #define IPG_IFG_IPGT_SHIFT 0 |
| 206 | #define IPG_IFG_IPGT_DEFAULT 0x60 |
| 207 | #define IPG_IFG_MIFG_SHIFT 8 |
| 208 | #define IPG_IFG_MIFG_DEFAULT 0x50 |
| 209 | #define IPG_IFG_IPG1_SHIFT 16 |
| 210 | #define IPG_IFG_IPG1_DEFAULT 0x40 |
| 211 | #define IPG_IFG_IPG2_SHIFT 24 |
| 212 | #define IPG_IFG_IPG2_DEFAULT 0x60 |
| 213 | |
| 214 | /* Station address. */ |
| 215 | #define ALE_PAR0 0x1488 |
| 216 | #define ALE_PAR1 0x148C |
| 217 | |
| 218 | /* 64bit multicast hash register. */ |
| 219 | #define ALE_MAR0 0x1490 |
| 220 | #define ALE_MAR1 0x1494 |
| 221 | |
| 222 | /* half-duplex parameter configuration. */ |
| 223 | #define ALE_HDPX_CFG 0x1498 |
| 224 | #define HDPX_CFG_LCOL_MASK 0x000003FF |
| 225 | #define HDPX_CFG_RETRY_MASK 0x0000F000 |
| 226 | #define HDPX_CFG_EXC_DEF_EN 0x00010000 |
| 227 | #define HDPX_CFG_NO_BACK_C 0x00020000 |
| 228 | #define HDPX_CFG_NO_BACK_P 0x00040000 |
| 229 | #define HDPX_CFG_ABEBE 0x00080000 |
| 230 | #define HDPX_CFG_ABEBT_MASK 0x00F00000 |
| 231 | #define HDPX_CFG_JAMIPG_MASK 0x0F000000 |
| 232 | #define HDPX_CFG_LCOL_SHIFT 0 |
| 233 | #define HDPX_CFG_LCOL_DEFAULT 0x37 |
| 234 | #define HDPX_CFG_RETRY_SHIFT 12 |
| 235 | #define HDPX_CFG_RETRY_DEFAULT 0x0F |
| 236 | #define HDPX_CFG_ABEBT_SHIFT 20 |
| 237 | #define HDPX_CFG_ABEBT_DEFAULT 0x0A |
| 238 | #define HDPX_CFG_JAMIPG_SHIFT 24 |
| 239 | #define HDPX_CFG_JAMIPG_DEFAULT 0x07 |
| 240 | |
| 241 | #define ALE_FRAME_SIZE 0x149C |
| 242 | |
| 243 | #define ALE_WOL_CFG 0x14A0 |
| 244 | #define WOL_CFG_PATTERN 0x00000001 |
| 245 | #define WOL_CFG_PATTERN_ENB 0x00000002 |
| 246 | #define WOL_CFG_MAGIC 0x00000004 |
| 247 | #define WOL_CFG_MAGIC_ENB 0x00000008 |
| 248 | #define WOL_CFG_LINK_CHG 0x00000010 |
| 249 | #define WOL_CFG_LINK_CHG_ENB 0x00000020 |
| 250 | #define WOL_CFG_PATTERN_DET 0x00000100 |
| 251 | #define WOL_CFG_MAGIC_DET 0x00000200 |
| 252 | #define WOL_CFG_LINK_CHG_DET 0x00000400 |
| 253 | #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 |
| 254 | #define WOL_CFG_PATTERN0 0x00010000 |
| 255 | #define WOL_CFG_PATTERN1 0x00020000 |
| 256 | #define WOL_CFG_PATTERN2 0x00040000 |
| 257 | #define WOL_CFG_PATTERN3 0x00080000 |
| 258 | #define WOL_CFG_PATTERN4 0x00100000 |
| 259 | #define WOL_CFG_PATTERN5 0x00200000 |
| 260 | #define WOL_CFG_PATTERN6 0x00400000 |
| 261 | |
| 262 | /* WOL pattern length. */ |
| 263 | #define ALE_PATTERN_CFG0 0x14A4 |
| 264 | #define PATTERN_CFG_0_LEN_MASK 0x0000007F |
| 265 | #define PATTERN_CFG_1_LEN_MASK 0x00007F00 |
| 266 | #define PATTERN_CFG_2_LEN_MASK 0x007F0000 |
| 267 | #define PATTERN_CFG_3_LEN_MASK 0x7F000000 |
| 268 | |
| 269 | #define ALE_PATTERN_CFG1 0x14A8 |
| 270 | #define PATTERN_CFG_4_LEN_MASK 0x0000007F |
| 271 | #define PATTERN_CFG_5_LEN_MASK 0x00007F00 |
| 272 | #define PATTERN_CFG_6_LEN_MASK 0x007F0000 |
| 273 | |
| 274 | /* RSS */ |
| 275 | #define 0x14B0 |
| 276 | |
| 277 | #define 0x14B4 |
| 278 | |
| 279 | #define 0x14B8 |
| 280 | |
| 281 | #define 0x14BC |
| 282 | |
| 283 | #define 0x14C0 |
| 284 | |
| 285 | #define 0x14C4 |
| 286 | |
| 287 | #define 0x14C8 |
| 288 | |
| 289 | #define 0x14CC |
| 290 | |
| 291 | #define 0x14D0 |
| 292 | |
| 293 | #define 0x14D4 |
| 294 | |
| 295 | #define 0x14E0 |
| 296 | |
| 297 | #define 0x14E4 |
| 298 | |
| 299 | #define 0x14E8 |
| 300 | |
| 301 | #define 0x14EC |
| 302 | |
| 303 | #define ALE_SRAM_RD_ADDR 0x1500 |
| 304 | |
| 305 | #define ALE_SRAM_RD_LEN 0x1504 |
| 306 | |
| 307 | #define ALE_SRAM_RRD_ADDR 0x1508 |
| 308 | |
| 309 | #define ALE_SRAM_RRD_LEN 0x150C |
| 310 | |
| 311 | #define ALE_SRAM_TPD_ADDR 0x1510 |
| 312 | |
| 313 | #define ALE_SRAM_TPD_LEN 0x1514 |
| 314 | |
| 315 | #define ALE_SRAM_TRD_ADDR 0x1518 |
| 316 | |
| 317 | #define ALE_SRAM_TRD_LEN 0x151C |
| 318 | |
| 319 | #define ALE_SRAM_RX_FIFO_ADDR 0x1520 |
| 320 | |
| 321 | #define ALE_SRAM_RX_FIFO_LEN 0x1524 |
| 322 | |
| 323 | #define ALE_SRAM_TX_FIFO_ADDR 0x1528 |
| 324 | |
| 325 | #define ALE_SRAM_TX_FIFO_LEN 0x152C |
| 326 | |
| 327 | #define ALE_SRAM_TCPH_ADDR 0x1530 |
| 328 | #define SRAM_TCPH_ADDR_MASK 0x00000FFF |
| 329 | #define SRAM_PATH_ADDR_MASK 0x0FFF0000 |
| 330 | #define SRAM_TCPH_ADDR_SHIFT 0 |
| 331 | #define SRAM_PATH_ADDR_SHIFT 16 |
| 332 | |
| 333 | #define ALE_DMA_BLOCK 0x1534 |
| 334 | #define DMA_BLOCK_LOAD 0x00000001 |
| 335 | |
| 336 | #define ALE_RXF3_ADDR_HI 0x153C |
| 337 | |
| 338 | #define ALE_TPD_ADDR_HI 0x1540 |
| 339 | |
| 340 | #define ALE_RXF0_PAGE0_ADDR_LO 0x1544 |
| 341 | |
| 342 | #define ALE_RXF0_PAGE1_ADDR_LO 0x1548 |
| 343 | |
| 344 | #define ALE_TPD_ADDR_LO 0x154C |
| 345 | |
| 346 | #define ALE_RXF1_ADDR_HI 0x1550 |
| 347 | |
| 348 | #define ALE_RXF2_ADDR_HI 0x1554 |
| 349 | |
| 350 | #define ALE_RXF_PAGE_SIZE 0x1558 |
| 351 | |
| 352 | #define ALE_TPD_CNT 0x155C |
| 353 | #define TPD_CNT_MASK 0x00003FF |
| 354 | #define TPD_CNT_SHIFT 0 |
| 355 | |
| 356 | #define 0x1560 |
| 357 | |
| 358 | #define 0x1564 |
| 359 | |
| 360 | #define 0x1568 |
| 361 | |
| 362 | #define 0x156C |
| 363 | |
| 364 | #define 0x1570 |
| 365 | |
| 366 | #define 0x1574 |
| 367 | |
| 368 | #define 0x157C |
| 369 | |
| 370 | #define ALE_TXQ_CFG 0x1580 |
| 371 | #define TXQ_CFG_TPD_BURST_MASK 0x0000000F |
| 372 | #define TXQ_CFG_ENB 0x00000020 |
| 373 | #define TXQ_CFG_ENHANCED_MODE 0x00000040 |
| 374 | #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 |
| 375 | #define TXQ_CFG_TPD_BURST_SHIFT 0 |
| 376 | #define TXQ_CFG_TPD_BURST_DEFAULT 4 |
| 377 | #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 |
| 378 | #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 |
| 379 | |
| 380 | #define ALE_TX_JUMBO_THRESH 0x1584 |
| 381 | #define TX_JUMBO_THRESH_MASK 0x000007FF |
| 382 | #define TX_JUMBO_THRESH_SHIFT 0 |
| 383 | #define TX_JUMBO_THRESH_UNIT 8 |
| 384 | #define TX_JUMBO_THRESH_UNIT_SHIFT 3 |
| 385 | |
| 386 | #define ALE_RXQ_CFG 0x15A0 |
| 387 | #define RXQ_CFG_ALIGN_32 0x00000000 |
| 388 | #define RXQ_CFG_ALIGN_64 0x00000001 |
| 389 | #define RXQ_CFG_ALIGN_128 0x00000002 |
| 390 | #define RXQ_CFG_ALIGN_256 0x00000003 |
| 391 | #define RXQ_CFG_QUEUE1_ENB 0x00000010 |
| 392 | #define RXQ_CFG_QUEUE2_ENB 0x00000020 |
| 393 | #define RXQ_CFG_QUEUE3_ENB 0x00000040 |
| 394 | #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 |
| 395 | #define 0x0000FF00 |
| 396 | #define 0x00010000 |
| 397 | #define 0x00020000 |
| 398 | #define 0x00040000 |
| 399 | #define 0x00080000 |
| 400 | #define 0x00000000 |
| 401 | #define 0x04000000 |
| 402 | #define 0x08000000 |
| 403 | #define 0x0C000000 |
| 404 | #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 |
| 405 | #define 0x20000000 |
| 406 | #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 |
| 407 | #define RXQ_CFG_ENB 0x80000000 |
| 408 | #define 8 |
| 409 | |
| 410 | #define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ |
| 411 | #define RX_JUMBO_THRESH_MASK 0x07FF |
| 412 | #define RX_JUMBO_LKAH_MASK 0x7800 |
| 413 | #define RX_JUMBO_THRESH_MASK_SHIFT 0 |
| 414 | #define RX_JUMBO_THRESH_UNIT 8 |
| 415 | #define RX_JUMBO_THRESH_UNIT_SHIFT 3 |
| 416 | #define RX_JUMBO_LKAH_SHIFT 11 |
| 417 | #define RX_JUMBO_LKAH_DEFAULT 1 |
| 418 | |
| 419 | #define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 |
| 420 | #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF |
| 421 | #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 |
| 422 | #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 |
| 423 | #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 |
| 424 | |
| 425 | #define ALE_CMB_RXF1 0x15B4 |
| 426 | |
| 427 | #define ALE_CMB_RXF2 0x15B8 |
| 428 | |
| 429 | #define ALE_CMB_RXF3 0x15BC |
| 430 | |
| 431 | #define ALE_DMA_CFG 0x15C0 |
| 432 | #define DMA_CFG_IN_ORDER 0x00000001 |
| 433 | #define DMA_CFG_ENH_ORDER 0x00000002 |
| 434 | #define DMA_CFG_OUT_ORDER 0x00000004 |
| 435 | #define DMA_CFG_RCB_64 0x00000000 |
| 436 | #define DMA_CFG_RCB_128 0x00000008 |
| 437 | #define DMA_CFG_RD_BURST_128 0x00000000 |
| 438 | #define DMA_CFG_RD_BURST_256 0x00000010 |
| 439 | #define DMA_CFG_RD_BURST_512 0x00000020 |
| 440 | #define DMA_CFG_RD_BURST_1024 0x00000030 |
| 441 | #define DMA_CFG_RD_BURST_2048 0x00000040 |
| 442 | #define DMA_CFG_RD_BURST_4096 0x00000050 |
| 443 | #define DMA_CFG_WR_BURST_128 0x00000000 |
| 444 | #define DMA_CFG_WR_BURST_256 0x00000080 |
| 445 | #define DMA_CFG_WR_BURST_512 0x00000100 |
| 446 | #define DMA_CFG_WR_BURST_1024 0x00000180 |
| 447 | #define DMA_CFG_WR_BURST_2048 0x00000200 |
| 448 | #define DMA_CFG_WR_BURST_4096 0x00000280 |
| 449 | #define DMA_CFG_RD_REQ_PRI 0x00000400 |
| 450 | #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 |
| 451 | #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 |
| 452 | #define DMA_CFG_TXCMB_ENB 0x00100000 |
| 453 | #define DMA_CFG_RXCMB_ENB 0x00200000 |
| 454 | #define DMA_CFG_RD_BURST_MASK 0x07 |
| 455 | #define DMA_CFG_RD_BURST_SHIFT 4 |
| 456 | #define DMA_CFG_WR_BURST_MASK 0x07 |
| 457 | #define DMA_CFG_WR_BURST_SHIFT 7 |
| 458 | #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 |
| 459 | #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 |
| 460 | #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 |
| 461 | #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 |
| 462 | |
| 463 | #define ALE_SMB_STAT_TIMER 0x15C4 |
| 464 | |
| 465 | #define ALE_INT_TRIG_THRESH 0x15C8 |
| 466 | #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF |
| 467 | #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 |
| 468 | #define INT_TRIG_TX_THRESH_SHIFT 0 |
| 469 | #define INT_TRIG_RX_THRESH_SHIFT 16 |
| 470 | |
| 471 | #define ALE_INT_TRIG_TIMER 0x15CC |
| 472 | #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF |
| 473 | #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF |
| 474 | #define INT_TRIG_TX_TIMER_SHIFT 0 |
| 475 | #define INT_TRIG_RX_TIMER_SHIFT 16 |
| 476 | |
| 477 | #define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 |
| 478 | |
| 479 | #define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 |
| 480 | |
| 481 | #define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 |
| 482 | |
| 483 | #define ALE_RXF2_PAGE1_ADDR_LO 0x15DC |
| 484 | |
| 485 | #define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 |
| 486 | |
| 487 | #define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 |
| 488 | |
| 489 | #define ALE_MBOX_TPD_PROD_IDX 0x15F0 |
| 490 | |
| 491 | #define ALE_RXF0_PAGE0 0x15F4 |
| 492 | |
| 493 | #define ALE_RXF0_PAGE1 0x15F5 |
| 494 | |
| 495 | #define ALE_RXF1_PAGE0 0x15F6 |
| 496 | |
| 497 | #define ALE_RXF1_PAGE1 0x15F7 |
| 498 | |
| 499 | #define ALE_RXF2_PAGE0 0x15F8 |
| 500 | |
| 501 | #define ALE_RXF2_PAGE1 0x15F9 |
| 502 | |
| 503 | #define ALE_RXF3_PAGE0 0x15FA |
| 504 | |
| 505 | #define ALE_RXF3_PAGE1 0x15FB |
| 506 | |
| 507 | #define RXF_VALID 0x01 |
| 508 | |
| 509 | #define ALE_INTR_STATUS 0x1600 |
| 510 | #define INTR_SMB 0x00000001 |
| 511 | #define INTR_TIMER 0x00000002 |
| 512 | #define INTR_MANUAL_TIMER 0x00000004 |
| 513 | #define INTR_RX_FIFO_OFLOW 0x00000008 |
| 514 | #define INTR_RXF0_OFLOW 0x00000010 |
| 515 | #define INTR_RXF1_OFLOW 0x00000020 |
| 516 | #define INTR_RXF2_OFLOW 0x00000040 |
| 517 | #define INTR_RXF3_OFLOW 0x00000080 |
| 518 | #define INTR_TX_FIFO_UNDERRUN 0x00000100 |
| 519 | #define INTR_RX0_PAGE_FULL 0x00000200 |
| 520 | #define INTR_DMA_RD_TO_RST 0x00000400 |
| 521 | #define INTR_DMA_WR_TO_RST 0x00000800 |
| 522 | #define INTR_GPHY 0x00001000 |
| 523 | #define INTR_TX_CREDIT 0x00002000 |
| 524 | #define INTR_GPHY_LOW_PW 0x00004000 |
| 525 | #define INTR_RX_PKT 0x00010000 |
| 526 | #define INTR_TX_PKT 0x00020000 |
| 527 | #define INTR_TX_DMA 0x00040000 |
| 528 | #define INTR_RX_PKT1 0x00080000 |
| 529 | #define INTR_RX_PKT2 0x00100000 |
| 530 | #define INTR_RX_PKT3 0x00200000 |
| 531 | #define INTR_MAC_RX 0x00400000 |
| 532 | #define INTR_MAC_TX 0x00800000 |
| 533 | #define INTR_UNDERRUN 0x01000000 |
| 534 | #define INTR_FRAME_ERROR 0x02000000 |
| 535 | #define INTR_FRAME_OK 0x04000000 |
| 536 | #define INTR_CSUM_ERROR 0x08000000 |
| 537 | #define INTR_PHY_LINK_DOWN 0x10000000 |
| 538 | #define INTR_DIS_INT 0x80000000 |
| 539 | |
| 540 | /* Interrupt Mask Register */ |
| 541 | #define ALE_INTR_MASK 0x1604 |
| 542 | |
| 543 | #define ALE_INTRS \ |
| 544 | (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ |
| 545 | INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ |
| 546 | INTR_TX_FIFO_UNDERRUN) |
| 547 | |
| 548 | /* |
| 549 | * AR81xx requires register access to get MAC statistics |
| 550 | * and the format of statistics seems to be the same of L1 . |
| 551 | */ |
| 552 | #define ALE_RX_MIB_BASE 0x1700 |
| 553 | |
| 554 | #define ALE_TX_MIB_BASE 0x1760 |
| 555 | |
| 556 | /* Statistics counters collected by the MAC. */ |
| 557 | struct smb { |
| 558 | /* Rx stats. */ |
| 559 | uint32_t rx_frames; |
| 560 | uint32_t rx_bcast_frames; |
| 561 | uint32_t rx_mcast_frames; |
| 562 | uint32_t rx_pause_frames; |
| 563 | uint32_t rx_control_frames; |
| 564 | uint32_t rx_crcerrs; |
| 565 | uint32_t rx_lenerrs; |
| 566 | uint32_t rx_bytes; |
| 567 | uint32_t rx_runts; |
| 568 | uint32_t rx_fragments; |
| 569 | uint32_t rx_pkts_64; |
| 570 | uint32_t rx_pkts_65_127; |
| 571 | uint32_t rx_pkts_128_255; |
| 572 | uint32_t rx_pkts_256_511; |
| 573 | uint32_t rx_pkts_512_1023; |
| 574 | uint32_t rx_pkts_1024_1518; |
| 575 | uint32_t rx_pkts_1519_max; |
| 576 | uint32_t rx_pkts_truncated; |
| 577 | uint32_t rx_fifo_oflows; |
| 578 | uint32_t rx_rrs_errs; |
| 579 | uint32_t rx_alignerrs; |
| 580 | uint32_t rx_bcast_bytes; |
| 581 | uint32_t rx_mcast_bytes; |
| 582 | uint32_t rx_pkts_filtered; |
| 583 | /* Tx stats. */ |
| 584 | uint32_t tx_frames; |
| 585 | uint32_t tx_bcast_frames; |
| 586 | uint32_t tx_mcast_frames; |
| 587 | uint32_t tx_pause_frames; |
| 588 | uint32_t tx_excess_defer; |
| 589 | uint32_t tx_control_frames; |
| 590 | uint32_t tx_deferred; |
| 591 | uint32_t tx_bytes; |
| 592 | uint32_t tx_pkts_64; |
| 593 | uint32_t tx_pkts_65_127; |
| 594 | uint32_t tx_pkts_128_255; |
| 595 | uint32_t tx_pkts_256_511; |
| 596 | uint32_t tx_pkts_512_1023; |
| 597 | uint32_t tx_pkts_1024_1518; |
| 598 | uint32_t tx_pkts_1519_max; |
| 599 | uint32_t tx_single_colls; |
| 600 | uint32_t tx_multi_colls; |
| 601 | uint32_t tx_late_colls; |
| 602 | uint32_t tx_excess_colls; |
| 603 | uint32_t tx_abort; |
| 604 | uint32_t tx_underrun; |
| 605 | uint32_t tx_desc_underrun; |
| 606 | uint32_t tx_lenerrs; |
| 607 | uint32_t tx_pkts_truncated; |
| 608 | uint32_t tx_bcast_bytes; |
| 609 | uint32_t tx_mcast_bytes; |
| 610 | } __packed; |
| 611 | |
| 612 | #define ALE_HOST_RXF0_PAGEOFF 0x1800 |
| 613 | |
| 614 | #define ALE_TPD_CONS_IDX 0x1804 |
| 615 | |
| 616 | #define ALE_HOST_RXF1_PAGEOFF 0x1808 |
| 617 | |
| 618 | #define ALE_HOST_RXF2_PAGEOFF 0x180C |
| 619 | |
| 620 | #define ALE_HOST_RXF3_PAGEOFF 0x1810 |
| 621 | |
| 622 | #define ALE_RXF0_CMB0_ADDR_LO 0x1820 |
| 623 | |
| 624 | #define ALE_RXF0_CMB1_ADDR_LO 0x1824 |
| 625 | |
| 626 | #define ALE_RXF1_CMB0_ADDR_LO 0x1828 |
| 627 | |
| 628 | #define ALE_RXF1_CMB1_ADDR_LO 0x182C |
| 629 | |
| 630 | #define ALE_RXF2_CMB0_ADDR_LO 0x1830 |
| 631 | |
| 632 | #define ALE_RXF2_CMB1_ADDR_LO 0x1834 |
| 633 | |
| 634 | #define ALE_RXF3_CMB0_ADDR_LO 0x1838 |
| 635 | |
| 636 | #define ALE_RXF3_CMB1_ADDR_LO 0x183C |
| 637 | |
| 638 | #define ALE_TX_CMB_ADDR_LO 0x1840 |
| 639 | |
| 640 | #define ALE_SMB_ADDR_LO 0x1844 |
| 641 | |
| 642 | /* |
| 643 | * RRS(receive return status) structure. |
| 644 | * |
| 645 | * Note: |
| 646 | * Atheros AR81xx does not support descriptor based DMA on Rx |
| 647 | * instead it just prepends a Rx status structure prior to a |
| 648 | * received frame which also resides on the same Rx buffer. |
| 649 | * This means driver should copy an entire frame from the |
| 650 | * buffer to new mbuf chain which in turn greatly increases CPU |
| 651 | * cycles and effectively nullify the advantage of DMA |
| 652 | * operation of controller. So you should have fast CPU to cope |
| 653 | * with the copy operation. Implementing flow-controls may help |
| 654 | * a lot to minimize Rx FIFO overflows but it's not available |
| 655 | * yet on FreeBSD and hardware doesn't seem to support |
| 656 | * fine-grained Tx/Rx flow controls. |
| 657 | */ |
| 658 | struct rx_rs { |
| 659 | uint32_t seqno; |
| 660 | #define ALE_RD_SEQNO_MASK 0x0000FFFF |
| 661 | #define ALE_RD_HASH_MASK 0xFFFF0000 |
| 662 | #define ALE_RD_SEQNO_SHIFT 0 |
| 663 | #define ALE_RD_HASH_SHIFT 16 |
| 664 | #define ALE_RX_SEQNO(x) \ |
| 665 | (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) |
| 666 | uint32_t length; |
| 667 | #define ALE_RD_CSUM_MASK 0x0000FFFF |
| 668 | #define ALE_RD_LEN_MASK 0x3FFF0000 |
| 669 | #define ALE_RD_CPU_MASK 0xC0000000 |
| 670 | #define ALE_RD_CSUM_SHIFT 0 |
| 671 | #define ALE_RD_LEN_SHIFT 16 |
| 672 | #define ALE_RD_CPU_SHIFT 30 |
| 673 | #define ALE_RX_CSUM(x) \ |
| 674 | (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) |
| 675 | #define ALE_RX_BYTES(x) \ |
| 676 | (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) |
| 677 | #define ALE_RX_CPU(x) \ |
| 678 | (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) |
| 679 | uint32_t flags; |
| 680 | #define 0x00000001 |
| 681 | #define 0x00000002 |
| 682 | #define 0x00000004 |
| 683 | #define 0x00000008 |
| 684 | #define ALE_RD_IPV6 0x00000010 |
| 685 | #define ALE_RD_IPV4_FRAG 0x00000020 |
| 686 | #define ALE_RD_IPV4_DF 0x00000040 |
| 687 | #define ALE_RD_802_3 0x00000080 |
| 688 | #define ALE_RD_VLAN 0x00000100 |
| 689 | #define ALE_RD_ERROR 0x00000200 |
| 690 | #define ALE_RD_IPV4 0x00000400 |
| 691 | #define ALE_RD_UDP 0x00000800 |
| 692 | #define ALE_RD_TCP 0x00001000 |
| 693 | #define ALE_RD_BCAST 0x00002000 |
| 694 | #define ALE_RD_MCAST 0x00004000 |
| 695 | #define ALE_RD_PAUSE 0x00008000 |
| 696 | #define ALE_RD_CRC 0x00010000 |
| 697 | #define ALE_RD_CODE 0x00020000 |
| 698 | #define ALE_RD_DRIBBLE 0x00040000 |
| 699 | #define ALE_RD_RUNT 0x00080000 |
| 700 | #define ALE_RD_OFLOW 0x00100000 |
| 701 | #define ALE_RD_TRUNC 0x00200000 |
| 702 | #define ALE_RD_IPCSUM_NOK 0x00400000 |
| 703 | #define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 |
| 704 | #define ALE_RD_LENGTH_NOK 0x01000000 |
| 705 | #define ALE_RD_DES_ADDR_FILTERED 0x02000000 |
| 706 | uint32_t vtags; |
| 707 | #define ALE_RD_HASH_HI_MASK 0x0000FFFF |
| 708 | #define ALE_RD_HASH_HI_SHIFT 0 |
| 709 | #define ALE_RD_VLAN_MASK 0xFFFF0000 |
| 710 | #define ALE_RD_VLAN_SHIFT 16 |
| 711 | #define ALE_RX_VLAN(x) \ |
| 712 | (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) |
| 713 | #define ALE_RX_VLAN_TAG(x) \ |
| 714 | (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) |
| 715 | } __packed; |
| 716 | |
| 717 | /* Tx descriptor. */ |
| 718 | struct tx_desc { |
| 719 | uint64_t addr; |
| 720 | uint32_t len; |
| 721 | #define ALE_TD_VLAN_MASK 0xFFFF0000 |
| 722 | #define ALE_TD_PKT_INT 0x00008000 |
| 723 | #define ALE_TD_DMA_INT 0x00004000 |
| 724 | #define ALE_TD_BUFLEN_MASK 0x00003FFF |
| 725 | #define ALE_TD_VLAN_SHIFT 16 |
| 726 | #define ALE_TX_VLAN_TAG(x) \ |
| 727 | (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) |
| 728 | #define ALE_TD_BUFLEN_SHIFT 0 |
| 729 | #define ALE_TX_BYTES(x) \ |
| 730 | (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) |
| 731 | uint32_t flags; |
| 732 | #define ALE_TD_MSS 0xFFF80000 |
| 733 | #define ALE_TD_TSO_HDR 0x00040000 |
| 734 | #define ALE_TD_TCPHDR_LEN 0x0003C000 |
| 735 | #define ALE_TD_IPHDR_LEN 0x00003C00 |
| 736 | #define ALE_TD_IPV6HDR_LEN2 0x00003C00 |
| 737 | #define ALE_TD_LLC_SNAP 0x00000200 |
| 738 | #define ALE_TD_VLAN_TAGGED 0x00000100 |
| 739 | #define ALE_TD_UDPCSUM 0x00000080 |
| 740 | #define ALE_TD_TCPCSUM 0x00000040 |
| 741 | #define ALE_TD_IPCSUM 0x00000020 |
| 742 | #define ALE_TD_IPV6HDR_LEN1 0x000000E0 |
| 743 | #define ALE_TD_TSO 0x00000010 |
| 744 | #define ALE_TD_CXSUM 0x00000008 |
| 745 | #define ALE_TD_INSERT_VLAN_TAG 0x00000004 |
| 746 | #define ALE_TD_IPV6 0x00000002 |
| 747 | #define ALE_TD_EOP 0x00000001 |
| 748 | |
| 749 | #define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 |
| 750 | #define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 |
| 751 | #define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 |
| 752 | #define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 |
| 753 | #define ALE_TD_MSS_SHIFT 19 |
| 754 | #define ALE_TD_TCPHDR_LEN_SHIFT 14 |
| 755 | #define ALE_TD_IPHDR_LEN_SHIFT 10 |
| 756 | } __packed; |
| 757 | |
| 758 | #define ALE_TX_RING_CNT 256 /* Should be multiple of 4. */ |
| 759 | #define ALE_TX_RING_CNT_MIN 32 |
| 760 | #define ALE_TX_RING_CNT_MAX 1020 |
| 761 | #define ALE_TX_RING_ALIGN 8 |
| 762 | #define ALE_RX_PAGE_ALIGN 32 |
| 763 | #define ALE_RX_PAGES 2 |
| 764 | #define ALE_CMB_ALIGN 32 |
| 765 | |
| 766 | #define ALE_TSO_MAXSEGSIZE 4096 |
| 767 | #define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) |
| 768 | #define ALE_MAXTXSEGS 32 |
| 769 | |
| 770 | #define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) |
| 771 | #define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32) |
| 772 | |
| 773 | /* Water mark to kick reclaiming Tx buffers. */ |
| 774 | #define ALE_TX_DESC_HIWAT (ALE_TX_RING_CNT - ((ALE_TX_RING_CNT * 4) / 10)) |
| 775 | |
| 776 | #define ALE_MSI_MESSAGES 1 |
| 777 | #define ALE_MSIX_MESSAGES 1 |
| 778 | |
| 779 | /* |
| 780 | * TODO : Should get real jumbo MTU size. |
| 781 | * The hardware seems to have trouble in dealing with large |
| 782 | * frame length. If you encounter unstability issue, use |
| 783 | * lower MTU size. |
| 784 | */ |
| 785 | #define ALE_JUMBO_FRAMELEN 8132 |
| 786 | #define ALE_JUMBO_MTU \ |
| 787 | (ALE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) |
| 788 | #define ALE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) |
| 789 | |
| 790 | #define ALE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) |
| 791 | |
| 792 | struct ale_txdesc { |
| 793 | struct mbuf *tx_m; |
| 794 | bus_dmamap_t tx_dmamap; |
| 795 | }; |
| 796 | |
| 797 | struct ale_rx_page { |
| 798 | bus_dmamap_t page_map; |
| 799 | bus_dma_segment_t page_seg; |
| 800 | uint8_t *page_addr; |
| 801 | bus_addr_t page_paddr; |
| 802 | bus_dmamap_t cmb_map; |
| 803 | bus_dma_segment_t cmb_seg; |
| 804 | uint32_t *cmb_addr; |
| 805 | bus_addr_t cmb_paddr; |
| 806 | uint32_t cons; |
| 807 | }; |
| 808 | |
| 809 | struct ale_chain_data{ |
| 810 | struct ale_txdesc ale_txdesc[ALE_TX_RING_CNT]; |
| 811 | bus_dmamap_t ale_tx_ring_map; |
| 812 | bus_dma_segment_t ale_tx_ring_seg; |
| 813 | bus_dmamap_t ale_rx_mblock_map[ALE_RX_PAGES]; |
| 814 | bus_dma_segment_t ale_rx_mblock_seg[ALE_RX_PAGES]; |
| 815 | struct tx_desc *ale_tx_ring; |
| 816 | bus_addr_t ale_tx_ring_paddr; |
| 817 | uint32_t *ale_tx_cmb; |
| 818 | bus_addr_t ale_tx_cmb_paddr; |
| 819 | bus_dmamap_t ale_tx_cmb_map; |
| 820 | bus_dma_segment_t ale_tx_cmb_seg; |
| 821 | |
| 822 | uint32_t ale_tx_prod; |
| 823 | uint32_t ale_tx_cons; |
| 824 | int ale_tx_cnt; |
| 825 | struct ale_rx_page ale_rx_page[ALE_RX_PAGES]; |
| 826 | int ale_rx_curp; |
| 827 | uint16_t ale_rx_seqno; |
| 828 | }; |
| 829 | |
| 830 | #define ALE_TX_RING_SZ \ |
| 831 | (sizeof(struct tx_desc) * ALE_TX_RING_CNT) |
| 832 | #define ALE_RX_PAGE_SZ_MIN (8 * 1024) |
| 833 | #define ALE_RX_PAGE_SZ_MAX (1024 * 1024) |
| 834 | #define ALE_RX_FRAMES_PAGE 128 |
| 835 | #define ALE_RX_PAGE_SZ \ |
| 836 | (roundup(ALE_MAX_FRAMELEN, ALE_RX_PAGE_ALIGN) * ALE_RX_FRAMES_PAGE) |
| 837 | #define ALE_TX_CMB_SZ (sizeof(uint32_t)) |
| 838 | #define ALE_RX_CMB_SZ (sizeof(uint32_t)) |
| 839 | |
| 840 | #define ALE_PROC_MIN (ALE_RX_FRAMES_PAGE / 4) |
| 841 | #define ALE_PROC_MAX \ |
| 842 | ((ALE_RX_PAGE_SZ * ALE_RX_PAGES) / ETHER_MAX_LEN) |
| 843 | #define ALE_PROC_DEFAULT (ALE_PROC_MAX / 4) |
| 844 | |
| 845 | struct ale_hw_stats { |
| 846 | /* Rx stats. */ |
| 847 | uint32_t rx_frames; |
| 848 | uint32_t rx_bcast_frames; |
| 849 | uint32_t rx_mcast_frames; |
| 850 | uint32_t rx_pause_frames; |
| 851 | uint32_t rx_control_frames; |
| 852 | uint32_t rx_crcerrs; |
| 853 | uint32_t rx_lenerrs; |
| 854 | uint64_t rx_bytes; |
| 855 | uint32_t rx_runts; |
| 856 | uint32_t rx_fragments; |
| 857 | uint32_t rx_pkts_64; |
| 858 | uint32_t rx_pkts_65_127; |
| 859 | uint32_t rx_pkts_128_255; |
| 860 | uint32_t rx_pkts_256_511; |
| 861 | uint32_t rx_pkts_512_1023; |
| 862 | uint32_t rx_pkts_1024_1518; |
| 863 | uint32_t rx_pkts_1519_max; |
| 864 | uint32_t rx_pkts_truncated; |
| 865 | uint32_t rx_fifo_oflows; |
| 866 | uint32_t rx_rrs_errs; |
| 867 | uint32_t rx_alignerrs; |
| 868 | uint64_t rx_bcast_bytes; |
| 869 | uint64_t rx_mcast_bytes; |
| 870 | uint32_t rx_pkts_filtered; |
| 871 | /* Tx stats. */ |
| 872 | uint32_t tx_frames; |
| 873 | uint32_t tx_bcast_frames; |
| 874 | uint32_t tx_mcast_frames; |
| 875 | uint32_t tx_pause_frames; |
| 876 | uint32_t tx_excess_defer; |
| 877 | uint32_t tx_control_frames; |
| 878 | uint32_t tx_deferred; |
| 879 | uint64_t tx_bytes; |
| 880 | uint32_t tx_pkts_64; |
| 881 | uint32_t tx_pkts_65_127; |
| 882 | uint32_t tx_pkts_128_255; |
| 883 | uint32_t tx_pkts_256_511; |
| 884 | uint32_t tx_pkts_512_1023; |
| 885 | uint32_t tx_pkts_1024_1518; |
| 886 | uint32_t tx_pkts_1519_max; |
| 887 | uint32_t tx_single_colls; |
| 888 | uint32_t tx_multi_colls; |
| 889 | uint32_t tx_late_colls; |
| 890 | uint32_t tx_excess_colls; |
| 891 | uint32_t tx_abort; |
| 892 | uint32_t tx_underrun; |
| 893 | uint32_t tx_desc_underrun; |
| 894 | uint32_t tx_lenerrs; |
| 895 | uint32_t tx_pkts_truncated; |
| 896 | uint64_t tx_bcast_bytes; |
| 897 | uint64_t tx_mcast_bytes; |
| 898 | /* Misc. */ |
| 899 | uint32_t reset_brk_seq; |
| 900 | }; |
| 901 | |
| 902 | /* |
| 903 | * Software state per device. |
| 904 | */ |
| 905 | struct ale_softc { |
| 906 | device_t sc_dev; |
| 907 | struct ethercom sc_ec; |
| 908 | |
| 909 | bus_space_tag_t sc_mem_bt; |
| 910 | bus_space_handle_t sc_mem_bh; |
| 911 | bus_size_t sc_mem_size; |
| 912 | bus_dma_tag_t sc_dmat; |
| 913 | pci_chipset_tag_t sc_pct; |
| 914 | pcitag_t sc_pcitag; |
| 915 | |
| 916 | void *sc_irq_handle; |
| 917 | |
| 918 | struct mii_data sc_miibus; |
| 919 | int ale_phyaddr; |
| 920 | |
| 921 | int ale_rev; |
| 922 | int ale_chip_rev; |
| 923 | uint8_t ale_eaddr[ETHER_ADDR_LEN]; |
| 924 | uint32_t ale_dma_rd_burst; |
| 925 | uint32_t ale_dma_wr_burst; |
| 926 | int ale_flags; |
| 927 | #define ALE_FLAG_PCIE 0x0001 |
| 928 | #define ALE_FLAG_PCIX 0x0002 |
| 929 | #define ALE_FLAG_MSI 0x0004 |
| 930 | #define ALE_FLAG_MSIX 0x0008 |
| 931 | #define ALE_FLAG_PMCAP 0x0010 |
| 932 | #define ALE_FLAG_FASTETHER 0x0020 |
| 933 | #define ALE_FLAG_JUMBO 0x0040 |
| 934 | #define ALE_FLAG_RXCSUM_BUG 0x0080 |
| 935 | #define ALE_FLAG_TXCSUM_BUG 0x0100 |
| 936 | #define ALE_FLAG_TXCMB_BUG 0x0200 |
| 937 | #define ALE_FLAG_DETACH 0x4000 |
| 938 | #define ALE_FLAG_LINK 0x8000 |
| 939 | |
| 940 | callout_t sc_tick_ch; |
| 941 | struct ale_hw_stats ale_stats; |
| 942 | struct ale_chain_data ale_cdata; |
| 943 | int ale_int_rx_mod; |
| 944 | int ale_int_tx_mod; |
| 945 | int ale_max_frame_size; |
| 946 | int ale_pagesize; |
| 947 | |
| 948 | }; |
| 949 | |
| 950 | /* Register access macros. */ |
| 951 | #define CSR_WRITE_4(_sc, reg, val) \ |
| 952 | bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 953 | #define CSR_WRITE_2(_sc, reg, val) \ |
| 954 | bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 955 | #define CSR_WRITE_1(_sc, reg, val) \ |
| 956 | bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 957 | #define CSR_READ_2(_sc, reg) \ |
| 958 | bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) |
| 959 | #define CSR_READ_4(_sc, reg) \ |
| 960 | bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) |
| 961 | |
| 962 | #define ALE_TX_TIMEOUT 5 |
| 963 | #define ALE_RESET_TIMEOUT 100 |
| 964 | #define ALE_TIMEOUT 1000 |
| 965 | #define ALE_PHY_TIMEOUT 1000 |
| 966 | |
| 967 | #endif /* _IF_ALEREG_H */ |
| 968 | |