| 1 | /* $NetBSD: if_vmxreg.h,v 1.1 2014/06/10 01:42:39 hikaru Exp $ */ |
| 2 | /* $OpenBSD: if_vmxreg.h,v 1.3 2013/08/28 10:19:19 reyk Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 2013 Tsubai Masanari |
| 6 | * |
| 7 | * Permission to use, copy, modify, and distribute this software for any |
| 8 | * purpose with or without fee is hereby granted, provided that the above |
| 9 | * copyright notice and this permission notice appear in all copies. |
| 10 | * |
| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 18 | */ |
| 19 | |
| 20 | struct UPT1_TxStats { |
| 21 | uint64_t TSO_packets; |
| 22 | uint64_t TSO_bytes; |
| 23 | uint64_t ucast_packets; |
| 24 | uint64_t ucast_bytes; |
| 25 | uint64_t mcast_packets; |
| 26 | uint64_t mcast_bytes; |
| 27 | uint64_t bcast_packets; |
| 28 | uint64_t bcast_bytes; |
| 29 | uint64_t error; |
| 30 | uint64_t discard; |
| 31 | } __packed; |
| 32 | |
| 33 | struct UPT1_RxStats { |
| 34 | uint64_t LRO_packets; |
| 35 | uint64_t LRO_bytes; |
| 36 | uint64_t ucast_packets; |
| 37 | uint64_t ucast_bytes; |
| 38 | uint64_t mcast_packets; |
| 39 | uint64_t mcast_bytes; |
| 40 | uint64_t bcast_packets; |
| 41 | uint64_t bcast_bytes; |
| 42 | uint64_t nobuffer; |
| 43 | uint64_t error; |
| 44 | } __packed; |
| 45 | |
| 46 | #define ETHER_ALIGN 2 |
| 47 | |
| 48 | /* interrupt moderation levels */ |
| 49 | #define UPT1_IMOD_NONE 0 /* no moderation */ |
| 50 | #define UPT1_IMOD_HIGHEST 7 /* least interrupts */ |
| 51 | #define UPT1_IMOD_ADAPTIVE 8 /* adaptive interrupt moderation */ |
| 52 | |
| 53 | /* hardware features */ |
| 54 | #define UPT1_F_CSUM 0x0001 /* Rx checksum verification */ |
| 55 | #define 0x0002 /* receive side scaling */ |
| 56 | #define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */ |
| 57 | #define UPT1_F_LRO 0x0008 /* large receive offloading */ |
| 58 | |
| 59 | #define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* interrupt mask */ |
| 60 | #define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */ |
| 61 | #define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* ring1 Rx head */ |
| 62 | #define VMXNET3_BAR0_RXH2(q) (0xa00 + (q) * 8) /* ring2 Rx head */ |
| 63 | #define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */ |
| 64 | #define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */ |
| 65 | #define VMXNET3_BAR1_DSL 0x010 /* driver shared address low */ |
| 66 | #define VMXNET3_BAR1_DSH 0x018 /* driver shared address high */ |
| 67 | #define VMXNET3_BAR1_CMD 0x020 /* command */ |
| 68 | #define VMXNET3_BAR1_MACL 0x028 /* MAC address low */ |
| 69 | #define VMXNET3_BAR1_MACH 0x030 /* MAC address high */ |
| 70 | #define VMXNET3_BAR1_INTR 0x038 /* interrupt status */ |
| 71 | #define VMXNET3_BAR1_EVENT 0x040 /* event status */ |
| 72 | |
| 73 | #define VMXNET3_CMD_ENABLE 0xcafe0000 /* enable VMXNET3 */ |
| 74 | #define VMXNET3_CMD_DISABLE 0xcafe0001 /* disable VMXNET3 */ |
| 75 | #define VMXNET3_CMD_RESET 0xcafe0002 /* reset device */ |
| 76 | #define VMXNET3_CMD_SET_RXMODE 0xcafe0003 /* set interface flags */ |
| 77 | #define VMXNET3_CMD_SET_FILTER 0xcafe0004 /* set address filter */ |
| 78 | #define VMXNET3_CMD_GET_STATUS 0xf00d0000 /* get queue errors */ |
| 79 | #define VMXNET3_CMD_GET_LINK 0xf00d0002 /* get link status */ |
| 80 | #define VMXNET3_CMD_GET_MACL 0xf00d0003 |
| 81 | #define VMXNET3_CMD_GET_MACH 0xf00d0004 |
| 82 | |
| 83 | #define VMXNET3_DMADESC_ALIGN 128 |
| 84 | |
| 85 | /* All descriptors are in little-endian format. */ |
| 86 | struct vmxnet3_txdesc { |
| 87 | uint64_t tx_addr; |
| 88 | |
| 89 | uint32_t tx_word2; |
| 90 | #define VMXNET3_TX_LEN_M 0x00003fff |
| 91 | #define VMXNET3_TX_LEN_S 0 |
| 92 | #define VMXNET3_TX_GEN_M 0x00000001 /* generation */ |
| 93 | #define VMXNET3_TX_GEN_S 14 |
| 94 | #define VMXNET3_TX_RES0 0x00008000 |
| 95 | #define VMXNET3_TX_DTYPE_M 0x00000001 /* descriptor type */ |
| 96 | #define VMXNET3_TX_DTYPE_S 16 /* descriptor type */ |
| 97 | #define VMXNET3_TX_RES1 0x00000002 |
| 98 | #define VMXNET3_TX_OP_M 0x00003fff /* offloading position */ |
| 99 | #define VMXNET3_TX_OP_S 18 |
| 100 | |
| 101 | uint32_t tx_word3; |
| 102 | #define VMXNET3_TX_HLEN_M 0x000003ff /* header len */ |
| 103 | #define VMXNET3_TX_HLEN_S 0 |
| 104 | #define VMXNET3_TX_OM_M 0x00000003 /* offloading mode */ |
| 105 | #define VMXNET3_TX_OM_S 10 |
| 106 | #define VMXNET3_TX_EOP 0x00001000 /* end of packet */ |
| 107 | #define VMXNET3_TX_COMPREQ 0x00002000 /* completion request */ |
| 108 | #define VMXNET3_TX_RES2 0x00004000 |
| 109 | #define VMXNET3_TX_VTAG_MODE 0x00008000 /* VLAN tag insertion mode */ |
| 110 | #define VMXNET3_TX_VLANTAG_M 0x0000ffff |
| 111 | #define VMXNET3_TX_VLANTAG_S 16 |
| 112 | } __packed; |
| 113 | |
| 114 | /* offloading modes */ |
| 115 | #define VMXNET3_OM_NONE 0 |
| 116 | #define VMXNET3_OM_CSUM 2 |
| 117 | #define VMXNET3_OM_TSO 3 |
| 118 | |
| 119 | struct vmxnet3_txcompdesc { |
| 120 | uint32_t txc_word0; |
| 121 | #define VMXNET3_TXC_EOPIDX_M 0x00000fff /* eop index in Tx ring */ |
| 122 | #define VMXNET3_TXC_EOPIDX_S 0 |
| 123 | #define VMXNET3_TXC_RES0_M 0x000fffff |
| 124 | #define VMXNET3_TXC_RES0_S 12 |
| 125 | |
| 126 | uint32_t txc_word1; |
| 127 | uint32_t txc_word2; |
| 128 | |
| 129 | uint32_t txc_word3; |
| 130 | #define VMXNET3_TXC_RES2_M 0x00ffffff |
| 131 | #define VMXNET3_TXC_TYPE_M 0x0000007f |
| 132 | #define VMXNET3_TXC_TYPE_S 24 |
| 133 | #define VMXNET3_TXC_GEN_M 0x00000001 |
| 134 | #define VMXNET3_TXC_GEN_S 31 |
| 135 | } __packed; |
| 136 | |
| 137 | struct vmxnet3_rxdesc { |
| 138 | uint64_t rx_addr; |
| 139 | |
| 140 | uint32_t rx_word2; |
| 141 | #define VMXNET3_RX_LEN_M 0x00003fff |
| 142 | #define VMXNET3_RX_LEN_S 0 |
| 143 | #define VMXNET3_RX_BTYPE_M 0x00000001 /* buffer type */ |
| 144 | #define VMXNET3_RX_BTYPE_S 14 |
| 145 | #define VMXNET3_RX_DTYPE_M 0x00000001 /* descriptor type */ |
| 146 | #define VMXNET3_RX_DTYPE_S 15 |
| 147 | #define VMXNET3_RX_RES0_M 0x00007fff |
| 148 | #define VMXNET3_RX_RES0_S 16 |
| 149 | #define VMXNET3_RX_GEN_M 0x00000001 |
| 150 | #define VMXNET3_RX_GEN_S 31 |
| 151 | |
| 152 | uint32_t rx_word3; |
| 153 | } __packed; |
| 154 | |
| 155 | /* buffer types */ |
| 156 | #define VMXNET3_BTYPE_HEAD 0 /* head only */ |
| 157 | #define VMXNET3_BTYPE_BODY 1 /* body only */ |
| 158 | |
| 159 | struct vmxnet3_rxcompdesc { |
| 160 | uint32_t rxc_word0; |
| 161 | #define VMXNET3_RXC_IDX_M 0x00000fff /* Rx descriptor index */ |
| 162 | #define VMXNET3_RXC_IDX_S 0 |
| 163 | #define VMXNET3_RXC_RES0_M 0x00000003 |
| 164 | #define VMXNET3_RXC_RES0_S 12 |
| 165 | #define VMXNET3_RXC_EOP 0x00004000 /* end of packet */ |
| 166 | #define VMXNET3_RXC_SOP 0x00008000 /* start of packet */ |
| 167 | #define VMXNET3_RXC_QID_M 0x000003ff |
| 168 | #define VMXNET3_RXC_QID_S 16 |
| 169 | #define 0x0000000f |
| 170 | #define 26 |
| 171 | #define VMXNET3_RXC_NOCSUM 0x40000000 /* no checksum calculated */ |
| 172 | #define VMXNET3_RXC_RES1 0x80000000 |
| 173 | |
| 174 | uint32_t rxc_word1; |
| 175 | #define 0xffffffff /* RSS hash value */ |
| 176 | #define 0 |
| 177 | |
| 178 | uint32_t rxc_word2; |
| 179 | #define VMXNET3_RXC_LEN_M 0x00003fff |
| 180 | #define VMXNET3_RXC_LEN_S 0 |
| 181 | #define VMXNET3_RXC_ERROR 0x00004000 |
| 182 | #define VMXNET3_RXC_VLAN 0x00008000 /* 802.1Q VLAN frame */ |
| 183 | #define VMXNET3_RXC_VLANTAG_M 0x0000ffff /* VLAN tag */ |
| 184 | #define VMXNET3_RXC_VLANTAG_S 16 |
| 185 | |
| 186 | uint32_t rxc_word3; |
| 187 | #define VMXNET3_RXC_CSUM_M 0x0000ffff /* TCP/UDP checksum */ |
| 188 | #define VMXNET3_RXC_CSUM_S 16 |
| 189 | #define VMXNET3_RXC_CSUM_OK 0x00010000 /* TCP/UDP checksum ok */ |
| 190 | #define VMXNET3_RXC_UDP 0x00020000 |
| 191 | #define VMXNET3_RXC_TCP 0x00040000 |
| 192 | #define VMXNET3_RXC_IPSUM_OK 0x00080000 /* IP checksum ok */ |
| 193 | #define VMXNET3_RXC_IPV6 0x00100000 |
| 194 | #define VMXNET3_RXC_IPV4 0x00200000 |
| 195 | #define VMXNET3_RXC_FRAGMENT 0x00400000 /* IP fragment */ |
| 196 | #define VMXNET3_RXC_FCS 0x00800000 /* frame CRC correct */ |
| 197 | #define VMXNET3_RXC_TYPE_M 0x7f000000 |
| 198 | #define VMXNET3_RXC_GEN_M 0x00000001 |
| 199 | #define VMXNET3_RXC_GEN_S 31 |
| 200 | } __packed; |
| 201 | |
| 202 | #define VMXNET3_REV1_MAGIC 0xbabefee1 |
| 203 | |
| 204 | #define VMXNET3_GOS_UNKNOWN 0x00 |
| 205 | #define VMXNET3_GOS_LINUX 0x04 |
| 206 | #define VMXNET3_GOS_WINDOWS 0x08 |
| 207 | #define VMXNET3_GOS_SOLARIS 0x0c |
| 208 | #define VMXNET3_GOS_FREEBSD 0x10 |
| 209 | #define VMXNET3_GOS_PXE 0x14 |
| 210 | |
| 211 | #define VMXNET3_GOS_32BIT 0x01 |
| 212 | #define VMXNET3_GOS_64BIT 0x02 |
| 213 | |
| 214 | #define VMXNET3_MAX_TX_QUEUES 8 |
| 215 | #define VMXNET3_MAX_RX_QUEUES 16 |
| 216 | #define VMXNET3_MAX_INTRS (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1) |
| 217 | #define VMXNET3_NINTR 1 |
| 218 | |
| 219 | #define VMXNET3_ICTRL_DISABLE_ALL 0x01 |
| 220 | |
| 221 | #define VMXNET3_RXMODE_UCAST 0x01 |
| 222 | #define VMXNET3_RXMODE_MCAST 0x02 |
| 223 | #define VMXNET3_RXMODE_BCAST 0x04 |
| 224 | #define VMXNET3_RXMODE_ALLMULTI 0x08 |
| 225 | #define VMXNET3_RXMODE_PROMISC 0x10 |
| 226 | |
| 227 | #define VMXNET3_EVENT_RQERROR 0x01 |
| 228 | #define VMXNET3_EVENT_TQERROR 0x02 |
| 229 | #define VMXNET3_EVENT_LINK 0x04 |
| 230 | #define VMXNET3_EVENT_DIC 0x08 |
| 231 | #define VMXNET3_EVENT_DEBUG 0x10 |
| 232 | |
| 233 | #define VMXNET3_MAX_MTU 9000 |
| 234 | #define VMXNET3_MIN_MTU 60 |
| 235 | |
| 236 | struct vmxnet3_driver_shared { |
| 237 | uint32_t magic; |
| 238 | uint32_t pad1; |
| 239 | |
| 240 | uint32_t version; /* driver version */ |
| 241 | uint32_t guest; /* guest OS */ |
| 242 | uint32_t vmxnet3_revision; /* supported VMXNET3 revision */ |
| 243 | uint32_t upt_version; /* supported UPT version */ |
| 244 | uint64_t upt_features; |
| 245 | uint64_t driver_data; |
| 246 | uint64_t queue_shared; |
| 247 | uint32_t driver_data_len; |
| 248 | uint32_t queue_shared_len; |
| 249 | uint32_t mtu; |
| 250 | uint16_t nrxsg_max; |
| 251 | uint8_t ntxqueue; |
| 252 | uint8_t nrxqueue; |
| 253 | uint32_t reserved1[4]; |
| 254 | |
| 255 | /* interrupt control */ |
| 256 | uint8_t automask; |
| 257 | uint8_t nintr; |
| 258 | uint8_t evintr; |
| 259 | uint8_t modlevel[VMXNET3_MAX_INTRS]; |
| 260 | uint32_t ictrl; |
| 261 | uint32_t reserved2[2]; |
| 262 | |
| 263 | /* receive filter parameters */ |
| 264 | uint32_t rxmode; |
| 265 | uint16_t mcast_tablelen; |
| 266 | uint16_t pad2; |
| 267 | uint64_t mcast_table; |
| 268 | uint32_t vlan_filter[4096 / 32]; |
| 269 | |
| 270 | struct { |
| 271 | uint32_t version; |
| 272 | uint32_t len; |
| 273 | uint64_t paddr; |
| 274 | } , pm, plugin; |
| 275 | |
| 276 | uint32_t event; |
| 277 | uint32_t reserved3[5]; |
| 278 | } __packed; |
| 279 | |
| 280 | struct vmxnet3_txq_shared { |
| 281 | uint32_t npending; |
| 282 | uint32_t intr_threshold; |
| 283 | uint64_t reserved1; |
| 284 | |
| 285 | uint64_t cmd_ring; |
| 286 | uint64_t data_ring; |
| 287 | uint64_t comp_ring; |
| 288 | uint64_t driver_data; |
| 289 | uint64_t reserved2; |
| 290 | uint32_t cmd_ring_len; |
| 291 | uint32_t data_ring_len; |
| 292 | uint32_t comp_ring_len; |
| 293 | uint32_t driver_data_len; |
| 294 | uint8_t intr_idx; |
| 295 | uint8_t pad1[7]; |
| 296 | |
| 297 | uint8_t stopped; |
| 298 | uint8_t pad2[3]; |
| 299 | uint32_t error; |
| 300 | |
| 301 | struct UPT1_TxStats stats; |
| 302 | |
| 303 | uint8_t pad3[88]; |
| 304 | } __packed; |
| 305 | |
| 306 | struct vmxnet3_rxq_shared { |
| 307 | uint8_t update_rxhead; |
| 308 | uint8_t pad1[7]; |
| 309 | uint64_t reserved1; |
| 310 | |
| 311 | uint64_t cmd_ring[2]; |
| 312 | uint64_t comp_ring; |
| 313 | uint64_t driver_data; |
| 314 | uint64_t reserved2; |
| 315 | uint32_t cmd_ring_len[2]; |
| 316 | uint32_t comp_ring_len; |
| 317 | uint32_t driver_data_len; |
| 318 | uint8_t intr_idx; |
| 319 | uint8_t pad2[7]; |
| 320 | |
| 321 | uint8_t stopped; |
| 322 | uint8_t pad3[3]; |
| 323 | uint32_t error; |
| 324 | |
| 325 | struct UPT1_RxStats stats; |
| 326 | |
| 327 | uint8_t pad4[88]; |
| 328 | } __packed; |
| 329 | |