| 1 | /* $NetBSD: sdmmcreg.h,v 1.22 2016/08/10 04:24:17 nonaka Exp $ */ |
| 2 | /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> |
| 6 | * |
| 7 | * Permission to use, copy, modify, and distribute this software for any |
| 8 | * purpose with or without fee is hereby granted, provided that the above |
| 9 | * copyright notice and this permission notice appear in all copies. |
| 10 | * |
| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 18 | */ |
| 19 | |
| 20 | #ifndef _SDMMCREG_H_ |
| 21 | #define _SDMMCREG_H_ |
| 22 | |
| 23 | /* MMC commands */ /* response type */ |
| 24 | #define MMC_GO_IDLE_STATE 0 /* R0 */ |
| 25 | #define MMC_SEND_OP_COND 1 /* R3 */ |
| 26 | #define MMC_ALL_SEND_CID 2 /* R2 */ |
| 27 | #define MMC_SET_RELATIVE_ADDR 3 /* R1 */ |
| 28 | #define MMC_SWITCH 6 /* R1b */ |
| 29 | #define MMC_SELECT_CARD 7 /* R1 */ |
| 30 | #define MMC_SEND_EXT_CSD 8 /* R1 */ |
| 31 | #define MMC_SEND_CSD 9 /* R2 */ |
| 32 | #define MMC_SEND_CID 10 /* R2 */ |
| 33 | #define MMC_STOP_TRANSMISSION 12 /* R1b */ |
| 34 | #define MMC_SEND_STATUS 13 /* R1 */ |
| 35 | #define MMC_INACTIVE_STATE 15 /* R0 */ |
| 36 | #define MMC_SET_BLOCKLEN 16 /* R1 */ |
| 37 | #define MMC_READ_BLOCK_SINGLE 17 /* R1 */ |
| 38 | #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ |
| 39 | #define MMC_SEND_TUNING_BLOCK 19 /* R1 */ |
| 40 | #define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */ |
| 41 | #define MMC_SET_BLOCK_COUNT 23 /* R1 */ |
| 42 | #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ |
| 43 | #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ |
| 44 | #define MMC_PROGRAM_CSD 27 /* R1 */ |
| 45 | #define MMC_SET_WRITE_PROT 28 /* R1b */ |
| 46 | #define MMC_SET_CLR_WRITE_PROT 29 /* R1b */ |
| 47 | #define MMC_SET_SEND_WRITE_PROT 30 /* R1 */ |
| 48 | #define MMC_TAG_SECTOR_START 32 /* R1 */ |
| 49 | #define MMC_TAG_SECTOR_END 33 /* R1 */ |
| 50 | #define MMC_UNTAG_SECTOR 34 /* R1 */ |
| 51 | #define MMC_TAG_ERASE_GROUP_START 35 /* R1 */ |
| 52 | #define MMC_TAG_ERASE_GROUP_END 36 /* R1 */ |
| 53 | #define MMC_UNTAG_ERASE_GROUP 37 /* R1 */ |
| 54 | #define MMC_ERASE 38 /* R1b */ |
| 55 | #define MMC_LOCK_UNLOCK 42 /* R1b */ |
| 56 | #define MMC_APP_CMD 55 /* R1 */ |
| 57 | #define MMC_READ_OCR 58 /* R3 */ |
| 58 | |
| 59 | /* SD commands */ /* response type */ |
| 60 | #define SD_SEND_RELATIVE_ADDR 3 /* R6 */ |
| 61 | #define SD_SEND_SWITCH_FUNC 6 /* R1 */ |
| 62 | #define SD_SEND_IF_COND 8 /* R7 */ |
| 63 | #define SD_VOLTAGE_SWITCH 11 /* R1 */ |
| 64 | |
| 65 | /* SD application commands */ /* response type */ |
| 66 | #define SD_APP_SET_BUS_WIDTH 6 /* R1 */ |
| 67 | #define SD_APP_SD_STATUS 13 /* R1 */ |
| 68 | #define SD_APP_OP_COND 41 /* R3 */ |
| 69 | #define SD_APP_SEND_SCR 51 /* R1 */ |
| 70 | |
| 71 | /* OCR bits */ |
| 72 | #define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */ |
| 73 | #define MMC_OCR_HCS (1<<30) /* SD only */ |
| 74 | #define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */ |
| 75 | #define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */ |
| 76 | #define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */ |
| 77 | #define MMC_OCR_S18A (1<<24) |
| 78 | #define MMC_OCR_3_5V_3_6V (1<<23) |
| 79 | #define MMC_OCR_3_4V_3_5V (1<<22) |
| 80 | #define MMC_OCR_3_3V_3_4V (1<<21) |
| 81 | #define MMC_OCR_3_2V_3_3V (1<<20) |
| 82 | #define MMC_OCR_3_1V_3_2V (1<<19) |
| 83 | #define MMC_OCR_3_0V_3_1V (1<<18) |
| 84 | #define MMC_OCR_2_9V_3_0V (1<<17) |
| 85 | #define MMC_OCR_2_8V_2_9V (1<<16) |
| 86 | #define MMC_OCR_2_7V_2_8V (1<<15) |
| 87 | #define MMC_OCR_2_6V_2_7V (1<<14) |
| 88 | #define MMC_OCR_2_5V_2_6V (1<<13) |
| 89 | #define MMC_OCR_2_4V_2_5V (1<<12) |
| 90 | #define MMC_OCR_2_3V_2_4V (1<<11) |
| 91 | #define MMC_OCR_2_2V_2_3V (1<<10) |
| 92 | #define MMC_OCR_2_1V_2_2V (1<<9) |
| 93 | #define MMC_OCR_2_0V_2_1V (1<<8) |
| 94 | #define MMC_OCR_1_65V_1_95V (1<<7) |
| 95 | |
| 96 | /* R1 response type bits */ |
| 97 | #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ |
| 98 | #define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */ |
| 99 | #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ |
| 100 | |
| 101 | /* 48-bit response decoding (32 bits w/o CRC) */ |
| 102 | #define MMC_R1(resp) ((resp)[0]) |
| 103 | #define MMC_R3(resp) ((resp)[0]) |
| 104 | #define SD_R6(resp) ((resp)[0]) |
| 105 | #define MMC_R7(resp) ((resp)[0]) |
| 106 | #define MMC_SPI_R1(resp) ((resp)[0]) |
| 107 | #define MMC_SPI_R7(resp) ((resp)[1]) |
| 108 | |
| 109 | /* RCA argument and response */ |
| 110 | #define MMC_ARG_RCA(rca) ((rca) << 16) |
| 111 | #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) |
| 112 | |
| 113 | /* bus width argument */ |
| 114 | #define SD_ARG_BUS_WIDTH_1 0 |
| 115 | #define SD_ARG_BUS_WIDTH_4 2 |
| 116 | |
| 117 | /* EXT_CSD fields */ |
| 118 | #define EXT_CSD_BUS_WIDTH 183 /* WO */ |
| 119 | #define EXT_CSD_HS_TIMING 185 /* R/W */ |
| 120 | #define EXT_CSD_REV 192 /* RO */ |
| 121 | #define EXT_CSD_STRUCTURE 194 /* RO */ |
| 122 | #define EXT_CSD_CARD_TYPE 196 /* RO */ |
| 123 | #define EXT_CSD_SEC_COUNT 212 /* RO */ |
| 124 | |
| 125 | /* EXT_CSD field definitions */ |
| 126 | #define EXT_CSD_CMD_SET_NORMAL (1U << 0) |
| 127 | #define EXT_CSD_CMD_SET_SECURE (1U << 1) |
| 128 | #define EXT_CSD_CMD_SET_CPSECURE (1U << 2) |
| 129 | |
| 130 | /* EXT_CSD_BUS_WIDTH */ |
| 131 | #define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */ |
| 132 | #define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */ |
| 133 | #define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */ |
| 134 | |
| 135 | /* EXT_CSD_STRUCTURE */ |
| 136 | #define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */ |
| 137 | #define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */ |
| 138 | #define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */ |
| 139 | |
| 140 | /* EXT_CSD_CARD_TYPE */ |
| 141 | #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) |
| 142 | #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) |
| 143 | #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) |
| 144 | #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) |
| 145 | #define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4) |
| 146 | #define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5) |
| 147 | #define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6) |
| 148 | #define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7) |
| 149 | #define EXT_CSD_CARD_TYPE_26M 0x01 |
| 150 | #define EXT_CSD_CARD_TYPE_52M 0x03 |
| 151 | #define EXT_CSD_CARD_TYPE_52M_V18 0x07 |
| 152 | #define EXT_CSD_CARD_TYPE_52M_V12 0x0b |
| 153 | #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f |
| 154 | |
| 155 | /* MMC_SWITCH access mode */ |
| 156 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ |
| 157 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ |
| 158 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ |
| 159 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ |
| 160 | |
| 161 | /* SPI mode reports R1/R2(SEND_STATUS) status. */ |
| 162 | #define R1_SPI_IDLE (1 << 0) |
| 163 | #define R1_SPI_ERASE_RESET (1 << 1) |
| 164 | #define R1_SPI_ILLEGAL_COMMAND (1 << 2) |
| 165 | #define R1_SPI_COM_CRC (1 << 3) |
| 166 | #define R1_SPI_ERASE_SEQ (1 << 4) |
| 167 | #define R1_SPI_ADDRESS (1 << 5) |
| 168 | #define R1_SPI_PARAMETER (1 << 6) |
| 169 | /* R1 bit 7 is always zero */ |
| 170 | #define R2_SPI_CARD_LOCKED (1 << 8) |
| 171 | #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ |
| 172 | #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP |
| 173 | #define R2_SPI_ERROR (1 << 10) |
| 174 | #define R2_SPI_CC_ERROR (1 << 11) |
| 175 | #define R2_SPI_CARD_ECC_ERROR (1 << 12) |
| 176 | #define R2_SPI_WP_VIOLATION (1 << 13) |
| 177 | #define R2_SPI_ERASE_PARAM (1 << 14) |
| 178 | #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ |
| 179 | #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE |
| 180 | |
| 181 | /* MMC R2 response (CSD) */ |
| 182 | #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) |
| 183 | #define MMC_CSD_CSDVER_1_0 0 |
| 184 | #define MMC_CSD_CSDVER_1_1 1 |
| 185 | #define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */ |
| 186 | #define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ |
| 187 | #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) |
| 188 | #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ |
| 189 | #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ |
| 190 | #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ |
| 191 | #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ |
| 192 | #define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */ |
| 193 | #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) |
| 194 | #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4) |
| 195 | #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3) |
| 196 | #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) |
| 197 | #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) |
| 198 | #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) |
| 199 | #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) |
| 200 | #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) |
| 201 | #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) |
| 202 | #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ |
| 203 | (MMC_CSD_C_SIZE_MULT((resp))+2)) |
| 204 | #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) |
| 205 | #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) |
| 206 | #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) |
| 207 | |
| 208 | /* MMC v1 R2 response (CID) */ |
| 209 | #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) |
| 210 | #define MMC_CID_PNM_V1_CPY(resp, pnm) \ |
| 211 | do { \ |
| 212 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ |
| 213 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ |
| 214 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ |
| 215 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ |
| 216 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ |
| 217 | (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ |
| 218 | (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ |
| 219 | (pnm)[7] = '\0'; \ |
| 220 | } while (/*CONSTCOND*/0) |
| 221 | #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) |
| 222 | #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) |
| 223 | #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) |
| 224 | |
| 225 | /* MMC v2 R2 response (CID) */ |
| 226 | #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) |
| 227 | #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) |
| 228 | #define MMC_CID_PNM_V2_CPY(resp, pnm) \ |
| 229 | do { \ |
| 230 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ |
| 231 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ |
| 232 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ |
| 233 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ |
| 234 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ |
| 235 | (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ |
| 236 | (pnm)[6] = '\0'; \ |
| 237 | } while (/*CONSTCOND*/0) |
| 238 | #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) |
| 239 | |
| 240 | /* SD R2 response (CSD) */ |
| 241 | #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) |
| 242 | #define SD_CSD_CSDVER_1_0 0 |
| 243 | #define SD_CSD_CSDVER_2_0 1 |
| 244 | #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) |
| 245 | #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) |
| 246 | #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4) |
| 247 | #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3) |
| 248 | #define SD_CSD_TAAC_1_5_MSEC 0x26 |
| 249 | #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) |
| 250 | #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) |
| 251 | #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) |
| 252 | #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) |
| 253 | #define SD_CSD_SPEED_25_MHZ 0x32 |
| 254 | #define SD_CSD_SPEED_50_MHZ 0x5a |
| 255 | #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) |
| 256 | #define SD_CSD_CCC_BASIC (1 << 0) /* basic */ |
| 257 | #define SD_CSD_CCC_BR (1 << 2) /* block read */ |
| 258 | #define SD_CSD_CCC_BW (1 << 4) /* block write */ |
| 259 | #define SD_CSD_CCC_ERACE (1 << 5) /* erase */ |
| 260 | #define SD_CSD_CCC_WP (1 << 6) /* write protection */ |
| 261 | #define SD_CSD_CCC_LC (1 << 7) /* lock card */ |
| 262 | #define SD_CSD_CCC_AS (1 << 8) /*application specific*/ |
| 263 | #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ |
| 264 | #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ |
| 265 | #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) |
| 266 | #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) |
| 267 | #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) |
| 268 | #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) |
| 269 | #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) |
| 270 | #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) |
| 271 | #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ |
| 272 | (SD_CSD_C_SIZE_MULT((resp))+2)) |
| 273 | #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) |
| 274 | #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) |
| 275 | #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) |
| 276 | #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) |
| 277 | #define SD_CSD_VDD_RW_CURR_100mA 0x7 |
| 278 | #define SD_CSD_VDD_RW_CURR_80mA 0x6 |
| 279 | #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) |
| 280 | #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) |
| 281 | #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ |
| 282 | #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) |
| 283 | #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) |
| 284 | #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ |
| 285 | #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ |
| 286 | #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) |
| 287 | #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) |
| 288 | #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) |
| 289 | #define SD_CSD_RW_BL_LEN_2G 0xa |
| 290 | #define SD_CSD_RW_BL_LEN_1G 0x9 |
| 291 | #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) |
| 292 | #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) |
| 293 | #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) |
| 294 | #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) |
| 295 | #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) |
| 296 | #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) |
| 297 | |
| 298 | /* SD R2 response (CID) */ |
| 299 | #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) |
| 300 | #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) |
| 301 | #define SD_CID_PNM_CPY(resp, pnm) \ |
| 302 | do { \ |
| 303 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ |
| 304 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ |
| 305 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ |
| 306 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ |
| 307 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ |
| 308 | (pnm)[5] = '\0'; \ |
| 309 | } while (/*CONSTCOND*/0) |
| 310 | #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) |
| 311 | #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) |
| 312 | #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) |
| 313 | |
| 314 | /* SCR (SD Configuration Register) */ |
| 315 | #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) |
| 316 | #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ |
| 317 | #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) |
| 318 | #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ |
| 319 | #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ |
| 320 | #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ |
| 321 | #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) |
| 322 | #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) |
| 323 | #define SCR_SD_SECURITY_NONE 0 /* no security */ |
| 324 | #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ |
| 325 | #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ |
| 326 | #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) |
| 327 | #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ |
| 328 | #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ |
| 329 | #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) |
| 330 | #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) |
| 331 | #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9) |
| 332 | #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) |
| 333 | #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) |
| 334 | #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) |
| 335 | |
| 336 | /* Status of Switch Function */ |
| 337 | #define SFUNC_STATUS_GROUP(status, group) \ |
| 338 | (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16)) |
| 339 | |
| 340 | #define SD_ACCESS_MODE_SDR12 0 |
| 341 | #define SD_ACCESS_MODE_SDR25 1 |
| 342 | #define SD_ACCESS_MODE_SDR50 2 |
| 343 | #define SD_ACCESS_MODE_SDR104 3 |
| 344 | #define SD_ACCESS_MODE_DDR50 4 |
| 345 | |
| 346 | /* This assumes the response fields are in host byte order in 32-bit units. */ |
| 347 | #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) |
| 348 | static inline uint32_t |
| 349 | __bitfield(const uint32_t *src, size_t start, size_t len) |
| 350 | { |
| 351 | if (start + len > 512 || len == 0 || len > 32) |
| 352 | return 0; |
| 353 | |
| 354 | src += start / 32; |
| 355 | start %= 32; |
| 356 | |
| 357 | uint32_t dst = src[0] >> start; |
| 358 | |
| 359 | if (__predict_false((start + len - 1) / 32 != start / 32)) { |
| 360 | dst |= src[1] << (32 - start); |
| 361 | } |
| 362 | |
| 363 | return dst & (__BIT(len) - 1); |
| 364 | } |
| 365 | |
| 366 | #endif /* _SDMMCREG_H_ */ |
| 367 | |