| 1 | /* |
| 2 | * Copyright © 2011-2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * This file implements HW context support. On gen5+ a HW context consists of an |
| 30 | * opaque GPU object which is referenced at times of context saves and restores. |
| 31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
| 32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
| 33 | * something like a context does exist for the media ring, the code only |
| 34 | * supports contexts for the render ring. |
| 35 | * |
| 36 | * In software, there is a distinction between contexts created by the user, |
| 37 | * and the default HW context. The default HW context is used by GPU clients |
| 38 | * that do not request setup of their own hardware context. The default |
| 39 | * context's state is never restored to help prevent programming errors. This |
| 40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
| 41 | * The default context only exists to give the GPU some offset to load as the |
| 42 | * current to invoke a save of the context we actually care about. In fact, the |
| 43 | * code could likely be constructed, albeit in a more complicated fashion, to |
| 44 | * never use the default context, though that limits the driver's ability to |
| 45 | * swap out, and/or destroy other contexts. |
| 46 | * |
| 47 | * All other contexts are created as a request by the GPU client. These contexts |
| 48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
| 49 | * potentially query certain state) at any time. The kernel driver makes |
| 50 | * certain that the appropriate commands are inserted. |
| 51 | * |
| 52 | * The context life cycle is semi-complicated in that context BOs may live |
| 53 | * longer than the context itself because of the way the hardware, and object |
| 54 | * tracking works. Below is a very crude representation of the state machine |
| 55 | * describing the context life. |
| 56 | * refcount pincount active |
| 57 | * S0: initial state 0 0 0 |
| 58 | * S1: context created 1 0 0 |
| 59 | * S2: context is currently running 2 1 X |
| 60 | * S3: GPU referenced, but not current 2 0 1 |
| 61 | * S4: context is current, but destroyed 1 1 0 |
| 62 | * S5: like S3, but destroyed 1 0 1 |
| 63 | * |
| 64 | * The most common (but not all) transitions: |
| 65 | * S0->S1: client creates a context |
| 66 | * S1->S2: client submits execbuf with context |
| 67 | * S2->S3: other clients submits execbuf with context |
| 68 | * S3->S1: context object was retired |
| 69 | * S3->S2: clients submits another execbuf |
| 70 | * S2->S4: context destroy called with current context |
| 71 | * S3->S5->S0: destroy path |
| 72 | * S4->S5->S0: destroy path on current context |
| 73 | * |
| 74 | * There are two confusing terms used above: |
| 75 | * The "current context" means the context which is currently running on the |
| 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
| 77 | * offset of the BO. The GPU is not actively referencing the data at this |
| 78 | * offset, but it will on the next context switch. The only way to avoid this |
| 79 | * is to do a GPU reset. |
| 80 | * |
| 81 | * An "active context' is one which was previously the "current context" and is |
| 82 | * on the active list waiting for the next context switch to occur. Until this |
| 83 | * happens, the object must remain at the same gtt offset. It is therefore |
| 84 | * possible to destroy a context, but it is still active. |
| 85 | * |
| 86 | */ |
| 87 | |
| 88 | #include <linux/err.h> |
| 89 | #include <drm/drmP.h> |
| 90 | #include <drm/i915_drm.h> |
| 91 | #include "i915_drv.h" |
| 92 | |
| 93 | /* This is a HW constraint. The value below is the largest known requirement |
| 94 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
| 95 | * part. It should be safe to decrease this, but it's more future proof as is. |
| 96 | */ |
| 97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
| 98 | #define GEN7_CONTEXT_ALIGN 4096 |
| 99 | |
| 100 | static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
| 101 | { |
| 102 | struct drm_device *dev = ppgtt->base.dev; |
| 103 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 104 | struct i915_address_space *vm = &ppgtt->base; |
| 105 | |
| 106 | if (ppgtt == dev_priv->mm.aliasing_ppgtt || |
| 107 | (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) { |
| 108 | ppgtt->base.cleanup(&ppgtt->base); |
| 109 | return; |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Make sure vmas are unbound before we take down the drm_mm |
| 114 | * |
| 115 | * FIXME: Proper refcounting should take care of this, this shouldn't be |
| 116 | * needed at all. |
| 117 | */ |
| 118 | if (!list_empty(&vm->active_list)) { |
| 119 | struct i915_vma *vma; |
| 120 | |
| 121 | list_for_each_entry(vma, &vm->active_list, mm_list) |
| 122 | if (WARN_ON(list_empty(&vma->vma_link) || |
| 123 | list_is_singular(&vma->vma_link))) |
| 124 | break; |
| 125 | |
| 126 | i915_gem_evict_vm(&ppgtt->base, true); |
| 127 | } else { |
| 128 | i915_gem_retire_requests(dev); |
| 129 | i915_gem_evict_vm(&ppgtt->base, false); |
| 130 | } |
| 131 | |
| 132 | ppgtt->base.cleanup(&ppgtt->base); |
| 133 | } |
| 134 | |
| 135 | static void ppgtt_release(struct kref *kref) |
| 136 | { |
| 137 | struct i915_hw_ppgtt *ppgtt = |
| 138 | container_of(kref, struct i915_hw_ppgtt, ref); |
| 139 | |
| 140 | do_ppgtt_cleanup(ppgtt); |
| 141 | kfree(ppgtt); |
| 142 | } |
| 143 | |
| 144 | static size_t get_context_alignment(struct drm_device *dev) |
| 145 | { |
| 146 | if (IS_GEN6(dev)) |
| 147 | return GEN6_CONTEXT_ALIGN; |
| 148 | |
| 149 | return GEN7_CONTEXT_ALIGN; |
| 150 | } |
| 151 | |
| 152 | static int get_context_size(struct drm_device *dev) |
| 153 | { |
| 154 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 155 | int ret; |
| 156 | u32 reg; |
| 157 | |
| 158 | switch (INTEL_INFO(dev)->gen) { |
| 159 | case 6: |
| 160 | reg = I915_READ(CXT_SIZE); |
| 161 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
| 162 | break; |
| 163 | case 7: |
| 164 | reg = I915_READ(GEN7_CXT_SIZE); |
| 165 | if (IS_HASWELL(dev)) |
| 166 | ret = HSW_CXT_TOTAL_SIZE; |
| 167 | else |
| 168 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
| 169 | break; |
| 170 | case 8: |
| 171 | ret = GEN8_CXT_TOTAL_SIZE; |
| 172 | break; |
| 173 | default: |
| 174 | BUG(); |
| 175 | } |
| 176 | |
| 177 | return ret; |
| 178 | } |
| 179 | |
| 180 | void i915_gem_context_free(struct kref *ctx_ref) |
| 181 | { |
| 182 | struct i915_hw_context *ctx = container_of(ctx_ref, |
| 183 | typeof(*ctx), ref); |
| 184 | struct i915_hw_ppgtt *ppgtt = NULL; |
| 185 | |
| 186 | if (ctx->obj) { |
| 187 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ |
| 188 | if (USES_PPGTT(ctx->obj->base.dev)) |
| 189 | ppgtt = ctx_to_ppgtt(ctx); |
| 190 | |
| 191 | /* XXX: Free up the object before tearing down the address space, in |
| 192 | * case we're bound in the PPGTT */ |
| 193 | drm_gem_object_unreference(&ctx->obj->base); |
| 194 | } |
| 195 | |
| 196 | if (ppgtt) |
| 197 | kref_put(&ppgtt->ref, ppgtt_release); |
| 198 | list_del(&ctx->link); |
| 199 | kfree(ctx); |
| 200 | } |
| 201 | |
| 202 | static struct i915_hw_ppgtt * |
| 203 | create_vm_for_ctx(struct drm_device *dev, struct i915_hw_context *ctx) |
| 204 | { |
| 205 | struct i915_hw_ppgtt *ppgtt; |
| 206 | int ret; |
| 207 | |
| 208 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 209 | if (!ppgtt) |
| 210 | return ERR_PTR(-ENOMEM); |
| 211 | |
| 212 | ret = i915_gem_init_ppgtt(dev, ppgtt); |
| 213 | if (ret) { |
| 214 | kfree(ppgtt); |
| 215 | return ERR_PTR(ret); |
| 216 | } |
| 217 | |
| 218 | ppgtt->ctx = ctx; |
| 219 | return ppgtt; |
| 220 | } |
| 221 | |
| 222 | static struct i915_hw_context * |
| 223 | __create_hw_context(struct drm_device *dev, |
| 224 | struct drm_i915_file_private *file_priv) |
| 225 | { |
| 226 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 227 | struct i915_hw_context *ctx; |
| 228 | int ret; |
| 229 | |
| 230 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
| 231 | if (ctx == NULL) |
| 232 | return ERR_PTR(-ENOMEM); |
| 233 | |
| 234 | kref_init(&ctx->ref); |
| 235 | list_add_tail(&ctx->link, &dev_priv->context_list); |
| 236 | |
| 237 | if (dev_priv->hw_context_size) { |
| 238 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
| 239 | if (ctx->obj == NULL) { |
| 240 | ret = -ENOMEM; |
| 241 | goto err_out; |
| 242 | } |
| 243 | |
| 244 | if (INTEL_INFO(dev)->gen >= 7) { |
| 245 | ret = i915_gem_object_set_cache_level(ctx->obj, |
| 246 | I915_CACHE_L3_LLC); |
| 247 | /* Failure shouldn't ever happen this early */ |
| 248 | if (WARN_ON(ret)) |
| 249 | goto err_out; |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | /* Default context will never have a file_priv */ |
| 254 | if (file_priv != NULL) { |
| 255 | idr_preload(GFP_KERNEL); |
| 256 | ret = idr_alloc(&file_priv->context_idr, ctx, |
| 257 | DEFAULT_CONTEXT_ID, 0, GFP_KERNEL); |
| 258 | idr_preload_end(); |
| 259 | if (ret < 0) |
| 260 | goto err_out; |
| 261 | } else |
| 262 | ret = DEFAULT_CONTEXT_ID; |
| 263 | |
| 264 | ctx->file_priv = file_priv; |
| 265 | ctx->id = ret; |
| 266 | /* NB: Mark all slices as needing a remap so that when the context first |
| 267 | * loads it will restore whatever remap state already exists. If there |
| 268 | * is no remap info, it will be a NOP. */ |
| 269 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; |
| 270 | |
| 271 | return ctx; |
| 272 | |
| 273 | err_out: |
| 274 | i915_gem_context_unreference(ctx); |
| 275 | return ERR_PTR(ret); |
| 276 | } |
| 277 | |
| 278 | /** |
| 279 | * The default context needs to exist per ring that uses contexts. It stores the |
| 280 | * context state of the GPU for applications that don't utilize HW contexts, as |
| 281 | * well as an idle case. |
| 282 | */ |
| 283 | static struct i915_hw_context * |
| 284 | i915_gem_create_context(struct drm_device *dev, |
| 285 | struct drm_i915_file_private *file_priv, |
| 286 | bool create_vm) |
| 287 | { |
| 288 | const bool is_global_default_ctx = file_priv == NULL; |
| 289 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 290 | struct i915_hw_context *ctx; |
| 291 | int ret = 0; |
| 292 | |
| 293 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 294 | |
| 295 | ctx = __create_hw_context(dev, file_priv); |
| 296 | if (IS_ERR(ctx)) |
| 297 | return ctx; |
| 298 | |
| 299 | if (is_global_default_ctx && ctx->obj) { |
| 300 | /* We may need to do things with the shrinker which |
| 301 | * require us to immediately switch back to the default |
| 302 | * context. This can cause a problem as pinning the |
| 303 | * default context also requires GTT space which may not |
| 304 | * be available. To avoid this we always pin the default |
| 305 | * context. |
| 306 | */ |
| 307 | ret = i915_gem_obj_ggtt_pin(ctx->obj, |
| 308 | get_context_alignment(dev), 0); |
| 309 | if (ret) { |
| 310 | DRM_DEBUG_DRIVER("Couldn't pin %d\n" , ret); |
| 311 | goto err_destroy; |
| 312 | } |
| 313 | } |
| 314 | |
| 315 | if (create_vm) { |
| 316 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); |
| 317 | |
| 318 | if (IS_ERR_OR_NULL(ppgtt)) { |
| 319 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n" , |
| 320 | PTR_ERR(ppgtt)); |
| 321 | ret = PTR_ERR(ppgtt); |
| 322 | goto err_unpin; |
| 323 | } else |
| 324 | ctx->vm = &ppgtt->base; |
| 325 | |
| 326 | /* This case is reserved for the global default context and |
| 327 | * should only happen once. */ |
| 328 | if (is_global_default_ctx) { |
| 329 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { |
| 330 | ret = -EEXIST; |
| 331 | goto err_unpin; |
| 332 | } |
| 333 | |
| 334 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
| 335 | } |
| 336 | } else if (USES_PPGTT(dev)) { |
| 337 | /* For platforms which only have aliasing PPGTT, we fake the |
| 338 | * address space and refcounting. */ |
| 339 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; |
| 340 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); |
| 341 | } else |
| 342 | ctx->vm = &dev_priv->gtt.base; |
| 343 | |
| 344 | return ctx; |
| 345 | |
| 346 | err_unpin: |
| 347 | if (is_global_default_ctx && ctx->obj) |
| 348 | i915_gem_object_ggtt_unpin(ctx->obj); |
| 349 | err_destroy: |
| 350 | i915_gem_context_unreference(ctx); |
| 351 | return ERR_PTR(ret); |
| 352 | } |
| 353 | |
| 354 | void i915_gem_context_reset(struct drm_device *dev) |
| 355 | { |
| 356 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 357 | int i; |
| 358 | |
| 359 | /* Prevent the hardware from restoring the last context (which hung) on |
| 360 | * the next switch */ |
| 361 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 362 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 363 | struct i915_hw_context *dctx = ring->default_context; |
| 364 | |
| 365 | /* Do a fake switch to the default context */ |
| 366 | if (ring->last_context == dctx) |
| 367 | continue; |
| 368 | |
| 369 | if (!ring->last_context) |
| 370 | continue; |
| 371 | |
| 372 | if (dctx->obj && i == RCS) { |
| 373 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, |
| 374 | get_context_alignment(dev), 0)); |
| 375 | /* Fake a finish/inactive */ |
| 376 | dctx->obj->base.write_domain = 0; |
| 377 | dctx->obj->active = 0; |
| 378 | } |
| 379 | |
| 380 | i915_gem_context_unreference(ring->last_context); |
| 381 | i915_gem_context_reference(dctx); |
| 382 | ring->last_context = dctx; |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | int i915_gem_context_init(struct drm_device *dev) |
| 387 | { |
| 388 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 389 | struct i915_hw_context *ctx; |
| 390 | int i; |
| 391 | |
| 392 | /* Init should only be called once per module load. Eventually the |
| 393 | * restriction on the context_disabled check can be loosened. */ |
| 394 | if (WARN_ON(dev_priv->ring[RCS].default_context)) |
| 395 | return 0; |
| 396 | |
| 397 | if (HAS_HW_CONTEXTS(dev)) { |
| 398 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
| 399 | if (dev_priv->hw_context_size > (1<<20)) { |
| 400 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n" , |
| 401 | dev_priv->hw_context_size); |
| 402 | dev_priv->hw_context_size = 0; |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev)); |
| 407 | if (IS_ERR(ctx)) { |
| 408 | DRM_ERROR("Failed to create default global context (error %ld)\n" , |
| 409 | PTR_ERR(ctx)); |
| 410 | return PTR_ERR(ctx); |
| 411 | } |
| 412 | |
| 413 | /* NB: RCS will hold a ref for all rings */ |
| 414 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 415 | dev_priv->ring[i].default_context = ctx; |
| 416 | |
| 417 | DRM_DEBUG_DRIVER("%s context support initialized\n" , dev_priv->hw_context_size ? "HW" : "fake" ); |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | void i915_gem_context_fini(struct drm_device *dev) |
| 422 | { |
| 423 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 424 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
| 425 | int i; |
| 426 | |
| 427 | if (dctx->obj) { |
| 428 | /* The only known way to stop the gpu from accessing the hw context is |
| 429 | * to reset it. Do this as the very last operation to avoid confusing |
| 430 | * other code, leading to spurious errors. */ |
| 431 | intel_gpu_reset(dev); |
| 432 | |
| 433 | /* When default context is created and switched to, base object refcount |
| 434 | * will be 2 (+1 from object creation and +1 from do_switch()). |
| 435 | * i915_gem_context_fini() will be called after gpu_idle() has switched |
| 436 | * to default context. So we need to unreference the base object once |
| 437 | * to offset the do_switch part, so that i915_gem_context_unreference() |
| 438 | * can then free the base object correctly. */ |
| 439 | WARN_ON(!dev_priv->ring[RCS].last_context); |
| 440 | if (dev_priv->ring[RCS].last_context == dctx) { |
| 441 | /* Fake switch to NULL context */ |
| 442 | WARN_ON(dctx->obj->active); |
| 443 | i915_gem_object_ggtt_unpin(dctx->obj); |
| 444 | i915_gem_context_unreference(dctx); |
| 445 | dev_priv->ring[RCS].last_context = NULL; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 450 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 451 | |
| 452 | if (ring->last_context) |
| 453 | i915_gem_context_unreference(ring->last_context); |
| 454 | |
| 455 | ring->default_context = NULL; |
| 456 | ring->last_context = NULL; |
| 457 | } |
| 458 | |
| 459 | if (dctx->obj) |
| 460 | i915_gem_object_ggtt_unpin(dctx->obj); |
| 461 | i915_gem_context_unreference(dctx); |
| 462 | } |
| 463 | |
| 464 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
| 465 | { |
| 466 | struct intel_ring_buffer *ring; |
| 467 | int ret, i; |
| 468 | |
| 469 | /* This is the only place the aliasing PPGTT gets enabled, which means |
| 470 | * it has to happen before we bail on reset */ |
| 471 | if (dev_priv->mm.aliasing_ppgtt) { |
| 472 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 473 | ppgtt->enable(ppgtt); |
| 474 | } |
| 475 | |
| 476 | /* FIXME: We should make this work, even in reset */ |
| 477 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
| 478 | return 0; |
| 479 | |
| 480 | BUG_ON(!dev_priv->ring[RCS].default_context); |
| 481 | |
| 482 | for_each_ring(ring, dev_priv, i) { |
| 483 | ret = i915_switch_context(ring, ring->default_context); |
| 484 | if (ret) |
| 485 | return ret; |
| 486 | } |
| 487 | |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | static int context_idr_cleanup(int id, void *p, void *data) |
| 492 | { |
| 493 | struct i915_hw_context *ctx = p; |
| 494 | |
| 495 | /* Ignore the default context because close will handle it */ |
| 496 | if (i915_gem_context_is_default(ctx)) |
| 497 | return 0; |
| 498 | |
| 499 | i915_gem_context_unreference(ctx); |
| 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
| 504 | { |
| 505 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 506 | |
| 507 | idr_init(&file_priv->context_idr); |
| 508 | |
| 509 | mutex_lock(&dev->struct_mutex); |
| 510 | file_priv->private_default_ctx = |
| 511 | i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
| 512 | mutex_unlock(&dev->struct_mutex); |
| 513 | |
| 514 | if (IS_ERR(file_priv->private_default_ctx)) { |
| 515 | idr_destroy(&file_priv->context_idr); |
| 516 | return PTR_ERR(file_priv->private_default_ctx); |
| 517 | } |
| 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
| 523 | { |
| 524 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 525 | |
| 526 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
| 527 | idr_destroy(&file_priv->context_idr); |
| 528 | |
| 529 | i915_gem_context_unreference(file_priv->private_default_ctx); |
| 530 | } |
| 531 | |
| 532 | struct i915_hw_context * |
| 533 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
| 534 | { |
| 535 | struct i915_hw_context *ctx; |
| 536 | |
| 537 | ctx = (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); |
| 538 | if (!ctx) |
| 539 | return ERR_PTR(-ENOENT); |
| 540 | |
| 541 | return ctx; |
| 542 | } |
| 543 | |
| 544 | static inline int |
| 545 | mi_set_context(struct intel_ring_buffer *ring, |
| 546 | struct i915_hw_context *new_context, |
| 547 | u32 hw_flags) |
| 548 | { |
| 549 | int ret; |
| 550 | |
| 551 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
| 552 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
| 553 | * explicitly, so we rely on the value at ring init, stored in |
| 554 | * itlb_before_ctx_switch. |
| 555 | */ |
| 556 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { |
| 557 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
| 558 | if (ret) |
| 559 | return ret; |
| 560 | } |
| 561 | |
| 562 | ret = intel_ring_begin(ring, 6); |
| 563 | if (ret) |
| 564 | return ret; |
| 565 | |
| 566 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */ |
| 567 | if (IS_GEN7(ring->dev)) |
| 568 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
| 569 | else |
| 570 | intel_ring_emit(ring, MI_NOOP); |
| 571 | |
| 572 | intel_ring_emit(ring, MI_NOOP); |
| 573 | intel_ring_emit(ring, MI_SET_CONTEXT); |
| 574 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
| 575 | MI_MM_SPACE_GTT | |
| 576 | MI_SAVE_EXT_STATE_EN | |
| 577 | MI_RESTORE_EXT_STATE_EN | |
| 578 | hw_flags); |
| 579 | /* |
| 580 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
| 581 | * WaMiSetContext_Hang:snb,ivb,vlv |
| 582 | */ |
| 583 | intel_ring_emit(ring, MI_NOOP); |
| 584 | |
| 585 | if (IS_GEN7(ring->dev)) |
| 586 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
| 587 | else |
| 588 | intel_ring_emit(ring, MI_NOOP); |
| 589 | |
| 590 | intel_ring_advance(ring); |
| 591 | |
| 592 | return ret; |
| 593 | } |
| 594 | |
| 595 | static int do_switch(struct intel_ring_buffer *ring, |
| 596 | struct i915_hw_context *to) |
| 597 | { |
| 598 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 599 | struct i915_hw_context *from = ring->last_context; |
| 600 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); |
| 601 | u32 hw_flags = 0; |
| 602 | int ret, i; |
| 603 | |
| 604 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
| 605 | BUG_ON(from->obj == NULL); |
| 606 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); |
| 607 | } |
| 608 | |
| 609 | if (from == to && from->last_ring == ring && !to->remap_slice) |
| 610 | return 0; |
| 611 | |
| 612 | /* Trying to pin first makes error handling easier. */ |
| 613 | if (ring == &dev_priv->ring[RCS]) { |
| 614 | ret = i915_gem_obj_ggtt_pin(to->obj, |
| 615 | get_context_alignment(ring->dev), 0); |
| 616 | if (ret) |
| 617 | return ret; |
| 618 | } |
| 619 | |
| 620 | /* |
| 621 | * Pin can switch back to the default context if we end up calling into |
| 622 | * evict_everything - as a last ditch gtt defrag effort that also |
| 623 | * switches to the default context. Hence we need to reload from here. |
| 624 | */ |
| 625 | from = ring->last_context; |
| 626 | |
| 627 | if (USES_FULL_PPGTT(ring->dev)) { |
| 628 | ret = ppgtt->switch_mm(ppgtt, ring, false); |
| 629 | if (ret) |
| 630 | goto unpin_out; |
| 631 | } |
| 632 | |
| 633 | if (ring != &dev_priv->ring[RCS]) { |
| 634 | if (from) |
| 635 | i915_gem_context_unreference(from); |
| 636 | goto done; |
| 637 | } |
| 638 | |
| 639 | /* |
| 640 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
| 641 | * that thanks to write = false in this call and us not setting any gpu |
| 642 | * write domains when putting a context object onto the active list |
| 643 | * (when switching away from it), this won't block. |
| 644 | * |
| 645 | * XXX: We need a real interface to do this instead of trickery. |
| 646 | */ |
| 647 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); |
| 648 | if (ret) |
| 649 | goto unpin_out; |
| 650 | |
| 651 | if (!to->obj->has_global_gtt_mapping) { |
| 652 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, |
| 653 | &dev_priv->gtt.base); |
| 654 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); |
| 655 | } |
| 656 | |
| 657 | if (!to->is_initialized || i915_gem_context_is_default(to)) |
| 658 | hw_flags |= MI_RESTORE_INHIBIT; |
| 659 | |
| 660 | ret = mi_set_context(ring, to, hw_flags); |
| 661 | if (ret) |
| 662 | goto unpin_out; |
| 663 | |
| 664 | for (i = 0; i < MAX_L3_SLICES; i++) { |
| 665 | if (!(to->remap_slice & (1<<i))) |
| 666 | continue; |
| 667 | |
| 668 | ret = i915_gem_l3_remap(ring, i); |
| 669 | /* If it failed, try again next round */ |
| 670 | if (ret) |
| 671 | DRM_DEBUG_DRIVER("L3 remapping failed\n" ); |
| 672 | else |
| 673 | to->remap_slice &= ~(1<<i); |
| 674 | } |
| 675 | |
| 676 | /* The backing object for the context is done after switching to the |
| 677 | * *next* context. Therefore we cannot retire the previous context until |
| 678 | * the next context has already started running. In fact, the below code |
| 679 | * is a bit suboptimal because the retiring can occur simply after the |
| 680 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
| 681 | */ |
| 682 | if (from != NULL) { |
| 683 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
| 684 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
| 685 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
| 686 | * whole damn pipeline, we don't need to explicitly mark the |
| 687 | * object dirty. The only exception is that the context must be |
| 688 | * correct in case the object gets swapped out. Ideally we'd be |
| 689 | * able to defer doing this until we know the object would be |
| 690 | * swapped, but there is no way to do that yet. |
| 691 | */ |
| 692 | from->obj->dirty = 1; |
| 693 | BUG_ON(from->obj->ring != ring); |
| 694 | |
| 695 | /* obj is kept alive until the next request by its active ref */ |
| 696 | i915_gem_object_ggtt_unpin(from->obj); |
| 697 | i915_gem_context_unreference(from); |
| 698 | } |
| 699 | |
| 700 | to->is_initialized = true; |
| 701 | |
| 702 | done: |
| 703 | i915_gem_context_reference(to); |
| 704 | ring->last_context = to; |
| 705 | to->last_ring = ring; |
| 706 | |
| 707 | return 0; |
| 708 | |
| 709 | unpin_out: |
| 710 | if (ring->id == RCS) |
| 711 | i915_gem_object_ggtt_unpin(to->obj); |
| 712 | return ret; |
| 713 | } |
| 714 | |
| 715 | /** |
| 716 | * i915_switch_context() - perform a GPU context switch. |
| 717 | * @ring: ring for which we'll execute the context switch |
| 718 | * @to: the context to switch to |
| 719 | * |
| 720 | * The context life cycle is simple. The context refcount is incremented and |
| 721 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
| 722 | * it will have a refoucnt > 1. This allows us to destroy the context abstract |
| 723 | * object while letting the normal object tracking destroy the backing BO. |
| 724 | */ |
| 725 | int i915_switch_context(struct intel_ring_buffer *ring, |
| 726 | struct i915_hw_context *to) |
| 727 | { |
| 728 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 729 | |
| 730 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
| 731 | |
| 732 | if (to->obj == NULL) { /* We have the fake context */ |
| 733 | if (to != ring->last_context) { |
| 734 | i915_gem_context_reference(to); |
| 735 | if (ring->last_context) |
| 736 | i915_gem_context_unreference(ring->last_context); |
| 737 | ring->last_context = to; |
| 738 | } |
| 739 | return 0; |
| 740 | } |
| 741 | |
| 742 | return do_switch(ring, to); |
| 743 | } |
| 744 | |
| 745 | static bool hw_context_enabled(struct drm_device *dev) |
| 746 | { |
| 747 | return to_i915(dev)->hw_context_size; |
| 748 | } |
| 749 | |
| 750 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 751 | struct drm_file *file) |
| 752 | { |
| 753 | struct drm_i915_gem_context_create *args = data; |
| 754 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 755 | struct i915_hw_context *ctx; |
| 756 | int ret; |
| 757 | |
| 758 | if (!hw_context_enabled(dev)) |
| 759 | return -ENODEV; |
| 760 | |
| 761 | ret = i915_mutex_lock_interruptible(dev); |
| 762 | if (ret) |
| 763 | return ret; |
| 764 | |
| 765 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
| 766 | mutex_unlock(&dev->struct_mutex); |
| 767 | if (IS_ERR(ctx)) |
| 768 | return PTR_ERR(ctx); |
| 769 | |
| 770 | args->ctx_id = ctx->id; |
| 771 | DRM_DEBUG_DRIVER("HW context %d created\n" , args->ctx_id); |
| 772 | |
| 773 | return 0; |
| 774 | } |
| 775 | |
| 776 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 777 | struct drm_file *file) |
| 778 | { |
| 779 | struct drm_i915_gem_context_destroy *args = data; |
| 780 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 781 | struct i915_hw_context *ctx; |
| 782 | int ret; |
| 783 | |
| 784 | if (args->ctx_id == DEFAULT_CONTEXT_ID) |
| 785 | return -ENOENT; |
| 786 | |
| 787 | ret = i915_mutex_lock_interruptible(dev); |
| 788 | if (ret) |
| 789 | return ret; |
| 790 | |
| 791 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
| 792 | if (IS_ERR(ctx)) { |
| 793 | mutex_unlock(&dev->struct_mutex); |
| 794 | return PTR_ERR(ctx); |
| 795 | } |
| 796 | |
| 797 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
| 798 | i915_gem_context_unreference(ctx); |
| 799 | mutex_unlock(&dev->struct_mutex); |
| 800 | |
| 801 | DRM_DEBUG_DRIVER("HW context %d destroyed\n" , args->ctx_id); |
| 802 | return 0; |
| 803 | } |
| 804 | |