| 1 | /* $NetBSD: atw.c,v 1.160 2016/06/10 13:27:13 ozaki-r Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. |
| 34 | */ |
| 35 | |
| 36 | #include <sys/cdefs.h> |
| 37 | __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.160 2016/06/10 13:27:13 ozaki-r Exp $" ); |
| 38 | |
| 39 | |
| 40 | #include <sys/param.h> |
| 41 | #include <sys/systm.h> |
| 42 | #include <sys/callout.h> |
| 43 | #include <sys/mbuf.h> |
| 44 | #include <sys/malloc.h> |
| 45 | #include <sys/kernel.h> |
| 46 | #include <sys/socket.h> |
| 47 | #include <sys/ioctl.h> |
| 48 | #include <sys/errno.h> |
| 49 | #include <sys/device.h> |
| 50 | #include <sys/kauth.h> |
| 51 | #include <sys/time.h> |
| 52 | #include <sys/proc.h> |
| 53 | #include <lib/libkern/libkern.h> |
| 54 | |
| 55 | #include <machine/endian.h> |
| 56 | |
| 57 | #include <net/if.h> |
| 58 | #include <net/if_dl.h> |
| 59 | #include <net/if_media.h> |
| 60 | #include <net/if_ether.h> |
| 61 | |
| 62 | #include <net80211/ieee80211_netbsd.h> |
| 63 | #include <net80211/ieee80211_var.h> |
| 64 | #include <net80211/ieee80211_radiotap.h> |
| 65 | |
| 66 | #include <net/bpf.h> |
| 67 | |
| 68 | #include <sys/bus.h> |
| 69 | #include <sys/intr.h> |
| 70 | |
| 71 | #include <dev/ic/atwreg.h> |
| 72 | #include <dev/ic/rf3000reg.h> |
| 73 | #include <dev/ic/si4136reg.h> |
| 74 | #include <dev/ic/atwvar.h> |
| 75 | #include <dev/ic/smc93cx6var.h> |
| 76 | |
| 77 | /* XXX TBD open questions |
| 78 | * |
| 79 | * |
| 80 | * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps |
| 81 | * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC |
| 82 | * handle this for me? |
| 83 | * |
| 84 | */ |
| 85 | /* device attachment |
| 86 | * |
| 87 | * print TOFS[012] |
| 88 | * |
| 89 | * device initialization |
| 90 | * |
| 91 | * clear ATW_FRCTL_MAXPSP to disable max power saving |
| 92 | * set ATW_TXBR_ALCUPDATE to enable ALC |
| 93 | * set TOFS[012]? (hope not) |
| 94 | * disable rx/tx |
| 95 | * set ATW_PAR_SWR (software reset) |
| 96 | * wait for ATW_PAR_SWR clear |
| 97 | * disable interrupts |
| 98 | * ack status register |
| 99 | * enable interrupts |
| 100 | * |
| 101 | * rx/tx initialization |
| 102 | * |
| 103 | * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST |
| 104 | * allocate and init descriptor rings |
| 105 | * write ATW_PAR_DSL (descriptor skip length) |
| 106 | * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB |
| 107 | * write ATW_NAR_SQ for one/both transmit descriptor rings |
| 108 | * write ATW_NAR_SQ for one/both transmit descriptor rings |
| 109 | * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST |
| 110 | * |
| 111 | * rx/tx end |
| 112 | * |
| 113 | * stop DMA |
| 114 | * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST |
| 115 | * flush tx w/ ATW_NAR_HF |
| 116 | * |
| 117 | * scan |
| 118 | * |
| 119 | * initialize rx/tx |
| 120 | * |
| 121 | * BSS join: (re)association response |
| 122 | * |
| 123 | * set ATW_FRCTL_AID |
| 124 | * |
| 125 | * optimizations ??? |
| 126 | * |
| 127 | */ |
| 128 | |
| 129 | #define ATW_REFSLAVE /* slavishly do what the reference driver does */ |
| 130 | |
| 131 | int atw_pseudo_milli = 1; |
| 132 | int atw_magic_delay1 = 100 * 1000; |
| 133 | int atw_magic_delay2 = 100 * 1000; |
| 134 | /* more magic multi-millisecond delays (units: microseconds) */ |
| 135 | int atw_nar_delay = 20 * 1000; |
| 136 | int atw_magic_delay4 = 10 * 1000; |
| 137 | int atw_rf_delay1 = 10 * 1000; |
| 138 | int atw_rf_delay2 = 5 * 1000; |
| 139 | int atw_plcphd_delay = 2 * 1000; |
| 140 | int atw_bbp_io_enable_delay = 20 * 1000; |
| 141 | int atw_bbp_io_disable_delay = 2 * 1000; |
| 142 | int atw_writewep_delay = 1000; |
| 143 | int atw_beacon_len_adjust = 4; |
| 144 | int atw_dwelltime = 200; |
| 145 | int atw_xindiv2 = 0; |
| 146 | |
| 147 | #ifdef ATW_DEBUG |
| 148 | int atw_debug = 0; |
| 149 | |
| 150 | #define ATW_DPRINTF(x) if (atw_debug > 0) printf x |
| 151 | #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x |
| 152 | #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x |
| 153 | #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x |
| 154 | #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) |
| 155 | #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) |
| 156 | |
| 157 | static void atw_dump_pkt(struct ifnet *, struct mbuf *); |
| 158 | static void atw_print_regs(struct atw_softc *, const char *); |
| 159 | |
| 160 | /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ |
| 161 | # ifdef ATW_BBPDEBUG |
| 162 | static void atw_rf3000_print(struct atw_softc *); |
| 163 | static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); |
| 164 | # endif /* ATW_BBPDEBUG */ |
| 165 | |
| 166 | # ifdef ATW_SYNDEBUG |
| 167 | static void atw_si4126_print(struct atw_softc *); |
| 168 | static int atw_si4126_read(struct atw_softc *, u_int, u_int *); |
| 169 | # endif /* ATW_SYNDEBUG */ |
| 170 | #define __atwdebugused /* empty */ |
| 171 | #else |
| 172 | #define ATW_DPRINTF(x) |
| 173 | #define ATW_DPRINTF2(x) |
| 174 | #define ATW_DPRINTF3(x) |
| 175 | #define DPRINTF(sc, x) /* nothing */ |
| 176 | #define DPRINTF2(sc, x) /* nothing */ |
| 177 | #define DPRINTF3(sc, x) /* nothing */ |
| 178 | #define __atwdebugused __unused |
| 179 | #endif |
| 180 | |
| 181 | /* ifnet methods */ |
| 182 | int atw_init(struct ifnet *); |
| 183 | int atw_ioctl(struct ifnet *, u_long, void *); |
| 184 | void atw_start(struct ifnet *); |
| 185 | void atw_stop(struct ifnet *, int); |
| 186 | void atw_watchdog(struct ifnet *); |
| 187 | |
| 188 | /* Device attachment */ |
| 189 | void atw_attach(struct atw_softc *); |
| 190 | int atw_detach(struct atw_softc *); |
| 191 | static void atw_evcnt_attach(struct atw_softc *); |
| 192 | static void atw_evcnt_detach(struct atw_softc *); |
| 193 | |
| 194 | /* Rx/Tx process */ |
| 195 | int atw_add_rxbuf(struct atw_softc *, int); |
| 196 | void atw_idle(struct atw_softc *, u_int32_t); |
| 197 | void atw_rxdrain(struct atw_softc *); |
| 198 | void atw_txdrain(struct atw_softc *); |
| 199 | |
| 200 | /* Device (de)activation and power state */ |
| 201 | void atw_reset(struct atw_softc *); |
| 202 | |
| 203 | /* Interrupt handlers */ |
| 204 | void atw_linkintr(struct atw_softc *, u_int32_t); |
| 205 | void atw_rxintr(struct atw_softc *); |
| 206 | void atw_txintr(struct atw_softc *, uint32_t); |
| 207 | |
| 208 | /* 802.11 state machine */ |
| 209 | static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); |
| 210 | static void atw_next_scan(void *); |
| 211 | static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, |
| 212 | struct ieee80211_node *, int, int, u_int32_t); |
| 213 | static int atw_tune(struct atw_softc *); |
| 214 | |
| 215 | /* Device initialization */ |
| 216 | static void atw_bbp_io_init(struct atw_softc *); |
| 217 | static void atw_cfp_init(struct atw_softc *); |
| 218 | static void atw_cmdr_init(struct atw_softc *); |
| 219 | static void atw_ifs_init(struct atw_softc *); |
| 220 | static void atw_nar_init(struct atw_softc *); |
| 221 | static void atw_response_times_init(struct atw_softc *); |
| 222 | static void atw_rf_reset(struct atw_softc *); |
| 223 | static void atw_test1_init(struct atw_softc *); |
| 224 | static void atw_tofs0_init(struct atw_softc *); |
| 225 | static void atw_tofs2_init(struct atw_softc *); |
| 226 | static void atw_txlmt_init(struct atw_softc *); |
| 227 | static void atw_wcsr_init(struct atw_softc *); |
| 228 | |
| 229 | /* Key management */ |
| 230 | static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); |
| 231 | static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, |
| 232 | const u_int8_t[IEEE80211_ADDR_LEN]); |
| 233 | static void atw_key_update_begin(struct ieee80211com *); |
| 234 | static void atw_key_update_end(struct ieee80211com *); |
| 235 | |
| 236 | /* RAM/ROM utilities */ |
| 237 | static void atw_clear_sram(struct atw_softc *); |
| 238 | static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); |
| 239 | static int atw_read_srom(struct atw_softc *); |
| 240 | |
| 241 | /* BSS setup */ |
| 242 | static void atw_predict_beacon(struct atw_softc *); |
| 243 | static void atw_start_beacon(struct atw_softc *, int); |
| 244 | static void atw_write_bssid(struct atw_softc *); |
| 245 | static void atw_write_ssid(struct atw_softc *); |
| 246 | static void atw_write_sup_rates(struct atw_softc *); |
| 247 | static void atw_write_wep(struct atw_softc *); |
| 248 | |
| 249 | /* Media */ |
| 250 | static int atw_media_change(struct ifnet *); |
| 251 | |
| 252 | static void atw_filter_setup(struct atw_softc *); |
| 253 | |
| 254 | /* 802.11 utilities */ |
| 255 | static uint64_t atw_get_tsft(struct atw_softc *); |
| 256 | static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, |
| 257 | uint32_t); |
| 258 | static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); |
| 259 | static void atw_node_free(struct ieee80211_node *); |
| 260 | |
| 261 | /* |
| 262 | * Tuner/transceiver/modem |
| 263 | */ |
| 264 | static void atw_bbp_io_enable(struct atw_softc *, int); |
| 265 | |
| 266 | /* RFMD RF3000 Baseband Processor */ |
| 267 | static int atw_rf3000_init(struct atw_softc *); |
| 268 | static int atw_rf3000_tune(struct atw_softc *, u_int); |
| 269 | static int atw_rf3000_write(struct atw_softc *, u_int, u_int); |
| 270 | |
| 271 | /* Silicon Laboratories Si4126 RF/IF Synthesizer */ |
| 272 | static void atw_si4126_tune(struct atw_softc *, u_int); |
| 273 | static void atw_si4126_write(struct atw_softc *, u_int, u_int); |
| 274 | |
| 275 | const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; |
| 276 | const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; |
| 277 | |
| 278 | const char *atw_tx_state[] = { |
| 279 | "STOPPED" , |
| 280 | "RUNNING - read descriptor" , |
| 281 | "RUNNING - transmitting" , |
| 282 | "RUNNING - filling fifo" , /* XXX */ |
| 283 | "SUSPENDED" , |
| 284 | "RUNNING -- write descriptor" , |
| 285 | "RUNNING -- write last descriptor" , |
| 286 | "RUNNING - fifo full" |
| 287 | }; |
| 288 | |
| 289 | const char *atw_rx_state[] = { |
| 290 | "STOPPED" , |
| 291 | "RUNNING - read descriptor" , |
| 292 | "RUNNING - check this packet, pre-fetch next" , |
| 293 | "RUNNING - wait for reception" , |
| 294 | "SUSPENDED" , |
| 295 | "RUNNING - write descriptor" , |
| 296 | "RUNNING - flush fifo" , |
| 297 | "RUNNING - fifo drain" |
| 298 | }; |
| 299 | |
| 300 | static inline int |
| 301 | is_running(struct ifnet *ifp) |
| 302 | { |
| 303 | return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); |
| 304 | } |
| 305 | |
| 306 | int |
| 307 | atw_activate(device_t self, enum devact act) |
| 308 | { |
| 309 | struct atw_softc *sc = device_private(self); |
| 310 | |
| 311 | switch (act) { |
| 312 | case DVACT_DEACTIVATE: |
| 313 | if_deactivate(&sc->sc_if); |
| 314 | return 0; |
| 315 | default: |
| 316 | return EOPNOTSUPP; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | bool |
| 321 | atw_suspend(device_t self, const pmf_qual_t *qual) |
| 322 | { |
| 323 | struct atw_softc *sc = device_private(self); |
| 324 | |
| 325 | atw_rxdrain(sc); |
| 326 | sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; |
| 327 | |
| 328 | return true; |
| 329 | } |
| 330 | |
| 331 | /* Returns -1 on failure. */ |
| 332 | static int |
| 333 | atw_read_srom(struct atw_softc *sc) |
| 334 | { |
| 335 | struct seeprom_descriptor sd; |
| 336 | uint32_t test0, fail_bits; |
| 337 | |
| 338 | (void)memset(&sd, 0, sizeof(sd)); |
| 339 | |
| 340 | test0 = ATW_READ(sc, ATW_TEST0); |
| 341 | |
| 342 | switch (sc->sc_rev) { |
| 343 | case ATW_REVISION_BA: |
| 344 | case ATW_REVISION_CA: |
| 345 | fail_bits = ATW_TEST0_EPNE; |
| 346 | break; |
| 347 | default: |
| 348 | fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; |
| 349 | break; |
| 350 | } |
| 351 | if ((test0 & fail_bits) != 0) { |
| 352 | aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n" ); |
| 353 | return -1; |
| 354 | } |
| 355 | |
| 356 | switch (test0 & ATW_TEST0_EPTYP_MASK) { |
| 357 | case ATW_TEST0_EPTYP_93c66: |
| 358 | ATW_DPRINTF(("%s: 93c66 SROM\n" , device_xname(sc->sc_dev))); |
| 359 | sc->sc_sromsz = 512; |
| 360 | sd.sd_chip = C56_66; |
| 361 | break; |
| 362 | case ATW_TEST0_EPTYP_93c46: |
| 363 | ATW_DPRINTF(("%s: 93c46 SROM\n" , device_xname(sc->sc_dev))); |
| 364 | sc->sc_sromsz = 128; |
| 365 | sd.sd_chip = C46; |
| 366 | break; |
| 367 | default: |
| 368 | printf("%s: unknown SROM type %" __PRIuBITS "\n" , |
| 369 | device_xname(sc->sc_dev), |
| 370 | __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); |
| 371 | return -1; |
| 372 | } |
| 373 | |
| 374 | sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); |
| 375 | |
| 376 | if (sc->sc_srom == NULL) { |
| 377 | aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n" ); |
| 378 | return -1; |
| 379 | } |
| 380 | |
| 381 | (void)memset(sc->sc_srom, 0, sc->sc_sromsz); |
| 382 | |
| 383 | /* ADM8211 has a single 32-bit register for controlling the |
| 384 | * 93cx6 SROM. Bit SRS enables the serial port. There is no |
| 385 | * "ready" bit. The ADM8211 input/output sense is the reverse |
| 386 | * of read_seeprom's. |
| 387 | */ |
| 388 | sd.sd_tag = sc->sc_st; |
| 389 | sd.sd_bsh = sc->sc_sh; |
| 390 | sd.sd_regsize = 4; |
| 391 | sd.sd_control_offset = ATW_SPR; |
| 392 | sd.sd_status_offset = ATW_SPR; |
| 393 | sd.sd_dataout_offset = ATW_SPR; |
| 394 | sd.sd_CK = ATW_SPR_SCLK; |
| 395 | sd.sd_CS = ATW_SPR_SCS; |
| 396 | sd.sd_DI = ATW_SPR_SDO; |
| 397 | sd.sd_DO = ATW_SPR_SDI; |
| 398 | sd.sd_MS = ATW_SPR_SRS; |
| 399 | sd.sd_RDY = 0; |
| 400 | |
| 401 | if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { |
| 402 | aprint_error_dev(sc->sc_dev, "could not read SROM\n" ); |
| 403 | free(sc->sc_srom, M_DEVBUF); |
| 404 | return -1; |
| 405 | } |
| 406 | #ifdef ATW_DEBUG |
| 407 | { |
| 408 | int i; |
| 409 | ATW_DPRINTF(("\nSerial EEPROM:\n\t" )); |
| 410 | for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { |
| 411 | if (((i % 8) == 0) && (i != 0)) { |
| 412 | ATW_DPRINTF(("\n\t" )); |
| 413 | } |
| 414 | ATW_DPRINTF((" 0x%x" , sc->sc_srom[i])); |
| 415 | } |
| 416 | ATW_DPRINTF(("\n" )); |
| 417 | } |
| 418 | #endif /* ATW_DEBUG */ |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | #ifdef ATW_DEBUG |
| 423 | static void |
| 424 | atw_print_regs(struct atw_softc *sc, const char *where) |
| 425 | { |
| 426 | #define PRINTREG(sc, reg) \ |
| 427 | ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ |
| 428 | device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) |
| 429 | |
| 430 | ATW_DPRINTF2(("%s: %s\n" , device_xname(sc->sc_dev), where)); |
| 431 | |
| 432 | PRINTREG(sc, ATW_PAR); |
| 433 | PRINTREG(sc, ATW_FRCTL); |
| 434 | PRINTREG(sc, ATW_TDR); |
| 435 | PRINTREG(sc, ATW_WTDP); |
| 436 | PRINTREG(sc, ATW_RDR); |
| 437 | PRINTREG(sc, ATW_WRDP); |
| 438 | PRINTREG(sc, ATW_RDB); |
| 439 | PRINTREG(sc, ATW_CSR3A); |
| 440 | PRINTREG(sc, ATW_TDBD); |
| 441 | PRINTREG(sc, ATW_TDBP); |
| 442 | PRINTREG(sc, ATW_STSR); |
| 443 | PRINTREG(sc, ATW_CSR5A); |
| 444 | PRINTREG(sc, ATW_NAR); |
| 445 | PRINTREG(sc, ATW_CSR6A); |
| 446 | PRINTREG(sc, ATW_IER); |
| 447 | PRINTREG(sc, ATW_CSR7A); |
| 448 | PRINTREG(sc, ATW_LPC); |
| 449 | PRINTREG(sc, ATW_TEST1); |
| 450 | PRINTREG(sc, ATW_SPR); |
| 451 | PRINTREG(sc, ATW_TEST0); |
| 452 | PRINTREG(sc, ATW_WCSR); |
| 453 | PRINTREG(sc, ATW_WPDR); |
| 454 | PRINTREG(sc, ATW_GPTMR); |
| 455 | PRINTREG(sc, ATW_GPIO); |
| 456 | PRINTREG(sc, ATW_BBPCTL); |
| 457 | PRINTREG(sc, ATW_SYNCTL); |
| 458 | PRINTREG(sc, ATW_PLCPHD); |
| 459 | PRINTREG(sc, ATW_MMIWADDR); |
| 460 | PRINTREG(sc, ATW_MMIRADDR1); |
| 461 | PRINTREG(sc, ATW_MMIRADDR2); |
| 462 | PRINTREG(sc, ATW_TXBR); |
| 463 | PRINTREG(sc, ATW_CSR15A); |
| 464 | PRINTREG(sc, ATW_ALCSTAT); |
| 465 | PRINTREG(sc, ATW_TOFS2); |
| 466 | PRINTREG(sc, ATW_CMDR); |
| 467 | PRINTREG(sc, ATW_PCIC); |
| 468 | PRINTREG(sc, ATW_PMCSR); |
| 469 | PRINTREG(sc, ATW_PAR0); |
| 470 | PRINTREG(sc, ATW_PAR1); |
| 471 | PRINTREG(sc, ATW_MAR0); |
| 472 | PRINTREG(sc, ATW_MAR1); |
| 473 | PRINTREG(sc, ATW_ATIMDA0); |
| 474 | PRINTREG(sc, ATW_ABDA1); |
| 475 | PRINTREG(sc, ATW_BSSID0); |
| 476 | PRINTREG(sc, ATW_TXLMT); |
| 477 | PRINTREG(sc, ATW_MIBCNT); |
| 478 | PRINTREG(sc, ATW_BCNT); |
| 479 | PRINTREG(sc, ATW_TSFTH); |
| 480 | PRINTREG(sc, ATW_TSC); |
| 481 | PRINTREG(sc, ATW_SYNRF); |
| 482 | PRINTREG(sc, ATW_BPLI); |
| 483 | PRINTREG(sc, ATW_CAP0); |
| 484 | PRINTREG(sc, ATW_CAP1); |
| 485 | PRINTREG(sc, ATW_RMD); |
| 486 | PRINTREG(sc, ATW_CFPP); |
| 487 | PRINTREG(sc, ATW_TOFS0); |
| 488 | PRINTREG(sc, ATW_TOFS1); |
| 489 | PRINTREG(sc, ATW_IFST); |
| 490 | PRINTREG(sc, ATW_RSPT); |
| 491 | PRINTREG(sc, ATW_TSFTL); |
| 492 | PRINTREG(sc, ATW_WEPCTL); |
| 493 | PRINTREG(sc, ATW_WESK); |
| 494 | PRINTREG(sc, ATW_WEPCNT); |
| 495 | PRINTREG(sc, ATW_MACTEST); |
| 496 | PRINTREG(sc, ATW_FER); |
| 497 | PRINTREG(sc, ATW_FEMR); |
| 498 | PRINTREG(sc, ATW_FPSR); |
| 499 | PRINTREG(sc, ATW_FFER); |
| 500 | #undef PRINTREG |
| 501 | } |
| 502 | #endif /* ATW_DEBUG */ |
| 503 | |
| 504 | /* |
| 505 | * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. |
| 506 | */ |
| 507 | void |
| 508 | atw_attach(struct atw_softc *sc) |
| 509 | { |
| 510 | static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { |
| 511 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 512 | }; |
| 513 | struct ieee80211com *ic = &sc->sc_ic; |
| 514 | struct ifnet *ifp = &sc->sc_if; |
| 515 | int country_code, error, i, nrate, srom_major; |
| 516 | u_int32_t reg; |
| 517 | static const char *type_strings[] = {"Intersil (not supported)" , |
| 518 | "RFMD" , "Marvel (not supported)" }; |
| 519 | |
| 520 | pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); |
| 521 | |
| 522 | sc->sc_txth = atw_txthresh_tab_lo; |
| 523 | |
| 524 | SIMPLEQ_INIT(&sc->sc_txfreeq); |
| 525 | SIMPLEQ_INIT(&sc->sc_txdirtyq); |
| 526 | |
| 527 | #ifdef ATW_DEBUG |
| 528 | atw_print_regs(sc, "atw_attach" ); |
| 529 | #endif /* ATW_DEBUG */ |
| 530 | |
| 531 | /* |
| 532 | * Allocate the control data structures, and create and load the |
| 533 | * DMA map for it. |
| 534 | */ |
| 535 | if ((error = bus_dmamem_alloc(sc->sc_dmat, |
| 536 | sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, |
| 537 | 1, &sc->sc_cdnseg, 0)) != 0) { |
| 538 | aprint_error_dev(sc->sc_dev, |
| 539 | "unable to allocate control data, error = %d\n" , |
| 540 | error); |
| 541 | goto fail_0; |
| 542 | } |
| 543 | |
| 544 | if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, |
| 545 | sizeof(struct atw_control_data), (void **)&sc->sc_control_data, |
| 546 | BUS_DMA_COHERENT)) != 0) { |
| 547 | aprint_error_dev(sc->sc_dev, |
| 548 | "unable to map control data, error = %d\n" , |
| 549 | error); |
| 550 | goto fail_1; |
| 551 | } |
| 552 | |
| 553 | if ((error = bus_dmamap_create(sc->sc_dmat, |
| 554 | sizeof(struct atw_control_data), 1, |
| 555 | sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { |
| 556 | aprint_error_dev(sc->sc_dev, |
| 557 | "unable to create control data DMA map, error = %d\n" , |
| 558 | error); |
| 559 | goto fail_2; |
| 560 | } |
| 561 | |
| 562 | if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, |
| 563 | sc->sc_control_data, sizeof(struct atw_control_data), NULL, |
| 564 | 0)) != 0) { |
| 565 | aprint_error_dev(sc->sc_dev, |
| 566 | "unable to load control data DMA map, error = %d\n" , error); |
| 567 | goto fail_3; |
| 568 | } |
| 569 | |
| 570 | /* |
| 571 | * Create the transmit buffer DMA maps. |
| 572 | */ |
| 573 | sc->sc_ntxsegs = ATW_NTXSEGS; |
| 574 | for (i = 0; i < ATW_TXQUEUELEN; i++) { |
| 575 | if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, |
| 576 | sc->sc_ntxsegs, MCLBYTES, 0, 0, |
| 577 | &sc->sc_txsoft[i].txs_dmamap)) != 0) { |
| 578 | aprint_error_dev(sc->sc_dev, |
| 579 | "unable to create tx DMA map %d, error = %d\n" , i, |
| 580 | error); |
| 581 | goto fail_4; |
| 582 | } |
| 583 | } |
| 584 | |
| 585 | /* |
| 586 | * Create the receive buffer DMA maps. |
| 587 | */ |
| 588 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 589 | if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, |
| 590 | MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { |
| 591 | aprint_error_dev(sc->sc_dev, |
| 592 | "unable to create rx DMA map %d, error = %d\n" , i, |
| 593 | error); |
| 594 | goto fail_5; |
| 595 | } |
| 596 | } |
| 597 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 598 | sc->sc_rxsoft[i].rxs_mbuf = NULL; |
| 599 | } |
| 600 | |
| 601 | switch (sc->sc_rev) { |
| 602 | case ATW_REVISION_AB: |
| 603 | case ATW_REVISION_AF: |
| 604 | sc->sc_sramlen = ATW_SRAM_A_SIZE; |
| 605 | break; |
| 606 | case ATW_REVISION_BA: |
| 607 | case ATW_REVISION_CA: |
| 608 | sc->sc_sramlen = ATW_SRAM_B_SIZE; |
| 609 | break; |
| 610 | } |
| 611 | |
| 612 | /* Reset the chip to a known state. */ |
| 613 | atw_reset(sc); |
| 614 | |
| 615 | if (atw_read_srom(sc) == -1) |
| 616 | return; |
| 617 | |
| 618 | sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], |
| 619 | ATW_SR_RFTYPE_MASK); |
| 620 | |
| 621 | sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], |
| 622 | ATW_SR_BBPTYPE_MASK); |
| 623 | |
| 624 | if (sc->sc_rftype >= __arraycount(type_strings)) { |
| 625 | aprint_error_dev(sc->sc_dev, "unknown RF\n" ); |
| 626 | return; |
| 627 | } |
| 628 | if (sc->sc_bbptype >= __arraycount(type_strings)) { |
| 629 | aprint_error_dev(sc->sc_dev, "unknown BBP\n" ); |
| 630 | return; |
| 631 | } |
| 632 | |
| 633 | printf("%s: %s RF, %s BBP" , device_xname(sc->sc_dev), |
| 634 | type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); |
| 635 | |
| 636 | /* XXX There exists a Linux driver which seems to use RFType = 0 for |
| 637 | * MARVEL. My bug, or theirs? |
| 638 | */ |
| 639 | |
| 640 | reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); |
| 641 | |
| 642 | switch (sc->sc_rftype) { |
| 643 | case ATW_RFTYPE_INTERSIL: |
| 644 | reg |= ATW_SYNCTL_CS1; |
| 645 | break; |
| 646 | case ATW_RFTYPE_RFMD: |
| 647 | reg |= ATW_SYNCTL_CS0; |
| 648 | break; |
| 649 | case ATW_RFTYPE_MARVEL: |
| 650 | break; |
| 651 | } |
| 652 | |
| 653 | sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; |
| 654 | sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; |
| 655 | |
| 656 | reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); |
| 657 | |
| 658 | switch (sc->sc_bbptype) { |
| 659 | case ATW_BBPTYPE_INTERSIL: |
| 660 | reg |= ATW_BBPCTL_TWI; |
| 661 | break; |
| 662 | case ATW_BBPTYPE_RFMD: |
| 663 | reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | |
| 664 | ATW_BBPCTL_CCA_ACTLO; |
| 665 | break; |
| 666 | case ATW_BBPTYPE_MARVEL: |
| 667 | break; |
| 668 | case ATW_C_BBPTYPE_RFMD: |
| 669 | printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n" , |
| 670 | device_xname(sc->sc_dev)); |
| 671 | break; |
| 672 | } |
| 673 | |
| 674 | sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; |
| 675 | sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; |
| 676 | |
| 677 | /* |
| 678 | * From this point forward, the attachment cannot fail. A failure |
| 679 | * before this point releases all resources that may have been |
| 680 | * allocated. |
| 681 | */ |
| 682 | sc->sc_flags |= ATWF_ATTACHED; |
| 683 | |
| 684 | ATW_DPRINTF((" SROM MAC %04x%04x%04x" , |
| 685 | htole16(sc->sc_srom[ATW_SR_MAC00]), |
| 686 | htole16(sc->sc_srom[ATW_SR_MAC01]), |
| 687 | htole16(sc->sc_srom[ATW_SR_MAC10]))); |
| 688 | |
| 689 | srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], |
| 690 | ATW_SR_MAJOR_MASK); |
| 691 | |
| 692 | if (srom_major < 2) |
| 693 | sc->sc_rf3000_options1 = 0; |
| 694 | else if (sc->sc_rev == ATW_REVISION_BA) { |
| 695 | sc->sc_rf3000_options1 = |
| 696 | __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], |
| 697 | ATW_SR_CR28_MASK); |
| 698 | } else |
| 699 | sc->sc_rf3000_options1 = 0; |
| 700 | |
| 701 | sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], |
| 702 | ATW_SR_CR29_MASK); |
| 703 | |
| 704 | country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], |
| 705 | ATW_SR_CTRY_MASK); |
| 706 | |
| 707 | #define ADD_CHANNEL(_ic, _chan) do { \ |
| 708 | _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ |
| 709 | _ic->ic_channels[_chan].ic_freq = \ |
| 710 | ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ |
| 711 | } while (0) |
| 712 | |
| 713 | /* Find available channels */ |
| 714 | switch (country_code) { |
| 715 | case COUNTRY_MMK2: /* 1-14 */ |
| 716 | ADD_CHANNEL(ic, 14); |
| 717 | /*FALLTHROUGH*/ |
| 718 | case COUNTRY_ETSI: /* 1-13 */ |
| 719 | for (i = 1; i <= 13; i++) |
| 720 | ADD_CHANNEL(ic, i); |
| 721 | break; |
| 722 | case COUNTRY_FCC: /* 1-11 */ |
| 723 | case COUNTRY_IC: /* 1-11 */ |
| 724 | for (i = 1; i <= 11; i++) |
| 725 | ADD_CHANNEL(ic, i); |
| 726 | break; |
| 727 | case COUNTRY_MMK: /* 14 */ |
| 728 | ADD_CHANNEL(ic, 14); |
| 729 | break; |
| 730 | case COUNTRY_FRANCE: /* 10-13 */ |
| 731 | for (i = 10; i <= 13; i++) |
| 732 | ADD_CHANNEL(ic, i); |
| 733 | break; |
| 734 | default: /* assume channels 10-11 */ |
| 735 | case COUNTRY_SPAIN: /* 10-11 */ |
| 736 | for (i = 10; i <= 11; i++) |
| 737 | ADD_CHANNEL(ic, i); |
| 738 | break; |
| 739 | } |
| 740 | |
| 741 | /* Read the MAC address. */ |
| 742 | reg = ATW_READ(sc, ATW_PAR0); |
| 743 | ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); |
| 744 | ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); |
| 745 | ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); |
| 746 | ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); |
| 747 | reg = ATW_READ(sc, ATW_PAR1); |
| 748 | ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); |
| 749 | ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); |
| 750 | |
| 751 | if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { |
| 752 | printf(" could not get mac address, attach failed\n" ); |
| 753 | return; |
| 754 | } |
| 755 | |
| 756 | printf(" 802.11 address %s\n" , ether_sprintf(ic->ic_myaddr)); |
| 757 | |
| 758 | memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); |
| 759 | ifp->if_softc = sc; |
| 760 | ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | |
| 761 | IFF_NOTRAILERS; |
| 762 | ifp->if_ioctl = atw_ioctl; |
| 763 | ifp->if_start = atw_start; |
| 764 | ifp->if_watchdog = atw_watchdog; |
| 765 | ifp->if_init = atw_init; |
| 766 | ifp->if_stop = atw_stop; |
| 767 | IFQ_SET_READY(&ifp->if_snd); |
| 768 | |
| 769 | ic->ic_ifp = ifp; |
| 770 | ic->ic_phytype = IEEE80211_T_DS; |
| 771 | ic->ic_opmode = IEEE80211_M_STA; |
| 772 | ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | |
| 773 | IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; |
| 774 | |
| 775 | nrate = 0; |
| 776 | ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; |
| 777 | ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; |
| 778 | ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; |
| 779 | ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; |
| 780 | ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; |
| 781 | |
| 782 | /* |
| 783 | * Call MI attach routines. |
| 784 | */ |
| 785 | |
| 786 | if_attach(ifp); |
| 787 | ieee80211_ifattach(ic); |
| 788 | |
| 789 | atw_evcnt_attach(sc); |
| 790 | |
| 791 | sc->sc_newstate = ic->ic_newstate; |
| 792 | ic->ic_newstate = atw_newstate; |
| 793 | |
| 794 | sc->sc_recv_mgmt = ic->ic_recv_mgmt; |
| 795 | ic->ic_recv_mgmt = atw_recv_mgmt; |
| 796 | |
| 797 | sc->sc_node_free = ic->ic_node_free; |
| 798 | ic->ic_node_free = atw_node_free; |
| 799 | |
| 800 | sc->sc_node_alloc = ic->ic_node_alloc; |
| 801 | ic->ic_node_alloc = atw_node_alloc; |
| 802 | |
| 803 | ic->ic_crypto.cs_key_delete = atw_key_delete; |
| 804 | ic->ic_crypto.cs_key_set = atw_key_set; |
| 805 | ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; |
| 806 | ic->ic_crypto.cs_key_update_end = atw_key_update_end; |
| 807 | |
| 808 | /* possibly we should fill in our own sc_send_prresp, since |
| 809 | * the ADM8211 is probably sending probe responses in ad hoc |
| 810 | * mode. |
| 811 | */ |
| 812 | |
| 813 | /* complete initialization */ |
| 814 | ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); |
| 815 | callout_init(&sc->sc_scan_ch, 0); |
| 816 | |
| 817 | bpf_attach2(ifp, DLT_IEEE802_11_RADIO, |
| 818 | sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); |
| 819 | |
| 820 | memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); |
| 821 | sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); |
| 822 | sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); |
| 823 | |
| 824 | memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); |
| 825 | sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); |
| 826 | sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); |
| 827 | |
| 828 | ieee80211_announce(ic); |
| 829 | return; |
| 830 | |
| 831 | /* |
| 832 | * Free any resources we've allocated during the failed attach |
| 833 | * attempt. Do this in reverse order and fall through. |
| 834 | */ |
| 835 | fail_5: |
| 836 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 837 | if (sc->sc_rxsoft[i].rxs_dmamap == NULL) |
| 838 | continue; |
| 839 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); |
| 840 | } |
| 841 | fail_4: |
| 842 | for (i = 0; i < ATW_TXQUEUELEN; i++) { |
| 843 | if (sc->sc_txsoft[i].txs_dmamap == NULL) |
| 844 | continue; |
| 845 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); |
| 846 | } |
| 847 | bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); |
| 848 | fail_3: |
| 849 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); |
| 850 | fail_2: |
| 851 | bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, |
| 852 | sizeof(struct atw_control_data)); |
| 853 | fail_1: |
| 854 | bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); |
| 855 | fail_0: |
| 856 | return; |
| 857 | } |
| 858 | |
| 859 | static struct ieee80211_node * |
| 860 | atw_node_alloc(struct ieee80211_node_table *nt) |
| 861 | { |
| 862 | struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; |
| 863 | struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); |
| 864 | |
| 865 | DPRINTF(sc, ("%s: alloc node %p\n" , device_xname(sc->sc_dev), ni)); |
| 866 | return ni; |
| 867 | } |
| 868 | |
| 869 | static void |
| 870 | atw_node_free(struct ieee80211_node *ni) |
| 871 | { |
| 872 | struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; |
| 873 | |
| 874 | DPRINTF(sc, ("%s: freeing node %p %s\n" , device_xname(sc->sc_dev), ni, |
| 875 | ether_sprintf(ni->ni_bssid))); |
| 876 | (*sc->sc_node_free)(ni); |
| 877 | } |
| 878 | |
| 879 | |
| 880 | static void |
| 881 | atw_test1_reset(struct atw_softc *sc) |
| 882 | { |
| 883 | switch (sc->sc_rev) { |
| 884 | case ATW_REVISION_BA: |
| 885 | if (1 /* XXX condition on transceiver type */) { |
| 886 | ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); |
| 887 | } |
| 888 | break; |
| 889 | case ATW_REVISION_CA: |
| 890 | ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); |
| 891 | break; |
| 892 | default: |
| 893 | break; |
| 894 | } |
| 895 | } |
| 896 | |
| 897 | /* |
| 898 | * atw_reset: |
| 899 | * |
| 900 | * Perform a soft reset on the ADM8211. |
| 901 | */ |
| 902 | void |
| 903 | atw_reset(struct atw_softc *sc) |
| 904 | { |
| 905 | int i; |
| 906 | uint32_t lpc __atwdebugused; |
| 907 | |
| 908 | ATW_WRITE(sc, ATW_NAR, 0x0); |
| 909 | DELAY(atw_nar_delay); |
| 910 | |
| 911 | /* Reference driver has a cryptic remark indicating that this might |
| 912 | * power-on the chip. I know that it turns off power-saving.... |
| 913 | */ |
| 914 | ATW_WRITE(sc, ATW_FRCTL, 0x0); |
| 915 | |
| 916 | ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); |
| 917 | |
| 918 | for (i = 0; i < 50000 / atw_pseudo_milli; i++) { |
| 919 | if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) |
| 920 | break; |
| 921 | DELAY(atw_pseudo_milli); |
| 922 | } |
| 923 | |
| 924 | /* ... and then pause 100ms longer for good measure. */ |
| 925 | DELAY(atw_magic_delay1); |
| 926 | |
| 927 | DPRINTF2(sc, ("%s: atw_reset %d iterations\n" , device_xname(sc->sc_dev), i)); |
| 928 | |
| 929 | if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) |
| 930 | aprint_error_dev(sc->sc_dev, "reset failed to complete\n" ); |
| 931 | |
| 932 | /* |
| 933 | * Initialize the PCI Access Register. |
| 934 | */ |
| 935 | sc->sc_busmode = ATW_PAR_PBL_8DW; |
| 936 | |
| 937 | ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); |
| 938 | DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n" , device_xname(sc->sc_dev), |
| 939 | ATW_READ(sc, ATW_PAR), sc->sc_busmode)); |
| 940 | |
| 941 | atw_test1_reset(sc); |
| 942 | |
| 943 | /* Turn off maximum power saving, etc. */ |
| 944 | ATW_WRITE(sc, ATW_FRCTL, 0x0); |
| 945 | |
| 946 | DELAY(atw_magic_delay2); |
| 947 | |
| 948 | /* Recall EEPROM. */ |
| 949 | ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); |
| 950 | |
| 951 | DELAY(atw_magic_delay4); |
| 952 | |
| 953 | lpc = ATW_READ(sc, ATW_LPC); |
| 954 | |
| 955 | DPRINTF(sc, ("%s: ATW_LPC %#08x\n" , __func__, lpc)); |
| 956 | |
| 957 | /* A reset seems to affect the SRAM contents, so put them into |
| 958 | * a known state. |
| 959 | */ |
| 960 | atw_clear_sram(sc); |
| 961 | |
| 962 | memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); |
| 963 | } |
| 964 | |
| 965 | static void |
| 966 | atw_clear_sram(struct atw_softc *sc) |
| 967 | { |
| 968 | memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); |
| 969 | sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; |
| 970 | /* XXX not for revision 0x20. */ |
| 971 | atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); |
| 972 | } |
| 973 | |
| 974 | /* TBD atw_init |
| 975 | * |
| 976 | * set MAC based on ic->ic_bss->myaddr |
| 977 | * write WEP keys |
| 978 | * set TX rate |
| 979 | */ |
| 980 | |
| 981 | /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass |
| 982 | * without receiving a beacon with the preferred BSSID & SSID. |
| 983 | * atw_write_bssid & atw_write_ssid set the BSSID & SSID. |
| 984 | */ |
| 985 | static void |
| 986 | atw_wcsr_init(struct atw_softc *sc) |
| 987 | { |
| 988 | uint32_t wcsr; |
| 989 | |
| 990 | wcsr = ATW_READ(sc, ATW_WCSR); |
| 991 | wcsr &= ~ATW_WCSR_BLN_MASK; |
| 992 | wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); |
| 993 | /* We always want to wake up on link loss or TSFT out of range */ |
| 994 | wcsr |= ATW_WCSR_LSOE|ATW_WCSR_TSFTWE; |
| 995 | ATW_WRITE(sc, ATW_WCSR, wcsr); |
| 996 | |
| 997 | DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n" , |
| 998 | device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); |
| 999 | } |
| 1000 | |
| 1001 | /* Turn off power management. Set Rx store-and-forward mode. */ |
| 1002 | static void |
| 1003 | atw_cmdr_init(struct atw_softc *sc) |
| 1004 | { |
| 1005 | uint32_t cmdr; |
| 1006 | cmdr = ATW_READ(sc, ATW_CMDR); |
| 1007 | cmdr &= ~ATW_CMDR_APM; |
| 1008 | cmdr |= ATW_CMDR_RTE; |
| 1009 | cmdr &= ~ATW_CMDR_DRT_MASK; |
| 1010 | cmdr |= ATW_CMDR_DRT_SF; |
| 1011 | |
| 1012 | ATW_WRITE(sc, ATW_CMDR, cmdr); |
| 1013 | } |
| 1014 | |
| 1015 | static void |
| 1016 | atw_tofs2_init(struct atw_softc *sc) |
| 1017 | { |
| 1018 | uint32_t tofs2; |
| 1019 | /* XXX this magic can probably be figured out from the RFMD docs */ |
| 1020 | #ifndef ATW_REFSLAVE |
| 1021 | tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ |
| 1022 | __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ |
| 1023 | __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ |
| 1024 | __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ |
| 1025 | __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ |
| 1026 | __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ |
| 1027 | __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ |
| 1028 | __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ |
| 1029 | #else |
| 1030 | /* XXX new magic from reference driver source */ |
| 1031 | tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ |
| 1032 | __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ |
| 1033 | __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ |
| 1034 | __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ |
| 1035 | __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ |
| 1036 | __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ |
| 1037 | __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ |
| 1038 | __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ |
| 1039 | #endif |
| 1040 | ATW_WRITE(sc, ATW_TOFS2, tofs2); |
| 1041 | } |
| 1042 | |
| 1043 | static void |
| 1044 | atw_nar_init(struct atw_softc *sc) |
| 1045 | { |
| 1046 | ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); |
| 1047 | } |
| 1048 | |
| 1049 | static void |
| 1050 | atw_txlmt_init(struct atw_softc *sc) |
| 1051 | { |
| 1052 | ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | |
| 1053 | __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); |
| 1054 | } |
| 1055 | |
| 1056 | static void |
| 1057 | atw_test1_init(struct atw_softc *sc) |
| 1058 | { |
| 1059 | uint32_t test1; |
| 1060 | |
| 1061 | test1 = ATW_READ(sc, ATW_TEST1); |
| 1062 | test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); |
| 1063 | /* XXX magic 0x1 */ |
| 1064 | test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; |
| 1065 | ATW_WRITE(sc, ATW_TEST1, test1); |
| 1066 | } |
| 1067 | |
| 1068 | static void |
| 1069 | atw_rf_reset(struct atw_softc *sc) |
| 1070 | { |
| 1071 | /* XXX this resets an Intersil RF front-end? */ |
| 1072 | /* TBD condition on Intersil RFType? */ |
| 1073 | ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); |
| 1074 | DELAY(atw_rf_delay1); |
| 1075 | ATW_WRITE(sc, ATW_SYNRF, 0); |
| 1076 | DELAY(atw_rf_delay2); |
| 1077 | } |
| 1078 | |
| 1079 | /* Set 16 TU max duration for the contention-free period (CFP). */ |
| 1080 | static void |
| 1081 | atw_cfp_init(struct atw_softc *sc) |
| 1082 | { |
| 1083 | uint32_t cfpp; |
| 1084 | |
| 1085 | cfpp = ATW_READ(sc, ATW_CFPP); |
| 1086 | cfpp &= ~ATW_CFPP_CFPMD; |
| 1087 | cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); |
| 1088 | ATW_WRITE(sc, ATW_CFPP, cfpp); |
| 1089 | } |
| 1090 | |
| 1091 | static void |
| 1092 | atw_tofs0_init(struct atw_softc *sc) |
| 1093 | { |
| 1094 | /* XXX I guess that the Cardbus clock is 22 MHz? |
| 1095 | * I am assuming that the role of ATW_TOFS0_USCNT is |
| 1096 | * to divide the bus clock to get a 1 MHz clock---the datasheet is not |
| 1097 | * very clear on this point. It says in the datasheet that it is |
| 1098 | * possible for the ADM8211 to accommodate bus speeds between 22 MHz |
| 1099 | * and 33 MHz; maybe this is the way? I see a binary-only driver write |
| 1100 | * these values. These values are also the power-on default. |
| 1101 | */ |
| 1102 | ATW_WRITE(sc, ATW_TOFS0, |
| 1103 | __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | |
| 1104 | ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); |
| 1105 | } |
| 1106 | |
| 1107 | /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ |
| 1108 | static void |
| 1109 | atw_ifs_init(struct atw_softc *sc) |
| 1110 | { |
| 1111 | uint32_t ifst; |
| 1112 | /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. |
| 1113 | * Go figure. |
| 1114 | */ |
| 1115 | ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | |
| 1116 | __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, |
| 1117 | ATW_IFST_SIFS_MASK) | |
| 1118 | __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | |
| 1119 | __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); |
| 1120 | |
| 1121 | ATW_WRITE(sc, ATW_IFST, ifst); |
| 1122 | } |
| 1123 | |
| 1124 | static void |
| 1125 | atw_response_times_init(struct atw_softc *sc) |
| 1126 | { |
| 1127 | /* XXX More magic. Relates to ACK timing? The datasheet seems to |
| 1128 | * indicate that the MAC expects at least SIFS + MIRT microseconds |
| 1129 | * to pass after it transmits a frame that requires a response; |
| 1130 | * it waits at most SIFS + MART microseconds for the response. |
| 1131 | * Surely this is not the ACK timeout? |
| 1132 | */ |
| 1133 | ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | |
| 1134 | __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); |
| 1135 | } |
| 1136 | |
| 1137 | /* Set up the MMI read/write addresses for the baseband. The Tx/Rx |
| 1138 | * engines read and write baseband registers after Rx and before |
| 1139 | * Tx, respectively. |
| 1140 | */ |
| 1141 | static void |
| 1142 | atw_bbp_io_init(struct atw_softc *sc) |
| 1143 | { |
| 1144 | uint32_t mmiraddr2; |
| 1145 | |
| 1146 | /* XXX The reference driver does this, but is it *really* |
| 1147 | * necessary? |
| 1148 | */ |
| 1149 | switch (sc->sc_rev) { |
| 1150 | case ATW_REVISION_AB: |
| 1151 | case ATW_REVISION_AF: |
| 1152 | mmiraddr2 = 0x0; |
| 1153 | break; |
| 1154 | default: |
| 1155 | mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); |
| 1156 | mmiraddr2 &= |
| 1157 | ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); |
| 1158 | break; |
| 1159 | } |
| 1160 | |
| 1161 | switch (sc->sc_bbptype) { |
| 1162 | case ATW_BBPTYPE_INTERSIL: |
| 1163 | ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); |
| 1164 | ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); |
| 1165 | mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; |
| 1166 | break; |
| 1167 | case ATW_BBPTYPE_MARVEL: |
| 1168 | /* TBD find out the Marvel settings. */ |
| 1169 | break; |
| 1170 | case ATW_BBPTYPE_RFMD: |
| 1171 | default: |
| 1172 | ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); |
| 1173 | ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); |
| 1174 | mmiraddr2 |= ATW_MMIRADDR2_RFMD; |
| 1175 | break; |
| 1176 | } |
| 1177 | ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); |
| 1178 | ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); |
| 1179 | } |
| 1180 | |
| 1181 | /* |
| 1182 | * atw_init: [ ifnet interface function ] |
| 1183 | * |
| 1184 | * Initialize the interface. Must be called at splnet(). |
| 1185 | */ |
| 1186 | int |
| 1187 | atw_init(struct ifnet *ifp) |
| 1188 | { |
| 1189 | struct atw_softc *sc = ifp->if_softc; |
| 1190 | struct ieee80211com *ic = &sc->sc_ic; |
| 1191 | struct atw_txsoft *txs; |
| 1192 | struct atw_rxsoft *rxs; |
| 1193 | int i, error = 0; |
| 1194 | |
| 1195 | if (device_is_active(sc->sc_dev)) { |
| 1196 | /* |
| 1197 | * Cancel any pending I/O. |
| 1198 | */ |
| 1199 | atw_stop(ifp, 0); |
| 1200 | } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || |
| 1201 | !device_is_active(sc->sc_dev)) |
| 1202 | return 0; |
| 1203 | |
| 1204 | /* |
| 1205 | * Reset the chip to a known state. |
| 1206 | */ |
| 1207 | atw_reset(sc); |
| 1208 | |
| 1209 | DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n" , |
| 1210 | __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), |
| 1211 | ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); |
| 1212 | |
| 1213 | atw_wcsr_init(sc); |
| 1214 | |
| 1215 | atw_cmdr_init(sc); |
| 1216 | |
| 1217 | /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. |
| 1218 | * |
| 1219 | * XXX Set transmit power for ATIM, RTS, Beacon. |
| 1220 | */ |
| 1221 | ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | |
| 1222 | __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); |
| 1223 | |
| 1224 | atw_tofs2_init(sc); |
| 1225 | |
| 1226 | atw_nar_init(sc); |
| 1227 | |
| 1228 | atw_txlmt_init(sc); |
| 1229 | |
| 1230 | atw_test1_init(sc); |
| 1231 | |
| 1232 | atw_rf_reset(sc); |
| 1233 | |
| 1234 | atw_cfp_init(sc); |
| 1235 | |
| 1236 | atw_tofs0_init(sc); |
| 1237 | |
| 1238 | atw_ifs_init(sc); |
| 1239 | |
| 1240 | /* XXX Fall asleep after one second of inactivity. |
| 1241 | * XXX A frame may only dribble in for 65536us. |
| 1242 | */ |
| 1243 | ATW_WRITE(sc, ATW_RMD, |
| 1244 | __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); |
| 1245 | |
| 1246 | atw_response_times_init(sc); |
| 1247 | |
| 1248 | atw_bbp_io_init(sc); |
| 1249 | |
| 1250 | ATW_WRITE(sc, ATW_STSR, 0xffffffff); |
| 1251 | |
| 1252 | if ((error = atw_rf3000_init(sc)) != 0) |
| 1253 | goto out; |
| 1254 | |
| 1255 | ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); |
| 1256 | DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n" , device_xname(sc->sc_dev), |
| 1257 | ATW_READ(sc, ATW_PAR), sc->sc_busmode)); |
| 1258 | |
| 1259 | /* |
| 1260 | * Initialize the transmit descriptor ring. |
| 1261 | */ |
| 1262 | memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); |
| 1263 | for (i = 0; i < ATW_NTXDESC; i++) { |
| 1264 | sc->sc_txdescs[i].at_ctl = 0; |
| 1265 | /* no transmit chaining */ |
| 1266 | sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; |
| 1267 | sc->sc_txdescs[i].at_buf2 = |
| 1268 | htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); |
| 1269 | } |
| 1270 | /* use ring mode */ |
| 1271 | sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); |
| 1272 | ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, |
| 1273 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 1274 | sc->sc_txfree = ATW_NTXDESC; |
| 1275 | sc->sc_txnext = 0; |
| 1276 | |
| 1277 | /* |
| 1278 | * Initialize the transmit job descriptors. |
| 1279 | */ |
| 1280 | SIMPLEQ_INIT(&sc->sc_txfreeq); |
| 1281 | SIMPLEQ_INIT(&sc->sc_txdirtyq); |
| 1282 | for (i = 0; i < ATW_TXQUEUELEN; i++) { |
| 1283 | txs = &sc->sc_txsoft[i]; |
| 1284 | txs->txs_mbuf = NULL; |
| 1285 | SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); |
| 1286 | } |
| 1287 | |
| 1288 | /* |
| 1289 | * Initialize the receive descriptor and receive job |
| 1290 | * descriptor rings. |
| 1291 | */ |
| 1292 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 1293 | rxs = &sc->sc_rxsoft[i]; |
| 1294 | if (rxs->rxs_mbuf == NULL) { |
| 1295 | if ((error = atw_add_rxbuf(sc, i)) != 0) { |
| 1296 | aprint_error_dev(sc->sc_dev, |
| 1297 | "unable to allocate or map rx buffer %d, " |
| 1298 | "error = %d\n" , i, error); |
| 1299 | /* |
| 1300 | * XXX Should attempt to run with fewer receive |
| 1301 | * XXX buffers instead of just failing. |
| 1302 | */ |
| 1303 | atw_rxdrain(sc); |
| 1304 | goto out; |
| 1305 | } |
| 1306 | } else |
| 1307 | atw_init_rxdesc(sc, i); |
| 1308 | } |
| 1309 | sc->sc_rxptr = 0; |
| 1310 | |
| 1311 | /* |
| 1312 | * Initialize the interrupt mask and enable interrupts. |
| 1313 | */ |
| 1314 | /* normal interrupts */ |
| 1315 | sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | |
| 1316 | ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; |
| 1317 | |
| 1318 | /* abnormal interrupts */ |
| 1319 | sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | |
| 1320 | ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | |
| 1321 | ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; |
| 1322 | |
| 1323 | sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | |
| 1324 | ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; |
| 1325 | sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; |
| 1326 | sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | |
| 1327 | ATW_INTR_TRT; |
| 1328 | |
| 1329 | sc->sc_linkint_mask &= sc->sc_inten; |
| 1330 | sc->sc_rxint_mask &= sc->sc_inten; |
| 1331 | sc->sc_txint_mask &= sc->sc_inten; |
| 1332 | |
| 1333 | ATW_WRITE(sc, ATW_IER, sc->sc_inten); |
| 1334 | ATW_WRITE(sc, ATW_STSR, 0xffffffff); |
| 1335 | |
| 1336 | DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n" , |
| 1337 | device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); |
| 1338 | |
| 1339 | /* |
| 1340 | * Give the transmit and receive rings to the ADM8211. |
| 1341 | */ |
| 1342 | ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); |
| 1343 | ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); |
| 1344 | |
| 1345 | sc->sc_txthresh = 0; |
| 1346 | sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | |
| 1347 | sc->sc_txth[sc->sc_txthresh].txth_opmode; |
| 1348 | |
| 1349 | /* common 802.11 configuration */ |
| 1350 | ic->ic_flags &= ~IEEE80211_F_IBSSON; |
| 1351 | switch (ic->ic_opmode) { |
| 1352 | case IEEE80211_M_STA: |
| 1353 | break; |
| 1354 | case IEEE80211_M_AHDEMO: /* XXX */ |
| 1355 | case IEEE80211_M_IBSS: |
| 1356 | ic->ic_flags |= IEEE80211_F_IBSSON; |
| 1357 | /*FALLTHROUGH*/ |
| 1358 | case IEEE80211_M_HOSTAP: /* XXX */ |
| 1359 | break; |
| 1360 | case IEEE80211_M_MONITOR: /* XXX */ |
| 1361 | break; |
| 1362 | } |
| 1363 | |
| 1364 | switch (ic->ic_opmode) { |
| 1365 | case IEEE80211_M_AHDEMO: |
| 1366 | case IEEE80211_M_HOSTAP: |
| 1367 | #ifndef IEEE80211_NO_HOSTAP |
| 1368 | ic->ic_bss->ni_intval = ic->ic_lintval; |
| 1369 | ic->ic_bss->ni_rssi = 0; |
| 1370 | ic->ic_bss->ni_rstamp = 0; |
| 1371 | #endif /* !IEEE80211_NO_HOSTAP */ |
| 1372 | break; |
| 1373 | default: /* XXX */ |
| 1374 | break; |
| 1375 | } |
| 1376 | |
| 1377 | sc->sc_wepctl = 0; |
| 1378 | |
| 1379 | atw_write_ssid(sc); |
| 1380 | atw_write_sup_rates(sc); |
| 1381 | atw_write_wep(sc); |
| 1382 | |
| 1383 | ic->ic_state = IEEE80211_S_INIT; |
| 1384 | |
| 1385 | /* |
| 1386 | * Set the receive filter. This will start the transmit and |
| 1387 | * receive processes. |
| 1388 | */ |
| 1389 | atw_filter_setup(sc); |
| 1390 | |
| 1391 | /* |
| 1392 | * Start the receive process. |
| 1393 | */ |
| 1394 | ATW_WRITE(sc, ATW_RDR, 0x1); |
| 1395 | |
| 1396 | /* |
| 1397 | * Note that the interface is now running. |
| 1398 | */ |
| 1399 | ifp->if_flags |= IFF_RUNNING; |
| 1400 | |
| 1401 | /* send no beacons, yet. */ |
| 1402 | atw_start_beacon(sc, 0); |
| 1403 | |
| 1404 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
| 1405 | error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); |
| 1406 | else |
| 1407 | error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); |
| 1408 | out: |
| 1409 | if (error) { |
| 1410 | ifp->if_flags &= ~IFF_RUNNING; |
| 1411 | sc->sc_tx_timer = 0; |
| 1412 | ifp->if_timer = 0; |
| 1413 | printf("%s: interface not running\n" , device_xname(sc->sc_dev)); |
| 1414 | } |
| 1415 | #ifdef ATW_DEBUG |
| 1416 | atw_print_regs(sc, "end of init" ); |
| 1417 | #endif /* ATW_DEBUG */ |
| 1418 | |
| 1419 | return (error); |
| 1420 | } |
| 1421 | |
| 1422 | /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. |
| 1423 | * 0: MAC control of RF3000/Si4126. |
| 1424 | * |
| 1425 | * Applies power, or selects RF front-end? Sets reset condition. |
| 1426 | * |
| 1427 | * TBD support non-RFMD BBP, non-SiLabs synth. |
| 1428 | */ |
| 1429 | static void |
| 1430 | atw_bbp_io_enable(struct atw_softc *sc, int enable) |
| 1431 | { |
| 1432 | if (enable) { |
| 1433 | ATW_WRITE(sc, ATW_SYNRF, |
| 1434 | ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); |
| 1435 | DELAY(atw_bbp_io_enable_delay); |
| 1436 | } else { |
| 1437 | ATW_WRITE(sc, ATW_SYNRF, 0); |
| 1438 | DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ |
| 1439 | } |
| 1440 | } |
| 1441 | |
| 1442 | static int |
| 1443 | atw_tune(struct atw_softc *sc) |
| 1444 | { |
| 1445 | int rc; |
| 1446 | u_int chan; |
| 1447 | struct ieee80211com *ic = &sc->sc_ic; |
| 1448 | |
| 1449 | chan = ieee80211_chan2ieee(ic, ic->ic_curchan); |
| 1450 | if (chan == IEEE80211_CHAN_ANY) |
| 1451 | panic("%s: chan == IEEE80211_CHAN_ANY\n" , __func__); |
| 1452 | |
| 1453 | if (chan == sc->sc_cur_chan) |
| 1454 | return 0; |
| 1455 | |
| 1456 | DPRINTF(sc, ("%s: chan %d -> %d\n" , device_xname(sc->sc_dev), |
| 1457 | sc->sc_cur_chan, chan)); |
| 1458 | |
| 1459 | atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); |
| 1460 | |
| 1461 | atw_si4126_tune(sc, chan); |
| 1462 | if ((rc = atw_rf3000_tune(sc, chan)) != 0) |
| 1463 | printf("%s: failed to tune channel %d\n" , device_xname(sc->sc_dev), |
| 1464 | chan); |
| 1465 | |
| 1466 | ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); |
| 1467 | DELAY(atw_nar_delay); |
| 1468 | ATW_WRITE(sc, ATW_RDR, 0x1); |
| 1469 | |
| 1470 | if (rc == 0) { |
| 1471 | sc->sc_cur_chan = chan; |
| 1472 | sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = |
| 1473 | htole16(ic->ic_curchan->ic_freq); |
| 1474 | sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = |
| 1475 | htole16(ic->ic_curchan->ic_flags); |
| 1476 | } |
| 1477 | |
| 1478 | return rc; |
| 1479 | } |
| 1480 | |
| 1481 | #ifdef ATW_SYNDEBUG |
| 1482 | static void |
| 1483 | atw_si4126_print(struct atw_softc *sc) |
| 1484 | { |
| 1485 | struct ifnet *ifp = &sc->sc_if; |
| 1486 | u_int addr, val; |
| 1487 | |
| 1488 | val = 0; |
| 1489 | |
| 1490 | if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) |
| 1491 | return; |
| 1492 | |
| 1493 | for (addr = 0; addr <= 8; addr++) { |
| 1494 | printf("%s: synth[%d] = " , device_xname(sc->sc_dev), addr); |
| 1495 | if (atw_si4126_read(sc, addr, &val) == 0) { |
| 1496 | printf("<unknown> (quitting print-out)\n" ); |
| 1497 | break; |
| 1498 | } |
| 1499 | printf("%05x\n" , val); |
| 1500 | } |
| 1501 | } |
| 1502 | #endif /* ATW_SYNDEBUG */ |
| 1503 | |
| 1504 | /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. |
| 1505 | * |
| 1506 | * The RF/IF synthesizer produces two reference frequencies for |
| 1507 | * the RF2948B transceiver. The first frequency the RF2948B requires |
| 1508 | * is two times the so-called "intermediate frequency" (IF). Since |
| 1509 | * a SAW filter on the radio fixes the IF at 374 MHz, I program the |
| 1510 | * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second |
| 1511 | * frequency required by the transceiver is the radio frequency |
| 1512 | * (RF). This is a superheterodyne transceiver; for f(chan) the |
| 1513 | * center frequency of the channel we are tuning, RF = f(chan) - |
| 1514 | * IF. |
| 1515 | * |
| 1516 | * XXX I am told by SiLabs that the Si4126 will accept a broader range |
| 1517 | * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* |
| 1518 | * XINDIV2 = 1. I've tried this (it is necessary to double R) and it |
| 1519 | * works, but I have still programmed for XINDIV2 = 1 to be safe. |
| 1520 | */ |
| 1521 | static void |
| 1522 | atw_si4126_tune(struct atw_softc *sc, u_int chan) |
| 1523 | { |
| 1524 | u_int mhz; |
| 1525 | u_int R; |
| 1526 | u_int32_t gpio; |
| 1527 | u_int16_t gain; |
| 1528 | |
| 1529 | #ifdef ATW_SYNDEBUG |
| 1530 | atw_si4126_print(sc); |
| 1531 | #endif /* ATW_SYNDEBUG */ |
| 1532 | |
| 1533 | if (chan == 14) |
| 1534 | mhz = 2484; |
| 1535 | else |
| 1536 | mhz = 2412 + 5 * (chan - 1); |
| 1537 | |
| 1538 | /* Tune IF to 748 MHz to suit the IF LO input of the |
| 1539 | * RF2494B, which is 2 x IF. No need to set an IF divider |
| 1540 | * because an IF in 526 MHz - 952 MHz is allowed. |
| 1541 | * |
| 1542 | * XIN is 44.000 MHz, so divide it by two to get allowable |
| 1543 | * range of 2-25 MHz. SiLabs tells me that this is not |
| 1544 | * strictly necessary. |
| 1545 | */ |
| 1546 | |
| 1547 | if (atw_xindiv2) |
| 1548 | R = 44; |
| 1549 | else |
| 1550 | R = 88; |
| 1551 | |
| 1552 | /* Power-up RF, IF synthesizers. */ |
| 1553 | atw_si4126_write(sc, SI4126_POWER, |
| 1554 | SI4126_POWER_PDIB|SI4126_POWER_PDRB); |
| 1555 | |
| 1556 | /* set LPWR, too? */ |
| 1557 | atw_si4126_write(sc, SI4126_MAIN, |
| 1558 | (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); |
| 1559 | |
| 1560 | /* Set the phase-locked loop gain. If RF2 N > 2047, then |
| 1561 | * set KP2 to 1. |
| 1562 | * |
| 1563 | * REFDIF This is different from the reference driver, which |
| 1564 | * always sets SI4126_GAIN to 0. |
| 1565 | */ |
| 1566 | gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); |
| 1567 | |
| 1568 | atw_si4126_write(sc, SI4126_GAIN, gain); |
| 1569 | |
| 1570 | /* XIN = 44 MHz. |
| 1571 | * |
| 1572 | * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, |
| 1573 | * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. |
| 1574 | * |
| 1575 | * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 |
| 1576 | * so that 1496/88 * 44 MHz = 748 MHz. |
| 1577 | */ |
| 1578 | atw_si4126_write(sc, SI4126_IFN, 1496); |
| 1579 | |
| 1580 | atw_si4126_write(sc, SI4126_IFR, R); |
| 1581 | |
| 1582 | #ifndef ATW_REFSLAVE |
| 1583 | /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because |
| 1584 | * then RF1 becomes the active RF synthesizer, even on the Si4126, |
| 1585 | * which has no RF1! |
| 1586 | */ |
| 1587 | atw_si4126_write(sc, SI4126_RF1R, R); |
| 1588 | |
| 1589 | atw_si4126_write(sc, SI4126_RF1N, mhz - 374); |
| 1590 | #endif |
| 1591 | |
| 1592 | /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, |
| 1593 | * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. |
| 1594 | * Now let's multiply it to mhz. So mhz - IF = N. |
| 1595 | */ |
| 1596 | atw_si4126_write(sc, SI4126_RF2R, R); |
| 1597 | |
| 1598 | atw_si4126_write(sc, SI4126_RF2N, mhz - 374); |
| 1599 | |
| 1600 | /* wait 100us from power-up for RF, IF to settle */ |
| 1601 | DELAY(100); |
| 1602 | |
| 1603 | gpio = ATW_READ(sc, ATW_GPIO); |
| 1604 | gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); |
| 1605 | gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); |
| 1606 | |
| 1607 | if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { |
| 1608 | /* Set a Prism RF front-end to a special mode for channel 14? |
| 1609 | * |
| 1610 | * Apparently the SMC2635W needs this, although I don't think |
| 1611 | * it has a Prism RF. |
| 1612 | */ |
| 1613 | gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); |
| 1614 | } |
| 1615 | ATW_WRITE(sc, ATW_GPIO, gpio); |
| 1616 | |
| 1617 | #ifdef ATW_SYNDEBUG |
| 1618 | atw_si4126_print(sc); |
| 1619 | #endif /* ATW_SYNDEBUG */ |
| 1620 | } |
| 1621 | |
| 1622 | /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna |
| 1623 | * diversity. |
| 1624 | * |
| 1625 | * !!! |
| 1626 | * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). |
| 1627 | * !!! |
| 1628 | */ |
| 1629 | static int |
| 1630 | atw_rf3000_init(struct atw_softc *sc) |
| 1631 | { |
| 1632 | int rc = 0; |
| 1633 | |
| 1634 | atw_bbp_io_enable(sc, 1); |
| 1635 | |
| 1636 | /* CCA is acquisition sensitive */ |
| 1637 | rc = atw_rf3000_write(sc, RF3000_CCACTL, |
| 1638 | __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); |
| 1639 | |
| 1640 | if (rc != 0) |
| 1641 | goto out; |
| 1642 | |
| 1643 | /* enable diversity */ |
| 1644 | rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); |
| 1645 | |
| 1646 | if (rc != 0) |
| 1647 | goto out; |
| 1648 | |
| 1649 | /* sensible setting from a binary-only driver */ |
| 1650 | rc = atw_rf3000_write(sc, RF3000_GAINCTL, |
| 1651 | __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); |
| 1652 | |
| 1653 | if (rc != 0) |
| 1654 | goto out; |
| 1655 | |
| 1656 | /* magic from a binary-only driver */ |
| 1657 | rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, |
| 1658 | __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); |
| 1659 | |
| 1660 | if (rc != 0) |
| 1661 | goto out; |
| 1662 | |
| 1663 | rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); |
| 1664 | |
| 1665 | if (rc != 0) |
| 1666 | goto out; |
| 1667 | |
| 1668 | /* XXX Reference driver remarks that Abocom sets this to 50. |
| 1669 | * Meaning 0x50, I think.... 50 = 0x32, which would set a bit |
| 1670 | * in the "reserved" area of register RF3000_OPTIONS1. |
| 1671 | */ |
| 1672 | rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); |
| 1673 | |
| 1674 | if (rc != 0) |
| 1675 | goto out; |
| 1676 | |
| 1677 | rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); |
| 1678 | |
| 1679 | if (rc != 0) |
| 1680 | goto out; |
| 1681 | |
| 1682 | out: |
| 1683 | atw_bbp_io_enable(sc, 0); |
| 1684 | return rc; |
| 1685 | } |
| 1686 | |
| 1687 | #ifdef ATW_BBPDEBUG |
| 1688 | static void |
| 1689 | atw_rf3000_print(struct atw_softc *sc) |
| 1690 | { |
| 1691 | struct ifnet *ifp = &sc->sc_if; |
| 1692 | u_int addr, val; |
| 1693 | |
| 1694 | if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) |
| 1695 | return; |
| 1696 | |
| 1697 | for (addr = 0x01; addr <= 0x15; addr++) { |
| 1698 | printf("%s: bbp[%d] = \n" , device_xname(sc->sc_dev), addr); |
| 1699 | if (atw_rf3000_read(sc, addr, &val) != 0) { |
| 1700 | printf("<unknown> (quitting print-out)\n" ); |
| 1701 | break; |
| 1702 | } |
| 1703 | printf("%08x\n" , val); |
| 1704 | } |
| 1705 | } |
| 1706 | #endif /* ATW_BBPDEBUG */ |
| 1707 | |
| 1708 | /* Set the power settings on the BBP for channel `chan'. */ |
| 1709 | static int |
| 1710 | atw_rf3000_tune(struct atw_softc *sc, u_int chan) |
| 1711 | { |
| 1712 | int rc = 0; |
| 1713 | u_int32_t reg; |
| 1714 | u_int16_t txpower, lpf_cutoff, lna_gs_thresh; |
| 1715 | |
| 1716 | txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; |
| 1717 | lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; |
| 1718 | lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; |
| 1719 | |
| 1720 | /* odd channels: LSB, even channels: MSB */ |
| 1721 | if (chan % 2 == 1) { |
| 1722 | txpower &= 0xFF; |
| 1723 | lpf_cutoff &= 0xFF; |
| 1724 | lna_gs_thresh &= 0xFF; |
| 1725 | } else { |
| 1726 | txpower >>= 8; |
| 1727 | lpf_cutoff >>= 8; |
| 1728 | lna_gs_thresh >>= 8; |
| 1729 | } |
| 1730 | |
| 1731 | #ifdef ATW_BBPDEBUG |
| 1732 | atw_rf3000_print(sc); |
| 1733 | #endif /* ATW_BBPDEBUG */ |
| 1734 | |
| 1735 | DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " |
| 1736 | "lna_gs_thresh %02x\n" , |
| 1737 | device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); |
| 1738 | |
| 1739 | atw_bbp_io_enable(sc, 1); |
| 1740 | |
| 1741 | if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, |
| 1742 | __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) |
| 1743 | goto out; |
| 1744 | |
| 1745 | if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) |
| 1746 | goto out; |
| 1747 | |
| 1748 | if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) |
| 1749 | goto out; |
| 1750 | |
| 1751 | rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); |
| 1752 | |
| 1753 | if (rc != 0) |
| 1754 | goto out; |
| 1755 | |
| 1756 | rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); |
| 1757 | |
| 1758 | if (rc != 0) |
| 1759 | goto out; |
| 1760 | |
| 1761 | #ifdef ATW_BBPDEBUG |
| 1762 | atw_rf3000_print(sc); |
| 1763 | #endif /* ATW_BBPDEBUG */ |
| 1764 | |
| 1765 | out: |
| 1766 | atw_bbp_io_enable(sc, 0); |
| 1767 | |
| 1768 | /* set beacon, rts, atim transmit power */ |
| 1769 | reg = ATW_READ(sc, ATW_PLCPHD); |
| 1770 | reg &= ~ATW_PLCPHD_SERVICE_MASK; |
| 1771 | reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), |
| 1772 | ATW_PLCPHD_SERVICE_MASK); |
| 1773 | ATW_WRITE(sc, ATW_PLCPHD, reg); |
| 1774 | DELAY(atw_plcphd_delay); |
| 1775 | |
| 1776 | return rc; |
| 1777 | } |
| 1778 | |
| 1779 | /* Write a register on the RF3000 baseband processor using the |
| 1780 | * registers provided by the ADM8211 for this purpose. |
| 1781 | * |
| 1782 | * Return 0 on success. |
| 1783 | */ |
| 1784 | static int |
| 1785 | atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) |
| 1786 | { |
| 1787 | u_int32_t reg; |
| 1788 | int i; |
| 1789 | |
| 1790 | reg = sc->sc_bbpctl_wr | |
| 1791 | __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | |
| 1792 | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); |
| 1793 | |
| 1794 | for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { |
| 1795 | ATW_WRITE(sc, ATW_BBPCTL, reg); |
| 1796 | DELAY(2 * atw_pseudo_milli); |
| 1797 | if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) |
| 1798 | break; |
| 1799 | } |
| 1800 | |
| 1801 | if (i < 0) { |
| 1802 | printf("%s: BBPCTL still busy\n" , device_xname(sc->sc_dev)); |
| 1803 | return ETIMEDOUT; |
| 1804 | } |
| 1805 | return 0; |
| 1806 | } |
| 1807 | |
| 1808 | /* Read a register on the RF3000 baseband processor using the registers |
| 1809 | * the ADM8211 provides for this purpose. |
| 1810 | * |
| 1811 | * The 7-bit register address is addr. Record the 8-bit data in the register |
| 1812 | * in *val. |
| 1813 | * |
| 1814 | * Return 0 on success. |
| 1815 | * |
| 1816 | * XXX This does not seem to work. The ADM8211 must require more or |
| 1817 | * different magic to read the chip than to write it. Possibly some |
| 1818 | * of the magic I have derived from a binary-only driver concerns |
| 1819 | * the "chip address" (see the RF3000 manual). |
| 1820 | */ |
| 1821 | #ifdef ATW_BBPDEBUG |
| 1822 | static int |
| 1823 | atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) |
| 1824 | { |
| 1825 | u_int32_t reg; |
| 1826 | int i; |
| 1827 | |
| 1828 | for (i = 1000; --i >= 0; ) { |
| 1829 | if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) |
| 1830 | break; |
| 1831 | DELAY(100); |
| 1832 | } |
| 1833 | |
| 1834 | if (i < 0) { |
| 1835 | printf("%s: start atw_rf3000_read, BBPCTL busy\n" , |
| 1836 | device_xname(sc->sc_dev)); |
| 1837 | return ETIMEDOUT; |
| 1838 | } |
| 1839 | |
| 1840 | reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); |
| 1841 | |
| 1842 | ATW_WRITE(sc, ATW_BBPCTL, reg); |
| 1843 | |
| 1844 | for (i = 1000; --i >= 0; ) { |
| 1845 | DELAY(100); |
| 1846 | if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) |
| 1847 | break; |
| 1848 | } |
| 1849 | |
| 1850 | ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); |
| 1851 | |
| 1852 | if (i < 0) { |
| 1853 | printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n" , |
| 1854 | device_xname(sc->sc_dev), reg); |
| 1855 | return ETIMEDOUT; |
| 1856 | } |
| 1857 | if (val != NULL) |
| 1858 | *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); |
| 1859 | return 0; |
| 1860 | } |
| 1861 | #endif /* ATW_BBPDEBUG */ |
| 1862 | |
| 1863 | /* Write a register on the Si4126 RF/IF synthesizer using the registers |
| 1864 | * provided by the ADM8211 for that purpose. |
| 1865 | * |
| 1866 | * val is 18 bits of data, and val is the 4-bit address of the register. |
| 1867 | * |
| 1868 | * Return 0 on success. |
| 1869 | */ |
| 1870 | static void |
| 1871 | atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) |
| 1872 | { |
| 1873 | uint32_t bits, mask, reg; |
| 1874 | const int nbits = 22; |
| 1875 | |
| 1876 | KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); |
| 1877 | KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); |
| 1878 | |
| 1879 | bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | |
| 1880 | __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); |
| 1881 | |
| 1882 | reg = ATW_SYNRF_SELSYN; |
| 1883 | /* reference driver: reset Si4126 serial bus to initial |
| 1884 | * conditions? |
| 1885 | */ |
| 1886 | ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); |
| 1887 | ATW_WRITE(sc, ATW_SYNRF, reg); |
| 1888 | |
| 1889 | for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { |
| 1890 | if ((bits & mask) != 0) |
| 1891 | reg |= ATW_SYNRF_SYNDATA; |
| 1892 | else |
| 1893 | reg &= ~ATW_SYNRF_SYNDATA; |
| 1894 | ATW_WRITE(sc, ATW_SYNRF, reg); |
| 1895 | ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); |
| 1896 | ATW_WRITE(sc, ATW_SYNRF, reg); |
| 1897 | } |
| 1898 | ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); |
| 1899 | ATW_WRITE(sc, ATW_SYNRF, 0x0); |
| 1900 | } |
| 1901 | |
| 1902 | /* Read 18-bit data from the 4-bit address addr in Si4126 |
| 1903 | * RF synthesizer and write the data to *val. Return 0 on success. |
| 1904 | * |
| 1905 | * XXX This does not seem to work. The ADM8211 must require more or |
| 1906 | * different magic to read the chip than to write it. |
| 1907 | */ |
| 1908 | #ifdef ATW_SYNDEBUG |
| 1909 | static int |
| 1910 | atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) |
| 1911 | { |
| 1912 | u_int32_t reg; |
| 1913 | int i; |
| 1914 | |
| 1915 | KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); |
| 1916 | |
| 1917 | for (i = 1000; --i >= 0; ) { |
| 1918 | if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) |
| 1919 | break; |
| 1920 | DELAY(100); |
| 1921 | } |
| 1922 | |
| 1923 | if (i < 0) { |
| 1924 | printf("%s: start atw_si4126_read, SYNCTL busy\n" , |
| 1925 | device_xname(sc->sc_dev)); |
| 1926 | return ETIMEDOUT; |
| 1927 | } |
| 1928 | |
| 1929 | reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); |
| 1930 | |
| 1931 | ATW_WRITE(sc, ATW_SYNCTL, reg); |
| 1932 | |
| 1933 | for (i = 1000; --i >= 0; ) { |
| 1934 | DELAY(100); |
| 1935 | if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) |
| 1936 | break; |
| 1937 | } |
| 1938 | |
| 1939 | ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); |
| 1940 | |
| 1941 | if (i < 0) { |
| 1942 | printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n" , |
| 1943 | device_xname(sc->sc_dev), reg); |
| 1944 | return ETIMEDOUT; |
| 1945 | } |
| 1946 | if (val != NULL) |
| 1947 | *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), |
| 1948 | ATW_SYNCTL_DATA_MASK); |
| 1949 | return 0; |
| 1950 | } |
| 1951 | #endif /* ATW_SYNDEBUG */ |
| 1952 | |
| 1953 | /* XXX is the endianness correct? test. */ |
| 1954 | #define atw_calchash(addr) \ |
| 1955 | (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) |
| 1956 | |
| 1957 | /* |
| 1958 | * atw_filter_setup: |
| 1959 | * |
| 1960 | * Set the ADM8211's receive filter. |
| 1961 | */ |
| 1962 | static void |
| 1963 | atw_filter_setup(struct atw_softc *sc) |
| 1964 | { |
| 1965 | struct ieee80211com *ic = &sc->sc_ic; |
| 1966 | struct ethercom *ec = &sc->sc_ec; |
| 1967 | struct ifnet *ifp = &sc->sc_if; |
| 1968 | int hash; |
| 1969 | u_int32_t hashes[2]; |
| 1970 | struct ether_multi *enm; |
| 1971 | struct ether_multistep step; |
| 1972 | |
| 1973 | /* According to comments in tlp_al981_filter_setup |
| 1974 | * (dev/ic/tulip.c) the ADMtek AL981 does not like for its |
| 1975 | * multicast filter to be set while it is running. Hopefully |
| 1976 | * the ADM8211 is not the same! |
| 1977 | */ |
| 1978 | if ((ifp->if_flags & IFF_RUNNING) != 0) |
| 1979 | atw_idle(sc, ATW_NAR_SR); |
| 1980 | |
| 1981 | sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); |
| 1982 | ifp->if_flags &= ~IFF_ALLMULTI; |
| 1983 | |
| 1984 | /* XXX in scan mode, do not filter packets. Maybe this is |
| 1985 | * unnecessary. |
| 1986 | */ |
| 1987 | if (ic->ic_state == IEEE80211_S_SCAN || |
| 1988 | (ifp->if_flags & IFF_PROMISC) != 0) { |
| 1989 | sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; |
| 1990 | goto allmulti; |
| 1991 | } |
| 1992 | |
| 1993 | hashes[0] = hashes[1] = 0x0; |
| 1994 | |
| 1995 | /* |
| 1996 | * Program the 64-bit multicast hash filter. |
| 1997 | */ |
| 1998 | ETHER_FIRST_MULTI(step, ec, enm); |
| 1999 | while (enm != NULL) { |
| 2000 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, |
| 2001 | ETHER_ADDR_LEN) != 0) |
| 2002 | goto allmulti; |
| 2003 | |
| 2004 | hash = atw_calchash(enm->enm_addrlo); |
| 2005 | hashes[hash >> 5] |= 1 << (hash & 0x1f); |
| 2006 | ETHER_NEXT_MULTI(step, enm); |
| 2007 | sc->sc_opmode |= ATW_NAR_MM; |
| 2008 | } |
| 2009 | ifp->if_flags &= ~IFF_ALLMULTI; |
| 2010 | goto setit; |
| 2011 | |
| 2012 | allmulti: |
| 2013 | sc->sc_opmode |= ATW_NAR_MM; |
| 2014 | ifp->if_flags |= IFF_ALLMULTI; |
| 2015 | hashes[0] = hashes[1] = 0xffffffff; |
| 2016 | |
| 2017 | setit: |
| 2018 | ATW_WRITE(sc, ATW_MAR0, hashes[0]); |
| 2019 | ATW_WRITE(sc, ATW_MAR1, hashes[1]); |
| 2020 | ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); |
| 2021 | DELAY(atw_nar_delay); |
| 2022 | ATW_WRITE(sc, ATW_RDR, 0x1); |
| 2023 | |
| 2024 | DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n" , device_xname(sc->sc_dev), |
| 2025 | ATW_READ(sc, ATW_NAR), sc->sc_opmode)); |
| 2026 | } |
| 2027 | |
| 2028 | /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match |
| 2029 | * a beacon's BSSID and SSID against the preferred BSSID and SSID |
| 2030 | * before it will raise ATW_INTR_LINKON. When the ADM8211 receives |
| 2031 | * no beacon with the preferred BSSID and SSID in the number of |
| 2032 | * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. |
| 2033 | */ |
| 2034 | static void |
| 2035 | atw_write_bssid(struct atw_softc *sc) |
| 2036 | { |
| 2037 | struct ieee80211com *ic = &sc->sc_ic; |
| 2038 | u_int8_t *bssid; |
| 2039 | |
| 2040 | bssid = ic->ic_bss->ni_bssid; |
| 2041 | |
| 2042 | ATW_WRITE(sc, ATW_BSSID0, |
| 2043 | __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | |
| 2044 | __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | |
| 2045 | __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | |
| 2046 | __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); |
| 2047 | |
| 2048 | ATW_WRITE(sc, ATW_ABDA1, |
| 2049 | (ATW_READ(sc, ATW_ABDA1) & |
| 2050 | ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | |
| 2051 | __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | |
| 2052 | __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); |
| 2053 | |
| 2054 | DPRINTF(sc, ("%s: BSSID %s -> " , device_xname(sc->sc_dev), |
| 2055 | ether_sprintf(sc->sc_bssid))); |
| 2056 | DPRINTF(sc, ("%s\n" , ether_sprintf(bssid))); |
| 2057 | |
| 2058 | memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); |
| 2059 | } |
| 2060 | |
| 2061 | /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th |
| 2062 | * 16-bit word. |
| 2063 | */ |
| 2064 | static void |
| 2065 | atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) |
| 2066 | { |
| 2067 | u_int i; |
| 2068 | u_int8_t *ptr; |
| 2069 | |
| 2070 | memcpy(&sc->sc_sram[ofs], buf, buflen); |
| 2071 | |
| 2072 | KASSERT(ofs % 2 == 0 && buflen % 2 == 0); |
| 2073 | |
| 2074 | KASSERT(buflen + ofs <= sc->sc_sramlen); |
| 2075 | |
| 2076 | ptr = &sc->sc_sram[ofs]; |
| 2077 | |
| 2078 | for (i = 0; i < buflen; i += 2) { |
| 2079 | ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | |
| 2080 | __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); |
| 2081 | DELAY(atw_writewep_delay); |
| 2082 | |
| 2083 | ATW_WRITE(sc, ATW_WESK, |
| 2084 | __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); |
| 2085 | DELAY(atw_writewep_delay); |
| 2086 | } |
| 2087 | ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ |
| 2088 | |
| 2089 | if (sc->sc_if.if_flags & IFF_DEBUG) { |
| 2090 | int n_octets = 0; |
| 2091 | printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n" , |
| 2092 | device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); |
| 2093 | for (i = 0; i < buflen; i++) { |
| 2094 | printf(" %02x" , ptr[i]); |
| 2095 | if (++n_octets % 24 == 0) |
| 2096 | printf("\n" ); |
| 2097 | } |
| 2098 | if (n_octets % 24 != 0) |
| 2099 | printf("\n" ); |
| 2100 | } |
| 2101 | } |
| 2102 | |
| 2103 | static int |
| 2104 | atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) |
| 2105 | { |
| 2106 | struct atw_softc *sc = ic->ic_ifp->if_softc; |
| 2107 | u_int keyix = k->wk_keyix; |
| 2108 | |
| 2109 | DPRINTF(sc, ("%s: delete key %u\n" , __func__, keyix)); |
| 2110 | |
| 2111 | if (keyix >= IEEE80211_WEP_NKID) |
| 2112 | return 0; |
| 2113 | if (k->wk_keylen != 0) |
| 2114 | sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; |
| 2115 | |
| 2116 | return 1; |
| 2117 | } |
| 2118 | |
| 2119 | static int |
| 2120 | atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, |
| 2121 | const u_int8_t mac[IEEE80211_ADDR_LEN]) |
| 2122 | { |
| 2123 | struct atw_softc *sc = ic->ic_ifp->if_softc; |
| 2124 | |
| 2125 | DPRINTF(sc, ("%s: set key %u\n" , __func__, k->wk_keyix)); |
| 2126 | |
| 2127 | if (k->wk_keyix >= IEEE80211_WEP_NKID) |
| 2128 | return 0; |
| 2129 | |
| 2130 | sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; |
| 2131 | |
| 2132 | return 1; |
| 2133 | } |
| 2134 | |
| 2135 | static void |
| 2136 | atw_key_update_begin(struct ieee80211com *ic) |
| 2137 | { |
| 2138 | #ifdef ATW_DEBUG |
| 2139 | struct ifnet *ifp = ic->ic_ifp; |
| 2140 | struct atw_softc *sc = ifp->if_softc; |
| 2141 | #endif |
| 2142 | |
| 2143 | DPRINTF(sc, ("%s:\n" , __func__)); |
| 2144 | } |
| 2145 | |
| 2146 | static void |
| 2147 | atw_key_update_end(struct ieee80211com *ic) |
| 2148 | { |
| 2149 | struct ifnet *ifp = ic->ic_ifp; |
| 2150 | struct atw_softc *sc = ifp->if_softc; |
| 2151 | |
| 2152 | DPRINTF(sc, ("%s:\n" , __func__)); |
| 2153 | |
| 2154 | if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) |
| 2155 | return; |
| 2156 | if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) |
| 2157 | return; |
| 2158 | atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); |
| 2159 | atw_write_wep(sc); |
| 2160 | ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); |
| 2161 | DELAY(atw_nar_delay); |
| 2162 | ATW_WRITE(sc, ATW_RDR, 0x1); |
| 2163 | } |
| 2164 | |
| 2165 | /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ |
| 2166 | static void |
| 2167 | atw_write_wep(struct atw_softc *sc) |
| 2168 | { |
| 2169 | #if 0 |
| 2170 | struct ieee80211com *ic = &sc->sc_ic; |
| 2171 | u_int32_t reg; |
| 2172 | int i; |
| 2173 | #endif |
| 2174 | /* SRAM shared-key record format: key0 flags key1 ... key12 */ |
| 2175 | u_int8_t buf[IEEE80211_WEP_NKID] |
| 2176 | [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; |
| 2177 | |
| 2178 | sc->sc_wepctl = 0; |
| 2179 | ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); |
| 2180 | |
| 2181 | memset(&buf[0][0], 0, sizeof(buf)); |
| 2182 | |
| 2183 | #if 0 |
| 2184 | for (i = 0; i < IEEE80211_WEP_NKID; i++) { |
| 2185 | if (ic->ic_nw_keys[i].wk_keylen > 5) { |
| 2186 | buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; |
| 2187 | } else if (ic->ic_nw_keys[i].wk_keylen != 0) { |
| 2188 | buf[i][1] = ATW_WEP_ENABLED; |
| 2189 | } else { |
| 2190 | buf[i][1] = 0; |
| 2191 | continue; |
| 2192 | } |
| 2193 | buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; |
| 2194 | memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], |
| 2195 | ic->ic_nw_keys[i].wk_keylen - 1); |
| 2196 | } |
| 2197 | |
| 2198 | reg = ATW_READ(sc, ATW_MACTEST); |
| 2199 | reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; |
| 2200 | reg &= ~ATW_MACTEST_KEYID_MASK; |
| 2201 | reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); |
| 2202 | ATW_WRITE(sc, ATW_MACTEST, reg); |
| 2203 | |
| 2204 | if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) |
| 2205 | sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; |
| 2206 | |
| 2207 | switch (sc->sc_rev) { |
| 2208 | case ATW_REVISION_AB: |
| 2209 | case ATW_REVISION_AF: |
| 2210 | /* Bypass WEP on Rx. */ |
| 2211 | sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; |
| 2212 | break; |
| 2213 | default: |
| 2214 | break; |
| 2215 | } |
| 2216 | #endif |
| 2217 | |
| 2218 | atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], |
| 2219 | sizeof(buf)); |
| 2220 | |
| 2221 | sc->sc_flags |= ATWF_WEP_SRAM_VALID; |
| 2222 | } |
| 2223 | |
| 2224 | static void |
| 2225 | atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, |
| 2226 | struct ieee80211_node *ni, int subtype, int , u_int32_t rstamp) |
| 2227 | { |
| 2228 | struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; |
| 2229 | |
| 2230 | /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ |
| 2231 | if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) |
| 2232 | return; |
| 2233 | |
| 2234 | (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); |
| 2235 | |
| 2236 | switch (subtype) { |
| 2237 | case IEEE80211_FC0_SUBTYPE_PROBE_RESP: |
| 2238 | case IEEE80211_FC0_SUBTYPE_BEACON: |
| 2239 | if (ic->ic_opmode == IEEE80211_M_IBSS && |
| 2240 | ic->ic_state == IEEE80211_S_RUN) { |
| 2241 | if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) |
| 2242 | (void)ieee80211_ibss_merge(ni); |
| 2243 | } |
| 2244 | break; |
| 2245 | default: |
| 2246 | break; |
| 2247 | } |
| 2248 | return; |
| 2249 | } |
| 2250 | |
| 2251 | /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. |
| 2252 | * In ad hoc mode, the SSID is written to the beacons sent by the |
| 2253 | * ADM8211. In both ad hoc and infrastructure mode, beacons received |
| 2254 | * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF |
| 2255 | * indications. |
| 2256 | */ |
| 2257 | static void |
| 2258 | atw_write_ssid(struct atw_softc *sc) |
| 2259 | { |
| 2260 | struct ieee80211com *ic = &sc->sc_ic; |
| 2261 | /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but |
| 2262 | * it only expects the element length, not its ID. |
| 2263 | */ |
| 2264 | u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; |
| 2265 | |
| 2266 | memset(buf, 0, sizeof(buf)); |
| 2267 | buf[0] = ic->ic_bss->ni_esslen; |
| 2268 | memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); |
| 2269 | |
| 2270 | atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, |
| 2271 | roundup(1 + ic->ic_bss->ni_esslen, 2)); |
| 2272 | } |
| 2273 | |
| 2274 | /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. |
| 2275 | * In ad hoc mode, the supported rates are written to beacons sent by the |
| 2276 | * ADM8211. |
| 2277 | */ |
| 2278 | static void |
| 2279 | atw_write_sup_rates(struct atw_softc *sc) |
| 2280 | { |
| 2281 | struct ieee80211com *ic = &sc->sc_ic; |
| 2282 | /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for |
| 2283 | * supported rates |
| 2284 | */ |
| 2285 | u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; |
| 2286 | |
| 2287 | memset(buf, 0, sizeof(buf)); |
| 2288 | |
| 2289 | buf[0] = ic->ic_bss->ni_rates.rs_nrates; |
| 2290 | |
| 2291 | memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, |
| 2292 | ic->ic_bss->ni_rates.rs_nrates); |
| 2293 | |
| 2294 | atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); |
| 2295 | } |
| 2296 | |
| 2297 | /* Start/stop sending beacons. */ |
| 2298 | void |
| 2299 | atw_start_beacon(struct atw_softc *sc, int start) |
| 2300 | { |
| 2301 | struct ieee80211com *ic = &sc->sc_ic; |
| 2302 | uint16_t chan; |
| 2303 | uint32_t bcnt, bpli, cap0, cap1, capinfo; |
| 2304 | size_t len; |
| 2305 | |
| 2306 | if (!device_is_active(sc->sc_dev)) |
| 2307 | return; |
| 2308 | |
| 2309 | /* start beacons */ |
| 2310 | len = sizeof(struct ieee80211_frame) + |
| 2311 | 8 /* timestamp */ + 2 /* beacon interval */ + |
| 2312 | 2 /* capability info */ + |
| 2313 | 2 + ic->ic_bss->ni_esslen /* SSID element */ + |
| 2314 | 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + |
| 2315 | 3 /* DS parameters */ + |
| 2316 | IEEE80211_CRC_LEN; |
| 2317 | |
| 2318 | bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; |
| 2319 | cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; |
| 2320 | cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; |
| 2321 | |
| 2322 | ATW_WRITE(sc, ATW_BCNT, bcnt); |
| 2323 | ATW_WRITE(sc, ATW_CAP1, cap1); |
| 2324 | |
| 2325 | if (!start) |
| 2326 | return; |
| 2327 | |
| 2328 | /* TBD use ni_capinfo */ |
| 2329 | |
| 2330 | capinfo = 0; |
| 2331 | if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) |
| 2332 | capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; |
| 2333 | if (ic->ic_flags & IEEE80211_F_PRIVACY) |
| 2334 | capinfo |= IEEE80211_CAPINFO_PRIVACY; |
| 2335 | |
| 2336 | switch (ic->ic_opmode) { |
| 2337 | case IEEE80211_M_IBSS: |
| 2338 | len += 4; /* IBSS parameters */ |
| 2339 | capinfo |= IEEE80211_CAPINFO_IBSS; |
| 2340 | break; |
| 2341 | case IEEE80211_M_HOSTAP: |
| 2342 | /* XXX 6-byte minimum TIM */ |
| 2343 | len += atw_beacon_len_adjust; |
| 2344 | capinfo |= IEEE80211_CAPINFO_ESS; |
| 2345 | break; |
| 2346 | default: |
| 2347 | return; |
| 2348 | } |
| 2349 | |
| 2350 | /* set listen interval |
| 2351 | * XXX do software units agree w/ hardware? |
| 2352 | */ |
| 2353 | bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | |
| 2354 | __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); |
| 2355 | |
| 2356 | chan = ieee80211_chan2ieee(ic, ic->ic_curchan); |
| 2357 | |
| 2358 | bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); |
| 2359 | cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); |
| 2360 | cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); |
| 2361 | |
| 2362 | ATW_WRITE(sc, ATW_BCNT, bcnt); |
| 2363 | ATW_WRITE(sc, ATW_BPLI, bpli); |
| 2364 | ATW_WRITE(sc, ATW_CAP0, cap0); |
| 2365 | ATW_WRITE(sc, ATW_CAP1, cap1); |
| 2366 | |
| 2367 | DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n" , |
| 2368 | device_xname(sc->sc_dev), bcnt)); |
| 2369 | |
| 2370 | DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n" , |
| 2371 | device_xname(sc->sc_dev), cap1)); |
| 2372 | } |
| 2373 | |
| 2374 | /* Return the 32 lsb of the last TSFT divisible by ival. */ |
| 2375 | static inline uint32_t |
| 2376 | atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) |
| 2377 | { |
| 2378 | /* Following the reference driver's lead, I compute |
| 2379 | * |
| 2380 | * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) |
| 2381 | * |
| 2382 | * without using 64-bit arithmetic, using the following |
| 2383 | * relationship: |
| 2384 | * |
| 2385 | * (0x100000000 * H + L) % m |
| 2386 | * = ((0x100000000 % m) * H + L) % m |
| 2387 | * = (((0xffffffff + 1) % m) * H + L) % m |
| 2388 | * = ((0xffffffff % m + 1 % m) * H + L) % m |
| 2389 | * = ((0xffffffff % m + 1) * H + L) % m |
| 2390 | */ |
| 2391 | return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; |
| 2392 | } |
| 2393 | |
| 2394 | static uint64_t |
| 2395 | atw_get_tsft(struct atw_softc *sc) |
| 2396 | { |
| 2397 | int i; |
| 2398 | uint32_t tsfth, tsftl; |
| 2399 | for (i = 0; i < 2; i++) { |
| 2400 | tsfth = ATW_READ(sc, ATW_TSFTH); |
| 2401 | tsftl = ATW_READ(sc, ATW_TSFTL); |
| 2402 | if (ATW_READ(sc, ATW_TSFTH) == tsfth) |
| 2403 | break; |
| 2404 | } |
| 2405 | return ((uint64_t)tsfth << 32) | tsftl; |
| 2406 | } |
| 2407 | |
| 2408 | /* If we've created an IBSS, write the TSF time in the ADM8211 to |
| 2409 | * the ieee80211com. |
| 2410 | * |
| 2411 | * Predict the next target beacon transmission time (TBTT) and |
| 2412 | * write it to the ADM8211. |
| 2413 | */ |
| 2414 | static void |
| 2415 | atw_predict_beacon(struct atw_softc *sc) |
| 2416 | { |
| 2417 | #define TBTTOFS 20 /* TU */ |
| 2418 | |
| 2419 | struct ieee80211com *ic = &sc->sc_ic; |
| 2420 | uint64_t tsft; |
| 2421 | uint32_t ival, past_even, tbtt, tsfth, tsftl; |
| 2422 | union { |
| 2423 | uint64_t word; |
| 2424 | uint8_t tstamp[8]; |
| 2425 | } u; |
| 2426 | |
| 2427 | if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || |
| 2428 | ((ic->ic_opmode == IEEE80211_M_IBSS) && |
| 2429 | (ic->ic_flags & IEEE80211_F_SIBSS))) { |
| 2430 | tsft = atw_get_tsft(sc); |
| 2431 | u.word = htole64(tsft); |
| 2432 | (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], |
| 2433 | sizeof(ic->ic_bss->ni_tstamp)); |
| 2434 | } else |
| 2435 | tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); |
| 2436 | |
| 2437 | ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; |
| 2438 | |
| 2439 | tsftl = tsft & 0xFFFFFFFF; |
| 2440 | tsfth = tsft >> 32; |
| 2441 | |
| 2442 | /* We sent/received the last beacon `past' microseconds |
| 2443 | * after the interval divided the TSF timer. |
| 2444 | */ |
| 2445 | past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); |
| 2446 | |
| 2447 | /* Skip ten beacons so that the TBTT cannot pass before |
| 2448 | * we've programmed it. Ten is an arbitrary number. |
| 2449 | */ |
| 2450 | tbtt = past_even + ival * 10; |
| 2451 | |
| 2452 | ATW_WRITE(sc, ATW_TOFS1, |
| 2453 | __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | |
| 2454 | __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | |
| 2455 | __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, |
| 2456 | ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); |
| 2457 | #undef TBTTOFS |
| 2458 | } |
| 2459 | |
| 2460 | static void |
| 2461 | atw_next_scan(void *arg) |
| 2462 | { |
| 2463 | struct atw_softc *sc = arg; |
| 2464 | struct ieee80211com *ic = &sc->sc_ic; |
| 2465 | int s; |
| 2466 | |
| 2467 | /* don't call atw_start w/o network interrupts blocked */ |
| 2468 | s = splnet(); |
| 2469 | if (ic->ic_state == IEEE80211_S_SCAN) |
| 2470 | ieee80211_next_scan(ic); |
| 2471 | splx(s); |
| 2472 | } |
| 2473 | |
| 2474 | /* Synchronize the hardware state with the software state. */ |
| 2475 | static int |
| 2476 | atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) |
| 2477 | { |
| 2478 | struct ifnet *ifp = ic->ic_ifp; |
| 2479 | struct atw_softc *sc = ifp->if_softc; |
| 2480 | int error = 0; |
| 2481 | |
| 2482 | callout_stop(&sc->sc_scan_ch); |
| 2483 | |
| 2484 | switch (nstate) { |
| 2485 | case IEEE80211_S_AUTH: |
| 2486 | case IEEE80211_S_ASSOC: |
| 2487 | atw_write_bssid(sc); |
| 2488 | error = atw_tune(sc); |
| 2489 | break; |
| 2490 | case IEEE80211_S_INIT: |
| 2491 | callout_stop(&sc->sc_scan_ch); |
| 2492 | sc->sc_cur_chan = IEEE80211_CHAN_ANY; |
| 2493 | atw_start_beacon(sc, 0); |
| 2494 | break; |
| 2495 | case IEEE80211_S_SCAN: |
| 2496 | error = atw_tune(sc); |
| 2497 | callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, |
| 2498 | atw_next_scan, sc); |
| 2499 | break; |
| 2500 | case IEEE80211_S_RUN: |
| 2501 | error = atw_tune(sc); |
| 2502 | atw_write_bssid(sc); |
| 2503 | atw_write_ssid(sc); |
| 2504 | atw_write_sup_rates(sc); |
| 2505 | |
| 2506 | if (ic->ic_opmode == IEEE80211_M_AHDEMO || |
| 2507 | ic->ic_opmode == IEEE80211_M_MONITOR) |
| 2508 | break; |
| 2509 | |
| 2510 | /* set listen interval |
| 2511 | * XXX do software units agree w/ hardware? |
| 2512 | */ |
| 2513 | ATW_WRITE(sc, ATW_BPLI, |
| 2514 | __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | |
| 2515 | __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, |
| 2516 | ATW_BPLI_LI_MASK)); |
| 2517 | |
| 2518 | DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n" , device_xname(sc->sc_dev), |
| 2519 | ATW_READ(sc, ATW_BPLI))); |
| 2520 | |
| 2521 | atw_predict_beacon(sc); |
| 2522 | |
| 2523 | switch (ic->ic_opmode) { |
| 2524 | case IEEE80211_M_AHDEMO: |
| 2525 | case IEEE80211_M_HOSTAP: |
| 2526 | case IEEE80211_M_IBSS: |
| 2527 | atw_start_beacon(sc, 1); |
| 2528 | break; |
| 2529 | case IEEE80211_M_MONITOR: |
| 2530 | case IEEE80211_M_STA: |
| 2531 | break; |
| 2532 | } |
| 2533 | |
| 2534 | break; |
| 2535 | } |
| 2536 | return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); |
| 2537 | } |
| 2538 | |
| 2539 | /* |
| 2540 | * atw_add_rxbuf: |
| 2541 | * |
| 2542 | * Add a receive buffer to the indicated descriptor. |
| 2543 | */ |
| 2544 | int |
| 2545 | atw_add_rxbuf(struct atw_softc *sc, int idx) |
| 2546 | { |
| 2547 | struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; |
| 2548 | struct mbuf *m; |
| 2549 | int error; |
| 2550 | |
| 2551 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
| 2552 | if (m == NULL) |
| 2553 | return (ENOBUFS); |
| 2554 | |
| 2555 | MCLGET(m, M_DONTWAIT); |
| 2556 | if ((m->m_flags & M_EXT) == 0) { |
| 2557 | m_freem(m); |
| 2558 | return (ENOBUFS); |
| 2559 | } |
| 2560 | |
| 2561 | if (rxs->rxs_mbuf != NULL) |
| 2562 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
| 2563 | |
| 2564 | rxs->rxs_mbuf = m; |
| 2565 | |
| 2566 | error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, |
| 2567 | m->m_ext.ext_buf, m->m_ext.ext_size, NULL, |
| 2568 | BUS_DMA_READ|BUS_DMA_NOWAIT); |
| 2569 | if (error) { |
| 2570 | aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n" , |
| 2571 | idx, error); |
| 2572 | panic("atw_add_rxbuf" ); /* XXX */ |
| 2573 | } |
| 2574 | |
| 2575 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
| 2576 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); |
| 2577 | |
| 2578 | atw_init_rxdesc(sc, idx); |
| 2579 | |
| 2580 | return (0); |
| 2581 | } |
| 2582 | |
| 2583 | /* |
| 2584 | * Release any queued transmit buffers. |
| 2585 | */ |
| 2586 | void |
| 2587 | atw_txdrain(struct atw_softc *sc) |
| 2588 | { |
| 2589 | struct atw_txsoft *txs; |
| 2590 | |
| 2591 | while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { |
| 2592 | SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); |
| 2593 | if (txs->txs_mbuf != NULL) { |
| 2594 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
| 2595 | m_freem(txs->txs_mbuf); |
| 2596 | txs->txs_mbuf = NULL; |
| 2597 | } |
| 2598 | SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); |
| 2599 | sc->sc_txfree += txs->txs_ndescs; |
| 2600 | } |
| 2601 | |
| 2602 | KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || |
| 2603 | !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || |
| 2604 | sc->sc_txfree != ATW_NTXDESC)); |
| 2605 | sc->sc_if.if_flags &= ~IFF_OACTIVE; |
| 2606 | sc->sc_tx_timer = 0; |
| 2607 | } |
| 2608 | |
| 2609 | /* |
| 2610 | * atw_stop: [ ifnet interface function ] |
| 2611 | * |
| 2612 | * Stop transmission on the interface. |
| 2613 | */ |
| 2614 | void |
| 2615 | atw_stop(struct ifnet *ifp, int disable) |
| 2616 | { |
| 2617 | struct atw_softc *sc = ifp->if_softc; |
| 2618 | struct ieee80211com *ic = &sc->sc_ic; |
| 2619 | |
| 2620 | ieee80211_new_state(ic, IEEE80211_S_INIT, -1); |
| 2621 | |
| 2622 | if (device_is_active(sc->sc_dev)) { |
| 2623 | /* Disable interrupts. */ |
| 2624 | ATW_WRITE(sc, ATW_IER, 0); |
| 2625 | |
| 2626 | /* Stop the transmit and receive processes. */ |
| 2627 | ATW_WRITE(sc, ATW_NAR, 0); |
| 2628 | DELAY(atw_nar_delay); |
| 2629 | ATW_WRITE(sc, ATW_TDBD, 0); |
| 2630 | ATW_WRITE(sc, ATW_TDBP, 0); |
| 2631 | ATW_WRITE(sc, ATW_RDB, 0); |
| 2632 | } |
| 2633 | |
| 2634 | sc->sc_opmode = 0; |
| 2635 | |
| 2636 | atw_txdrain(sc); |
| 2637 | |
| 2638 | /* |
| 2639 | * Mark the interface down and cancel the watchdog timer. |
| 2640 | */ |
| 2641 | ifp->if_flags &= ~IFF_RUNNING; |
| 2642 | ifp->if_timer = 0; |
| 2643 | |
| 2644 | if (disable) |
| 2645 | pmf_device_suspend(sc->sc_dev, &sc->sc_qual); |
| 2646 | } |
| 2647 | |
| 2648 | /* |
| 2649 | * atw_rxdrain: |
| 2650 | * |
| 2651 | * Drain the receive queue. |
| 2652 | */ |
| 2653 | void |
| 2654 | atw_rxdrain(struct atw_softc *sc) |
| 2655 | { |
| 2656 | struct atw_rxsoft *rxs; |
| 2657 | int i; |
| 2658 | |
| 2659 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 2660 | rxs = &sc->sc_rxsoft[i]; |
| 2661 | if (rxs->rxs_mbuf == NULL) |
| 2662 | continue; |
| 2663 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
| 2664 | m_freem(rxs->rxs_mbuf); |
| 2665 | rxs->rxs_mbuf = NULL; |
| 2666 | } |
| 2667 | } |
| 2668 | |
| 2669 | /* |
| 2670 | * atw_detach: |
| 2671 | * |
| 2672 | * Detach an ADM8211 interface. |
| 2673 | */ |
| 2674 | int |
| 2675 | atw_detach(struct atw_softc *sc) |
| 2676 | { |
| 2677 | struct ifnet *ifp = &sc->sc_if; |
| 2678 | struct atw_rxsoft *rxs; |
| 2679 | struct atw_txsoft *txs; |
| 2680 | int i; |
| 2681 | |
| 2682 | /* |
| 2683 | * Succeed now if there isn't any work to do. |
| 2684 | */ |
| 2685 | if ((sc->sc_flags & ATWF_ATTACHED) == 0) |
| 2686 | return (0); |
| 2687 | |
| 2688 | pmf_device_deregister(sc->sc_dev); |
| 2689 | |
| 2690 | callout_stop(&sc->sc_scan_ch); |
| 2691 | |
| 2692 | ieee80211_ifdetach(&sc->sc_ic); |
| 2693 | if_detach(ifp); |
| 2694 | |
| 2695 | for (i = 0; i < ATW_NRXDESC; i++) { |
| 2696 | rxs = &sc->sc_rxsoft[i]; |
| 2697 | if (rxs->rxs_mbuf != NULL) { |
| 2698 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
| 2699 | m_freem(rxs->rxs_mbuf); |
| 2700 | rxs->rxs_mbuf = NULL; |
| 2701 | } |
| 2702 | bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); |
| 2703 | } |
| 2704 | for (i = 0; i < ATW_TXQUEUELEN; i++) { |
| 2705 | txs = &sc->sc_txsoft[i]; |
| 2706 | if (txs->txs_mbuf != NULL) { |
| 2707 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
| 2708 | m_freem(txs->txs_mbuf); |
| 2709 | txs->txs_mbuf = NULL; |
| 2710 | } |
| 2711 | bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); |
| 2712 | } |
| 2713 | bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); |
| 2714 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); |
| 2715 | bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, |
| 2716 | sizeof(struct atw_control_data)); |
| 2717 | bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); |
| 2718 | |
| 2719 | if (sc->sc_srom) |
| 2720 | free(sc->sc_srom, M_DEVBUF); |
| 2721 | |
| 2722 | atw_evcnt_detach(sc); |
| 2723 | |
| 2724 | return (0); |
| 2725 | } |
| 2726 | |
| 2727 | /* atw_shutdown: make sure the interface is stopped at reboot time. */ |
| 2728 | bool |
| 2729 | atw_shutdown(device_t self, int flags) |
| 2730 | { |
| 2731 | struct atw_softc *sc = device_private(self); |
| 2732 | |
| 2733 | atw_stop(&sc->sc_if, 1); |
| 2734 | return true; |
| 2735 | } |
| 2736 | |
| 2737 | #if 0 |
| 2738 | static void |
| 2739 | atw_workaround1(struct atw_softc *sc) |
| 2740 | { |
| 2741 | uint32_t test1; |
| 2742 | |
| 2743 | test1 = ATW_READ(sc, ATW_TEST1); |
| 2744 | |
| 2745 | sc->sc_misc_ev.ev_count++; |
| 2746 | |
| 2747 | if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { |
| 2748 | sc->sc_rxpkt1in_ev.ev_count++; |
| 2749 | return; |
| 2750 | } |
| 2751 | if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == |
| 2752 | __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { |
| 2753 | sc->sc_rxamatch_ev.ev_count++; |
| 2754 | return; |
| 2755 | } |
| 2756 | sc->sc_workaround1_ev.ev_count++; |
| 2757 | (void)atw_init(&sc->sc_if); |
| 2758 | } |
| 2759 | #endif |
| 2760 | |
| 2761 | int |
| 2762 | atw_intr(void *arg) |
| 2763 | { |
| 2764 | struct atw_softc *sc = arg; |
| 2765 | struct ifnet *ifp = &sc->sc_if; |
| 2766 | u_int32_t status, rxstatus, txstatus, linkstatus; |
| 2767 | int handled = 0, txthresh; |
| 2768 | |
| 2769 | #ifdef DEBUG |
| 2770 | if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) |
| 2771 | panic("%s: atw_intr: not enabled" , device_xname(sc->sc_dev)); |
| 2772 | #endif |
| 2773 | |
| 2774 | /* |
| 2775 | * If the interface isn't running, the interrupt couldn't |
| 2776 | * possibly have come from us. |
| 2777 | */ |
| 2778 | if ((ifp->if_flags & IFF_RUNNING) == 0 || |
| 2779 | !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) |
| 2780 | return (0); |
| 2781 | |
| 2782 | for (;;) { |
| 2783 | status = ATW_READ(sc, ATW_STSR); |
| 2784 | |
| 2785 | if (status) |
| 2786 | ATW_WRITE(sc, ATW_STSR, status); |
| 2787 | |
| 2788 | #ifdef ATW_DEBUG |
| 2789 | #define PRINTINTR(flag) do { \ |
| 2790 | if ((status & flag) != 0) { \ |
| 2791 | printf("%s" #flag, delim); \ |
| 2792 | delim = ","; \ |
| 2793 | } \ |
| 2794 | } while (0) |
| 2795 | |
| 2796 | if (atw_debug > 1 && status) { |
| 2797 | const char *delim = "<" ; |
| 2798 | |
| 2799 | printf("%s: reg[STSR] = %x" , |
| 2800 | device_xname(sc->sc_dev), status); |
| 2801 | |
| 2802 | PRINTINTR(ATW_INTR_FBE); |
| 2803 | PRINTINTR(ATW_INTR_LINKOFF); |
| 2804 | PRINTINTR(ATW_INTR_LINKON); |
| 2805 | PRINTINTR(ATW_INTR_RCI); |
| 2806 | PRINTINTR(ATW_INTR_RDU); |
| 2807 | PRINTINTR(ATW_INTR_REIS); |
| 2808 | PRINTINTR(ATW_INTR_RPS); |
| 2809 | PRINTINTR(ATW_INTR_TCI); |
| 2810 | PRINTINTR(ATW_INTR_TDU); |
| 2811 | PRINTINTR(ATW_INTR_TLT); |
| 2812 | PRINTINTR(ATW_INTR_TPS); |
| 2813 | PRINTINTR(ATW_INTR_TRT); |
| 2814 | PRINTINTR(ATW_INTR_TUF); |
| 2815 | PRINTINTR(ATW_INTR_BCNTC); |
| 2816 | PRINTINTR(ATW_INTR_ATIME); |
| 2817 | PRINTINTR(ATW_INTR_TBTT); |
| 2818 | PRINTINTR(ATW_INTR_TSCZ); |
| 2819 | PRINTINTR(ATW_INTR_TSFTF); |
| 2820 | printf(">\n" ); |
| 2821 | } |
| 2822 | #undef PRINTINTR |
| 2823 | #endif /* ATW_DEBUG */ |
| 2824 | |
| 2825 | if ((status & sc->sc_inten) == 0) |
| 2826 | break; |
| 2827 | |
| 2828 | handled = 1; |
| 2829 | |
| 2830 | rxstatus = status & sc->sc_rxint_mask; |
| 2831 | txstatus = status & sc->sc_txint_mask; |
| 2832 | linkstatus = status & sc->sc_linkint_mask; |
| 2833 | |
| 2834 | if (linkstatus) { |
| 2835 | atw_linkintr(sc, linkstatus); |
| 2836 | } |
| 2837 | |
| 2838 | if (rxstatus) { |
| 2839 | /* Grab any new packets. */ |
| 2840 | atw_rxintr(sc); |
| 2841 | |
| 2842 | if (rxstatus & ATW_INTR_RDU) { |
| 2843 | printf("%s: receive ring overrun\n" , |
| 2844 | device_xname(sc->sc_dev)); |
| 2845 | /* Get the receive process going again. */ |
| 2846 | ATW_WRITE(sc, ATW_RDR, 0x1); |
| 2847 | } |
| 2848 | } |
| 2849 | |
| 2850 | if (txstatus) { |
| 2851 | /* Sweep up transmit descriptors. */ |
| 2852 | atw_txintr(sc, txstatus); |
| 2853 | |
| 2854 | if (txstatus & ATW_INTR_TLT) { |
| 2855 | DPRINTF(sc, ("%s: tx lifetime exceeded\n" , |
| 2856 | device_xname(sc->sc_dev))); |
| 2857 | (void)atw_init(&sc->sc_if); |
| 2858 | } |
| 2859 | |
| 2860 | if (txstatus & ATW_INTR_TRT) { |
| 2861 | DPRINTF(sc, ("%s: tx retry limit exceeded\n" , |
| 2862 | device_xname(sc->sc_dev))); |
| 2863 | } |
| 2864 | |
| 2865 | /* If Tx under-run, increase our transmit threshold |
| 2866 | * if another is available. |
| 2867 | */ |
| 2868 | txthresh = sc->sc_txthresh + 1; |
| 2869 | if ((txstatus & ATW_INTR_TUF) && |
| 2870 | sc->sc_txth[txthresh].txth_name != NULL) { |
| 2871 | /* Idle the transmit process. */ |
| 2872 | atw_idle(sc, ATW_NAR_ST); |
| 2873 | |
| 2874 | sc->sc_txthresh = txthresh; |
| 2875 | sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); |
| 2876 | sc->sc_opmode |= |
| 2877 | sc->sc_txth[txthresh].txth_opmode; |
| 2878 | printf("%s: transmit underrun; new " |
| 2879 | "threshold: %s\n" , device_xname(sc->sc_dev), |
| 2880 | sc->sc_txth[txthresh].txth_name); |
| 2881 | |
| 2882 | /* Set the new threshold and restart |
| 2883 | * the transmit process. |
| 2884 | */ |
| 2885 | ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); |
| 2886 | DELAY(atw_nar_delay); |
| 2887 | ATW_WRITE(sc, ATW_TDR, 0x1); |
| 2888 | /* XXX Log every Nth underrun from |
| 2889 | * XXX now on? |
| 2890 | */ |
| 2891 | } |
| 2892 | } |
| 2893 | |
| 2894 | if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { |
| 2895 | if (status & ATW_INTR_TPS) |
| 2896 | printf("%s: transmit process stopped\n" , |
| 2897 | device_xname(sc->sc_dev)); |
| 2898 | if (status & ATW_INTR_RPS) |
| 2899 | printf("%s: receive process stopped\n" , |
| 2900 | device_xname(sc->sc_dev)); |
| 2901 | (void)atw_init(ifp); |
| 2902 | break; |
| 2903 | } |
| 2904 | |
| 2905 | if (status & ATW_INTR_FBE) { |
| 2906 | aprint_error_dev(sc->sc_dev, "fatal bus error\n" ); |
| 2907 | (void)atw_init(ifp); |
| 2908 | break; |
| 2909 | } |
| 2910 | |
| 2911 | /* |
| 2912 | * Not handled: |
| 2913 | * |
| 2914 | * Transmit buffer unavailable -- normal |
| 2915 | * condition, nothing to do, really. |
| 2916 | * |
| 2917 | * Early receive interrupt -- not available on |
| 2918 | * all chips, we just use RI. We also only |
| 2919 | * use single-segment receive DMA, so this |
| 2920 | * is mostly useless. |
| 2921 | * |
| 2922 | * TBD others |
| 2923 | */ |
| 2924 | } |
| 2925 | |
| 2926 | /* Try to get more packets going. */ |
| 2927 | atw_start(ifp); |
| 2928 | |
| 2929 | return (handled); |
| 2930 | } |
| 2931 | |
| 2932 | /* |
| 2933 | * atw_idle: |
| 2934 | * |
| 2935 | * Cause the transmit and/or receive processes to go idle. |
| 2936 | * |
| 2937 | * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx |
| 2938 | * process in STSR if I clear SR or ST after the process has already |
| 2939 | * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 |
| 2940 | * do not seem to be too reliable. Perhaps I have the sense of the |
| 2941 | * Rx bits switched with the Tx bits? |
| 2942 | */ |
| 2943 | void |
| 2944 | atw_idle(struct atw_softc *sc, u_int32_t bits) |
| 2945 | { |
| 2946 | u_int32_t ackmask = 0, opmode, stsr, test0; |
| 2947 | int i, s; |
| 2948 | |
| 2949 | s = splnet(); |
| 2950 | |
| 2951 | opmode = sc->sc_opmode & ~bits; |
| 2952 | |
| 2953 | if (bits & ATW_NAR_SR) |
| 2954 | ackmask |= ATW_INTR_RPS; |
| 2955 | |
| 2956 | if (bits & ATW_NAR_ST) { |
| 2957 | ackmask |= ATW_INTR_TPS; |
| 2958 | /* set ATW_NAR_HF to flush TX FIFO. */ |
| 2959 | opmode |= ATW_NAR_HF; |
| 2960 | } |
| 2961 | |
| 2962 | ATW_WRITE(sc, ATW_NAR, opmode); |
| 2963 | DELAY(atw_nar_delay); |
| 2964 | |
| 2965 | for (i = 0; i < 1000; i++) { |
| 2966 | stsr = ATW_READ(sc, ATW_STSR); |
| 2967 | if ((stsr & ackmask) == ackmask) |
| 2968 | break; |
| 2969 | DELAY(10); |
| 2970 | } |
| 2971 | |
| 2972 | ATW_WRITE(sc, ATW_STSR, stsr & ackmask); |
| 2973 | |
| 2974 | if ((stsr & ackmask) == ackmask) |
| 2975 | goto out; |
| 2976 | |
| 2977 | test0 = ATW_READ(sc, ATW_TEST0); |
| 2978 | |
| 2979 | if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && |
| 2980 | (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { |
| 2981 | printf("%s: transmit process not idle [%s]\n" , |
| 2982 | device_xname(sc->sc_dev), |
| 2983 | atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); |
| 2984 | printf("%s: bits %08x test0 %08x stsr %08x\n" , |
| 2985 | device_xname(sc->sc_dev), bits, test0, stsr); |
| 2986 | } |
| 2987 | |
| 2988 | if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && |
| 2989 | (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { |
| 2990 | DPRINTF2(sc, ("%s: receive process not idle [%s]\n" , |
| 2991 | device_xname(sc->sc_dev), |
| 2992 | atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); |
| 2993 | DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n" , |
| 2994 | device_xname(sc->sc_dev), bits, test0, stsr)); |
| 2995 | } |
| 2996 | out: |
| 2997 | if ((bits & ATW_NAR_ST) != 0) |
| 2998 | atw_txdrain(sc); |
| 2999 | splx(s); |
| 3000 | return; |
| 3001 | } |
| 3002 | |
| 3003 | /* |
| 3004 | * atw_linkintr: |
| 3005 | * |
| 3006 | * Helper; handle link-status interrupts. |
| 3007 | */ |
| 3008 | void |
| 3009 | atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) |
| 3010 | { |
| 3011 | struct ieee80211com *ic = &sc->sc_ic; |
| 3012 | |
| 3013 | if (ic->ic_state != IEEE80211_S_RUN) |
| 3014 | return; |
| 3015 | |
| 3016 | if (linkstatus & ATW_INTR_LINKON) { |
| 3017 | DPRINTF(sc, ("%s: link on\n" , device_xname(sc->sc_dev))); |
| 3018 | sc->sc_rescan_timer = 0; |
| 3019 | } else if (linkstatus & ATW_INTR_LINKOFF) { |
| 3020 | DPRINTF(sc, ("%s: link off\n" , device_xname(sc->sc_dev))); |
| 3021 | if (ic->ic_opmode != IEEE80211_M_STA) |
| 3022 | return; |
| 3023 | sc->sc_rescan_timer = 3; |
| 3024 | sc->sc_if.if_timer = 1; |
| 3025 | } |
| 3026 | } |
| 3027 | |
| 3028 | #if 0 |
| 3029 | static inline int |
| 3030 | atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) |
| 3031 | { |
| 3032 | if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) |
| 3033 | return 0; |
| 3034 | if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) |
| 3035 | return 0; |
| 3036 | return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; |
| 3037 | } |
| 3038 | #endif |
| 3039 | |
| 3040 | /* |
| 3041 | * atw_rxintr: |
| 3042 | * |
| 3043 | * Helper; handle receive interrupts. |
| 3044 | */ |
| 3045 | void |
| 3046 | atw_rxintr(struct atw_softc *sc) |
| 3047 | { |
| 3048 | static int rate_tbl[] = {2, 4, 11, 22, 44}; |
| 3049 | struct ieee80211com *ic = &sc->sc_ic; |
| 3050 | struct ieee80211_node *ni; |
| 3051 | struct ieee80211_frame_min *wh; |
| 3052 | struct ifnet *ifp = &sc->sc_if; |
| 3053 | struct atw_rxsoft *rxs; |
| 3054 | struct mbuf *m; |
| 3055 | u_int32_t rxstat; |
| 3056 | int i, len, rate, rate0; |
| 3057 | u_int32_t , ; |
| 3058 | |
| 3059 | for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { |
| 3060 | rxs = &sc->sc_rxsoft[i]; |
| 3061 | |
| 3062 | ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 3063 | |
| 3064 | rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); |
| 3065 | ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); |
| 3066 | rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); |
| 3067 | |
| 3068 | if (rxstat & ATW_RXSTAT_OWN) { |
| 3069 | ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); |
| 3070 | break; |
| 3071 | } |
| 3072 | |
| 3073 | sc->sc_rxptr = ATW_NEXTRX(i); |
| 3074 | |
| 3075 | DPRINTF3(sc, |
| 3076 | ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n" , |
| 3077 | device_xname(sc->sc_dev), |
| 3078 | rxstat, ctlrssi, |
| 3079 | le32toh(sc->sc_rxdescs[i].ar_buf1), |
| 3080 | le32toh(sc->sc_rxdescs[i].ar_buf2))); |
| 3081 | |
| 3082 | /* |
| 3083 | * Make sure the packet fits in one buffer. This should |
| 3084 | * always be the case. |
| 3085 | */ |
| 3086 | if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != |
| 3087 | (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { |
| 3088 | printf("%s: incoming packet spilled, resetting\n" , |
| 3089 | device_xname(sc->sc_dev)); |
| 3090 | (void)atw_init(ifp); |
| 3091 | return; |
| 3092 | } |
| 3093 | |
| 3094 | /* |
| 3095 | * If an error occurred, update stats, clear the status |
| 3096 | * word, and leave the packet buffer in place. It will |
| 3097 | * simply be reused the next time the ring comes around. |
| 3098 | */ |
| 3099 | if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { |
| 3100 | #define PRINTERR(bit, str) \ |
| 3101 | if (rxstat & (bit)) \ |
| 3102 | aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ |
| 3103 | str) |
| 3104 | ifp->if_ierrors++; |
| 3105 | PRINTERR(ATW_RXSTAT_DE, "descriptor error" ); |
| 3106 | PRINTERR(ATW_RXSTAT_RXTOE, "time-out" ); |
| 3107 | #if 0 |
| 3108 | PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error" ); |
| 3109 | PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error" ); |
| 3110 | PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error" ); |
| 3111 | PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error" ); |
| 3112 | #endif |
| 3113 | #undef PRINTERR |
| 3114 | atw_init_rxdesc(sc, i); |
| 3115 | continue; |
| 3116 | } |
| 3117 | |
| 3118 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
| 3119 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 3120 | |
| 3121 | /* |
| 3122 | * No errors; receive the packet. Note the ADM8211 |
| 3123 | * includes the CRC in promiscuous mode. |
| 3124 | */ |
| 3125 | len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); |
| 3126 | |
| 3127 | /* |
| 3128 | * Allocate a new mbuf cluster. If that fails, we are |
| 3129 | * out of memory, and must drop the packet and recycle |
| 3130 | * the buffer that's already attached to this descriptor. |
| 3131 | */ |
| 3132 | m = rxs->rxs_mbuf; |
| 3133 | if (atw_add_rxbuf(sc, i) != 0) { |
| 3134 | ifp->if_ierrors++; |
| 3135 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
| 3136 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); |
| 3137 | atw_init_rxdesc(sc, i); |
| 3138 | continue; |
| 3139 | } |
| 3140 | |
| 3141 | ifp->if_ipackets++; |
| 3142 | m_set_rcvif(m, ifp); |
| 3143 | m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); |
| 3144 | |
| 3145 | rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; |
| 3146 | |
| 3147 | /* The RSSI comes straight from a register in the |
| 3148 | * baseband processor. I know that for the RF3000, |
| 3149 | * the RSSI register also contains the antenna-selection |
| 3150 | * bits. Mask those off. |
| 3151 | * |
| 3152 | * TBD Treat other basebands. |
| 3153 | * TBD Use short-preamble bit and such in RF3000_RXSTAT. |
| 3154 | */ |
| 3155 | if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) |
| 3156 | rssi = ctlrssi & RF3000_RSSI_MASK; |
| 3157 | else |
| 3158 | rssi = ctlrssi; |
| 3159 | |
| 3160 | /* Pass this up to any BPF listeners. */ |
| 3161 | if (sc->sc_radiobpf != NULL) { |
| 3162 | struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; |
| 3163 | |
| 3164 | tap->ar_rate = rate; |
| 3165 | |
| 3166 | /* TBD verify units are dB */ |
| 3167 | tap->ar_antsignal = (int)rssi; |
| 3168 | if (sc->sc_opmode & ATW_NAR_PR) |
| 3169 | tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; |
| 3170 | else |
| 3171 | tap->ar_flags = 0; |
| 3172 | |
| 3173 | if ((rxstat & ATW_RXSTAT_CRC32E) != 0) |
| 3174 | tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; |
| 3175 | |
| 3176 | bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), |
| 3177 | m); |
| 3178 | } |
| 3179 | |
| 3180 | sc->sc_recv_ev.ev_count++; |
| 3181 | |
| 3182 | if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { |
| 3183 | if (rxstat & ATW_RXSTAT_CRC16E) |
| 3184 | sc->sc_crc16e_ev.ev_count++; |
| 3185 | if (rxstat & ATW_RXSTAT_CRC32E) |
| 3186 | sc->sc_crc32e_ev.ev_count++; |
| 3187 | if (rxstat & ATW_RXSTAT_ICVE) |
| 3188 | sc->sc_icve_ev.ev_count++; |
| 3189 | if (rxstat & ATW_RXSTAT_SFDE) |
| 3190 | sc->sc_sfde_ev.ev_count++; |
| 3191 | if (rxstat & ATW_RXSTAT_SIGE) |
| 3192 | sc->sc_sige_ev.ev_count++; |
| 3193 | ifp->if_ierrors++; |
| 3194 | m_freem(m); |
| 3195 | continue; |
| 3196 | } |
| 3197 | |
| 3198 | if (sc->sc_opmode & ATW_NAR_PR) |
| 3199 | m_adj(m, -IEEE80211_CRC_LEN); |
| 3200 | |
| 3201 | wh = mtod(m, struct ieee80211_frame_min *); |
| 3202 | ni = ieee80211_find_rxnode(ic, wh); |
| 3203 | #if 0 |
| 3204 | if (atw_hw_decrypted(sc, wh)) { |
| 3205 | wh->i_fc[1] &= ~IEEE80211_FC1_WEP; |
| 3206 | DPRINTF(sc, ("%s: hw decrypted\n" , __func__)); |
| 3207 | } |
| 3208 | #endif |
| 3209 | ieee80211_input(ic, m, ni, (int)rssi, 0); |
| 3210 | ieee80211_free_node(ni); |
| 3211 | } |
| 3212 | } |
| 3213 | |
| 3214 | /* |
| 3215 | * atw_txintr: |
| 3216 | * |
| 3217 | * Helper; handle transmit interrupts. |
| 3218 | */ |
| 3219 | void |
| 3220 | atw_txintr(struct atw_softc *sc, uint32_t status) |
| 3221 | { |
| 3222 | static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; |
| 3223 | struct ifnet *ifp = &sc->sc_if; |
| 3224 | struct atw_txsoft *txs; |
| 3225 | u_int32_t txstat; |
| 3226 | |
| 3227 | DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n" , |
| 3228 | device_xname(sc->sc_dev), sc->sc_flags)); |
| 3229 | |
| 3230 | /* |
| 3231 | * Go through our Tx list and free mbufs for those |
| 3232 | * frames that have been transmitted. |
| 3233 | */ |
| 3234 | while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { |
| 3235 | ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, |
| 3236 | BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 3237 | |
| 3238 | #ifdef ATW_DEBUG |
| 3239 | if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { |
| 3240 | int i; |
| 3241 | printf(" txsoft %p transmit chain:\n" , txs); |
| 3242 | ATW_CDTXSYNC(sc, txs->txs_firstdesc, |
| 3243 | txs->txs_ndescs - 1, |
| 3244 | BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
| 3245 | for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { |
| 3246 | printf(" descriptor %d:\n" , i); |
| 3247 | printf(" at_status: 0x%08x\n" , |
| 3248 | le32toh(sc->sc_txdescs[i].at_stat)); |
| 3249 | printf(" at_flags: 0x%08x\n" , |
| 3250 | le32toh(sc->sc_txdescs[i].at_flags)); |
| 3251 | printf(" at_buf1: 0x%08x\n" , |
| 3252 | le32toh(sc->sc_txdescs[i].at_buf1)); |
| 3253 | printf(" at_buf2: 0x%08x\n" , |
| 3254 | le32toh(sc->sc_txdescs[i].at_buf2)); |
| 3255 | if (i == txs->txs_lastdesc) |
| 3256 | break; |
| 3257 | } |
| 3258 | ATW_CDTXSYNC(sc, txs->txs_firstdesc, |
| 3259 | txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); |
| 3260 | } |
| 3261 | #endif |
| 3262 | |
| 3263 | txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); |
| 3264 | if (txstat & ATW_TXSTAT_OWN) { |
| 3265 | ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, |
| 3266 | BUS_DMASYNC_PREREAD); |
| 3267 | break; |
| 3268 | } |
| 3269 | |
| 3270 | SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); |
| 3271 | |
| 3272 | bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, |
| 3273 | 0, txs->txs_dmamap->dm_mapsize, |
| 3274 | BUS_DMASYNC_POSTWRITE); |
| 3275 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
| 3276 | m_freem(txs->txs_mbuf); |
| 3277 | txs->txs_mbuf = NULL; |
| 3278 | |
| 3279 | sc->sc_txfree += txs->txs_ndescs; |
| 3280 | SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); |
| 3281 | |
| 3282 | KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); |
| 3283 | sc->sc_tx_timer = 0; |
| 3284 | ifp->if_flags &= ~IFF_OACTIVE; |
| 3285 | |
| 3286 | if ((ifp->if_flags & IFF_DEBUG) != 0 && |
| 3287 | (txstat & ATW_TXSTAT_ERRMASK) != 0) { |
| 3288 | snprintb(txstat_buf, sizeof(txstat_buf), |
| 3289 | ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); |
| 3290 | printf("%s: txstat %s %" __PRIuBITS "\n" , |
| 3291 | device_xname(sc->sc_dev), txstat_buf, |
| 3292 | __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); |
| 3293 | } |
| 3294 | |
| 3295 | sc->sc_xmit_ev.ev_count++; |
| 3296 | |
| 3297 | /* |
| 3298 | * Check for errors and collisions. |
| 3299 | */ |
| 3300 | if (txstat & ATW_TXSTAT_TUF) |
| 3301 | sc->sc_tuf_ev.ev_count++; |
| 3302 | if (txstat & ATW_TXSTAT_TLT) |
| 3303 | sc->sc_tlt_ev.ev_count++; |
| 3304 | if (txstat & ATW_TXSTAT_TRT) |
| 3305 | sc->sc_trt_ev.ev_count++; |
| 3306 | if (txstat & ATW_TXSTAT_TRO) |
| 3307 | sc->sc_tro_ev.ev_count++; |
| 3308 | if (txstat & ATW_TXSTAT_SOFBR) |
| 3309 | sc->sc_sofbr_ev.ev_count++; |
| 3310 | |
| 3311 | if ((txstat & ATW_TXSTAT_ES) == 0) |
| 3312 | ifp->if_collisions += |
| 3313 | __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); |
| 3314 | else |
| 3315 | ifp->if_oerrors++; |
| 3316 | |
| 3317 | ifp->if_opackets++; |
| 3318 | } |
| 3319 | |
| 3320 | KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); |
| 3321 | } |
| 3322 | |
| 3323 | /* |
| 3324 | * atw_watchdog: [ifnet interface function] |
| 3325 | * |
| 3326 | * Watchdog timer handler. |
| 3327 | */ |
| 3328 | void |
| 3329 | atw_watchdog(struct ifnet *ifp) |
| 3330 | { |
| 3331 | struct atw_softc *sc = ifp->if_softc; |
| 3332 | struct ieee80211com *ic = &sc->sc_ic; |
| 3333 | |
| 3334 | ifp->if_timer = 0; |
| 3335 | if (!device_is_active(sc->sc_dev)) |
| 3336 | return; |
| 3337 | |
| 3338 | if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) |
| 3339 | (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); |
| 3340 | if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && |
| 3341 | !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { |
| 3342 | printf("%s: transmit timeout\n" , ifp->if_xname); |
| 3343 | ifp->if_oerrors++; |
| 3344 | (void)atw_init(ifp); |
| 3345 | atw_start(ifp); |
| 3346 | } |
| 3347 | if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) |
| 3348 | ifp->if_timer = 1; |
| 3349 | ieee80211_watchdog(ic); |
| 3350 | } |
| 3351 | |
| 3352 | static void |
| 3353 | atw_evcnt_detach(struct atw_softc *sc) |
| 3354 | { |
| 3355 | evcnt_detach(&sc->sc_sige_ev); |
| 3356 | evcnt_detach(&sc->sc_sfde_ev); |
| 3357 | evcnt_detach(&sc->sc_icve_ev); |
| 3358 | evcnt_detach(&sc->sc_crc32e_ev); |
| 3359 | evcnt_detach(&sc->sc_crc16e_ev); |
| 3360 | evcnt_detach(&sc->sc_recv_ev); |
| 3361 | |
| 3362 | evcnt_detach(&sc->sc_tuf_ev); |
| 3363 | evcnt_detach(&sc->sc_tro_ev); |
| 3364 | evcnt_detach(&sc->sc_trt_ev); |
| 3365 | evcnt_detach(&sc->sc_tlt_ev); |
| 3366 | evcnt_detach(&sc->sc_sofbr_ev); |
| 3367 | evcnt_detach(&sc->sc_xmit_ev); |
| 3368 | |
| 3369 | evcnt_detach(&sc->sc_rxpkt1in_ev); |
| 3370 | evcnt_detach(&sc->sc_rxamatch_ev); |
| 3371 | evcnt_detach(&sc->sc_workaround1_ev); |
| 3372 | evcnt_detach(&sc->sc_misc_ev); |
| 3373 | } |
| 3374 | |
| 3375 | static void |
| 3376 | atw_evcnt_attach(struct atw_softc *sc) |
| 3377 | { |
| 3378 | evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, |
| 3379 | NULL, sc->sc_if.if_xname, "recv" ); |
| 3380 | evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, |
| 3381 | &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error" ); |
| 3382 | evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, |
| 3383 | &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error" ); |
| 3384 | evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, |
| 3385 | &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error" ); |
| 3386 | evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, |
| 3387 | &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error" ); |
| 3388 | evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, |
| 3389 | &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error" ); |
| 3390 | |
| 3391 | evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, |
| 3392 | NULL, sc->sc_if.if_xname, "xmit" ); |
| 3393 | evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, |
| 3394 | &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow" ); |
| 3395 | evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, |
| 3396 | &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun" ); |
| 3397 | evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, |
| 3398 | &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded" ); |
| 3399 | evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, |
| 3400 | &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded" ); |
| 3401 | evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, |
| 3402 | &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch" ); |
| 3403 | |
| 3404 | evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, |
| 3405 | NULL, sc->sc_if.if_xname, "misc" ); |
| 3406 | evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, |
| 3407 | &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1" ); |
| 3408 | evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, |
| 3409 | &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa" ); |
| 3410 | evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, |
| 3411 | &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set" ); |
| 3412 | } |
| 3413 | |
| 3414 | #ifdef ATW_DEBUG |
| 3415 | static void |
| 3416 | atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) |
| 3417 | { |
| 3418 | struct atw_softc *sc = ifp->if_softc; |
| 3419 | struct mbuf *m; |
| 3420 | int i, noctets = 0; |
| 3421 | |
| 3422 | printf("%s: %d-byte packet\n" , device_xname(sc->sc_dev), |
| 3423 | m0->m_pkthdr.len); |
| 3424 | |
| 3425 | for (m = m0; m; m = m->m_next) { |
| 3426 | if (m->m_len == 0) |
| 3427 | continue; |
| 3428 | for (i = 0; i < m->m_len; i++) { |
| 3429 | printf(" %02x" , ((u_int8_t*)m->m_data)[i]); |
| 3430 | if (++noctets % 24 == 0) |
| 3431 | printf("\n" ); |
| 3432 | } |
| 3433 | } |
| 3434 | printf("%s%s: %d bytes emitted\n" , |
| 3435 | (noctets % 24 != 0) ? "\n" : "" , device_xname(sc->sc_dev), noctets); |
| 3436 | } |
| 3437 | #endif /* ATW_DEBUG */ |
| 3438 | |
| 3439 | /* |
| 3440 | * atw_start: [ifnet interface function] |
| 3441 | * |
| 3442 | * Start packet transmission on the interface. |
| 3443 | */ |
| 3444 | void |
| 3445 | atw_start(struct ifnet *ifp) |
| 3446 | { |
| 3447 | struct atw_softc *sc = ifp->if_softc; |
| 3448 | struct ieee80211_key *k; |
| 3449 | struct ieee80211com *ic = &sc->sc_ic; |
| 3450 | struct ieee80211_node *ni; |
| 3451 | struct ieee80211_frame_min *whm; |
| 3452 | struct ieee80211_frame *wh; |
| 3453 | struct atw_frame *hh; |
| 3454 | uint16_t hdrctl; |
| 3455 | struct mbuf *m0, *m; |
| 3456 | struct atw_txsoft *txs; |
| 3457 | struct atw_txdesc *txd; |
| 3458 | int npkt, rate; |
| 3459 | bus_dmamap_t dmamap; |
| 3460 | int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; |
| 3461 | |
| 3462 | DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n" , |
| 3463 | device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); |
| 3464 | |
| 3465 | if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) |
| 3466 | return; |
| 3467 | |
| 3468 | /* |
| 3469 | * Remember the previous number of free descriptors and |
| 3470 | * the first descriptor we'll use. |
| 3471 | */ |
| 3472 | ofree = sc->sc_txfree; |
| 3473 | firsttx = lasttx = sc->sc_txnext; |
| 3474 | |
| 3475 | DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n" , |
| 3476 | device_xname(sc->sc_dev), ofree, firsttx)); |
| 3477 | |
| 3478 | /* |
| 3479 | * Loop through the send queue, setting up transmit descriptors |
| 3480 | * until we drain the queue, or use up all available transmit |
| 3481 | * descriptors. |
| 3482 | */ |
| 3483 | while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && |
| 3484 | sc->sc_txfree != 0) { |
| 3485 | |
| 3486 | hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); |
| 3487 | |
| 3488 | /* |
| 3489 | * Grab a packet off the management queue, if it |
| 3490 | * is not empty. Otherwise, from the data queue. |
| 3491 | */ |
| 3492 | IF_DEQUEUE(&ic->ic_mgtq, m0); |
| 3493 | if (m0 != NULL) { |
| 3494 | ni = M_GETCTX(m0, struct ieee80211_node *); |
| 3495 | M_CLEARCTX(m0); |
| 3496 | } else if (ic->ic_state != IEEE80211_S_RUN) |
| 3497 | break; /* send no data until associated */ |
| 3498 | else { |
| 3499 | IFQ_DEQUEUE(&ifp->if_snd, m0); |
| 3500 | if (m0 == NULL) |
| 3501 | break; |
| 3502 | bpf_mtap(ifp, m0); |
| 3503 | ni = ieee80211_find_txnode(ic, |
| 3504 | mtod(m0, struct ether_header *)->ether_dhost); |
| 3505 | if (ni == NULL) { |
| 3506 | ifp->if_oerrors++; |
| 3507 | break; |
| 3508 | } |
| 3509 | if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { |
| 3510 | ieee80211_free_node(ni); |
| 3511 | ifp->if_oerrors++; |
| 3512 | break; |
| 3513 | } |
| 3514 | } |
| 3515 | |
| 3516 | rate = MAX(ieee80211_get_rate(ni), 2); |
| 3517 | |
| 3518 | whm = mtod(m0, struct ieee80211_frame_min *); |
| 3519 | |
| 3520 | if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) |
| 3521 | k = NULL; |
| 3522 | else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { |
| 3523 | m_freem(m0); |
| 3524 | ieee80211_free_node(ni); |
| 3525 | ifp->if_oerrors++; |
| 3526 | break; |
| 3527 | } |
| 3528 | #if 0 |
| 3529 | if (IEEE80211_IS_MULTICAST(wh->i_addr1) && |
| 3530 | m0->m_pkthdr.len > ic->ic_fragthreshold) |
| 3531 | hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); |
| 3532 | #endif |
| 3533 | |
| 3534 | if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) |
| 3535 | hdrctl |= htole16(ATW_HDRCTL_RTSCTS); |
| 3536 | |
| 3537 | if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, |
| 3538 | ic->ic_flags, ic->ic_fragthreshold, rate, |
| 3539 | &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { |
| 3540 | DPRINTF2(sc, ("%s: fail compute duration\n" , __func__)); |
| 3541 | m_freem(m0); |
| 3542 | break; |
| 3543 | } |
| 3544 | |
| 3545 | /* XXX Misleading if fragmentation is enabled. Better |
| 3546 | * to fragment in software? |
| 3547 | */ |
| 3548 | *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); |
| 3549 | |
| 3550 | /* |
| 3551 | * Pass the packet to any BPF listeners. |
| 3552 | */ |
| 3553 | bpf_mtap3(ic->ic_rawbpf, m0); |
| 3554 | |
| 3555 | if (sc->sc_radiobpf != NULL) { |
| 3556 | struct atw_tx_radiotap_header *tap = &sc->sc_txtap; |
| 3557 | |
| 3558 | tap->at_rate = rate; |
| 3559 | |
| 3560 | bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), |
| 3561 | m0); |
| 3562 | } |
| 3563 | |
| 3564 | M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); |
| 3565 | |
| 3566 | if (ni != NULL) |
| 3567 | ieee80211_free_node(ni); |
| 3568 | |
| 3569 | if (m0 == NULL) { |
| 3570 | ifp->if_oerrors++; |
| 3571 | break; |
| 3572 | } |
| 3573 | |
| 3574 | /* just to make sure. */ |
| 3575 | m0 = m_pullup(m0, sizeof(struct atw_frame)); |
| 3576 | |
| 3577 | if (m0 == NULL) { |
| 3578 | ifp->if_oerrors++; |
| 3579 | break; |
| 3580 | } |
| 3581 | |
| 3582 | hh = mtod(m0, struct atw_frame *); |
| 3583 | wh = &hh->atw_ihdr; |
| 3584 | |
| 3585 | /* Copy everything we need from the 802.11 header: |
| 3586 | * Frame Control; address 1, address 3, or addresses |
| 3587 | * 3 and 4. NIC fills in BSSID, SA. |
| 3588 | */ |
| 3589 | if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { |
| 3590 | if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) |
| 3591 | panic("%s: illegal WDS frame" , |
| 3592 | device_xname(sc->sc_dev)); |
| 3593 | memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); |
| 3594 | } else |
| 3595 | memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); |
| 3596 | |
| 3597 | *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; |
| 3598 | |
| 3599 | /* initialize remaining Tx parameters */ |
| 3600 | memset(&hh->u, 0, sizeof(hh->u)); |
| 3601 | |
| 3602 | hh->atw_rate = rate * 5; |
| 3603 | /* XXX this could be incorrect if M_FCS. _encap should |
| 3604 | * probably strip FCS just in case it sticks around in |
| 3605 | * bridged packets. |
| 3606 | */ |
| 3607 | hh->atw_service = 0x00; /* XXX guess */ |
| 3608 | hh->atw_paylen = htole16(m0->m_pkthdr.len - |
| 3609 | sizeof(struct atw_frame)); |
| 3610 | |
| 3611 | /* never fragment multicast frames */ |
| 3612 | if (IEEE80211_IS_MULTICAST(hh->atw_dst)) |
| 3613 | hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); |
| 3614 | else { |
| 3615 | if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && |
| 3616 | (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) |
| 3617 | hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); |
| 3618 | hh->atw_fragthr = htole16(ic->ic_fragthreshold); |
| 3619 | } |
| 3620 | |
| 3621 | hh->atw_rtylmt = 3; |
| 3622 | #if 0 |
| 3623 | if (do_encrypt) { |
| 3624 | hdrctl |= htole16(ATW_HDRCTL_WEP); |
| 3625 | hh->atw_keyid = ic->ic_def_txkey; |
| 3626 | } |
| 3627 | #endif |
| 3628 | |
| 3629 | hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); |
| 3630 | hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); |
| 3631 | if (txs->txs_d0.d_residue) |
| 3632 | hh->atw_head_plcplen |= htole16(0x8000); |
| 3633 | if (txs->txs_dn.d_residue) |
| 3634 | hh->atw_tail_plcplen |= htole16(0x8000); |
| 3635 | hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); |
| 3636 | hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); |
| 3637 | |
| 3638 | hh->atw_hdrctl = hdrctl; |
| 3639 | hh->atw_fragnum = npkt << 4; |
| 3640 | #ifdef ATW_DEBUG |
| 3641 | |
| 3642 | if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { |
| 3643 | printf("%s: dst = %s, rate = 0x%02x, " |
| 3644 | "service = 0x%02x, paylen = 0x%04x\n" , |
| 3645 | device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), |
| 3646 | hh->atw_rate, hh->atw_service, hh->atw_paylen); |
| 3647 | |
| 3648 | printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " |
| 3649 | "dur1 = 0x%04x, dur2 = 0x%04x, " |
| 3650 | "dur3 = 0x%04x, rts_dur = 0x%04x\n" , |
| 3651 | device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], |
| 3652 | hh->atw_tail_plcplen, hh->atw_head_plcplen, |
| 3653 | hh->atw_tail_dur, hh->atw_head_dur); |
| 3654 | |
| 3655 | printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " |
| 3656 | "fragnum = 0x%02x, rtylmt = 0x%04x\n" , |
| 3657 | device_xname(sc->sc_dev), hh->atw_hdrctl, |
| 3658 | hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); |
| 3659 | |
| 3660 | printf("%s: keyid = %d\n" , |
| 3661 | device_xname(sc->sc_dev), hh->atw_keyid); |
| 3662 | |
| 3663 | atw_dump_pkt(ifp, m0); |
| 3664 | } |
| 3665 | #endif /* ATW_DEBUG */ |
| 3666 | |
| 3667 | dmamap = txs->txs_dmamap; |
| 3668 | |
| 3669 | /* |
| 3670 | * Load the DMA map. Copy and try (once) again if the packet |
| 3671 | * didn't fit in the alloted number of segments. |
| 3672 | */ |
| 3673 | for (first = 1; |
| 3674 | (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, |
| 3675 | BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; |
| 3676 | first = 0) { |
| 3677 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
| 3678 | if (m == NULL) { |
| 3679 | aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n" ); |
| 3680 | break; |
| 3681 | } |
| 3682 | if (m0->m_pkthdr.len > MHLEN) { |
| 3683 | MCLGET(m, M_DONTWAIT); |
| 3684 | if ((m->m_flags & M_EXT) == 0) { |
| 3685 | aprint_error_dev(sc->sc_dev, "unable to allocate Tx " |
| 3686 | "cluster\n" ); |
| 3687 | m_freem(m); |
| 3688 | break; |
| 3689 | } |
| 3690 | } |
| 3691 | m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); |
| 3692 | m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; |
| 3693 | m_freem(m0); |
| 3694 | m0 = m; |
| 3695 | m = NULL; |
| 3696 | } |
| 3697 | if (error != 0) { |
| 3698 | aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " |
| 3699 | "error = %d\n" , error); |
| 3700 | m_freem(m0); |
| 3701 | break; |
| 3702 | } |
| 3703 | |
| 3704 | /* |
| 3705 | * Ensure we have enough descriptors free to describe |
| 3706 | * the packet. |
| 3707 | */ |
| 3708 | if (dmamap->dm_nsegs > sc->sc_txfree) { |
| 3709 | /* |
| 3710 | * Not enough free descriptors to transmit |
| 3711 | * this packet. Unload the DMA map and |
| 3712 | * drop the packet. Notify the upper layer |
| 3713 | * that there are no more slots left. |
| 3714 | * |
| 3715 | * XXX We could allocate an mbuf and copy, but |
| 3716 | * XXX it is worth it? |
| 3717 | */ |
| 3718 | bus_dmamap_unload(sc->sc_dmat, dmamap); |
| 3719 | m_freem(m0); |
| 3720 | break; |
| 3721 | } |
| 3722 | |
| 3723 | /* |
| 3724 | * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. |
| 3725 | */ |
| 3726 | |
| 3727 | /* Sync the DMA map. */ |
| 3728 | bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, |
| 3729 | BUS_DMASYNC_PREWRITE); |
| 3730 | |
| 3731 | /* XXX arbitrary retry limit; 8 because I have seen it in |
| 3732 | * use already and maybe 0 means "no tries" ! |
| 3733 | */ |
| 3734 | ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); |
| 3735 | |
| 3736 | DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n" , |
| 3737 | device_xname(sc->sc_dev), rate * 5)); |
| 3738 | ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); |
| 3739 | |
| 3740 | /* |
| 3741 | * Initialize the transmit descriptors. |
| 3742 | */ |
| 3743 | for (nexttx = sc->sc_txnext, seg = 0; |
| 3744 | seg < dmamap->dm_nsegs; |
| 3745 | seg++, nexttx = ATW_NEXTTX(nexttx)) { |
| 3746 | /* |
| 3747 | * If this is the first descriptor we're |
| 3748 | * enqueueing, don't set the OWN bit just |
| 3749 | * yet. That could cause a race condition. |
| 3750 | * We'll do it below. |
| 3751 | */ |
| 3752 | txd = &sc->sc_txdescs[nexttx]; |
| 3753 | txd->at_ctl = ctl | |
| 3754 | ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); |
| 3755 | |
| 3756 | txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); |
| 3757 | txd->at_flags = |
| 3758 | htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, |
| 3759 | ATW_TXFLAG_TBS1_MASK)) | |
| 3760 | ((nexttx == (ATW_NTXDESC - 1)) |
| 3761 | ? htole32(ATW_TXFLAG_TER) : 0); |
| 3762 | lasttx = nexttx; |
| 3763 | } |
| 3764 | |
| 3765 | /* Set `first segment' and `last segment' appropriately. */ |
| 3766 | sc->sc_txdescs[sc->sc_txnext].at_flags |= |
| 3767 | htole32(ATW_TXFLAG_FS); |
| 3768 | sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); |
| 3769 | |
| 3770 | #ifdef ATW_DEBUG |
| 3771 | if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { |
| 3772 | printf(" txsoft %p transmit chain:\n" , txs); |
| 3773 | for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { |
| 3774 | printf(" descriptor %d:\n" , seg); |
| 3775 | printf(" at_ctl: 0x%08x\n" , |
| 3776 | le32toh(sc->sc_txdescs[seg].at_ctl)); |
| 3777 | printf(" at_flags: 0x%08x\n" , |
| 3778 | le32toh(sc->sc_txdescs[seg].at_flags)); |
| 3779 | printf(" at_buf1: 0x%08x\n" , |
| 3780 | le32toh(sc->sc_txdescs[seg].at_buf1)); |
| 3781 | printf(" at_buf2: 0x%08x\n" , |
| 3782 | le32toh(sc->sc_txdescs[seg].at_buf2)); |
| 3783 | if (seg == lasttx) |
| 3784 | break; |
| 3785 | } |
| 3786 | } |
| 3787 | #endif |
| 3788 | |
| 3789 | /* Sync the descriptors we're using. */ |
| 3790 | ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, |
| 3791 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 3792 | |
| 3793 | /* |
| 3794 | * Store a pointer to the packet so we can free it later, |
| 3795 | * and remember what txdirty will be once the packet is |
| 3796 | * done. |
| 3797 | */ |
| 3798 | txs->txs_mbuf = m0; |
| 3799 | txs->txs_firstdesc = sc->sc_txnext; |
| 3800 | txs->txs_lastdesc = lasttx; |
| 3801 | txs->txs_ndescs = dmamap->dm_nsegs; |
| 3802 | |
| 3803 | /* Advance the tx pointer. */ |
| 3804 | sc->sc_txfree -= dmamap->dm_nsegs; |
| 3805 | sc->sc_txnext = nexttx; |
| 3806 | |
| 3807 | SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); |
| 3808 | SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); |
| 3809 | } |
| 3810 | |
| 3811 | if (sc->sc_txfree != ofree) { |
| 3812 | DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n" , |
| 3813 | device_xname(sc->sc_dev), lasttx, firsttx)); |
| 3814 | /* |
| 3815 | * Cause a transmit interrupt to happen on the |
| 3816 | * last packet we enqueued. |
| 3817 | */ |
| 3818 | sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); |
| 3819 | ATW_CDTXSYNC(sc, lasttx, 1, |
| 3820 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 3821 | |
| 3822 | /* |
| 3823 | * The entire packet chain is set up. Give the |
| 3824 | * first descriptor to the chip now. |
| 3825 | */ |
| 3826 | sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); |
| 3827 | ATW_CDTXSYNC(sc, firsttx, 1, |
| 3828 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
| 3829 | |
| 3830 | /* Wake up the transmitter. */ |
| 3831 | ATW_WRITE(sc, ATW_TDR, 0x1); |
| 3832 | |
| 3833 | if (txs == NULL || sc->sc_txfree == 0) |
| 3834 | ifp->if_flags |= IFF_OACTIVE; |
| 3835 | |
| 3836 | /* Set a watchdog timer in case the chip flakes out. */ |
| 3837 | sc->sc_tx_timer = 5; |
| 3838 | ifp->if_timer = 1; |
| 3839 | } |
| 3840 | } |
| 3841 | |
| 3842 | /* |
| 3843 | * atw_ioctl: [ifnet interface function] |
| 3844 | * |
| 3845 | * Handle control requests from the operator. |
| 3846 | */ |
| 3847 | int |
| 3848 | atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
| 3849 | { |
| 3850 | struct atw_softc *sc = ifp->if_softc; |
| 3851 | struct ieee80211req *ireq; |
| 3852 | int s, error = 0; |
| 3853 | |
| 3854 | s = splnet(); |
| 3855 | |
| 3856 | switch (cmd) { |
| 3857 | case SIOCSIFFLAGS: |
| 3858 | if ((error = ifioctl_common(ifp, cmd, data)) != 0) |
| 3859 | break; |
| 3860 | switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { |
| 3861 | case IFF_UP|IFF_RUNNING: |
| 3862 | /* |
| 3863 | * To avoid rescanning another access point, |
| 3864 | * do not call atw_init() here. Instead, |
| 3865 | * only reflect media settings. |
| 3866 | */ |
| 3867 | if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) |
| 3868 | atw_filter_setup(sc); |
| 3869 | break; |
| 3870 | case IFF_UP: |
| 3871 | error = atw_init(ifp); |
| 3872 | break; |
| 3873 | case IFF_RUNNING: |
| 3874 | atw_stop(ifp, 1); |
| 3875 | break; |
| 3876 | case 0: |
| 3877 | break; |
| 3878 | } |
| 3879 | break; |
| 3880 | case SIOCADDMULTI: |
| 3881 | case SIOCDELMULTI: |
| 3882 | if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { |
| 3883 | if (ifp->if_flags & IFF_RUNNING) |
| 3884 | atw_filter_setup(sc); /* do not rescan */ |
| 3885 | error = 0; |
| 3886 | } |
| 3887 | break; |
| 3888 | case SIOCS80211: |
| 3889 | ireq = data; |
| 3890 | if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { |
| 3891 | if ((error = kauth_authorize_network(curlwp->l_cred, |
| 3892 | KAUTH_NETWORK_INTERFACE, |
| 3893 | KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, |
| 3894 | (void *)cmd, NULL)) != 0) |
| 3895 | break; |
| 3896 | if (!(IEEE80211_FRAG_MIN <= ireq->i_val && |
| 3897 | ireq->i_val <= IEEE80211_FRAG_MAX)) |
| 3898 | error = EINVAL; |
| 3899 | else |
| 3900 | sc->sc_ic.ic_fragthreshold = ireq->i_val; |
| 3901 | break; |
| 3902 | } |
| 3903 | /*FALLTHROUGH*/ |
| 3904 | default: |
| 3905 | error = ieee80211_ioctl(&sc->sc_ic, cmd, data); |
| 3906 | if (error == ENETRESET || error == ERESTART) { |
| 3907 | if (is_running(ifp)) |
| 3908 | error = atw_init(ifp); |
| 3909 | else |
| 3910 | error = 0; |
| 3911 | } |
| 3912 | break; |
| 3913 | } |
| 3914 | |
| 3915 | /* Try to get more packets going. */ |
| 3916 | if (device_is_active(sc->sc_dev)) |
| 3917 | atw_start(ifp); |
| 3918 | |
| 3919 | splx(s); |
| 3920 | return (error); |
| 3921 | } |
| 3922 | |
| 3923 | static int |
| 3924 | atw_media_change(struct ifnet *ifp) |
| 3925 | { |
| 3926 | int error; |
| 3927 | |
| 3928 | error = ieee80211_media_change(ifp); |
| 3929 | if (error == ENETRESET) { |
| 3930 | if (is_running(ifp)) |
| 3931 | error = atw_init(ifp); |
| 3932 | else |
| 3933 | error = 0; |
| 3934 | } |
| 3935 | return error; |
| 3936 | } |
| 3937 | |