| 1 | /* $NetBSD: siisata.c,v 1.29 2016/09/19 19:07:53 jakllsch Exp $ */ |
| 2 | |
| 3 | /* from ahcisata_core.c */ |
| 4 | |
| 5 | /* |
| 6 | * Copyright (c) 2006 Manuel Bouyer. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | /* from atapi_wdc.c */ |
| 31 | |
| 32 | /* |
| 33 | * Copyright (c) 1998, 2001 Manuel Bouyer. |
| 34 | * |
| 35 | * Redistribution and use in source and binary forms, with or without |
| 36 | * modification, are permitted provided that the following conditions |
| 37 | * are met: |
| 38 | * 1. Redistributions of source code must retain the above copyright |
| 39 | * notice, this list of conditions and the following disclaimer. |
| 40 | * 2. Redistributions in binary form must reproduce the above copyright |
| 41 | * notice, this list of conditions and the following disclaimer in the |
| 42 | * documentation and/or other materials provided with the distribution. |
| 43 | * |
| 44 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 45 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 46 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 47 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 48 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 49 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 53 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 54 | */ |
| 55 | |
| 56 | /* |
| 57 | * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. |
| 58 | * All rights reserved. |
| 59 | * |
| 60 | * Redistribution and use in source and binary forms, with or without |
| 61 | * modification, are permitted provided that the following conditions |
| 62 | * are met: |
| 63 | * 1. Redistributions of source code must retain the above copyright |
| 64 | * notice, this list of conditions and the following disclaimer. |
| 65 | * 2. Redistributions in binary form must reproduce the above copyright |
| 66 | * notice, this list of conditions and the following disclaimer in the |
| 67 | * documentation and/or other materials provided with the distribution. |
| 68 | * |
| 69 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 70 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 71 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 72 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 73 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 74 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 75 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 76 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 77 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 78 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 79 | */ |
| 80 | |
| 81 | #include <sys/cdefs.h> |
| 82 | __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.29 2016/09/19 19:07:53 jakllsch Exp $" ); |
| 83 | |
| 84 | #include <sys/types.h> |
| 85 | #include <sys/malloc.h> |
| 86 | #include <sys/param.h> |
| 87 | #include <sys/kernel.h> |
| 88 | #include <sys/systm.h> |
| 89 | #include <sys/syslog.h> |
| 90 | #include <sys/disklabel.h> |
| 91 | #include <sys/buf.h> |
| 92 | #include <sys/proc.h> |
| 93 | |
| 94 | #include <dev/ata/atareg.h> |
| 95 | #include <dev/ata/satavar.h> |
| 96 | #include <dev/ata/satareg.h> |
| 97 | #include <dev/ata/satafisvar.h> |
| 98 | #include <dev/ata/satafisreg.h> |
| 99 | #include <dev/ata/satapmpreg.h> |
| 100 | #include <dev/ic/siisatavar.h> |
| 101 | #include <dev/ic/siisatareg.h> |
| 102 | |
| 103 | #include <dev/scsipi/scsi_all.h> /* for SCSI status */ |
| 104 | |
| 105 | #include "atapibus.h" |
| 106 | |
| 107 | #ifdef SIISATA_DEBUG |
| 108 | int siisata_debug_mask = 0; |
| 109 | #endif |
| 110 | |
| 111 | #define ATA_DELAY 10000 /* 10s for a drive I/O */ |
| 112 | |
| 113 | #ifndef __BUS_SPACE_HAS_STREAM_METHODS |
| 114 | #if _BYTE_ORDER == _LITTLE_ENDIAN |
| 115 | #define bus_space_read_stream_4 bus_space_read_4 |
| 116 | #define bus_space_read_region_stream_4 bus_space_read_region_4 |
| 117 | #else |
| 118 | static inline uint32_t |
| 119 | bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) |
| 120 | { |
| 121 | return htole32(bus_space_read_4(t, h, o)); |
| 122 | } |
| 123 | |
| 124 | static inline void |
| 125 | bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t *p, bus_size_t c) |
| 126 | { |
| 127 | bus_space_read_region_4(t, h, o, p, c); |
| 128 | for (bus_size_t i = 0; i < c; i++) { |
| 129 | p[i] = htole32(p[i]); |
| 130 | } |
| 131 | } |
| 132 | #endif |
| 133 | #endif |
| 134 | |
| 135 | static void siisata_attach_port(struct siisata_softc *, int); |
| 136 | static void siisata_intr_port(struct siisata_channel *); |
| 137 | |
| 138 | void siisata_probe_drive(struct ata_channel *); |
| 139 | void siisata_setup_channel(struct ata_channel *); |
| 140 | |
| 141 | int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); |
| 142 | void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); |
| 143 | void siisata_reset_channel(struct ata_channel *, int); |
| 144 | int siisata_ata_addref(struct ata_drive_datas *); |
| 145 | void siisata_ata_delref(struct ata_drive_datas *); |
| 146 | void siisata_killpending(struct ata_drive_datas *); |
| 147 | |
| 148 | void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); |
| 149 | int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); |
| 150 | void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); |
| 151 | void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); |
| 152 | |
| 153 | void siisata_bio_start(struct ata_channel *, struct ata_xfer *); |
| 154 | int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); |
| 155 | void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); |
| 156 | int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); |
| 157 | |
| 158 | void siisata_timeout(void *); |
| 159 | |
| 160 | static void siisata_reinit_port(struct ata_channel *); |
| 161 | static void siisata_device_reset(struct ata_channel *); |
| 162 | static void siisata_activate_prb(struct siisata_channel *, int); |
| 163 | static void siisata_deactivate_prb(struct siisata_channel *, int); |
| 164 | static int siisata_dma_setup(struct ata_channel *chp, int slot, |
| 165 | void *data, size_t, int); |
| 166 | |
| 167 | #if NATAPIBUS > 0 |
| 168 | void siisata_atapibus_attach(struct atabus_softc *); |
| 169 | void siisata_atapi_probe_device(struct atapibus_softc *, int); |
| 170 | void siisata_atapi_minphys(struct buf *); |
| 171 | void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); |
| 172 | int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); |
| 173 | void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); |
| 174 | void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); |
| 175 | void siisata_atapi_scsipi_request(struct scsipi_channel *, |
| 176 | scsipi_adapter_req_t, void *); |
| 177 | void siisata_atapi_kill_pending(struct scsipi_periph *); |
| 178 | #endif /* NATAPIBUS */ |
| 179 | |
| 180 | const struct ata_bustype siisata_ata_bustype = { |
| 181 | SCSIPI_BUSTYPE_ATA, |
| 182 | siisata_ata_bio, |
| 183 | siisata_reset_drive, |
| 184 | siisata_reset_channel, |
| 185 | siisata_exec_command, |
| 186 | ata_get_params, |
| 187 | siisata_ata_addref, |
| 188 | siisata_ata_delref, |
| 189 | siisata_killpending |
| 190 | }; |
| 191 | |
| 192 | #if NATAPIBUS > 0 |
| 193 | static const struct scsipi_bustype siisata_atapi_bustype = { |
| 194 | SCSIPI_BUSTYPE_ATAPI, |
| 195 | atapi_scsipi_cmd, |
| 196 | atapi_interpret_sense, |
| 197 | atapi_print_addr, |
| 198 | siisata_atapi_kill_pending, |
| 199 | NULL, |
| 200 | }; |
| 201 | #endif /* NATAPIBUS */ |
| 202 | |
| 203 | |
| 204 | void |
| 205 | siisata_attach(struct siisata_softc *sc) |
| 206 | { |
| 207 | int i; |
| 208 | |
| 209 | SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n" , |
| 210 | SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); |
| 211 | |
| 212 | sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; |
| 213 | sc->sc_atac.atac_pio_cap = 4; |
| 214 | sc->sc_atac.atac_dma_cap = 2; |
| 215 | sc->sc_atac.atac_udma_cap = 6; |
| 216 | sc->sc_atac.atac_channels = sc->sc_chanarray; |
| 217 | sc->sc_atac.atac_probe = siisata_probe_drive; |
| 218 | sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; |
| 219 | sc->sc_atac.atac_set_modes = siisata_setup_channel; |
| 220 | #if NATAPIBUS > 0 |
| 221 | sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; |
| 222 | #endif |
| 223 | |
| 224 | /* come out of reset state */ |
| 225 | GRWRITE(sc, GR_GC, 0); |
| 226 | |
| 227 | for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { |
| 228 | siisata_attach_port(sc, i); |
| 229 | } |
| 230 | |
| 231 | SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n" , |
| 232 | SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), |
| 233 | DEBUG_FUNCS); |
| 234 | return; |
| 235 | } |
| 236 | |
| 237 | static void |
| 238 | siisata_disable_port_interrupt(struct ata_channel *chp) |
| 239 | { |
| 240 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 241 | |
| 242 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); |
| 243 | } |
| 244 | |
| 245 | static void |
| 246 | siisata_enable_port_interrupt(struct ata_channel *chp) |
| 247 | { |
| 248 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 249 | |
| 250 | /* clear any interrupts */ |
| 251 | (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); |
| 252 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); |
| 253 | /* and enable CmdErrr+CmdCmpl interrupting */ |
| 254 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), |
| 255 | PR_PIS_CMDERRR | PR_PIS_CMDCMPL); |
| 256 | } |
| 257 | |
| 258 | static void |
| 259 | siisata_init_port(struct siisata_softc *sc, int port) |
| 260 | { |
| 261 | struct siisata_channel *schp; |
| 262 | struct ata_channel *chp; |
| 263 | |
| 264 | schp = &sc->sc_channels[port]; |
| 265 | chp = (struct ata_channel *)schp; |
| 266 | |
| 267 | /* come out of reset, 64-bit activation */ |
| 268 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), |
| 269 | PR_PC_32BA | PR_PC_PORT_RESET); |
| 270 | /* initialize port */ |
| 271 | siisata_reinit_port(chp); |
| 272 | /* enable CmdErrr+CmdCmpl interrupting */ |
| 273 | siisata_enable_port_interrupt(chp); |
| 274 | /* enable port interrupt */ |
| 275 | GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); |
| 276 | } |
| 277 | |
| 278 | static void |
| 279 | siisata_attach_port(struct siisata_softc *sc, int port) |
| 280 | { |
| 281 | int j; |
| 282 | int dmasize; |
| 283 | int error; |
| 284 | void *prbp; |
| 285 | struct siisata_channel *schp; |
| 286 | struct ata_channel *chp; |
| 287 | |
| 288 | schp = &sc->sc_channels[port]; |
| 289 | chp = (struct ata_channel *)schp; |
| 290 | sc->sc_chanarray[port] = chp; |
| 291 | chp->ch_channel = port; |
| 292 | chp->ch_atac = &sc->sc_atac; |
| 293 | chp->ch_queue = malloc(sizeof(struct ata_queue), |
| 294 | M_DEVBUF, M_NOWAIT|M_ZERO); |
| 295 | if (chp->ch_queue == NULL) { |
| 296 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 297 | "port %d: can't allocate memory " |
| 298 | "for command queue\n" , chp->ch_channel); |
| 299 | return; |
| 300 | } |
| 301 | |
| 302 | dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; |
| 303 | |
| 304 | SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n" , SIISATANAME(sc), |
| 305 | __func__, dmasize), DEBUG_FUNCS); |
| 306 | |
| 307 | error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, |
| 308 | &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); |
| 309 | if (error) { |
| 310 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 311 | "unable to allocate PRB table memory, " |
| 312 | "error=%d\n" , error); |
| 313 | return; |
| 314 | } |
| 315 | |
| 316 | error = bus_dmamem_map(sc->sc_dmat, |
| 317 | &schp->sch_prb_seg, schp->sch_prb_nseg, |
| 318 | dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); |
| 319 | if (error) { |
| 320 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 321 | "unable to map PRB table memory, " |
| 322 | "error=%d\n" , error); |
| 323 | bus_dmamem_free(sc->sc_dmat, |
| 324 | &schp->sch_prb_seg, schp->sch_prb_nseg); |
| 325 | return; |
| 326 | } |
| 327 | |
| 328 | error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, |
| 329 | BUS_DMA_NOWAIT, &schp->sch_prbd); |
| 330 | if (error) { |
| 331 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 332 | "unable to create PRB table map, " |
| 333 | "error=%d\n" , error); |
| 334 | bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); |
| 335 | bus_dmamem_free(sc->sc_dmat, |
| 336 | &schp->sch_prb_seg, schp->sch_prb_nseg); |
| 337 | return; |
| 338 | } |
| 339 | |
| 340 | error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, |
| 341 | prbp, dmasize, NULL, BUS_DMA_NOWAIT); |
| 342 | if (error) { |
| 343 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 344 | "unable to load PRB table map, " |
| 345 | "error=%d\n" , error); |
| 346 | bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); |
| 347 | bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); |
| 348 | bus_dmamem_free(sc->sc_dmat, |
| 349 | &schp->sch_prb_seg, schp->sch_prb_nseg); |
| 350 | return; |
| 351 | } |
| 352 | |
| 353 | for (j = 0; j < SIISATA_MAX_SLOTS; j++) { |
| 354 | schp->sch_prb[j] = (struct siisata_prb *) |
| 355 | ((char *)prbp + SIISATA_CMD_SIZE * j); |
| 356 | schp->sch_bus_prb[j] = |
| 357 | schp->sch_prbd->dm_segs[0].ds_addr + |
| 358 | SIISATA_CMD_SIZE * j; |
| 359 | error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, |
| 360 | SIISATA_NSGE, MAXPHYS, 0, |
| 361 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, |
| 362 | &schp->sch_datad[j]); |
| 363 | if (error) { |
| 364 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 365 | "couldn't create xfer DMA map, error=%d\n" , |
| 366 | error); |
| 367 | return; |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | if (bus_space_subregion(sc->sc_prt, sc->sc_prh, |
| 372 | PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { |
| 373 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 374 | "couldn't map port %d SStatus regs\n" , |
| 375 | chp->ch_channel); |
| 376 | return; |
| 377 | } |
| 378 | if (bus_space_subregion(sc->sc_prt, sc->sc_prh, |
| 379 | PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { |
| 380 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 381 | "couldn't map port %d SControl regs\n" , |
| 382 | chp->ch_channel); |
| 383 | return; |
| 384 | } |
| 385 | if (bus_space_subregion(sc->sc_prt, sc->sc_prh, |
| 386 | PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { |
| 387 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 388 | "couldn't map port %d SError regs\n" , |
| 389 | chp->ch_channel); |
| 390 | return; |
| 391 | } |
| 392 | |
| 393 | siisata_init_port(sc, port); |
| 394 | |
| 395 | ata_channel_attach(chp); |
| 396 | |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | int |
| 401 | siisata_detach(struct siisata_softc *sc, int flags) |
| 402 | { |
| 403 | struct atac_softc *atac = &sc->sc_atac; |
| 404 | struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; |
| 405 | struct siisata_channel *schp; |
| 406 | struct ata_channel *chp; |
| 407 | int i, j, error; |
| 408 | |
| 409 | for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { |
| 410 | schp = &sc->sc_channels[i]; |
| 411 | chp = sc->sc_chanarray[i]; |
| 412 | |
| 413 | if (chp->atabus == NULL) |
| 414 | continue; |
| 415 | if ((error = config_detach(chp->atabus, flags)) != 0) |
| 416 | return error; |
| 417 | |
| 418 | for (j = 0; j < SIISATA_MAX_SLOTS; j++) |
| 419 | bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); |
| 420 | |
| 421 | bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); |
| 422 | bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); |
| 423 | bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], |
| 424 | SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); |
| 425 | bus_dmamem_free(sc->sc_dmat, |
| 426 | &schp->sch_prb_seg, schp->sch_prb_nseg); |
| 427 | |
| 428 | free(chp->ch_queue, M_DEVBUF); |
| 429 | chp->atabus = NULL; |
| 430 | } |
| 431 | |
| 432 | if (adapt->adapt_refcnt != 0) |
| 433 | return EBUSY; |
| 434 | |
| 435 | /* leave the chip in reset */ |
| 436 | GRWRITE(sc, GR_GC, GR_GC_GLBLRST); |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | void |
| 442 | siisata_resume(struct siisata_softc *sc) |
| 443 | { |
| 444 | int i; |
| 445 | |
| 446 | /* come out of reset state */ |
| 447 | GRWRITE(sc, GR_GC, 0); |
| 448 | |
| 449 | for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { |
| 450 | siisata_init_port(sc, i); |
| 451 | } |
| 452 | |
| 453 | } |
| 454 | |
| 455 | int |
| 456 | siisata_intr(void *v) |
| 457 | { |
| 458 | struct siisata_softc *sc = v; |
| 459 | uint32_t is; |
| 460 | int i, r = 0; |
| 461 | while ((is = GRREAD(sc, GR_GIS))) { |
| 462 | SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n" , |
| 463 | SIISATANAME(sc), __func__, is), DEBUG_INTR); |
| 464 | r = 1; |
| 465 | for (i = 0; i < sc->sc_atac.atac_nchannels; i++) |
| 466 | if (is & GR_GIS_PXIS(i)) |
| 467 | siisata_intr_port(&sc->sc_channels[i]); |
| 468 | } |
| 469 | return r; |
| 470 | } |
| 471 | |
| 472 | static void |
| 473 | siisata_intr_port(struct siisata_channel *schp) |
| 474 | { |
| 475 | struct siisata_softc *sc; |
| 476 | struct ata_channel *chp; |
| 477 | struct ata_xfer *xfer; |
| 478 | int slot; |
| 479 | uint32_t pss, pis; |
| 480 | uint32_t prbfis; |
| 481 | |
| 482 | sc = (struct siisata_softc *)schp->ata_channel.ch_atac; |
| 483 | chp = &schp->ata_channel; |
| 484 | xfer = chp->ch_queue->active_xfer; |
| 485 | slot = SIISATA_NON_NCQ_SLOT; |
| 486 | |
| 487 | pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); |
| 488 | |
| 489 | SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x " , |
| 490 | SIISATANAME(sc), __func__, chp->ch_channel, pis), DEBUG_INTR); |
| 491 | |
| 492 | if (pis & PR_PIS_CMDCMPL) { |
| 493 | /* get slot status, clearing completion interrupt */ |
| 494 | pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); |
| 495 | SIISATA_DEBUG_PRINT(("pss 0x%x\n" , pss), DEBUG_INTR); |
| 496 | /* is this expected? */ |
| 497 | /* XXX improve */ |
| 498 | if ((schp->sch_active_slots & __BIT(slot)) == 0) { |
| 499 | aprint_error( "%s: unexpected command " |
| 500 | "completion on port %d\n" , |
| 501 | SIISATANAME(sc), chp->ch_channel); |
| 502 | return; |
| 503 | } |
| 504 | if ((~pss & __BIT(slot)) == 0) { |
| 505 | aprint_error( "%s: unknown slot " |
| 506 | "completion on port %d, pss 0x%x\n" , |
| 507 | SIISATANAME(sc), chp->ch_channel, pss); |
| 508 | return; |
| 509 | } |
| 510 | } else if (pis & PR_PIS_CMDERRR) { |
| 511 | uint32_t ec; |
| 512 | |
| 513 | /* emulate a CRC error by default */ |
| 514 | chp->ch_status = WDCS_ERR; |
| 515 | chp->ch_error = WDCE_CRC; |
| 516 | |
| 517 | ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); |
| 518 | SIISATA_DEBUG_PRINT(("ec %d\n" , ec), DEBUG_INTR); |
| 519 | if (ec <= PR_PCE_DATAFISERROR) { |
| 520 | if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { |
| 521 | /* read in specific information about error */ |
| 522 | prbfis = bus_space_read_stream_4( |
| 523 | sc->sc_prt, sc->sc_prh, |
| 524 | PRSX(chp->ch_channel, slot, PRSO_FIS)); |
| 525 | /* set ch_status and ch_error */ |
| 526 | satafis_rdh_parse(chp, (uint8_t *)&prbfis); |
| 527 | } |
| 528 | siisata_reinit_port(chp); |
| 529 | } else { |
| 530 | aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" |
| 531 | " on channel %d (ctx 0x%x), resetting\n" , |
| 532 | ec, chp->ch_channel, |
| 533 | PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); |
| 534 | /* okay, we have a "Fatal Error" */ |
| 535 | siisata_device_reset(chp); |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | /* clear some (ok, all) ints */ |
| 540 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); |
| 541 | if (xfer && xfer->c_intr) |
| 542 | xfer->c_intr(chp, xfer, slot); |
| 543 | |
| 544 | return; |
| 545 | } |
| 546 | |
| 547 | void |
| 548 | siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) |
| 549 | { |
| 550 | struct ata_channel *chp = drvp->chnl_softc; |
| 551 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 552 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 553 | struct siisata_prb *prb; |
| 554 | int slot = SIISATA_NON_NCQ_SLOT; |
| 555 | int i; |
| 556 | |
| 557 | /* wait for ready */ |
| 558 | while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) |
| 559 | DELAY(10); |
| 560 | |
| 561 | prb = schp->sch_prb[slot]; |
| 562 | memset(prb, 0, sizeof(struct siisata_prb)); |
| 563 | prb->prb_control = |
| 564 | htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); |
| 565 | KASSERT(drvp->drive <= PMP_PORT_CTL); |
| 566 | prb->prb_fis[rhd_c] = drvp->drive; |
| 567 | |
| 568 | siisata_activate_prb(schp, slot); |
| 569 | |
| 570 | for(i = 0; i < 3100; i++) { |
| 571 | if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & |
| 572 | PR_PXSS(slot)) == 0) |
| 573 | break; |
| 574 | if (flags & AT_WAIT) |
| 575 | tsleep(schp, PRIBIO, "siiprb" , mstohz(10)); |
| 576 | else |
| 577 | DELAY(10000); |
| 578 | } |
| 579 | |
| 580 | siisata_deactivate_prb(schp, slot); |
| 581 | if (i == 3100) { |
| 582 | /* timeout */ |
| 583 | siisata_device_reset(chp); |
| 584 | if (sigp) |
| 585 | *sigp = 0xffffffff; |
| 586 | } else { |
| 587 | /* read the signature out of the FIS */ |
| 588 | if (sigp) { |
| 589 | *sigp = 0; |
| 590 | *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, |
| 591 | PRSO_FIS+0x4)) & 0x00ffffff) << 8; |
| 592 | *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, |
| 593 | PRSO_FIS+0xc)) & 0xff; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | #if 1 |
| 598 | /* attempt to downgrade signaling in event of CRC error */ |
| 599 | /* XXX should be part of the MI (S)ATA subsystem */ |
| 600 | if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { |
| 601 | bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, |
| 602 | SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); |
| 603 | DELAY(10); |
| 604 | bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, |
| 605 | SControl_IPM_NONE | SControl_SPD_G1); |
| 606 | DELAY(10); |
| 607 | for (;;) { |
| 608 | if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) |
| 609 | & SStatus_DET_mask) == SStatus_DET_DEV) |
| 610 | break; |
| 611 | DELAY(10); |
| 612 | } |
| 613 | } |
| 614 | #endif |
| 615 | |
| 616 | #if 1 |
| 617 | chp->ch_status = 0; |
| 618 | chp->ch_error = 0; |
| 619 | #endif |
| 620 | return; |
| 621 | } |
| 622 | |
| 623 | void |
| 624 | siisata_reset_channel(struct ata_channel *chp, int flags) |
| 625 | { |
| 626 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 627 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 628 | |
| 629 | SIISATA_DEBUG_PRINT(("%s: %s\n" , SIISATANAME(sc), __func__), |
| 630 | DEBUG_FUNCS); |
| 631 | |
| 632 | if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, |
| 633 | schp->sch_sstatus, flags) != SStatus_DET_DEV) { |
| 634 | aprint_error("%s port %d: reset failed\n" , |
| 635 | SIISATANAME(sc), chp->ch_channel); |
| 636 | /* XXX and then ? */ |
| 637 | } |
| 638 | /* wait for ready */ |
| 639 | while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) |
| 640 | DELAY(10); |
| 641 | PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), |
| 642 | PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); |
| 643 | if (chp->ch_queue->active_xfer) { |
| 644 | chp->ch_queue->active_xfer->c_kill_xfer(chp, |
| 645 | chp->ch_queue->active_xfer, KILL_RESET); |
| 646 | } |
| 647 | |
| 648 | return; |
| 649 | } |
| 650 | |
| 651 | int |
| 652 | siisata_ata_addref(struct ata_drive_datas *drvp) |
| 653 | { |
| 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | void |
| 658 | siisata_ata_delref(struct ata_drive_datas *drvp) |
| 659 | { |
| 660 | return; |
| 661 | } |
| 662 | |
| 663 | void |
| 664 | siisata_killpending(struct ata_drive_datas *drvp) |
| 665 | { |
| 666 | return; |
| 667 | } |
| 668 | |
| 669 | void |
| 670 | siisata_probe_drive(struct ata_channel *chp) |
| 671 | { |
| 672 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 673 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 674 | int i; |
| 675 | uint32_t sig; |
| 676 | int slot = SIISATA_NON_NCQ_SLOT; |
| 677 | struct siisata_prb *prb; |
| 678 | bool timed_out; |
| 679 | |
| 680 | SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n" , SIISATANAME(sc), |
| 681 | __func__, chp->ch_channel), DEBUG_FUNCS); |
| 682 | |
| 683 | /* |
| 684 | * disable port interrupt as we're polling for PHY up and |
| 685 | * prb completion |
| 686 | */ |
| 687 | siisata_disable_port_interrupt(chp); |
| 688 | |
| 689 | switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, |
| 690 | schp->sch_sstatus, AT_WAIT)) { |
| 691 | case SStatus_DET_DEV: |
| 692 | /* clear any interrupts */ |
| 693 | (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); |
| 694 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); |
| 695 | /* wait for ready */ |
| 696 | while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) |
| 697 | & PR_PS_PORT_READY)) |
| 698 | DELAY(10); |
| 699 | prb = schp->sch_prb[slot]; |
| 700 | memset(prb, 0, sizeof(struct siisata_prb)); |
| 701 | prb->prb_control = htole16(PRB_CF_SOFT_RESET); |
| 702 | prb->prb_fis[rhd_c] = PMP_PORT_CTL; |
| 703 | |
| 704 | siisata_activate_prb(schp, slot); |
| 705 | |
| 706 | timed_out = 1; |
| 707 | for(i = 0; i < 3100; i++) { |
| 708 | if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & |
| 709 | PR_PXSS(slot)) == 0) { |
| 710 | /* prb completed */ |
| 711 | timed_out = 0; |
| 712 | break; |
| 713 | } |
| 714 | if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & |
| 715 | (PR_PIS_CMDERRR << 16)) { |
| 716 | /* we got an error; handle as timeout */ |
| 717 | break; |
| 718 | } |
| 719 | |
| 720 | tsleep(schp, PRIBIO, "siiprb" , mstohz(10)); |
| 721 | } |
| 722 | |
| 723 | siisata_deactivate_prb(schp, slot); |
| 724 | if (timed_out) { |
| 725 | aprint_error_dev(sc->sc_atac.atac_dev, |
| 726 | "SOFT_RESET failed on port %d (error %d PSS 0x%x), " |
| 727 | "resetting\n" , chp->ch_channel, |
| 728 | PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), |
| 729 | PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); |
| 730 | siisata_reinit_port(chp); |
| 731 | break; |
| 732 | } |
| 733 | |
| 734 | /* read the signature out of the FIS */ |
| 735 | sig = 0; |
| 736 | sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, |
| 737 | PRSO_FIS+0x4)) & 0x00ffffff) << 8; |
| 738 | sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, |
| 739 | PRSO_FIS+0xc)) & 0xff; |
| 740 | |
| 741 | SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n" , SIISATANAME(sc), |
| 742 | __func__, sig), DEBUG_PROBE); |
| 743 | |
| 744 | if (sig == 0x96690101) |
| 745 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), |
| 746 | PR_PC_PMP_ENABLE); |
| 747 | sata_interpret_sig(chp, 0, sig); |
| 748 | break; |
| 749 | default: |
| 750 | break; |
| 751 | } |
| 752 | |
| 753 | siisata_enable_port_interrupt(chp); |
| 754 | SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n" , SIISATANAME(sc), |
| 755 | __func__, chp->ch_channel), DEBUG_PROBE); |
| 756 | return; |
| 757 | } |
| 758 | |
| 759 | void |
| 760 | siisata_setup_channel(struct ata_channel *chp) |
| 761 | { |
| 762 | return; |
| 763 | } |
| 764 | |
| 765 | int |
| 766 | siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) |
| 767 | { |
| 768 | struct ata_channel *chp = drvp->chnl_softc; |
| 769 | struct ata_xfer *xfer; |
| 770 | int ret; |
| 771 | int s; |
| 772 | |
| 773 | SIISATA_DEBUG_PRINT(("%s: %s begins\n" , |
| 774 | SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), |
| 775 | DEBUG_FUNCS); |
| 776 | |
| 777 | xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? |
| 778 | ATAXF_CANSLEEP : ATAXF_NOSLEEP); |
| 779 | if (xfer == NULL) |
| 780 | return ATACMD_TRY_AGAIN; |
| 781 | if (ata_c->flags & AT_POLL) |
| 782 | xfer->c_flags |= C_POLL; |
| 783 | if (ata_c->flags & AT_WAIT) |
| 784 | xfer->c_flags |= C_WAIT; |
| 785 | xfer->c_drive = drvp->drive; |
| 786 | xfer->c_databuf = ata_c->data; |
| 787 | xfer->c_bcount = ata_c->bcount; |
| 788 | xfer->c_cmd = ata_c; |
| 789 | xfer->c_start = siisata_cmd_start; |
| 790 | xfer->c_intr = siisata_cmd_complete; |
| 791 | xfer->c_kill_xfer = siisata_cmd_kill_xfer; |
| 792 | s = splbio(); |
| 793 | ata_exec_xfer(chp, xfer); |
| 794 | #ifdef DIAGNOSTIC |
| 795 | if ((ata_c->flags & AT_POLL) != 0 && |
| 796 | (ata_c->flags & AT_DONE) == 0) |
| 797 | panic("%s: polled command not done" , __func__); |
| 798 | #endif |
| 799 | if (ata_c->flags & AT_DONE) { |
| 800 | ret = ATACMD_COMPLETE; |
| 801 | } else { |
| 802 | if (ata_c->flags & AT_WAIT) { |
| 803 | while ((ata_c->flags & AT_DONE) == 0) { |
| 804 | SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n" , |
| 805 | SIISATANAME( |
| 806 | (struct siisata_softc *)chp->ch_atac), |
| 807 | __func__), DEBUG_FUNCS); |
| 808 | tsleep(ata_c, PRIBIO, "siicmd" , 0); |
| 809 | } |
| 810 | ret = ATACMD_COMPLETE; |
| 811 | } else { |
| 812 | ret = ATACMD_QUEUED; |
| 813 | } |
| 814 | } |
| 815 | splx(s); |
| 816 | SIISATA_DEBUG_PRINT( ("%s: %s ends\n" , |
| 817 | SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), |
| 818 | DEBUG_FUNCS); |
| 819 | return ret; |
| 820 | } |
| 821 | |
| 822 | void |
| 823 | siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) |
| 824 | { |
| 825 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 826 | struct ata_command *ata_c = xfer->c_cmd; |
| 827 | int slot = SIISATA_NON_NCQ_SLOT; |
| 828 | struct siisata_prb *prb; |
| 829 | int i; |
| 830 | |
| 831 | SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n" , |
| 832 | SIISATANAME((struct siisata_softc *)chp->ch_atac), |
| 833 | __func__, chp->ch_channel, xfer->c_drive, |
| 834 | ata_c->r_command, slot), |
| 835 | DEBUG_FUNCS|DEBUG_XFERS); |
| 836 | |
| 837 | chp->ch_status = 0; |
| 838 | chp->ch_error = 0; |
| 839 | |
| 840 | prb = schp->sch_prb[slot]; |
| 841 | memset(prb, 0, sizeof(struct siisata_prb)); |
| 842 | |
| 843 | satafis_rhd_construct_cmd(ata_c, prb->prb_fis); |
| 844 | KASSERT(xfer->c_drive <= PMP_PORT_CTL); |
| 845 | prb->prb_fis[rhd_c] |= xfer->c_drive; |
| 846 | |
| 847 | memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); |
| 848 | |
| 849 | if (siisata_dma_setup(chp, slot, |
| 850 | (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, |
| 851 | ata_c->bcount, |
| 852 | (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { |
| 853 | ata_c->flags |= AT_DF; |
| 854 | siisata_cmd_complete(chp, xfer, slot); |
| 855 | return; |
| 856 | } |
| 857 | |
| 858 | if (xfer->c_flags & C_POLL) { |
| 859 | /* polled command, disable interrupts */ |
| 860 | prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); |
| 861 | siisata_disable_port_interrupt(chp); |
| 862 | } |
| 863 | |
| 864 | /* go for it */ |
| 865 | siisata_activate_prb(schp, slot); |
| 866 | |
| 867 | if ((ata_c->flags & AT_POLL) == 0) { |
| 868 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
| 869 | callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), |
| 870 | siisata_timeout, chp); |
| 871 | goto out; |
| 872 | } |
| 873 | |
| 874 | /* |
| 875 | * polled command |
| 876 | */ |
| 877 | for (i = 0; i < ata_c->timeout / 10; i++) { |
| 878 | if (ata_c->flags & AT_DONE) |
| 879 | break; |
| 880 | siisata_intr_port(schp); |
| 881 | DELAY(1000); |
| 882 | } |
| 883 | |
| 884 | if ((ata_c->flags & AT_DONE) == 0) { |
| 885 | siisata_timeout(chp); |
| 886 | } |
| 887 | |
| 888 | /* reenable interrupts */ |
| 889 | siisata_enable_port_interrupt(chp); |
| 890 | out: |
| 891 | SIISATA_DEBUG_PRINT( |
| 892 | ("%s: %s: done\n" , SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); |
| 893 | return; |
| 894 | } |
| 895 | |
| 896 | void |
| 897 | siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, |
| 898 | int reason) |
| 899 | { |
| 900 | int slot = SIISATA_NON_NCQ_SLOT; |
| 901 | |
| 902 | struct ata_command *ata_c = xfer->c_cmd; |
| 903 | switch (reason) { |
| 904 | case KILL_GONE: |
| 905 | ata_c->flags |= AT_GONE; |
| 906 | break; |
| 907 | case KILL_RESET: |
| 908 | ata_c->flags |= AT_RESET; |
| 909 | break; |
| 910 | default: |
| 911 | panic("%s: port %d: unknown reason %d" , |
| 912 | __func__, chp->ch_channel, reason); |
| 913 | } |
| 914 | siisata_cmd_done(chp, xfer, slot); |
| 915 | } |
| 916 | |
| 917 | int |
| 918 | siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) |
| 919 | { |
| 920 | struct ata_command *ata_c = xfer->c_cmd; |
| 921 | #ifdef SIISATA_DEBUG |
| 922 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 923 | #endif |
| 924 | |
| 925 | SIISATA_DEBUG_PRINT( |
| 926 | ("%s: %s\n" , SIISATANAME(sc), __func__), DEBUG_FUNCS|DEBUG_XFERS); |
| 927 | |
| 928 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
| 929 | if (xfer->c_flags & C_TIMEOU) |
| 930 | ata_c->flags |= AT_TIMEOU; |
| 931 | else |
| 932 | callout_stop(&chp->ch_callout); |
| 933 | |
| 934 | if (chp->ch_status & WDCS_BSY) { |
| 935 | ata_c->flags |= AT_TIMEOU; |
| 936 | } else if (chp->ch_status & WDCS_ERR) { |
| 937 | ata_c->r_error = chp->ch_error; |
| 938 | ata_c->flags |= AT_ERROR; |
| 939 | } |
| 940 | |
| 941 | if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { |
| 942 | siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); |
| 943 | chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; |
| 944 | wakeup(&chp->ch_queue->active_xfer); |
| 945 | return 0; |
| 946 | } else |
| 947 | siisata_cmd_done(chp, xfer, slot); |
| 948 | |
| 949 | return 0; |
| 950 | } |
| 951 | |
| 952 | void |
| 953 | siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) |
| 954 | { |
| 955 | uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; |
| 956 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 957 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 958 | struct ata_command *ata_c = xfer->c_cmd; |
| 959 | uint16_t *idwordbuf; |
| 960 | int i; |
| 961 | |
| 962 | SIISATA_DEBUG_PRINT( |
| 963 | ("%s: %s flags 0x%x error 0x%x\n" , SIISATANAME(sc), __func__, |
| 964 | ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); |
| 965 | |
| 966 | siisata_deactivate_prb(schp, slot); |
| 967 | |
| 968 | if (ata_c->flags & (AT_READ | AT_WRITE)) { |
| 969 | bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, |
| 970 | schp->sch_datad[slot]->dm_mapsize, |
| 971 | (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : |
| 972 | BUS_DMASYNC_POSTWRITE); |
| 973 | bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); |
| 974 | } |
| 975 | |
| 976 | if (ata_c->flags & AT_READREG) { |
| 977 | bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, |
| 978 | PRSX(chp->ch_channel, slot, PRSO_FIS), |
| 979 | fis, __arraycount(fis)); |
| 980 | satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); |
| 981 | } |
| 982 | |
| 983 | /* correct the endianess of IDENTIFY data */ |
| 984 | if (ata_c->r_command == WDCC_IDENTIFY || |
| 985 | ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { |
| 986 | idwordbuf = xfer->c_databuf; |
| 987 | for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { |
| 988 | idwordbuf[i] = le16toh(idwordbuf[i]); |
| 989 | } |
| 990 | } |
| 991 | |
| 992 | ata_c->flags |= AT_DONE; |
| 993 | if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) |
| 994 | ata_c->flags |= AT_XFDONE; |
| 995 | |
| 996 | chp->ch_queue->active_xfer = NULL; |
| 997 | ata_free_xfer(chp, xfer); |
| 998 | if (ata_c->flags & AT_WAIT) |
| 999 | wakeup(ata_c); |
| 1000 | else if (ata_c->callback) |
| 1001 | ata_c->callback(ata_c->callback_arg); |
| 1002 | atastart(chp); |
| 1003 | return; |
| 1004 | } |
| 1005 | |
| 1006 | int |
| 1007 | siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) |
| 1008 | { |
| 1009 | struct ata_channel *chp = drvp->chnl_softc; |
| 1010 | struct ata_xfer *xfer; |
| 1011 | |
| 1012 | SIISATA_DEBUG_PRINT( ("%s: %s.\n" , |
| 1013 | SIISATANAME((struct siisata_softc *)chp->ch_atac), |
| 1014 | __func__), DEBUG_FUNCS); |
| 1015 | |
| 1016 | xfer = ata_get_xfer(ATAXF_NOSLEEP); |
| 1017 | if (xfer == NULL) |
| 1018 | return ATACMD_TRY_AGAIN; |
| 1019 | if (ata_bio->flags & ATA_POLL) |
| 1020 | xfer->c_flags |= C_POLL; |
| 1021 | xfer->c_drive = drvp->drive; |
| 1022 | xfer->c_cmd = ata_bio; |
| 1023 | xfer->c_databuf = ata_bio->databuf; |
| 1024 | xfer->c_bcount = ata_bio->bcount; |
| 1025 | xfer->c_start = siisata_bio_start; |
| 1026 | xfer->c_intr = siisata_bio_complete; |
| 1027 | xfer->c_kill_xfer = siisata_bio_kill_xfer; |
| 1028 | ata_exec_xfer(chp, xfer); |
| 1029 | return (ata_bio->flags & ATA_ITSDONE) ? |
| 1030 | ATACMD_COMPLETE : ATACMD_QUEUED; |
| 1031 | } |
| 1032 | |
| 1033 | void |
| 1034 | siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) |
| 1035 | { |
| 1036 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1037 | struct siisata_prb *prb; |
| 1038 | struct ata_bio *ata_bio = xfer->c_cmd; |
| 1039 | int slot = SIISATA_NON_NCQ_SLOT; |
| 1040 | int i; |
| 1041 | |
| 1042 | SIISATA_DEBUG_PRINT( |
| 1043 | ("%s: %s port %d, slot %d\n" , |
| 1044 | SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, chp->ch_channel, slot), |
| 1045 | DEBUG_FUNCS); |
| 1046 | |
| 1047 | chp->ch_status = 0; |
| 1048 | chp->ch_error = 0; |
| 1049 | |
| 1050 | prb = schp->sch_prb[slot]; |
| 1051 | memset(prb, 0, sizeof(struct siisata_prb)); |
| 1052 | |
| 1053 | satafis_rhd_construct_bio(xfer, prb->prb_fis); |
| 1054 | KASSERT(xfer->c_drive <= PMP_PORT_CTL); |
| 1055 | prb->prb_fis[rhd_c] |= xfer->c_drive; |
| 1056 | |
| 1057 | memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); |
| 1058 | |
| 1059 | if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, |
| 1060 | (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { |
| 1061 | ata_bio->error = ERR_DMA; |
| 1062 | ata_bio->r_error = 0; |
| 1063 | siisata_bio_complete(chp, xfer, slot); |
| 1064 | return; |
| 1065 | } |
| 1066 | |
| 1067 | if (xfer->c_flags & C_POLL) { |
| 1068 | /* polled command, disable interrupts */ |
| 1069 | prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); |
| 1070 | siisata_disable_port_interrupt(chp); |
| 1071 | } |
| 1072 | |
| 1073 | siisata_activate_prb(schp, slot); |
| 1074 | |
| 1075 | if ((ata_bio->flags & ATA_POLL) == 0) { |
| 1076 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
| 1077 | callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), |
| 1078 | siisata_timeout, chp); |
| 1079 | goto out; |
| 1080 | } |
| 1081 | |
| 1082 | /* |
| 1083 | * polled command |
| 1084 | */ |
| 1085 | for (i = 0; i < ATA_DELAY / 10; i++) { |
| 1086 | if (ata_bio->flags & ATA_ITSDONE) |
| 1087 | break; |
| 1088 | siisata_intr_port(schp); |
| 1089 | DELAY(1000); |
| 1090 | } |
| 1091 | |
| 1092 | siisata_enable_port_interrupt(chp); |
| 1093 | out: |
| 1094 | SIISATA_DEBUG_PRINT( |
| 1095 | ("%s: %s: done\n" , SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); |
| 1096 | return; |
| 1097 | } |
| 1098 | |
| 1099 | void |
| 1100 | siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, |
| 1101 | int reason) |
| 1102 | { |
| 1103 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1104 | struct ata_bio *ata_bio = xfer->c_cmd; |
| 1105 | int drive = xfer->c_drive; |
| 1106 | int slot = SIISATA_NON_NCQ_SLOT; |
| 1107 | |
| 1108 | SIISATA_DEBUG_PRINT(("%s: %s: port %d\n" , |
| 1109 | SIISATANAME((struct siisata_softc *)chp->ch_atac), |
| 1110 | __func__, chp->ch_channel), DEBUG_FUNCS); |
| 1111 | |
| 1112 | siisata_deactivate_prb(schp, slot); |
| 1113 | |
| 1114 | ata_free_xfer(chp, xfer); |
| 1115 | ata_bio->flags |= ATA_ITSDONE; |
| 1116 | switch (reason) { |
| 1117 | case KILL_GONE: |
| 1118 | ata_bio->error = ERR_NODEV; |
| 1119 | break; |
| 1120 | case KILL_RESET: |
| 1121 | ata_bio->error = ERR_RESET; |
| 1122 | break; |
| 1123 | default: |
| 1124 | panic("%s: port %d: unknown reason %d" , |
| 1125 | __func__, chp->ch_channel, reason); |
| 1126 | } |
| 1127 | ata_bio->r_error = WDCE_ABRT; |
| 1128 | (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); |
| 1129 | } |
| 1130 | |
| 1131 | int |
| 1132 | siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) |
| 1133 | { |
| 1134 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 1135 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1136 | struct ata_bio *ata_bio = xfer->c_cmd; |
| 1137 | int drive = xfer->c_drive; |
| 1138 | |
| 1139 | schp->sch_active_slots &= ~__BIT(slot); |
| 1140 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
| 1141 | if (xfer->c_flags & C_TIMEOU) { |
| 1142 | ata_bio->error = TIMEOUT; |
| 1143 | } else { |
| 1144 | callout_stop(&chp->ch_callout); |
| 1145 | ata_bio->error = NOERROR; |
| 1146 | } |
| 1147 | |
| 1148 | bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, |
| 1149 | schp->sch_datad[slot]->dm_mapsize, |
| 1150 | (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : |
| 1151 | BUS_DMASYNC_POSTWRITE); |
| 1152 | bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); |
| 1153 | |
| 1154 | if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { |
| 1155 | siisata_bio_kill_xfer(chp, xfer, KILL_GONE); |
| 1156 | chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; |
| 1157 | wakeup(&chp->ch_queue->active_xfer); |
| 1158 | return 0; |
| 1159 | } |
| 1160 | |
| 1161 | chp->ch_queue->active_xfer = NULL; |
| 1162 | ata_free_xfer(chp, xfer); |
| 1163 | ata_bio->flags |= ATA_ITSDONE; |
| 1164 | if (chp->ch_status & WDCS_DWF) { |
| 1165 | ata_bio->error = ERR_DF; |
| 1166 | } else if (chp->ch_status & WDCS_ERR) { |
| 1167 | ata_bio->error = ERROR; |
| 1168 | ata_bio->r_error = chp->ch_error; |
| 1169 | } else if (chp->ch_status & WDCS_CORR) |
| 1170 | ata_bio->flags |= ATA_CORR; |
| 1171 | |
| 1172 | SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld" , SIISATANAME(sc), |
| 1173 | __func__, ata_bio->bcount), DEBUG_XFERS); |
| 1174 | if (ata_bio->error == NOERROR) { |
| 1175 | if (ata_bio->flags & ATA_READ) |
| 1176 | ata_bio->bcount -= |
| 1177 | PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); |
| 1178 | else |
| 1179 | ata_bio->bcount = 0; |
| 1180 | } |
| 1181 | SIISATA_DEBUG_PRINT((" now %ld\n" , ata_bio->bcount), DEBUG_XFERS); |
| 1182 | if (ata_bio->flags & ATA_POLL) |
| 1183 | return 1; |
| 1184 | (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); |
| 1185 | atastart(chp); |
| 1186 | return 0; |
| 1187 | } |
| 1188 | |
| 1189 | void |
| 1190 | siisata_timeout(void *v) |
| 1191 | { |
| 1192 | struct ata_channel *chp = (struct ata_channel *)v; |
| 1193 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
| 1194 | int slot = SIISATA_NON_NCQ_SLOT; |
| 1195 | int s = splbio(); |
| 1196 | SIISATA_DEBUG_PRINT(("%s: %p\n" , __func__, xfer), DEBUG_INTR); |
| 1197 | siisata_device_reset(chp); |
| 1198 | if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { |
| 1199 | xfer->c_flags |= C_TIMEOU; |
| 1200 | xfer->c_intr(chp, xfer, slot); |
| 1201 | } |
| 1202 | splx(s); |
| 1203 | } |
| 1204 | |
| 1205 | static int |
| 1206 | siisata_dma_setup(struct ata_channel *chp, int slot, void *data, |
| 1207 | size_t count, int op) |
| 1208 | { |
| 1209 | |
| 1210 | int error, seg; |
| 1211 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 1212 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1213 | |
| 1214 | struct siisata_prb *prbp; |
| 1215 | |
| 1216 | prbp = schp->sch_prb[slot]; |
| 1217 | |
| 1218 | if (data == NULL) { |
| 1219 | goto end; |
| 1220 | } |
| 1221 | |
| 1222 | error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], |
| 1223 | data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); |
| 1224 | if (error) { |
| 1225 | aprint_error("%s port %d: " |
| 1226 | "failed to load xfer in slot %d: error %d\n" , |
| 1227 | SIISATANAME(sc), chp->ch_channel, slot, error); |
| 1228 | return error; |
| 1229 | } |
| 1230 | |
| 1231 | bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, |
| 1232 | schp->sch_datad[slot]->dm_mapsize, |
| 1233 | (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); |
| 1234 | |
| 1235 | /* make sure it's clean */ |
| 1236 | memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); |
| 1237 | |
| 1238 | SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n" , __func__, |
| 1239 | schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), |
| 1240 | DEBUG_FUNCS | DEBUG_DEBUG); |
| 1241 | |
| 1242 | for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { |
| 1243 | prbp->prb_sge[seg].sge_da = |
| 1244 | htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); |
| 1245 | prbp->prb_sge[seg].sge_dc = |
| 1246 | htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); |
| 1247 | prbp->prb_sge[seg].sge_flags = htole32(0); |
| 1248 | } |
| 1249 | prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); |
| 1250 | end: |
| 1251 | return 0; |
| 1252 | } |
| 1253 | |
| 1254 | static void |
| 1255 | siisata_activate_prb(struct siisata_channel *schp, int slot) |
| 1256 | { |
| 1257 | struct siisata_softc *sc; |
| 1258 | bus_size_t offset; |
| 1259 | uint64_t pprb; |
| 1260 | |
| 1261 | sc = (struct siisata_softc *)schp->ata_channel.ch_atac; |
| 1262 | |
| 1263 | KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), |
| 1264 | "%s: trying to activate active slot %d" , SIISATANAME(sc), slot); |
| 1265 | |
| 1266 | SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); |
| 1267 | /* keep track of what's going on */ |
| 1268 | schp->sch_active_slots |= __BIT(slot); |
| 1269 | |
| 1270 | offset = PRO_CARX(schp->ata_channel.ch_channel, slot); |
| 1271 | |
| 1272 | pprb = schp->sch_bus_prb[slot]; |
| 1273 | |
| 1274 | PRWRITE(sc, offset + 0, pprb >> 0); |
| 1275 | PRWRITE(sc, offset + 4, pprb >> 32); |
| 1276 | } |
| 1277 | |
| 1278 | static void |
| 1279 | siisata_deactivate_prb(struct siisata_channel *schp, int slot) |
| 1280 | { |
| 1281 | struct siisata_softc *sc; |
| 1282 | |
| 1283 | sc = (struct siisata_softc *)schp->ata_channel.ch_atac; |
| 1284 | |
| 1285 | KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, |
| 1286 | "%s: trying to deactivate inactive slot %d" , SIISATANAME(sc), |
| 1287 | slot); |
| 1288 | |
| 1289 | schp->sch_active_slots &= ~__BIT(slot); /* mark free */ |
| 1290 | SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); |
| 1291 | } |
| 1292 | |
| 1293 | static void |
| 1294 | siisata_reinit_port(struct ata_channel *chp) |
| 1295 | { |
| 1296 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 1297 | |
| 1298 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); |
| 1299 | while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) |
| 1300 | DELAY(10); |
| 1301 | if (chp->ch_ndrives > 1) |
| 1302 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); |
| 1303 | } |
| 1304 | |
| 1305 | static void |
| 1306 | siisata_device_reset(struct ata_channel *chp) |
| 1307 | { |
| 1308 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 1309 | |
| 1310 | PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); |
| 1311 | while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) |
| 1312 | DELAY(10); |
| 1313 | } |
| 1314 | |
| 1315 | |
| 1316 | #if NATAPIBUS > 0 |
| 1317 | void |
| 1318 | siisata_atapibus_attach(struct atabus_softc *ata_sc) |
| 1319 | { |
| 1320 | struct ata_channel *chp = ata_sc->sc_chan; |
| 1321 | struct atac_softc *atac = chp->ch_atac; |
| 1322 | struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; |
| 1323 | struct scsipi_channel *chan = &chp->ch_atapi_channel; |
| 1324 | |
| 1325 | /* |
| 1326 | * Fill in the scsipi_adapter. |
| 1327 | */ |
| 1328 | adapt->adapt_dev = atac->atac_dev; |
| 1329 | adapt->adapt_nchannels = atac->atac_nchannels; |
| 1330 | adapt->adapt_request = siisata_atapi_scsipi_request; |
| 1331 | adapt->adapt_minphys = siisata_atapi_minphys; |
| 1332 | atac->atac_atapi_adapter.atapi_probe_device = |
| 1333 | siisata_atapi_probe_device; |
| 1334 | |
| 1335 | /* |
| 1336 | * Fill in the scsipi_channel. |
| 1337 | */ |
| 1338 | memset(chan, 0, sizeof(*chan)); |
| 1339 | chan->chan_adapter = adapt; |
| 1340 | chan->chan_bustype = &siisata_atapi_bustype; |
| 1341 | chan->chan_channel = chp->ch_channel; |
| 1342 | chan->chan_flags = SCSIPI_CHAN_OPENINGS; |
| 1343 | chan->chan_openings = 1; |
| 1344 | chan->chan_max_periph = 1; |
| 1345 | chan->chan_ntargets = 1; |
| 1346 | chan->chan_nluns = 1; |
| 1347 | |
| 1348 | chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi" , chan, |
| 1349 | atapiprint); |
| 1350 | } |
| 1351 | |
| 1352 | void |
| 1353 | siisata_atapi_minphys(struct buf *bp) |
| 1354 | { |
| 1355 | if (bp->b_bcount > MAXPHYS) |
| 1356 | bp->b_bcount = MAXPHYS; |
| 1357 | minphys(bp); |
| 1358 | } |
| 1359 | |
| 1360 | /* |
| 1361 | * Kill off all pending xfers for a periph. |
| 1362 | * |
| 1363 | * Must be called at splbio(). |
| 1364 | */ |
| 1365 | void |
| 1366 | siisata_atapi_kill_pending(struct scsipi_periph *periph) |
| 1367 | { |
| 1368 | struct atac_softc *atac = |
| 1369 | device_private(periph->periph_channel->chan_adapter->adapt_dev); |
| 1370 | struct ata_channel *chp = |
| 1371 | atac->atac_channels[periph->periph_channel->chan_channel]; |
| 1372 | |
| 1373 | ata_kill_pending(&chp->ch_drive[periph->periph_target]); |
| 1374 | } |
| 1375 | |
| 1376 | void |
| 1377 | siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, |
| 1378 | int reason) |
| 1379 | { |
| 1380 | struct scsipi_xfer *sc_xfer = xfer->c_cmd; |
| 1381 | |
| 1382 | /* remove this command from xfer queue */ |
| 1383 | switch (reason) { |
| 1384 | case KILL_GONE: |
| 1385 | sc_xfer->error = XS_DRIVER_STUFFUP; |
| 1386 | break; |
| 1387 | case KILL_RESET: |
| 1388 | sc_xfer->error = XS_RESET; |
| 1389 | break; |
| 1390 | default: |
| 1391 | panic("%s: port %d: unknown reason %d" , |
| 1392 | __func__, chp->ch_channel, reason); |
| 1393 | } |
| 1394 | ata_free_xfer(chp, xfer); |
| 1395 | scsipi_done(sc_xfer); |
| 1396 | } |
| 1397 | |
| 1398 | void |
| 1399 | siisata_atapi_probe_device(struct atapibus_softc *sc, int target) |
| 1400 | { |
| 1401 | struct scsipi_channel *chan = sc->sc_channel; |
| 1402 | struct scsipi_periph *periph; |
| 1403 | struct ataparams ids; |
| 1404 | struct ataparams *id = &ids; |
| 1405 | struct siisata_softc *siic = |
| 1406 | device_private(chan->chan_adapter->adapt_dev); |
| 1407 | struct atac_softc *atac = &siic->sc_atac; |
| 1408 | struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; |
| 1409 | struct ata_drive_datas *drvp = &chp->ch_drive[target]; |
| 1410 | struct scsipibus_attach_args sa; |
| 1411 | char serial_number[21], model[41], firmware_revision[9]; |
| 1412 | int s; |
| 1413 | |
| 1414 | /* skip if already attached */ |
| 1415 | if (scsipi_lookup_periph(chan, target, 0) != NULL) |
| 1416 | return; |
| 1417 | |
| 1418 | /* if no ATAPI device detected at attach time, skip */ |
| 1419 | if (drvp->drive_type != ATA_DRIVET_ATAPI) { |
| 1420 | SIISATA_DEBUG_PRINT(("%s: drive %d " |
| 1421 | "not present\n" , __func__, target), DEBUG_PROBE); |
| 1422 | return; |
| 1423 | } |
| 1424 | |
| 1425 | /* Some ATAPI devices need a bit more time after software reset. */ |
| 1426 | DELAY(5000); |
| 1427 | if (ata_get_params(drvp, AT_WAIT, id) == 0) { |
| 1428 | #ifdef ATAPI_DEBUG_PROBE |
| 1429 | log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n" , |
| 1430 | device_xname(sc->sc_dev), target, |
| 1431 | id->atap_config & ATAPI_CFG_CMD_MASK, |
| 1432 | id->atap_config & ATAPI_CFG_DRQ_MASK); |
| 1433 | #endif |
| 1434 | periph = scsipi_alloc_periph(M_NOWAIT); |
| 1435 | if (periph == NULL) { |
| 1436 | aprint_error_dev(sc->sc_dev, |
| 1437 | "%s: unable to allocate periph for " |
| 1438 | "channel %d drive %d\n" , __func__, |
| 1439 | chp->ch_channel, target); |
| 1440 | return; |
| 1441 | } |
| 1442 | periph->periph_dev = NULL; |
| 1443 | periph->periph_channel = chan; |
| 1444 | periph->periph_switch = &atapi_probe_periphsw; |
| 1445 | periph->periph_target = target; |
| 1446 | periph->periph_lun = 0; |
| 1447 | periph->periph_quirks = PQUIRK_ONLYBIG; |
| 1448 | |
| 1449 | #ifdef SCSIPI_DEBUG |
| 1450 | if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && |
| 1451 | SCSIPI_DEBUG_TARGET == target) |
| 1452 | periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; |
| 1453 | #endif |
| 1454 | periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); |
| 1455 | if (id->atap_config & ATAPI_CFG_REMOV) |
| 1456 | periph->periph_flags |= PERIPH_REMOVABLE; |
| 1457 | sa.sa_periph = periph; |
| 1458 | sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); |
| 1459 | sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? |
| 1460 | T_REMOV : T_FIXED; |
| 1461 | strnvisx(model, sizeof(model), id->atap_model, 40, |
| 1462 | VIS_TRIM|VIS_SAFE|VIS_OCTAL); |
| 1463 | strnvisx(serial_number, sizeof(serial_number), |
| 1464 | id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); |
| 1465 | strnvisx(firmware_revision, sizeof(firmware_revision), |
| 1466 | id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); |
| 1467 | sa.sa_inqbuf.vendor = model; |
| 1468 | sa.sa_inqbuf.product = serial_number; |
| 1469 | sa.sa_inqbuf.revision = firmware_revision; |
| 1470 | |
| 1471 | /* |
| 1472 | * Determine the operating mode capabilities of the device. |
| 1473 | */ |
| 1474 | if ((id->atap_config & ATAPI_CFG_CMD_MASK) |
| 1475 | == ATAPI_CFG_CMD_16) { |
| 1476 | periph->periph_cap |= PERIPH_CAP_CMD16; |
| 1477 | |
| 1478 | /* configure port for packet length */ |
| 1479 | PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), |
| 1480 | PR_PC_PACKET_LENGTH); |
| 1481 | } else { |
| 1482 | PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), |
| 1483 | PR_PC_PACKET_LENGTH); |
| 1484 | } |
| 1485 | |
| 1486 | /* XXX This is gross. */ |
| 1487 | periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); |
| 1488 | |
| 1489 | drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); |
| 1490 | |
| 1491 | if (drvp->drv_softc) |
| 1492 | ata_probe_caps(drvp); |
| 1493 | else { |
| 1494 | s = splbio(); |
| 1495 | drvp->drive_type &= ATA_DRIVET_NONE; |
| 1496 | splx(s); |
| 1497 | } |
| 1498 | } else { |
| 1499 | SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " |
| 1500 | "failed for drive %s:%d:%d: error 0x%x\n" , |
| 1501 | __func__, SIISATANAME(siic), chp->ch_channel, target, |
| 1502 | chp->ch_error), DEBUG_PROBE); |
| 1503 | s = splbio(); |
| 1504 | drvp->drive_type &= ATA_DRIVET_NONE; |
| 1505 | splx(s); |
| 1506 | } |
| 1507 | } |
| 1508 | |
| 1509 | void |
| 1510 | siisata_atapi_scsipi_request(struct scsipi_channel *chan, |
| 1511 | scsipi_adapter_req_t req, void *arg) |
| 1512 | { |
| 1513 | struct scsipi_adapter *adapt = chan->chan_adapter; |
| 1514 | struct scsipi_periph *periph; |
| 1515 | struct scsipi_xfer *sc_xfer; |
| 1516 | struct siisata_softc *sc = device_private(adapt->adapt_dev); |
| 1517 | struct atac_softc *atac = &sc->sc_atac; |
| 1518 | struct ata_xfer *xfer; |
| 1519 | int channel = chan->chan_channel; |
| 1520 | int drive, s; |
| 1521 | |
| 1522 | switch (req) { |
| 1523 | case ADAPTER_REQ_RUN_XFER: |
| 1524 | sc_xfer = arg; |
| 1525 | periph = sc_xfer->xs_periph; |
| 1526 | drive = periph->periph_target; |
| 1527 | |
| 1528 | SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n" , __func__, |
| 1529 | device_xname(atac->atac_dev), channel, drive), |
| 1530 | DEBUG_XFERS); |
| 1531 | |
| 1532 | if (!device_is_active(atac->atac_dev)) { |
| 1533 | sc_xfer->error = XS_DRIVER_STUFFUP; |
| 1534 | scsipi_done(sc_xfer); |
| 1535 | return; |
| 1536 | } |
| 1537 | xfer = ata_get_xfer(ATAXF_NOSLEEP); |
| 1538 | if (xfer == NULL) { |
| 1539 | sc_xfer->error = XS_RESOURCE_SHORTAGE; |
| 1540 | scsipi_done(sc_xfer); |
| 1541 | return; |
| 1542 | } |
| 1543 | |
| 1544 | if (sc_xfer->xs_control & XS_CTL_POLL) |
| 1545 | xfer->c_flags |= C_POLL; |
| 1546 | xfer->c_drive = drive; |
| 1547 | xfer->c_flags |= C_ATAPI; |
| 1548 | xfer->c_cmd = sc_xfer; |
| 1549 | xfer->c_databuf = sc_xfer->data; |
| 1550 | xfer->c_bcount = sc_xfer->datalen; |
| 1551 | xfer->c_start = siisata_atapi_start; |
| 1552 | xfer->c_intr = siisata_atapi_complete; |
| 1553 | xfer->c_kill_xfer = siisata_atapi_kill_xfer; |
| 1554 | xfer->c_dscpoll = 0; |
| 1555 | s = splbio(); |
| 1556 | ata_exec_xfer(atac->atac_channels[channel], xfer); |
| 1557 | #ifdef DIAGNOSTIC |
| 1558 | if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && |
| 1559 | (sc_xfer->xs_status & XS_STS_DONE) == 0) |
| 1560 | panic("%s: polled command not done" , __func__); |
| 1561 | #endif |
| 1562 | splx(s); |
| 1563 | return; |
| 1564 | |
| 1565 | default: |
| 1566 | /* Not supported, nothing to do. */ |
| 1567 | ; |
| 1568 | } |
| 1569 | } |
| 1570 | |
| 1571 | void |
| 1572 | siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) |
| 1573 | { |
| 1574 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1575 | struct siisata_prb *prbp; |
| 1576 | |
| 1577 | struct scsipi_xfer *sc_xfer = xfer->c_cmd; |
| 1578 | |
| 1579 | int slot = SIISATA_NON_NCQ_SLOT; |
| 1580 | int i; |
| 1581 | |
| 1582 | SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n" , __func__, |
| 1583 | SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, |
| 1584 | chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), |
| 1585 | DEBUG_XFERS); |
| 1586 | |
| 1587 | chp->ch_status = 0; |
| 1588 | chp->ch_error = 0; |
| 1589 | |
| 1590 | prbp = schp->sch_prb[slot]; |
| 1591 | memset(prbp, 0, sizeof(struct siisata_prb)); |
| 1592 | |
| 1593 | |
| 1594 | /* fill in direction for ATAPI command */ |
| 1595 | if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) |
| 1596 | prbp->prb_control |= htole16(PRB_CF_PACKET_READ); |
| 1597 | if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) |
| 1598 | prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); |
| 1599 | |
| 1600 | satafis_rhd_construct_atapi(xfer, prbp->prb_fis); |
| 1601 | KASSERT(xfer->c_drive <= PMP_PORT_CTL); |
| 1602 | prbp->prb_fis[rhd_c] |= xfer->c_drive; |
| 1603 | |
| 1604 | /* copy over ATAPI command */ |
| 1605 | memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); |
| 1606 | |
| 1607 | if (siisata_dma_setup(chp, slot, |
| 1608 | (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? |
| 1609 | xfer->c_databuf : NULL, |
| 1610 | xfer->c_bcount, |
| 1611 | (sc_xfer->xs_control & XS_CTL_DATA_IN) ? |
| 1612 | BUS_DMA_READ : BUS_DMA_WRITE) |
| 1613 | ) |
| 1614 | panic("%s" , __func__); |
| 1615 | |
| 1616 | if (xfer->c_flags & C_POLL) { |
| 1617 | /* polled command, disable interrupts */ |
| 1618 | prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); |
| 1619 | siisata_disable_port_interrupt(chp); |
| 1620 | } |
| 1621 | |
| 1622 | siisata_activate_prb(schp, slot); |
| 1623 | |
| 1624 | if ((xfer->c_flags & C_POLL) == 0) { |
| 1625 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
| 1626 | callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), |
| 1627 | siisata_timeout, chp); |
| 1628 | goto out; |
| 1629 | } |
| 1630 | |
| 1631 | /* |
| 1632 | * polled command |
| 1633 | */ |
| 1634 | for (i = 0; i < ATA_DELAY / 10; i++) { |
| 1635 | if (sc_xfer->xs_status & XS_STS_DONE) |
| 1636 | break; |
| 1637 | siisata_intr_port(schp); |
| 1638 | DELAY(1000); |
| 1639 | } |
| 1640 | if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { |
| 1641 | siisata_timeout(chp); |
| 1642 | } |
| 1643 | /* reenable interrupts */ |
| 1644 | siisata_enable_port_interrupt(chp); |
| 1645 | out: |
| 1646 | SIISATA_DEBUG_PRINT( |
| 1647 | ("%s: %s: done\n" , SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); |
| 1648 | return; |
| 1649 | } |
| 1650 | |
| 1651 | int |
| 1652 | siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, |
| 1653 | int slot) |
| 1654 | { |
| 1655 | struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; |
| 1656 | struct siisata_channel *schp = (struct siisata_channel *)chp; |
| 1657 | struct scsipi_xfer *sc_xfer = xfer->c_cmd; |
| 1658 | |
| 1659 | SIISATA_DEBUG_PRINT( |
| 1660 | ("%s: %s()\n" , SIISATANAME(sc), __func__), DEBUG_INTR); |
| 1661 | |
| 1662 | /* this comamnd is not active any more */ |
| 1663 | schp->sch_active_slots &= ~__BIT(slot); |
| 1664 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
| 1665 | if (xfer->c_flags & C_TIMEOU) { |
| 1666 | sc_xfer->error = XS_TIMEOUT; |
| 1667 | } else { |
| 1668 | callout_stop(&chp->ch_callout); |
| 1669 | sc_xfer->error = XS_NOERROR; |
| 1670 | } |
| 1671 | |
| 1672 | bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, |
| 1673 | schp->sch_datad[slot]->dm_mapsize, |
| 1674 | (sc_xfer->xs_control & XS_CTL_DATA_IN) ? |
| 1675 | BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); |
| 1676 | bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); |
| 1677 | |
| 1678 | if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { |
| 1679 | siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); |
| 1680 | chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; |
| 1681 | wakeup(&chp->ch_queue->active_xfer); |
| 1682 | return 0; /* XXX verify */ |
| 1683 | } |
| 1684 | |
| 1685 | chp->ch_queue->active_xfer = NULL; |
| 1686 | ata_free_xfer(chp, xfer); |
| 1687 | sc_xfer->resid = sc_xfer->datalen; |
| 1688 | sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); |
| 1689 | SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n" , SIISATANAME(sc), |
| 1690 | __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); |
| 1691 | if ((chp->ch_status & WDCS_ERR) && |
| 1692 | ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || |
| 1693 | sc_xfer->resid == sc_xfer->datalen)) { |
| 1694 | sc_xfer->error = XS_SHORTSENSE; |
| 1695 | sc_xfer->sense.atapi_sense = chp->ch_error; |
| 1696 | if ((sc_xfer->xs_periph->periph_quirks & |
| 1697 | PQUIRK_NOSENSE) == 0) { |
| 1698 | /* request sense */ |
| 1699 | sc_xfer->error = XS_BUSY; |
| 1700 | sc_xfer->status = SCSI_CHECK; |
| 1701 | } |
| 1702 | } |
| 1703 | scsipi_done(sc_xfer); |
| 1704 | atastart(chp); |
| 1705 | return 0; /* XXX verify */ |
| 1706 | } |
| 1707 | |
| 1708 | #endif /* NATAPIBUS */ |
| 1709 | |