| 1 | /* $NetBSD: at24cxx.c,v 1.23 2016/09/10 13:16:12 jakllsch Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2003 Wasabi Systems, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. |
| 8 | * |
| 9 | * Redistribution and use in source and binary forms, with or without |
| 10 | * modification, are permitted provided that the following conditions |
| 11 | * are met: |
| 12 | * 1. Redistributions of source code must retain the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer. |
| 14 | * 2. Redistributions in binary form must reproduce the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer in the |
| 16 | * documentation and/or other materials provided with the distribution. |
| 17 | * 3. All advertising materials mentioning features or use of this software |
| 18 | * must display the following acknowledgement: |
| 19 | * This product includes software developed for the NetBSD Project by |
| 20 | * Wasabi Systems, Inc. |
| 21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
| 22 | * or promote products derived from this software without specific prior |
| 23 | * written permission. |
| 24 | * |
| 25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
| 26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
| 29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 35 | * POSSIBILITY OF SUCH DAMAGE. |
| 36 | */ |
| 37 | |
| 38 | #include <sys/cdefs.h> |
| 39 | __KERNEL_RCSID(0, "$NetBSD: at24cxx.c,v 1.23 2016/09/10 13:16:12 jakllsch Exp $" ); |
| 40 | |
| 41 | #include <sys/param.h> |
| 42 | #include <sys/systm.h> |
| 43 | #include <sys/device.h> |
| 44 | #include <sys/kernel.h> |
| 45 | #include <sys/fcntl.h> |
| 46 | #include <sys/uio.h> |
| 47 | #include <sys/conf.h> |
| 48 | #include <sys/proc.h> |
| 49 | #include <sys/event.h> |
| 50 | |
| 51 | #include <sys/bus.h> |
| 52 | |
| 53 | #include <dev/i2c/i2cvar.h> |
| 54 | #include <dev/i2c/at24cxxvar.h> |
| 55 | |
| 56 | /* |
| 57 | * AT24Cxx EEPROM I2C address: |
| 58 | * 101 0xxx |
| 59 | * (and others depending on the exact model) The bigger 8-bit parts |
| 60 | * decode multiple addresses. The bigger 16-bit parts do too (those |
| 61 | * larger than 512kb). Be sure to check the datasheet of your EEPROM |
| 62 | * because there's much variation between models. |
| 63 | */ |
| 64 | #define AT24CXX_ADDRMASK 0x3f8 |
| 65 | #define AT24CXX_ADDR 0x50 |
| 66 | |
| 67 | #define AT24CXX_WRITE_CYCLE_MS 10 |
| 68 | #define AT24CXX_ADDR_HI(a) (((a) >> 8) & 0x1f) |
| 69 | #define AT24CXX_ADDR_LO(a) ((a) & 0xff) |
| 70 | |
| 71 | #include "seeprom.h" |
| 72 | |
| 73 | #if NSEEPROM > 0 |
| 74 | |
| 75 | struct seeprom_softc { |
| 76 | device_t sc_dev; |
| 77 | i2c_tag_t sc_tag; |
| 78 | int sc_address; |
| 79 | int sc_size; |
| 80 | int sc_cmdlen; |
| 81 | int sc_open; |
| 82 | }; |
| 83 | |
| 84 | static int seeprom_match(device_t, cfdata_t, void *); |
| 85 | static void seeprom_attach(device_t, device_t, void *); |
| 86 | |
| 87 | CFATTACH_DECL_NEW(seeprom, sizeof(struct seeprom_softc), |
| 88 | seeprom_match, seeprom_attach, NULL, NULL); |
| 89 | extern struct cfdriver seeprom_cd; |
| 90 | |
| 91 | dev_type_open(seeprom_open); |
| 92 | dev_type_close(seeprom_close); |
| 93 | dev_type_read(seeprom_read); |
| 94 | dev_type_write(seeprom_write); |
| 95 | |
| 96 | const struct cdevsw seeprom_cdevsw = { |
| 97 | .d_open = seeprom_open, |
| 98 | .d_close = seeprom_close, |
| 99 | .d_read = seeprom_read, |
| 100 | .d_write = seeprom_write, |
| 101 | .d_ioctl = noioctl, |
| 102 | .d_stop = nostop, |
| 103 | .d_tty = notty, |
| 104 | .d_poll = nopoll, |
| 105 | .d_mmap = nommap, |
| 106 | .d_kqfilter = nokqfilter, |
| 107 | .d_discard = nodiscard, |
| 108 | .d_flag = D_OTHER |
| 109 | }; |
| 110 | |
| 111 | static int seeprom_wait_idle(struct seeprom_softc *); |
| 112 | |
| 113 | static const char * seeprom_compats[] = { |
| 114 | "i2c-at24c64" , |
| 115 | "i2c-at34c02" , |
| 116 | "atmel,24c02" , |
| 117 | NULL |
| 118 | }; |
| 119 | |
| 120 | static const struct seeprom_size { |
| 121 | const char *name; |
| 122 | int size; |
| 123 | } seeprom_sizes[] = { |
| 124 | { "atmel,24c02" , 256 }, |
| 125 | }; |
| 126 | |
| 127 | static int |
| 128 | seeprom_match(device_t parent, cfdata_t cf, void *aux) |
| 129 | { |
| 130 | struct i2c_attach_args *ia = aux; |
| 131 | |
| 132 | if (ia->ia_name) { |
| 133 | if (ia->ia_ncompat > 0) { |
| 134 | if (iic_compat_match(ia, seeprom_compats)) |
| 135 | return (1); |
| 136 | } else { |
| 137 | if (strcmp(ia->ia_name, "seeprom" ) == 0) |
| 138 | return (1); |
| 139 | } |
| 140 | } else { |
| 141 | if ((ia->ia_addr & AT24CXX_ADDRMASK) == AT24CXX_ADDR) |
| 142 | return (1); |
| 143 | } |
| 144 | |
| 145 | return (0); |
| 146 | } |
| 147 | |
| 148 | static void |
| 149 | seeprom_attach(device_t parent, device_t self, void *aux) |
| 150 | { |
| 151 | struct seeprom_softc *sc = device_private(self); |
| 152 | struct i2c_attach_args *ia = aux; |
| 153 | u_int n, m; |
| 154 | |
| 155 | sc->sc_tag = ia->ia_tag; |
| 156 | sc->sc_address = ia->ia_addr; |
| 157 | sc->sc_dev = self; |
| 158 | |
| 159 | if (ia->ia_name != NULL) { |
| 160 | aprint_naive(": %s" , ia->ia_name); |
| 161 | aprint_normal(": %s" , ia->ia_name); |
| 162 | } else { |
| 163 | aprint_naive(": EEPROM" ); |
| 164 | aprint_normal(": AT24Cxx or compatible EEPROM" ); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * The AT24C01A/02/04/08/16 EEPROMs use a 1 byte command |
| 169 | * word to select the offset into the EEPROM page. The |
| 170 | * AT24C04/08/16 decode fewer of the i2c address bits, |
| 171 | * using the bottom 1, 2, or 3 to select the 256-byte |
| 172 | * super-page. |
| 173 | * |
| 174 | * The AT24C32/64/128/256/512 EEPROMs use a 2 byte command |
| 175 | * word and decode all of the i2c address bits. |
| 176 | * |
| 177 | * The AT24C1024 EEPROMs use a 2 byte command and also do bank |
| 178 | * switching to select the proper super-page. This isn't |
| 179 | * supported by this driver. |
| 180 | */ |
| 181 | if (device_cfdata(self)->cf_flags) |
| 182 | sc->sc_size = (device_cfdata(self)->cf_flags << 7); |
| 183 | else |
| 184 | sc->sc_size = ia->ia_size; |
| 185 | |
| 186 | if (sc->sc_size <= 0 && ia->ia_ncompat > 0) { |
| 187 | for (n = 0; n < __arraycount(seeprom_sizes); n++) { |
| 188 | for (m = 0; m < ia->ia_ncompat; m++) { |
| 189 | if (!strcmp(seeprom_sizes[n].name, |
| 190 | ia->ia_compat[m])) { |
| 191 | sc->sc_size = seeprom_sizes[n].size; |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | switch (sc->sc_size) { |
| 199 | case 128: /* 1Kbit */ |
| 200 | case 256: /* 2Kbit */ |
| 201 | case 512: /* 4Kbit */ |
| 202 | case 1024: /* 8Kbit */ |
| 203 | case 2048: /* 16Kbit */ |
| 204 | sc->sc_cmdlen = 1; |
| 205 | aprint_normal(": size %d\n" , sc->sc_size); |
| 206 | break; |
| 207 | |
| 208 | case 4096: /* 32Kbit */ |
| 209 | case 8192: /* 64Kbit */ |
| 210 | case 16384: /* 128Kbit */ |
| 211 | case 32768: /* 256Kbit */ |
| 212 | case 65536: /* 512Kbit */ |
| 213 | sc->sc_cmdlen = 2; |
| 214 | aprint_normal(": size %d\n" , sc->sc_size); |
| 215 | break; |
| 216 | |
| 217 | default: |
| 218 | /* |
| 219 | * Default to 2KB. If we happen to have a 2KB |
| 220 | * EEPROM this will allow us to access it. If we |
| 221 | * have a smaller one, the worst that can happen |
| 222 | * is that we end up trying to read a different |
| 223 | * EEPROM on the bus when accessing it. |
| 224 | * |
| 225 | * Obviously this will not work for 4KB or 8KB |
| 226 | * EEPROMs, but them's the breaks. |
| 227 | */ |
| 228 | aprint_normal("\n" ); |
| 229 | aprint_error_dev(self, "invalid size specified; " |
| 230 | "assuming 2KB (16Kb)\n" ); |
| 231 | sc->sc_size = 2048; |
| 232 | sc->sc_cmdlen = 1; |
| 233 | } |
| 234 | |
| 235 | sc->sc_open = 0; |
| 236 | } |
| 237 | |
| 238 | /*ARGSUSED*/ |
| 239 | int |
| 240 | seeprom_open(dev_t dev, int flag, int fmt, struct lwp *l) |
| 241 | { |
| 242 | struct seeprom_softc *sc; |
| 243 | |
| 244 | if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) |
| 245 | return (ENXIO); |
| 246 | |
| 247 | /* XXX: Locking */ |
| 248 | |
| 249 | if (sc->sc_open) |
| 250 | return (EBUSY); |
| 251 | |
| 252 | sc->sc_open = 1; |
| 253 | return (0); |
| 254 | } |
| 255 | |
| 256 | /*ARGSUSED*/ |
| 257 | int |
| 258 | seeprom_close(dev_t dev, int flag, int fmt, struct lwp *l) |
| 259 | { |
| 260 | struct seeprom_softc *sc; |
| 261 | |
| 262 | if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) |
| 263 | return (ENXIO); |
| 264 | |
| 265 | sc->sc_open = 0; |
| 266 | return (0); |
| 267 | } |
| 268 | |
| 269 | /*ARGSUSED*/ |
| 270 | int |
| 271 | seeprom_read(dev_t dev, struct uio *uio, int flags) |
| 272 | { |
| 273 | struct seeprom_softc *sc; |
| 274 | i2c_addr_t addr; |
| 275 | u_int8_t ch, cmdbuf[2]; |
| 276 | int a, error; |
| 277 | |
| 278 | if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) |
| 279 | return (ENXIO); |
| 280 | |
| 281 | if (uio->uio_offset >= sc->sc_size) |
| 282 | return (EINVAL); |
| 283 | |
| 284 | /* |
| 285 | * Even though the AT24Cxx EEPROMs support sequential |
| 286 | * reads within a page, some I2C controllers do not |
| 287 | * support anything other than single-byte transfers, |
| 288 | * so we're stuck with this lowest-common-denominator. |
| 289 | */ |
| 290 | |
| 291 | while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { |
| 292 | a = (int)uio->uio_offset; |
| 293 | if (sc->sc_cmdlen == 1) { |
| 294 | addr = sc->sc_address + (a >> 8); |
| 295 | cmdbuf[0] = a & 0xff; |
| 296 | } else { |
| 297 | addr = sc->sc_address; |
| 298 | cmdbuf[0] = AT24CXX_ADDR_HI(a); |
| 299 | cmdbuf[1] = AT24CXX_ADDR_LO(a); |
| 300 | } |
| 301 | |
| 302 | if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) |
| 303 | return (error); |
| 304 | if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, |
| 305 | addr, cmdbuf, sc->sc_cmdlen, |
| 306 | &ch, 1, 0)) != 0) { |
| 307 | iic_release_bus(sc->sc_tag, 0); |
| 308 | aprint_error_dev(sc->sc_dev, |
| 309 | "seeprom_read: byte read failed at 0x%x\n" , a); |
| 310 | return (error); |
| 311 | } |
| 312 | iic_release_bus(sc->sc_tag, 0); |
| 313 | |
| 314 | if ((error = uiomove(&ch, 1, uio)) != 0) { |
| 315 | return (error); |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | return (0); |
| 320 | } |
| 321 | |
| 322 | /*ARGSUSED*/ |
| 323 | int |
| 324 | seeprom_write(dev_t dev, struct uio *uio, int flags) |
| 325 | { |
| 326 | struct seeprom_softc *sc; |
| 327 | i2c_addr_t addr; |
| 328 | u_int8_t ch, cmdbuf[2]; |
| 329 | int a, error; |
| 330 | |
| 331 | if ((sc = device_lookup_private(&seeprom_cd, minor(dev))) == NULL) |
| 332 | return (ENXIO); |
| 333 | |
| 334 | if (uio->uio_offset >= sc->sc_size) |
| 335 | return (EINVAL); |
| 336 | |
| 337 | /* |
| 338 | * See seeprom_read() for why we don't use sequential |
| 339 | * writes within a page. |
| 340 | */ |
| 341 | |
| 342 | while (uio->uio_resid > 0 && uio->uio_offset < sc->sc_size) { |
| 343 | a = (int)uio->uio_offset; |
| 344 | if (sc->sc_cmdlen == 1) { |
| 345 | addr = sc->sc_address + (a >> 8); |
| 346 | cmdbuf[0] = a & 0xff; |
| 347 | } else { |
| 348 | addr = sc->sc_address; |
| 349 | cmdbuf[0] = AT24CXX_ADDR_HI(a); |
| 350 | cmdbuf[1] = AT24CXX_ADDR_LO(a); |
| 351 | } |
| 352 | if ((error = uiomove(&ch, 1, uio)) != 0) { |
| 353 | iic_release_bus(sc->sc_tag, 0); |
| 354 | return (error); |
| 355 | } |
| 356 | |
| 357 | if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) |
| 358 | return (error); |
| 359 | if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, |
| 360 | addr, cmdbuf, sc->sc_cmdlen, |
| 361 | &ch, 1, 0)) != 0) { |
| 362 | iic_release_bus(sc->sc_tag, 0); |
| 363 | aprint_error_dev(sc->sc_dev, |
| 364 | "seeprom_write: byte write failed at 0x%x\n" , a); |
| 365 | return (error); |
| 366 | } |
| 367 | iic_release_bus(sc->sc_tag, 0); |
| 368 | |
| 369 | /* Wait until the device commits the byte. */ |
| 370 | if ((error = seeprom_wait_idle(sc)) != 0) { |
| 371 | return (error); |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | return (0); |
| 376 | } |
| 377 | |
| 378 | static int |
| 379 | seeprom_wait_idle(struct seeprom_softc *sc) |
| 380 | { |
| 381 | uint8_t cmdbuf[2] = { 0, 0 }; |
| 382 | int rv, timeout; |
| 383 | u_int8_t dummy; |
| 384 | int error; |
| 385 | |
| 386 | timeout = (1000 / hz) / AT24CXX_WRITE_CYCLE_MS; |
| 387 | if (timeout == 0) |
| 388 | timeout = 1; |
| 389 | |
| 390 | delay(10); |
| 391 | |
| 392 | /* |
| 393 | * Read the byte at address 0. This is just a dummy |
| 394 | * read to wait for the EEPROM's write cycle to complete. |
| 395 | */ |
| 396 | for (;;) { |
| 397 | if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) |
| 398 | return error; |
| 399 | error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, |
| 400 | sc->sc_address, cmdbuf, sc->sc_cmdlen, &dummy, 1, 0); |
| 401 | iic_release_bus(sc->sc_tag, 0); |
| 402 | if (error == 0) |
| 403 | break; |
| 404 | |
| 405 | rv = tsleep(sc, PRIBIO | PCATCH, "seepromwr" , timeout); |
| 406 | if (rv != EWOULDBLOCK) |
| 407 | return (rv); |
| 408 | } |
| 409 | |
| 410 | return (0); |
| 411 | } |
| 412 | |
| 413 | #endif /* NSEEPROM > 0 */ |
| 414 | |
| 415 | int |
| 416 | seeprom_bootstrap_read(i2c_tag_t tag, int i2caddr, int offset, int devsize, |
| 417 | u_int8_t *rvp, size_t len) |
| 418 | { |
| 419 | i2c_addr_t addr; |
| 420 | int cmdlen; |
| 421 | uint8_t cmdbuf[2]; |
| 422 | |
| 423 | if (len == 0) |
| 424 | return (0); |
| 425 | |
| 426 | /* We are very forgiving about devsize during bootstrap. */ |
| 427 | cmdlen = (devsize >= 4096) ? 2 : 1; |
| 428 | |
| 429 | if (iic_acquire_bus(tag, I2C_F_POLL) != 0) |
| 430 | return (-1); |
| 431 | |
| 432 | while (len) { |
| 433 | if (cmdlen == 1) { |
| 434 | addr = i2caddr + (offset >> 8); |
| 435 | cmdbuf[0] = offset & 0xff; |
| 436 | } else { |
| 437 | addr = i2caddr; |
| 438 | cmdbuf[0] = AT24CXX_ADDR_HI(offset); |
| 439 | cmdbuf[1] = AT24CXX_ADDR_LO(offset); |
| 440 | } |
| 441 | |
| 442 | /* Read a single byte. */ |
| 443 | if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, |
| 444 | cmdbuf, cmdlen, rvp, 1, I2C_F_POLL)) { |
| 445 | iic_release_bus(tag, I2C_F_POLL); |
| 446 | return (-1); |
| 447 | } |
| 448 | |
| 449 | len--; |
| 450 | rvp++; |
| 451 | offset++; |
| 452 | } |
| 453 | |
| 454 | iic_release_bus(tag, I2C_F_POLL); |
| 455 | return (0); |
| 456 | } |
| 457 | |