| 1 | /* $NetBSD: if_jme.c,v 1.30 2016/06/10 13:27:14 ozaki-r Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2008 Manuel Bouyer. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | */ |
| 26 | |
| 27 | /*- |
| 28 | * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> |
| 29 | * All rights reserved. |
| 30 | * |
| 31 | * Redistribution and use in source and binary forms, with or without |
| 32 | * modification, are permitted provided that the following conditions |
| 33 | * are met: |
| 34 | * 1. Redistributions of source code must retain the above copyright |
| 35 | * notice unmodified, this list of conditions, and the following |
| 36 | * disclaimer. |
| 37 | * 2. Redistributions in binary form must reproduce the above copyright |
| 38 | * notice, this list of conditions and the following disclaimer in the |
| 39 | * documentation and/or other materials provided with the distribution. |
| 40 | * |
| 41 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 42 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 44 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 47 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 48 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 49 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 50 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 51 | * SUCH DAMAGE. |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | /* |
| 56 | * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) |
| 57 | * Ethernet Controllers. |
| 58 | */ |
| 59 | |
| 60 | #include <sys/cdefs.h> |
| 61 | __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.30 2016/06/10 13:27:14 ozaki-r Exp $" ); |
| 62 | |
| 63 | |
| 64 | #include <sys/param.h> |
| 65 | #include <sys/systm.h> |
| 66 | #include <sys/mbuf.h> |
| 67 | #include <sys/protosw.h> |
| 68 | #include <sys/socket.h> |
| 69 | #include <sys/ioctl.h> |
| 70 | #include <sys/errno.h> |
| 71 | #include <sys/malloc.h> |
| 72 | #include <sys/kernel.h> |
| 73 | #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ |
| 74 | #include <sys/device.h> |
| 75 | #include <sys/syslog.h> |
| 76 | #include <sys/sysctl.h> |
| 77 | |
| 78 | #include <net/if.h> |
| 79 | #if defined(SIOCSIFMEDIA) |
| 80 | #include <net/if_media.h> |
| 81 | #endif |
| 82 | #include <net/if_types.h> |
| 83 | #include <net/if_dl.h> |
| 84 | #include <net/route.h> |
| 85 | #include <net/netisr.h> |
| 86 | |
| 87 | #include <net/bpf.h> |
| 88 | #include <net/bpfdesc.h> |
| 89 | |
| 90 | #include <sys/rndsource.h> |
| 91 | |
| 92 | #include <netinet/in.h> |
| 93 | #include <netinet/in_systm.h> |
| 94 | #include <netinet/ip.h> |
| 95 | |
| 96 | #ifdef INET |
| 97 | #include <netinet/in_var.h> |
| 98 | #endif |
| 99 | |
| 100 | #include <netinet/tcp.h> |
| 101 | |
| 102 | #include <net/if_ether.h> |
| 103 | #if defined(INET) |
| 104 | #include <netinet/if_inarp.h> |
| 105 | #endif |
| 106 | |
| 107 | #include <sys/bus.h> |
| 108 | #include <sys/intr.h> |
| 109 | |
| 110 | #include <dev/pci/pcireg.h> |
| 111 | #include <dev/pci/pcivar.h> |
| 112 | #include <dev/pci/pcidevs.h> |
| 113 | #include <dev/pci/if_jmereg.h> |
| 114 | |
| 115 | #include <dev/mii/mii.h> |
| 116 | #include <dev/mii/miivar.h> |
| 117 | |
| 118 | struct jme_product_desc { |
| 119 | u_int32_t jme_product; |
| 120 | const char *jme_desc; |
| 121 | }; |
| 122 | |
| 123 | /* number of entries in transmit and receive rings */ |
| 124 | #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) |
| 125 | |
| 126 | #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) |
| 127 | |
| 128 | /* Water mark to kick reclaiming Tx buffers. */ |
| 129 | #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) |
| 130 | |
| 131 | |
| 132 | struct jme_softc { |
| 133 | device_t jme_dev; /* base device */ |
| 134 | bus_space_tag_t jme_bt_mac; |
| 135 | bus_space_handle_t jme_bh_mac; /* Mac registers */ |
| 136 | bus_space_tag_t jme_bt_phy; |
| 137 | bus_space_handle_t jme_bh_phy; /* PHY registers */ |
| 138 | bus_space_tag_t jme_bt_misc; |
| 139 | bus_space_handle_t jme_bh_misc; /* Misc registers */ |
| 140 | bus_dma_tag_t jme_dmatag; |
| 141 | bus_dma_segment_t jme_txseg; /* transmit ring seg */ |
| 142 | bus_dmamap_t jme_txmap; /* transmit ring DMA map */ |
| 143 | struct jme_desc* jme_txring; /* transmit ring */ |
| 144 | bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ |
| 145 | struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ |
| 146 | int jme_tx_cons; /* transmit ring consumer */ |
| 147 | int jme_tx_prod; /* transmit ring producer */ |
| 148 | int jme_tx_cnt; /* transmit ring active count */ |
| 149 | bus_dma_segment_t jme_rxseg; /* receive ring seg */ |
| 150 | bus_dmamap_t jme_rxmap; /* receive ring DMA map */ |
| 151 | struct jme_desc* jme_rxring; /* receive ring */ |
| 152 | bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ |
| 153 | struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ |
| 154 | int jme_rx_cons; /* receive ring consumer */ |
| 155 | int jme_rx_prod; /* receive ring producer */ |
| 156 | void* jme_ih; /* our interrupt */ |
| 157 | struct ethercom jme_ec; |
| 158 | struct callout jme_tick_ch; /* tick callout */ |
| 159 | u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ |
| 160 | u_int8_t jme_phyaddr; /* address of integrated phy */ |
| 161 | u_int8_t jme_chip_rev; /* chip revision */ |
| 162 | u_int8_t jme_rev; /* PCI revision */ |
| 163 | mii_data_t jme_mii; /* mii bus */ |
| 164 | u_int32_t jme_flags; /* device features, see below */ |
| 165 | uint32_t jme_txcsr; /* TX config register */ |
| 166 | uint32_t jme_rxcsr; /* RX config register */ |
| 167 | krndsource_t rnd_source; |
| 168 | /* interrupt coalition parameters */ |
| 169 | struct sysctllog *jme_clog; |
| 170 | int jme_intrxto; /* interrupt RX timeout */ |
| 171 | int jme_intrxct; /* interrupt RX packets counter */ |
| 172 | int jme_inttxto; /* interrupt TX timeout */ |
| 173 | int jme_inttxct; /* interrupt TX packets counter */ |
| 174 | }; |
| 175 | |
| 176 | #define JME_FLAG_FPGA 0x0001 /* FPGA version */ |
| 177 | #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ |
| 178 | |
| 179 | |
| 180 | #define jme_if jme_ec.ec_if |
| 181 | #define jme_bpf jme_if.if_bpf |
| 182 | |
| 183 | typedef struct jme_softc jme_softc_t; |
| 184 | typedef u_long ioctl_cmd_t; |
| 185 | |
| 186 | static int jme_pci_match(device_t, cfdata_t, void *); |
| 187 | static void jme_pci_attach(device_t, device_t, void *); |
| 188 | static void jme_intr_rx(jme_softc_t *); |
| 189 | static int jme_intr(void *); |
| 190 | |
| 191 | static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); |
| 192 | static int jme_mediachange(struct ifnet *); |
| 193 | static void jme_ifwatchdog(struct ifnet *); |
| 194 | static bool jme_shutdown(device_t, int); |
| 195 | |
| 196 | static void jme_txeof(struct jme_softc *); |
| 197 | static void jme_ifstart(struct ifnet *); |
| 198 | static void jme_reset(jme_softc_t *); |
| 199 | static int jme_ifinit(struct ifnet *); |
| 200 | static int jme_init(struct ifnet *, int); |
| 201 | static void jme_stop(struct ifnet *, int); |
| 202 | // static void jme_restart(void *); |
| 203 | static void jme_ticks(void *); |
| 204 | static void jme_mac_config(jme_softc_t *); |
| 205 | static void jme_set_filter(jme_softc_t *); |
| 206 | |
| 207 | int jme_mii_read(device_t, int, int); |
| 208 | void jme_mii_write(device_t, int, int, int); |
| 209 | void jme_statchg(struct ifnet *); |
| 210 | |
| 211 | static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); |
| 212 | static int jme_eeprom_macaddr(struct jme_softc *); |
| 213 | static int jme_reg_macaddr(struct jme_softc *); |
| 214 | |
| 215 | #define JME_TIMEOUT 1000 |
| 216 | #define JME_PHY_TIMEOUT 1000 |
| 217 | #define JME_EEPROM_TIMEOUT 1000 |
| 218 | |
| 219 | static int jme_sysctl_intrxto(SYSCTLFN_PROTO); |
| 220 | static int jme_sysctl_intrxct(SYSCTLFN_PROTO); |
| 221 | static int jme_sysctl_inttxto(SYSCTLFN_PROTO); |
| 222 | static int jme_sysctl_inttxct(SYSCTLFN_PROTO); |
| 223 | static int jme_root_num; |
| 224 | |
| 225 | |
| 226 | CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), |
| 227 | jme_pci_match, jme_pci_attach, NULL, NULL); |
| 228 | |
| 229 | static const struct jme_product_desc jme_products[] = { |
| 230 | { PCI_PRODUCT_JMICRON_JMC250, |
| 231 | "JMicron JMC250 Gigabit Ethernet Controller" }, |
| 232 | { PCI_PRODUCT_JMICRON_JMC260, |
| 233 | "JMicron JMC260 Gigabit Ethernet Controller" }, |
| 234 | { 0, NULL }, |
| 235 | }; |
| 236 | |
| 237 | static const struct jme_product_desc *jme_lookup_product(uint32_t); |
| 238 | |
| 239 | static const struct jme_product_desc * |
| 240 | jme_lookup_product(uint32_t id) |
| 241 | { |
| 242 | const struct jme_product_desc *jp; |
| 243 | |
| 244 | for (jp = jme_products ; jp->jme_desc != NULL; jp++) |
| 245 | if (PCI_PRODUCT(id) == jp->jme_product) |
| 246 | return jp; |
| 247 | |
| 248 | return NULL; |
| 249 | } |
| 250 | |
| 251 | static int |
| 252 | jme_pci_match(device_t parent, cfdata_t cf, void *aux) |
| 253 | { |
| 254 | struct pci_attach_args *pa = (struct pci_attach_args *)aux; |
| 255 | |
| 256 | if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) |
| 257 | return 0; |
| 258 | |
| 259 | if (jme_lookup_product(pa->pa_id) != NULL) |
| 260 | return 1; |
| 261 | |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | static void |
| 266 | jme_pci_attach(device_t parent, device_t self, void *aux) |
| 267 | { |
| 268 | jme_softc_t *sc = device_private(self); |
| 269 | struct pci_attach_args * const pa = (struct pci_attach_args *)aux; |
| 270 | const struct jme_product_desc *jp; |
| 271 | struct ifnet * const ifp = &sc->jme_if; |
| 272 | bus_space_tag_t iot1, iot2, memt; |
| 273 | bus_space_handle_t ioh1, ioh2, memh; |
| 274 | bus_size_t size, size2; |
| 275 | pci_intr_handle_t intrhandle; |
| 276 | const char *intrstr; |
| 277 | pcireg_t csr; |
| 278 | int nsegs, i; |
| 279 | const struct sysctlnode *node; |
| 280 | int jme_nodenum; |
| 281 | char intrbuf[PCI_INTRSTR_LEN]; |
| 282 | |
| 283 | sc->jme_dev = self; |
| 284 | aprint_normal("\n" ); |
| 285 | callout_init(&sc->jme_tick_ch, 0); |
| 286 | |
| 287 | jp = jme_lookup_product(pa->pa_id); |
| 288 | if (jp == NULL) |
| 289 | panic("jme_pci_attach: impossible" ); |
| 290 | |
| 291 | if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) |
| 292 | sc->jme_flags = JME_FLAG_GIGA; |
| 293 | |
| 294 | /* |
| 295 | * Map the card space. Try Mem first. |
| 296 | */ |
| 297 | if (pci_mapreg_map(pa, JME_PCI_BAR0, |
| 298 | PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, |
| 299 | 0, &memt, &memh, NULL, &size) == 0) { |
| 300 | sc->jme_bt_mac = memt; |
| 301 | sc->jme_bh_mac = memh; |
| 302 | sc->jme_bt_phy = memt; |
| 303 | if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, |
| 304 | JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { |
| 305 | aprint_error_dev(self, "can't subregion PHY space\n" ); |
| 306 | bus_space_unmap(memt, memh, size); |
| 307 | return; |
| 308 | } |
| 309 | sc->jme_bt_misc = memt; |
| 310 | if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, |
| 311 | JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { |
| 312 | aprint_error_dev(self, "can't subregion misc space\n" ); |
| 313 | bus_space_unmap(memt, memh, size); |
| 314 | return; |
| 315 | } |
| 316 | } else { |
| 317 | if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, |
| 318 | 0, &iot1, &ioh1, NULL, &size) != 0) { |
| 319 | aprint_error_dev(self, "can't map I/O space 1\n" ); |
| 320 | return; |
| 321 | } |
| 322 | sc->jme_bt_mac = iot1; |
| 323 | sc->jme_bh_mac = ioh1; |
| 324 | if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, |
| 325 | 0, &iot2, &ioh2, NULL, &size2) != 0) { |
| 326 | aprint_error_dev(self, "can't map I/O space 2\n" ); |
| 327 | bus_space_unmap(iot1, ioh1, size); |
| 328 | return; |
| 329 | } |
| 330 | sc->jme_bt_phy = iot2; |
| 331 | sc->jme_bh_phy = ioh2; |
| 332 | sc->jme_bt_misc = iot2; |
| 333 | if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, |
| 334 | JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { |
| 335 | aprint_error_dev(self, "can't subregion misc space\n" ); |
| 336 | bus_space_unmap(iot1, ioh1, size); |
| 337 | bus_space_unmap(iot2, ioh2, size2); |
| 338 | return; |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | if (pci_dma64_available(pa)) |
| 343 | sc->jme_dmatag = pa->pa_dmat64; |
| 344 | else |
| 345 | sc->jme_dmatag = pa->pa_dmat; |
| 346 | |
| 347 | /* Enable the device. */ |
| 348 | csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
| 349 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, |
| 350 | csr | PCI_COMMAND_MASTER_ENABLE); |
| 351 | |
| 352 | aprint_normal_dev(self, "%s\n" , jp->jme_desc); |
| 353 | |
| 354 | sc->jme_rev = PCI_REVISION(pa->pa_class); |
| 355 | |
| 356 | csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); |
| 357 | if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != |
| 358 | CHIPMODE_NOT_FPGA) |
| 359 | sc->jme_flags |= JME_FLAG_FPGA; |
| 360 | sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; |
| 361 | aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " |
| 362 | "0x%x" , sc->jme_rev, sc->jme_chip_rev); |
| 363 | if (sc->jme_flags & JME_FLAG_FPGA) |
| 364 | aprint_verbose(" FPGA revision: 0x%x" , |
| 365 | (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); |
| 366 | aprint_verbose("\n" ); |
| 367 | |
| 368 | /* |
| 369 | * Save PHY address. |
| 370 | * Integrated JR0211 has fixed PHY address whereas FPGA version |
| 371 | * requires PHY probing to get correct PHY address. |
| 372 | */ |
| 373 | if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { |
| 374 | sc->jme_phyaddr = |
| 375 | bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 376 | JME_GPREG0) & GPREG0_PHY_ADDR_MASK; |
| 377 | } else |
| 378 | sc->jme_phyaddr = 0; |
| 379 | |
| 380 | |
| 381 | jme_reset(sc); |
| 382 | |
| 383 | /* read mac addr */ |
| 384 | if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { |
| 385 | aprint_error_dev(self, "error reading Ethernet address\n" ); |
| 386 | /* return; */ |
| 387 | } |
| 388 | aprint_normal_dev(self, "Ethernet address %s\n" , |
| 389 | ether_sprintf(sc->jme_enaddr)); |
| 390 | |
| 391 | /* Map and establish interrupts */ |
| 392 | if (pci_intr_map(pa, &intrhandle)) { |
| 393 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
| 394 | return; |
| 395 | } |
| 396 | intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); |
| 397 | sc->jme_if.if_softc = sc; |
| 398 | sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, |
| 399 | jme_intr, sc); |
| 400 | if (sc->jme_ih == NULL) { |
| 401 | aprint_error_dev(self, "couldn't establish interrupt" ); |
| 402 | if (intrstr != NULL) |
| 403 | aprint_error(" at %s" , intrstr); |
| 404 | aprint_error("\n" ); |
| 405 | return; |
| 406 | } |
| 407 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
| 408 | |
| 409 | /* allocate and map DMA-safe memory for transmit ring */ |
| 410 | if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, |
| 411 | &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || |
| 412 | bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, |
| 413 | nsegs, PAGE_SIZE, (void **)&sc->jme_txring, |
| 414 | BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || |
| 415 | bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, |
| 416 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || |
| 417 | bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, |
| 418 | PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { |
| 419 | aprint_error_dev(self, "can't allocate DMA memory TX ring\n" ); |
| 420 | return; |
| 421 | } |
| 422 | /* allocate and map DMA-safe memory for receive ring */ |
| 423 | if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, |
| 424 | &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || |
| 425 | bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, |
| 426 | nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, |
| 427 | BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || |
| 428 | bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, |
| 429 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || |
| 430 | bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, |
| 431 | PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { |
| 432 | aprint_error_dev(self, "can't allocate DMA memory RX ring\n" ); |
| 433 | return; |
| 434 | } |
| 435 | for (i = 0; i < JME_NBUFS; i++) { |
| 436 | sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; |
| 437 | if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, |
| 438 | JME_NBUFS, JME_MAX_TX_LEN, 0, |
| 439 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, |
| 440 | &sc->jme_txmbufm[i]) != 0) { |
| 441 | aprint_error_dev(self, "can't allocate DMA TX map\n" ); |
| 442 | return; |
| 443 | } |
| 444 | if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, |
| 445 | 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, |
| 446 | &sc->jme_rxmbufm[i]) != 0) { |
| 447 | aprint_error_dev(self, "can't allocate DMA RX map\n" ); |
| 448 | return; |
| 449 | } |
| 450 | } |
| 451 | /* |
| 452 | * Initialize our media structures and probe the MII. |
| 453 | * |
| 454 | * Note that we don't care about the media instance. We |
| 455 | * are expecting to have multiple PHYs on the 10/100 cards, |
| 456 | * and on those cards we exclude the internal PHY from providing |
| 457 | * 10baseT. By ignoring the instance, it allows us to not have |
| 458 | * to specify it on the command line when switching media. |
| 459 | */ |
| 460 | sc->jme_mii.mii_ifp = ifp; |
| 461 | sc->jme_mii.mii_readreg = jme_mii_read; |
| 462 | sc->jme_mii.mii_writereg = jme_mii_write; |
| 463 | sc->jme_mii.mii_statchg = jme_statchg; |
| 464 | sc->jme_ec.ec_mii = &sc->jme_mii; |
| 465 | ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, |
| 466 | ether_mediastatus); |
| 467 | mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, |
| 468 | MII_OFFSET_ANY, 0); |
| 469 | if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { |
| 470 | ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); |
| 471 | ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); |
| 472 | } else |
| 473 | ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); |
| 474 | |
| 475 | /* |
| 476 | * We can support 802.1Q VLAN-sized frames. |
| 477 | */ |
| 478 | sc->jme_ec.ec_capabilities |= |
| 479 | ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; |
| 480 | |
| 481 | if (sc->jme_flags & JME_FLAG_GIGA) |
| 482 | sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
| 483 | |
| 484 | |
| 485 | strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); |
| 486 | ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; |
| 487 | ifp->if_ioctl = jme_ifioctl; |
| 488 | ifp->if_start = jme_ifstart; |
| 489 | ifp->if_watchdog = jme_ifwatchdog; |
| 490 | ifp->if_init = jme_ifinit; |
| 491 | ifp->if_stop = jme_stop; |
| 492 | ifp->if_timer = 0; |
| 493 | ifp->if_capabilities |= |
| 494 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | |
| 495 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | |
| 496 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | |
| 497 | IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ |
| 498 | IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ |
| 499 | IFCAP_TSOv4 | IFCAP_TSOv6; |
| 500 | IFQ_SET_READY(&ifp->if_snd); |
| 501 | if_attach(ifp); |
| 502 | ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); |
| 503 | |
| 504 | /* |
| 505 | * Add shutdown hook so that DMA is disabled prior to reboot. |
| 506 | */ |
| 507 | if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) |
| 508 | pmf_class_network_register(self, ifp); |
| 509 | else |
| 510 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 511 | |
| 512 | rnd_attach_source(&sc->rnd_source, device_xname(self), |
| 513 | RND_TYPE_NET, RND_FLAG_DEFAULT); |
| 514 | |
| 515 | sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; |
| 516 | sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; |
| 517 | sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; |
| 518 | sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; |
| 519 | if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, |
| 520 | 0, CTLTYPE_NODE, device_xname(sc->jme_dev), |
| 521 | SYSCTL_DESCR("jme per-controller controls" ), |
| 522 | NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, |
| 523 | CTL_EOL) != 0) { |
| 524 | aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n" ); |
| 525 | return; |
| 526 | } |
| 527 | jme_nodenum = node->sysctl_num; |
| 528 | |
| 529 | /* interrupt moderation sysctls */ |
| 530 | if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, |
| 531 | CTLFLAG_READWRITE, |
| 532 | CTLTYPE_INT, "int_rxto" , |
| 533 | SYSCTL_DESCR("jme RX interrupt moderation timer" ), |
| 534 | jme_sysctl_intrxto, 0, (void *)sc, |
| 535 | 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, |
| 536 | CTL_EOL) != 0) { |
| 537 | aprint_normal_dev(sc->jme_dev, |
| 538 | "couldn't create int_rxto sysctl node\n" ); |
| 539 | } |
| 540 | if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, |
| 541 | CTLFLAG_READWRITE, |
| 542 | CTLTYPE_INT, "int_rxct" , |
| 543 | SYSCTL_DESCR("jme RX interrupt moderation packet counter" ), |
| 544 | jme_sysctl_intrxct, 0, (void *)sc, |
| 545 | 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, |
| 546 | CTL_EOL) != 0) { |
| 547 | aprint_normal_dev(sc->jme_dev, |
| 548 | "couldn't create int_rxct sysctl node\n" ); |
| 549 | } |
| 550 | if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, |
| 551 | CTLFLAG_READWRITE, |
| 552 | CTLTYPE_INT, "int_txto" , |
| 553 | SYSCTL_DESCR("jme TX interrupt moderation timer" ), |
| 554 | jme_sysctl_inttxto, 0, (void *)sc, |
| 555 | 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, |
| 556 | CTL_EOL) != 0) { |
| 557 | aprint_normal_dev(sc->jme_dev, |
| 558 | "couldn't create int_txto sysctl node\n" ); |
| 559 | } |
| 560 | if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, |
| 561 | CTLFLAG_READWRITE, |
| 562 | CTLTYPE_INT, "int_txct" , |
| 563 | SYSCTL_DESCR("jme TX interrupt moderation packet counter" ), |
| 564 | jme_sysctl_inttxct, 0, (void *)sc, |
| 565 | 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, |
| 566 | CTL_EOL) != 0) { |
| 567 | aprint_normal_dev(sc->jme_dev, |
| 568 | "couldn't create int_txct sysctl node\n" ); |
| 569 | } |
| 570 | } |
| 571 | |
| 572 | static void |
| 573 | jme_stop_rx(jme_softc_t *sc) |
| 574 | { |
| 575 | uint32_t reg; |
| 576 | int i; |
| 577 | |
| 578 | reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); |
| 579 | if ((reg & RXCSR_RX_ENB) == 0) |
| 580 | return; |
| 581 | reg &= ~RXCSR_RX_ENB; |
| 582 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); |
| 583 | for (i = JME_TIMEOUT / 10; i > 0; i--) { |
| 584 | DELAY(10); |
| 585 | if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 586 | JME_RXCSR) & RXCSR_RX_ENB) == 0) |
| 587 | break; |
| 588 | } |
| 589 | if (i == 0) |
| 590 | aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n" ); |
| 591 | |
| 592 | } |
| 593 | |
| 594 | static void |
| 595 | jme_stop_tx(jme_softc_t *sc) |
| 596 | { |
| 597 | uint32_t reg; |
| 598 | int i; |
| 599 | |
| 600 | reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); |
| 601 | if ((reg & TXCSR_TX_ENB) == 0) |
| 602 | return; |
| 603 | reg &= ~TXCSR_TX_ENB; |
| 604 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); |
| 605 | for (i = JME_TIMEOUT / 10; i > 0; i--) { |
| 606 | DELAY(10); |
| 607 | if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 608 | JME_TXCSR) & TXCSR_TX_ENB) == 0) |
| 609 | break; |
| 610 | } |
| 611 | if (i == 0) |
| 612 | aprint_error_dev(sc->jme_dev, |
| 613 | "stopping transmitter timeout!\n" ); |
| 614 | } |
| 615 | |
| 616 | static void |
| 617 | jme_reset(jme_softc_t *sc) |
| 618 | { |
| 619 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); |
| 620 | DELAY(10); |
| 621 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); |
| 622 | } |
| 623 | |
| 624 | static bool |
| 625 | jme_shutdown(device_t self, int howto) |
| 626 | { |
| 627 | jme_softc_t *sc; |
| 628 | struct ifnet *ifp; |
| 629 | |
| 630 | sc = device_private(self); |
| 631 | ifp = &sc->jme_if; |
| 632 | jme_stop(ifp, 1); |
| 633 | |
| 634 | return true; |
| 635 | } |
| 636 | |
| 637 | static void |
| 638 | jme_stop(struct ifnet *ifp, int disable) |
| 639 | { |
| 640 | jme_softc_t *sc = ifp->if_softc; |
| 641 | int i; |
| 642 | /* Stop receiver, transmitter. */ |
| 643 | jme_stop_rx(sc); |
| 644 | jme_stop_tx(sc); |
| 645 | /* free receive mbufs */ |
| 646 | for (i = 0; i < JME_NBUFS; i++) { |
| 647 | if (sc->jme_rxmbuf[i]) { |
| 648 | bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); |
| 649 | m_freem(sc->jme_rxmbuf[i]); |
| 650 | } |
| 651 | sc->jme_rxmbuf[i] = NULL; |
| 652 | } |
| 653 | /* process completed transmits */ |
| 654 | jme_txeof(sc); |
| 655 | /* free abort pending transmits */ |
| 656 | for (i = 0; i < JME_NBUFS; i++) { |
| 657 | if (sc->jme_txmbuf[i]) { |
| 658 | bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); |
| 659 | m_freem(sc->jme_txmbuf[i]); |
| 660 | sc->jme_txmbuf[i] = NULL; |
| 661 | } |
| 662 | } |
| 663 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
| 664 | ifp->if_timer = 0; |
| 665 | } |
| 666 | |
| 667 | #if 0 |
| 668 | static void |
| 669 | jme_restart(void *v) |
| 670 | { |
| 671 | |
| 672 | jme_init(v); |
| 673 | } |
| 674 | #endif |
| 675 | |
| 676 | static int |
| 677 | jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) |
| 678 | { |
| 679 | int error; |
| 680 | bus_dmamap_t map; |
| 681 | int i = sc->jme_rx_prod; |
| 682 | |
| 683 | if (sc->jme_rxmbuf[i] != NULL) { |
| 684 | aprint_error_dev(sc->jme_dev, |
| 685 | "mbuf already here: rxprod %d rxcons %d\n" , |
| 686 | sc->jme_rx_prod, sc->jme_rx_cons); |
| 687 | if (m) |
| 688 | m_freem(m); |
| 689 | return EINVAL; |
| 690 | } |
| 691 | |
| 692 | if (m == NULL) { |
| 693 | sc->jme_rxmbuf[i] = NULL; |
| 694 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
| 695 | if (m == NULL) |
| 696 | return (ENOBUFS); |
| 697 | MCLGET(m, M_DONTWAIT); |
| 698 | if ((m->m_flags & M_EXT) == 0) { |
| 699 | m_freem(m); |
| 700 | return (ENOBUFS); |
| 701 | } |
| 702 | } |
| 703 | map = sc->jme_rxmbufm[i]; |
| 704 | m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; |
| 705 | KASSERT(m->m_len == MCLBYTES); |
| 706 | |
| 707 | error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, |
| 708 | BUS_DMA_READ|BUS_DMA_NOWAIT); |
| 709 | if (error) { |
| 710 | sc->jme_rxmbuf[i] = NULL; |
| 711 | aprint_error_dev(sc->jme_dev, |
| 712 | "unable to load rx DMA map %d, error = %d\n" , |
| 713 | i, error); |
| 714 | m_freem(m); |
| 715 | return (error); |
| 716 | } |
| 717 | bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, |
| 718 | BUS_DMASYNC_PREREAD); |
| 719 | |
| 720 | sc->jme_rxmbuf[i] = m; |
| 721 | |
| 722 | sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); |
| 723 | sc->jme_rxring[i].addr_lo = |
| 724 | htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); |
| 725 | sc->jme_rxring[i].addr_hi = |
| 726 | htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); |
| 727 | sc->jme_rxring[i].flags = |
| 728 | htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); |
| 729 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, |
| 730 | i * sizeof(struct jme_desc), sizeof(struct jme_desc), |
| 731 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
| 732 | JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); |
| 733 | return (0); |
| 734 | } |
| 735 | |
| 736 | static int |
| 737 | jme_ifinit(struct ifnet *ifp) |
| 738 | { |
| 739 | return jme_init(ifp, 1); |
| 740 | } |
| 741 | |
| 742 | static int |
| 743 | jme_init(struct ifnet *ifp, int do_ifinit) |
| 744 | { |
| 745 | jme_softc_t *sc = ifp->if_softc; |
| 746 | int i, s; |
| 747 | uint8_t eaddr[ETHER_ADDR_LEN]; |
| 748 | uint32_t reg; |
| 749 | |
| 750 | s = splnet(); |
| 751 | /* cancel any pending IO */ |
| 752 | jme_stop(ifp, 1); |
| 753 | jme_reset(sc); |
| 754 | if ((sc->jme_if.if_flags & IFF_UP) == 0) { |
| 755 | splx(s); |
| 756 | return 0; |
| 757 | } |
| 758 | /* allocate receive ring */ |
| 759 | sc->jme_rx_prod = 0; |
| 760 | for (i = 0; i < JME_NBUFS; i++) { |
| 761 | if (jme_add_rxbuf(sc, NULL) < 0) { |
| 762 | aprint_error_dev(sc->jme_dev, |
| 763 | "can't allocate rx mbuf\n" ); |
| 764 | for (i--; i >= 0; i--) { |
| 765 | bus_dmamap_unload(sc->jme_dmatag, |
| 766 | sc->jme_rxmbufm[i]); |
| 767 | m_freem(sc->jme_rxmbuf[i]); |
| 768 | sc->jme_rxmbuf[i] = NULL; |
| 769 | } |
| 770 | splx(s); |
| 771 | return ENOMEM; |
| 772 | } |
| 773 | } |
| 774 | /* init TX ring */ |
| 775 | memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); |
| 776 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, |
| 777 | 0, JME_NBUFS * sizeof(struct jme_desc), |
| 778 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
| 779 | for (i = 0; i < JME_NBUFS; i++) |
| 780 | sc->jme_txmbuf[i] = NULL; |
| 781 | sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; |
| 782 | |
| 783 | /* Reprogram the station address. */ |
| 784 | memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); |
| 785 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, |
| 786 | eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); |
| 787 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 788 | JME_PAR1, eaddr[5] << 8 | eaddr[4]); |
| 789 | |
| 790 | /* |
| 791 | * Configure Tx queue. |
| 792 | * Tx priority queue weight value : 0 |
| 793 | * Tx FIFO threshold for processing next packet : 16QW |
| 794 | * Maximum Tx DMA length : 512 |
| 795 | * Allow Tx DMA burst. |
| 796 | */ |
| 797 | sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); |
| 798 | sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); |
| 799 | sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; |
| 800 | sc->jme_txcsr |= TXCSR_DMA_SIZE_512; |
| 801 | sc->jme_txcsr |= TXCSR_DMA_BURST; |
| 802 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 803 | JME_TXCSR, sc->jme_txcsr); |
| 804 | |
| 805 | /* Set Tx descriptor counter. */ |
| 806 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 807 | JME_TXQDC, JME_NBUFS); |
| 808 | |
| 809 | /* Set Tx ring address to the hardware. */ |
| 810 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, |
| 811 | JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); |
| 812 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, |
| 813 | JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); |
| 814 | |
| 815 | /* Configure TxMAC parameters. */ |
| 816 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, |
| 817 | TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | |
| 818 | TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); |
| 819 | |
| 820 | /* |
| 821 | * Configure Rx queue. |
| 822 | * FIFO full threshold for transmitting Tx pause packet : 128T |
| 823 | * FIFO threshold for processing next packet : 128QW |
| 824 | * Rx queue 0 select |
| 825 | * Max Rx DMA length : 128 |
| 826 | * Rx descriptor retry : 32 |
| 827 | * Rx descriptor retry time gap : 256ns |
| 828 | * Don't receive runt/bad frame. |
| 829 | */ |
| 830 | sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; |
| 831 | /* |
| 832 | * Since Rx FIFO size is 4K bytes, receiving frames larger |
| 833 | * than 4K bytes will suffer from Rx FIFO overruns. So |
| 834 | * decrease FIFO threshold to reduce the FIFO overruns for |
| 835 | * frames larger than 4000 bytes. |
| 836 | * For best performance of standard MTU sized frames use |
| 837 | * maximum allowable FIFO threshold, 128QW. |
| 838 | */ |
| 839 | if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + |
| 840 | ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) |
| 841 | sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; |
| 842 | else |
| 843 | sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; |
| 844 | sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); |
| 845 | sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); |
| 846 | sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; |
| 847 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 848 | JME_RXCSR, sc->jme_rxcsr); |
| 849 | |
| 850 | /* Set Rx descriptor counter. */ |
| 851 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 852 | JME_RXQDC, JME_NBUFS); |
| 853 | |
| 854 | /* Set Rx ring address to the hardware. */ |
| 855 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, |
| 856 | JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); |
| 857 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, |
| 858 | JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); |
| 859 | |
| 860 | /* Clear receive filter. */ |
| 861 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); |
| 862 | /* Set up the receive filter. */ |
| 863 | jme_set_filter(sc); |
| 864 | |
| 865 | /* |
| 866 | * Disable all WOL bits as WOL can interfere normal Rx |
| 867 | * operation. Also clear WOL detection status bits. |
| 868 | */ |
| 869 | reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); |
| 870 | reg &= ~PMCS_WOL_ENB_MASK; |
| 871 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); |
| 872 | |
| 873 | reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); |
| 874 | /* |
| 875 | * Pad 10bytes right before received frame. This will greatly |
| 876 | * help Rx performance on strict-alignment architectures as |
| 877 | * it does not need to copy the frame to align the payload. |
| 878 | */ |
| 879 | reg |= RXMAC_PAD_10BYTES; |
| 880 | if ((ifp->if_capenable & |
| 881 | (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| |
| 882 | IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) |
| 883 | reg |= RXMAC_CSUM_ENB; |
| 884 | reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ |
| 885 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); |
| 886 | |
| 887 | /* Configure general purpose reg0 */ |
| 888 | reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); |
| 889 | reg &= ~GPREG0_PCC_UNIT_MASK; |
| 890 | /* Set PCC timer resolution to micro-seconds unit. */ |
| 891 | reg |= GPREG0_PCC_UNIT_US; |
| 892 | /* |
| 893 | * Disable all shadow register posting as we have to read |
| 894 | * JME_INTR_STATUS register in jme_int_task. Also it seems |
| 895 | * that it's hard to synchronize interrupt status between |
| 896 | * hardware and software with shadow posting due to |
| 897 | * requirements of bus_dmamap_sync(9). |
| 898 | */ |
| 899 | reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | |
| 900 | GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | |
| 901 | GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | |
| 902 | GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; |
| 903 | /* Disable posting of DW0. */ |
| 904 | reg &= ~GPREG0_POST_DW0_ENB; |
| 905 | /* Clear PME message. */ |
| 906 | reg &= ~GPREG0_PME_ENB; |
| 907 | /* Set PHY address. */ |
| 908 | reg &= ~GPREG0_PHY_ADDR_MASK; |
| 909 | reg |= sc->jme_phyaddr; |
| 910 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); |
| 911 | |
| 912 | /* Configure Tx queue 0 packet completion coalescing. */ |
| 913 | reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; |
| 914 | reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; |
| 915 | reg |= PCCTX_COAL_TXQ0; |
| 916 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); |
| 917 | |
| 918 | /* Configure Rx queue 0 packet completion coalescing. */ |
| 919 | reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; |
| 920 | reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; |
| 921 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); |
| 922 | |
| 923 | /* Disable Timers */ |
| 924 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); |
| 925 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); |
| 926 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); |
| 927 | |
| 928 | /* Configure retry transmit period, retry limit value. */ |
| 929 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, |
| 930 | ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & |
| 931 | TXTRHD_RT_PERIOD_MASK) | |
| 932 | ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & |
| 933 | TXTRHD_RT_LIMIT_SHIFT)); |
| 934 | |
| 935 | /* Disable RSS. */ |
| 936 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 937 | JME_RSSC, RSSC_DIS_RSS); |
| 938 | |
| 939 | /* Initialize the interrupt mask. */ |
| 940 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 941 | JME_INTR_MASK_SET, JME_INTRS_ENABLE); |
| 942 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 943 | JME_INTR_STATUS, 0xFFFFFFFF); |
| 944 | |
| 945 | /* set media, if not already handling a media change */ |
| 946 | if (do_ifinit) { |
| 947 | int error; |
| 948 | if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) |
| 949 | error = 0; |
| 950 | else if (error != 0) { |
| 951 | aprint_error_dev(sc->jme_dev, "could not set media\n" ); |
| 952 | splx(s); |
| 953 | return error; |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | /* Program MAC with resolved speed/duplex/flow-control. */ |
| 958 | jme_mac_config(sc); |
| 959 | |
| 960 | /* Start receiver/transmitter. */ |
| 961 | sc->jme_rx_cons = 0; |
| 962 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, |
| 963 | sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); |
| 964 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, |
| 965 | sc->jme_txcsr | TXCSR_TX_ENB); |
| 966 | |
| 967 | /* start ticks calls */ |
| 968 | callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); |
| 969 | sc->jme_if.if_flags |= IFF_RUNNING; |
| 970 | sc->jme_if.if_flags &= ~IFF_OACTIVE; |
| 971 | splx(s); |
| 972 | return 0; |
| 973 | } |
| 974 | |
| 975 | |
| 976 | int |
| 977 | jme_mii_read(device_t self, int phy, int reg) |
| 978 | { |
| 979 | struct jme_softc *sc = device_private(self); |
| 980 | int val, i; |
| 981 | |
| 982 | /* For FPGA version, PHY address 0 should be ignored. */ |
| 983 | if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { |
| 984 | if (phy == 0) |
| 985 | return (0); |
| 986 | } else { |
| 987 | if (sc->jme_phyaddr != phy) |
| 988 | return (0); |
| 989 | } |
| 990 | |
| 991 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, |
| 992 | SMI_OP_READ | SMI_OP_EXECUTE | |
| 993 | SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); |
| 994 | for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { |
| 995 | delay(10); |
| 996 | if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 997 | JME_SMI)) & SMI_OP_EXECUTE) == 0) |
| 998 | break; |
| 999 | } |
| 1000 | |
| 1001 | if (i == 0) { |
| 1002 | aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n" , reg); |
| 1003 | return (0); |
| 1004 | } |
| 1005 | |
| 1006 | return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); |
| 1007 | } |
| 1008 | |
| 1009 | void |
| 1010 | jme_mii_write(device_t self, int phy, int reg, int val) |
| 1011 | { |
| 1012 | struct jme_softc *sc = device_private(self); |
| 1013 | int i; |
| 1014 | |
| 1015 | /* For FPGA version, PHY address 0 should be ignored. */ |
| 1016 | if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { |
| 1017 | if (phy == 0) |
| 1018 | return; |
| 1019 | } else { |
| 1020 | if (sc->jme_phyaddr != phy) |
| 1021 | return; |
| 1022 | } |
| 1023 | |
| 1024 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, |
| 1025 | SMI_OP_WRITE | SMI_OP_EXECUTE | |
| 1026 | ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | |
| 1027 | SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); |
| 1028 | for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { |
| 1029 | delay(10); |
| 1030 | if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 1031 | JME_SMI)) & SMI_OP_EXECUTE) == 0) |
| 1032 | break; |
| 1033 | } |
| 1034 | |
| 1035 | if (i == 0) |
| 1036 | aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n" , reg); |
| 1037 | |
| 1038 | return; |
| 1039 | } |
| 1040 | |
| 1041 | void |
| 1042 | jme_statchg(struct ifnet *ifp) |
| 1043 | { |
| 1044 | if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) |
| 1045 | jme_init(ifp, 0); |
| 1046 | } |
| 1047 | |
| 1048 | static void |
| 1049 | jme_intr_rx(jme_softc_t *sc) { |
| 1050 | struct mbuf *m, *mhead; |
| 1051 | bus_dmamap_t mmap; |
| 1052 | struct ifnet *ifp = &sc->jme_if; |
| 1053 | uint32_t flags, buflen; |
| 1054 | int i, ipackets, nsegs, seg, error; |
| 1055 | struct jme_desc *desc; |
| 1056 | |
| 1057 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, |
| 1058 | sizeof(struct jme_desc) * JME_NBUFS, |
| 1059 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); |
| 1060 | #ifdef JMEDEBUG_RX |
| 1061 | printf("rxintr sc->jme_rx_cons %d flags 0x%x\n" , |
| 1062 | sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); |
| 1063 | #endif |
| 1064 | ipackets = 0; |
| 1065 | while((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) |
| 1066 | == 0) { |
| 1067 | i = sc->jme_rx_cons; |
| 1068 | desc = &sc->jme_rxring[i]; |
| 1069 | #ifdef JMEDEBUG_RX |
| 1070 | printf("rxintr i %d flags 0x%x buflen 0x%x\n" , |
| 1071 | i, le32toh(desc->flags), le32toh(desc->buflen)); |
| 1072 | #endif |
| 1073 | if (sc->jme_rxmbuf[i] == NULL) { |
| 1074 | if ((error = jme_add_rxbuf(sc, NULL)) != 0) { |
| 1075 | aprint_error_dev(sc->jme_dev, |
| 1076 | "can't add new mbuf to empty slot: %d\n" , |
| 1077 | error); |
| 1078 | break; |
| 1079 | } |
| 1080 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1081 | i = sc->jme_rx_cons; |
| 1082 | continue; |
| 1083 | } |
| 1084 | if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) |
| 1085 | break; |
| 1086 | |
| 1087 | buflen = le32toh(desc->buflen); |
| 1088 | nsegs = JME_RX_NSEGS(buflen); |
| 1089 | flags = le32toh(desc->flags); |
| 1090 | if ((buflen & JME_RX_ERR_STAT) != 0 || |
| 1091 | JME_RX_BYTES(buflen) < sizeof(struct ether_header) || |
| 1092 | JME_RX_BYTES(buflen) > |
| 1093 | (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { |
| 1094 | #ifdef JMEDEBUG_RX |
| 1095 | printf("rx error flags 0x%x buflen 0x%x\n" , |
| 1096 | flags, buflen); |
| 1097 | #endif |
| 1098 | ifp->if_ierrors++; |
| 1099 | /* reuse the mbufs */ |
| 1100 | for (seg = 0; seg < nsegs; seg++) { |
| 1101 | m = sc->jme_rxmbuf[i]; |
| 1102 | sc->jme_rxmbuf[i] = NULL; |
| 1103 | mmap = sc->jme_rxmbufm[i]; |
| 1104 | bus_dmamap_sync(sc->jme_dmatag, mmap, 0, |
| 1105 | mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 1106 | bus_dmamap_unload(sc->jme_dmatag, mmap); |
| 1107 | if ((error = jme_add_rxbuf(sc, m)) != 0) |
| 1108 | aprint_error_dev(sc->jme_dev, |
| 1109 | "can't reuse mbuf: %d\n" , error); |
| 1110 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1111 | i = sc->jme_rx_cons; |
| 1112 | } |
| 1113 | continue; |
| 1114 | } |
| 1115 | /* receive this packet */ |
| 1116 | mhead = m = sc->jme_rxmbuf[i]; |
| 1117 | sc->jme_rxmbuf[i] = NULL; |
| 1118 | mmap = sc->jme_rxmbufm[i]; |
| 1119 | bus_dmamap_sync(sc->jme_dmatag, mmap, 0, |
| 1120 | mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 1121 | bus_dmamap_unload(sc->jme_dmatag, mmap); |
| 1122 | /* add a new buffer to chain */ |
| 1123 | if (jme_add_rxbuf(sc, NULL) != 0) { |
| 1124 | if ((error = jme_add_rxbuf(sc, m)) != 0) |
| 1125 | aprint_error_dev(sc->jme_dev, |
| 1126 | "can't reuse mbuf: %d\n" , error); |
| 1127 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1128 | i = sc->jme_rx_cons; |
| 1129 | for (seg = 1; seg < nsegs; seg++) { |
| 1130 | m = sc->jme_rxmbuf[i]; |
| 1131 | sc->jme_rxmbuf[i] = NULL; |
| 1132 | mmap = sc->jme_rxmbufm[i]; |
| 1133 | bus_dmamap_sync(sc->jme_dmatag, mmap, 0, |
| 1134 | mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 1135 | bus_dmamap_unload(sc->jme_dmatag, mmap); |
| 1136 | if ((error = jme_add_rxbuf(sc, m)) != 0) |
| 1137 | aprint_error_dev(sc->jme_dev, |
| 1138 | "can't reuse mbuf: %d\n" , error); |
| 1139 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1140 | i = sc->jme_rx_cons; |
| 1141 | } |
| 1142 | ifp->if_ierrors++; |
| 1143 | continue; |
| 1144 | } |
| 1145 | |
| 1146 | /* build mbuf chain: head, then remaining segments */ |
| 1147 | m_set_rcvif(m, ifp); |
| 1148 | m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; |
| 1149 | m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : |
| 1150 | m->m_pkthdr.len; |
| 1151 | m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; |
| 1152 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1153 | for (seg = 1; seg < nsegs; seg++) { |
| 1154 | i = sc->jme_rx_cons; |
| 1155 | m = sc->jme_rxmbuf[i]; |
| 1156 | sc->jme_rxmbuf[i] = NULL; |
| 1157 | mmap = sc->jme_rxmbufm[i]; |
| 1158 | bus_dmamap_sync(sc->jme_dmatag, mmap, 0, |
| 1159 | mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
| 1160 | bus_dmamap_unload(sc->jme_dmatag, mmap); |
| 1161 | if ((error = jme_add_rxbuf(sc, NULL)) != 0) |
| 1162 | aprint_error_dev(sc->jme_dev, |
| 1163 | "can't add new mbuf: %d\n" , error); |
| 1164 | m->m_flags &= ~M_PKTHDR; |
| 1165 | m_cat(mhead, m); |
| 1166 | JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); |
| 1167 | } |
| 1168 | /* and adjust last mbuf's size */ |
| 1169 | if (nsegs > 1) { |
| 1170 | m->m_len = |
| 1171 | JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); |
| 1172 | } |
| 1173 | ifp->if_ipackets++; |
| 1174 | ipackets++; |
| 1175 | bpf_mtap(ifp, mhead); |
| 1176 | |
| 1177 | if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && |
| 1178 | (flags & JME_RD_IPV4)) { |
| 1179 | mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; |
| 1180 | if (!(flags & JME_RD_IPCSUM)) |
| 1181 | mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; |
| 1182 | } |
| 1183 | if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && |
| 1184 | (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { |
| 1185 | mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; |
| 1186 | if (!(flags & JME_RD_TCPCSUM)) |
| 1187 | mhead->m_pkthdr.csum_flags |= |
| 1188 | M_CSUM_TCP_UDP_BAD; |
| 1189 | } |
| 1190 | if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && |
| 1191 | (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { |
| 1192 | mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; |
| 1193 | if (!(flags & JME_RD_UDPCSUM)) |
| 1194 | mhead->m_pkthdr.csum_flags |= |
| 1195 | M_CSUM_TCP_UDP_BAD; |
| 1196 | } |
| 1197 | if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && |
| 1198 | (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { |
| 1199 | mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; |
| 1200 | if (!(flags & JME_RD_TCPCSUM)) |
| 1201 | mhead->m_pkthdr.csum_flags |= |
| 1202 | M_CSUM_TCP_UDP_BAD; |
| 1203 | } |
| 1204 | if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && |
| 1205 | (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { |
| 1206 | m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; |
| 1207 | if (!(flags & JME_RD_UDPCSUM)) |
| 1208 | mhead->m_pkthdr.csum_flags |= |
| 1209 | M_CSUM_TCP_UDP_BAD; |
| 1210 | } |
| 1211 | if (flags & JME_RD_VLAN_TAG) { |
| 1212 | /* pass to vlan_input() */ |
| 1213 | VLAN_INPUT_TAG(ifp, mhead, |
| 1214 | (flags & JME_RD_VLAN_MASK), continue); |
| 1215 | } |
| 1216 | if_percpuq_enqueue(ifp->if_percpuq, mhead); |
| 1217 | } |
| 1218 | if (ipackets) |
| 1219 | rnd_add_uint32(&sc->rnd_source, ipackets); |
| 1220 | } |
| 1221 | |
| 1222 | static int |
| 1223 | jme_intr(void *v) |
| 1224 | { |
| 1225 | jme_softc_t *sc = v; |
| 1226 | uint32_t istatus; |
| 1227 | |
| 1228 | istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1229 | JME_INTR_STATUS); |
| 1230 | if (istatus == 0 || istatus == 0xFFFFFFFF) |
| 1231 | return 0; |
| 1232 | /* Disable interrupts. */ |
| 1233 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1234 | JME_INTR_MASK_CLR, 0xFFFFFFFF); |
| 1235 | again: |
| 1236 | /* and update istatus */ |
| 1237 | istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1238 | JME_INTR_STATUS); |
| 1239 | if ((istatus & JME_INTRS_CHECK) == 0) |
| 1240 | goto done; |
| 1241 | /* Reset PCC counter/timer and Ack interrupts. */ |
| 1242 | if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) |
| 1243 | istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; |
| 1244 | if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) |
| 1245 | istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; |
| 1246 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1247 | JME_INTR_STATUS, istatus); |
| 1248 | |
| 1249 | if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) |
| 1250 | goto done; |
| 1251 | #ifdef JMEDEBUG_RX |
| 1252 | printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n" , istatus, |
| 1253 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), |
| 1254 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), |
| 1255 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), |
| 1256 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), |
| 1257 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), |
| 1258 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); |
| 1259 | printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n" , |
| 1260 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), |
| 1261 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), |
| 1262 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), |
| 1263 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), |
| 1264 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); |
| 1265 | #endif |
| 1266 | if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) |
| 1267 | jme_intr_rx(sc); |
| 1268 | if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { |
| 1269 | /* |
| 1270 | * Notify hardware availability of new Rx |
| 1271 | * buffers. |
| 1272 | * Reading RXCSR takes very long time under |
| 1273 | * heavy load so cache RXCSR value and writes |
| 1274 | * the ORed value with the kick command to |
| 1275 | * the RXCSR. This saves one register access |
| 1276 | * cycle. |
| 1277 | */ |
| 1278 | sc->jme_rx_cons = 0; |
| 1279 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 1280 | JME_RXCSR, |
| 1281 | sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); |
| 1282 | } |
| 1283 | if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) |
| 1284 | jme_ifstart(&sc->jme_if); |
| 1285 | |
| 1286 | goto again; |
| 1287 | |
| 1288 | done: |
| 1289 | /* enable interrupts. */ |
| 1290 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1291 | JME_INTR_MASK_SET, JME_INTRS_ENABLE); |
| 1292 | return 1; |
| 1293 | } |
| 1294 | |
| 1295 | |
| 1296 | static int |
| 1297 | jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) |
| 1298 | { |
| 1299 | struct jme_softc *sc = ifp->if_softc; |
| 1300 | int s, error; |
| 1301 | struct ifreq *ifr; |
| 1302 | struct ifcapreq *ifcr; |
| 1303 | |
| 1304 | s = splnet(); |
| 1305 | /* |
| 1306 | * we can't support at the same time jumbo frames and |
| 1307 | * TX checksums offload/TSO |
| 1308 | */ |
| 1309 | switch(cmd) { |
| 1310 | case SIOCSIFMTU: |
| 1311 | ifr = data; |
| 1312 | if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && |
| 1313 | (ifp->if_capenable & ( |
| 1314 | IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| |
| 1315 | IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| |
| 1316 | IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { |
| 1317 | splx(s); |
| 1318 | return EINVAL; |
| 1319 | } |
| 1320 | break; |
| 1321 | case SIOCSIFCAP: |
| 1322 | ifcr = data; |
| 1323 | if (ifp->if_mtu > JME_TX_FIFO_SIZE && |
| 1324 | (ifcr->ifcr_capenable & ( |
| 1325 | IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| |
| 1326 | IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| |
| 1327 | IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { |
| 1328 | splx(s); |
| 1329 | return EINVAL; |
| 1330 | } |
| 1331 | break; |
| 1332 | } |
| 1333 | |
| 1334 | error = ether_ioctl(ifp, cmd, data); |
| 1335 | if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { |
| 1336 | if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { |
| 1337 | jme_set_filter(sc); |
| 1338 | error = 0; |
| 1339 | } else { |
| 1340 | error = jme_init(ifp, 0); |
| 1341 | } |
| 1342 | } |
| 1343 | splx(s); |
| 1344 | return error; |
| 1345 | } |
| 1346 | |
| 1347 | static int |
| 1348 | jme_encap(struct jme_softc *sc, struct mbuf **m_head) |
| 1349 | { |
| 1350 | struct jme_desc *desc; |
| 1351 | struct mbuf *m; |
| 1352 | struct m_tag *mtag; |
| 1353 | int error, i, prod, headdsc, nsegs; |
| 1354 | uint32_t cflags, tso_segsz; |
| 1355 | |
| 1356 | if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ |
| 1357 | /* |
| 1358 | * Due to the adherence to NDIS specification JMC250 |
| 1359 | * assumes upper stack computed TCP pseudo checksum |
| 1360 | * without including payload length. This breaks |
| 1361 | * checksum offload for TSO case so recompute TCP |
| 1362 | * pseudo checksum for JMC250. Hopefully this wouldn't |
| 1363 | * be much burden on modern CPUs. |
| 1364 | */ |
| 1365 | bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; |
| 1366 | int iphl = v4 ? |
| 1367 | M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : |
| 1368 | M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); |
| 1369 | /* |
| 1370 | * note: we support vlan offloading, so we should never have |
| 1371 | * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always |
| 1372 | * right. |
| 1373 | */ |
| 1374 | int hlen = ETHER_HDR_LEN + iphl; |
| 1375 | |
| 1376 | if (__predict_false((*m_head)->m_len < |
| 1377 | (hlen + sizeof(struct tcphdr)))) { |
| 1378 | /* |
| 1379 | * TCP/IP headers are not in the first mbuf; we need |
| 1380 | * to do this the slow and painful way. Let's just |
| 1381 | * hope this doesn't happen very often. |
| 1382 | */ |
| 1383 | struct tcphdr th; |
| 1384 | |
| 1385 | m_copydata((*m_head), hlen, sizeof(th), &th); |
| 1386 | if (v4) { |
| 1387 | struct ip ip; |
| 1388 | |
| 1389 | m_copydata((*m_head), ETHER_HDR_LEN, |
| 1390 | sizeof(ip), &ip); |
| 1391 | ip.ip_len = 0; |
| 1392 | m_copyback((*m_head), |
| 1393 | ETHER_HDR_LEN + offsetof(struct ip, ip_len), |
| 1394 | sizeof(ip.ip_len), &ip.ip_len); |
| 1395 | th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, |
| 1396 | ip.ip_dst.s_addr, htons(IPPROTO_TCP)); |
| 1397 | } else { |
| 1398 | #if INET6 |
| 1399 | struct ip6_hdr ip6; |
| 1400 | |
| 1401 | m_copydata((*m_head), ETHER_HDR_LEN, |
| 1402 | sizeof(ip6), &ip6); |
| 1403 | ip6.ip6_plen = 0; |
| 1404 | m_copyback((*m_head), ETHER_HDR_LEN + |
| 1405 | offsetof(struct ip6_hdr, ip6_plen), |
| 1406 | sizeof(ip6.ip6_plen), &ip6.ip6_plen); |
| 1407 | th.th_sum = in6_cksum_phdr(&ip6.ip6_src, |
| 1408 | &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); |
| 1409 | #endif /* INET6 */ |
| 1410 | } |
| 1411 | m_copyback((*m_head), |
| 1412 | hlen + offsetof(struct tcphdr, th_sum), |
| 1413 | sizeof(th.th_sum), &th.th_sum); |
| 1414 | |
| 1415 | hlen += th.th_off << 2; |
| 1416 | } else { |
| 1417 | /* |
| 1418 | * TCP/IP headers are in the first mbuf; we can do |
| 1419 | * this the easy way. |
| 1420 | */ |
| 1421 | struct tcphdr *th; |
| 1422 | |
| 1423 | if (v4) { |
| 1424 | struct ip *ip = |
| 1425 | (void *)(mtod((*m_head), char *) + |
| 1426 | ETHER_HDR_LEN); |
| 1427 | th = (void *)(mtod((*m_head), char *) + hlen); |
| 1428 | |
| 1429 | ip->ip_len = 0; |
| 1430 | th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, |
| 1431 | ip->ip_dst.s_addr, htons(IPPROTO_TCP)); |
| 1432 | } else { |
| 1433 | #if INET6 |
| 1434 | struct ip6_hdr *ip6 = |
| 1435 | (void *)(mtod((*m_head), char *) + |
| 1436 | ETHER_HDR_LEN); |
| 1437 | th = (void *)(mtod((*m_head), char *) + hlen); |
| 1438 | |
| 1439 | ip6->ip6_plen = 0; |
| 1440 | th->th_sum = in6_cksum_phdr(&ip6->ip6_src, |
| 1441 | &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); |
| 1442 | #endif /* INET6 */ |
| 1443 | } |
| 1444 | hlen += th->th_off << 2; |
| 1445 | } |
| 1446 | |
| 1447 | } |
| 1448 | |
| 1449 | prod = sc->jme_tx_prod; |
| 1450 | |
| 1451 | error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], |
| 1452 | *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); |
| 1453 | if (error) { |
| 1454 | if (error == EFBIG) { |
| 1455 | log(LOG_ERR, "%s: Tx packet consumes too many " |
| 1456 | "DMA segments, dropping...\n" , |
| 1457 | device_xname(sc->jme_dev)); |
| 1458 | m_freem(*m_head); |
| 1459 | m_head = NULL; |
| 1460 | } |
| 1461 | return (error); |
| 1462 | } |
| 1463 | /* |
| 1464 | * Check descriptor overrun. Leave one free descriptor. |
| 1465 | * Since we always use 64bit address mode for transmitting, |
| 1466 | * each Tx request requires one more dummy descriptor. |
| 1467 | */ |
| 1468 | nsegs = sc->jme_txmbufm[prod]->dm_nsegs; |
| 1469 | #ifdef JMEDEBUG_TX |
| 1470 | printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n" , prod, nsegs, sc->jme_tx_cnt); |
| 1471 | #endif |
| 1472 | if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { |
| 1473 | bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); |
| 1474 | return (ENOBUFS); |
| 1475 | } |
| 1476 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], |
| 1477 | 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); |
| 1478 | |
| 1479 | m = *m_head; |
| 1480 | cflags = 0; |
| 1481 | tso_segsz = 0; |
| 1482 | /* Configure checksum offload and TSO. */ |
| 1483 | if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { |
| 1484 | tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; |
| 1485 | cflags |= JME_TD_TSO; |
| 1486 | } else { |
| 1487 | if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) |
| 1488 | cflags |= JME_TD_IPCSUM; |
| 1489 | if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) |
| 1490 | cflags |= JME_TD_TCPCSUM; |
| 1491 | if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) |
| 1492 | cflags |= JME_TD_UDPCSUM; |
| 1493 | } |
| 1494 | /* Configure VLAN. */ |
| 1495 | if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { |
| 1496 | cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); |
| 1497 | cflags |= JME_TD_VLAN_TAG; |
| 1498 | } |
| 1499 | |
| 1500 | desc = &sc->jme_txring[prod]; |
| 1501 | desc->flags = htole32(cflags); |
| 1502 | desc->buflen = htole32(tso_segsz); |
| 1503 | desc->addr_hi = htole32(m->m_pkthdr.len); |
| 1504 | desc->addr_lo = 0; |
| 1505 | headdsc = prod; |
| 1506 | sc->jme_tx_cnt++; |
| 1507 | JME_DESC_INC(prod, JME_NBUFS); |
| 1508 | for (i = 0; i < nsegs; i++) { |
| 1509 | desc = &sc->jme_txring[prod]; |
| 1510 | desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); |
| 1511 | desc->buflen = |
| 1512 | htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); |
| 1513 | desc->addr_hi = htole32( |
| 1514 | JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); |
| 1515 | desc->addr_lo = htole32( |
| 1516 | JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); |
| 1517 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, |
| 1518 | prod * sizeof(struct jme_desc), sizeof(struct jme_desc), |
| 1519 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
| 1520 | sc->jme_txmbuf[prod] = NULL; |
| 1521 | sc->jme_tx_cnt++; |
| 1522 | JME_DESC_INC(prod, JME_NBUFS); |
| 1523 | } |
| 1524 | |
| 1525 | /* Update producer index. */ |
| 1526 | sc->jme_tx_prod = prod; |
| 1527 | #ifdef JMEDEBUG_TX |
| 1528 | printf("jme_encap prod now %d\n" , sc->jme_tx_prod); |
| 1529 | #endif |
| 1530 | /* |
| 1531 | * Finally request interrupt and give the first descriptor |
| 1532 | * owenership to hardware. |
| 1533 | */ |
| 1534 | desc = &sc->jme_txring[headdsc]; |
| 1535 | desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); |
| 1536 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, |
| 1537 | headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), |
| 1538 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
| 1539 | |
| 1540 | sc->jme_txmbuf[headdsc] = m; |
| 1541 | return (0); |
| 1542 | } |
| 1543 | |
| 1544 | static void |
| 1545 | jme_txeof(struct jme_softc *sc) |
| 1546 | { |
| 1547 | struct ifnet *ifp; |
| 1548 | struct jme_desc *desc; |
| 1549 | uint32_t status; |
| 1550 | int cons, cons0, nsegs, seg; |
| 1551 | |
| 1552 | ifp = &sc->jme_if; |
| 1553 | |
| 1554 | #ifdef JMEDEBUG_TX |
| 1555 | printf("jme_txeof cons %d prod %d\n" , |
| 1556 | sc->jme_tx_cons, sc->jme_tx_prod); |
| 1557 | printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " |
| 1558 | "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " |
| 1559 | "JME_TXTRHD 0x%x\n" , |
| 1560 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), |
| 1561 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), |
| 1562 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), |
| 1563 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), |
| 1564 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), |
| 1565 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), |
| 1566 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), |
| 1567 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); |
| 1568 | for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { |
| 1569 | desc = &sc->jme_txring[cons]; |
| 1570 | printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n" , cons, |
| 1571 | desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); |
| 1572 | JME_DESC_INC(cons, JME_NBUFS); |
| 1573 | } |
| 1574 | #endif |
| 1575 | |
| 1576 | cons = sc->jme_tx_cons; |
| 1577 | if (cons == sc->jme_tx_prod) |
| 1578 | return; |
| 1579 | |
| 1580 | /* |
| 1581 | * Go through our Tx list and free mbufs for those |
| 1582 | * frames which have been transmitted. |
| 1583 | */ |
| 1584 | for (; cons != sc->jme_tx_prod;) { |
| 1585 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, |
| 1586 | cons * sizeof(struct jme_desc), sizeof(struct jme_desc), |
| 1587 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); |
| 1588 | |
| 1589 | desc = &sc->jme_txring[cons]; |
| 1590 | status = le32toh(desc->flags); |
| 1591 | #ifdef JMEDEBUG_TX |
| 1592 | printf("jme_txeof %i status 0x%x nsegs %d\n" , cons, status, |
| 1593 | sc->jme_txmbufm[cons]->dm_nsegs); |
| 1594 | #endif |
| 1595 | if (status & JME_TD_OWN) |
| 1596 | break; |
| 1597 | |
| 1598 | if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) |
| 1599 | ifp->if_oerrors++; |
| 1600 | else { |
| 1601 | ifp->if_opackets++; |
| 1602 | if ((status & JME_TD_COLLISION) != 0) |
| 1603 | ifp->if_collisions += |
| 1604 | le32toh(desc->buflen) & |
| 1605 | JME_TD_BUF_LEN_MASK; |
| 1606 | } |
| 1607 | /* |
| 1608 | * Only the first descriptor of multi-descriptor |
| 1609 | * transmission is updated so driver have to skip entire |
| 1610 | * chained buffers for the transmiited frame. In other |
| 1611 | * words, JME_TD_OWN bit is valid only at the first |
| 1612 | * descriptor of a multi-descriptor transmission. |
| 1613 | */ |
| 1614 | nsegs = sc->jme_txmbufm[cons]->dm_nsegs; |
| 1615 | cons0 = cons; |
| 1616 | JME_DESC_INC(cons, JME_NBUFS); |
| 1617 | for (seg = 1; seg < nsegs + 1; seg++) { |
| 1618 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, |
| 1619 | cons * sizeof(struct jme_desc), |
| 1620 | sizeof(struct jme_desc), |
| 1621 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); |
| 1622 | sc->jme_txring[cons].flags = 0; |
| 1623 | JME_DESC_INC(cons, JME_NBUFS); |
| 1624 | } |
| 1625 | /* Reclaim transferred mbufs. */ |
| 1626 | bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], |
| 1627 | 0, sc->jme_txmbufm[cons0]->dm_mapsize, |
| 1628 | BUS_DMASYNC_POSTWRITE); |
| 1629 | bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); |
| 1630 | |
| 1631 | KASSERT(sc->jme_txmbuf[cons0] != NULL); |
| 1632 | m_freem(sc->jme_txmbuf[cons0]); |
| 1633 | sc->jme_txmbuf[cons0] = NULL; |
| 1634 | sc->jme_tx_cnt -= nsegs + 1; |
| 1635 | KASSERT(sc->jme_tx_cnt >= 0); |
| 1636 | sc->jme_if.if_flags &= ~IFF_OACTIVE; |
| 1637 | } |
| 1638 | sc->jme_tx_cons = cons; |
| 1639 | /* Unarm watchog timer when there is no pending descriptors in queue. */ |
| 1640 | if (sc->jme_tx_cnt == 0) |
| 1641 | ifp->if_timer = 0; |
| 1642 | #ifdef JMEDEBUG_TX |
| 1643 | printf("jme_txeof jme_tx_cnt %d\n" , sc->jme_tx_cnt); |
| 1644 | #endif |
| 1645 | } |
| 1646 | |
| 1647 | static void |
| 1648 | jme_ifstart(struct ifnet *ifp) |
| 1649 | { |
| 1650 | jme_softc_t *sc = ifp->if_softc; |
| 1651 | struct mbuf *mb_head; |
| 1652 | int enq; |
| 1653 | |
| 1654 | /* |
| 1655 | * check if we can free some desc. |
| 1656 | * Clear TX interrupt status to reset TX coalescing counters. |
| 1657 | */ |
| 1658 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1659 | JME_INTR_STATUS, INTR_TXQ_COMP); |
| 1660 | jme_txeof(sc); |
| 1661 | |
| 1662 | if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) |
| 1663 | return; |
| 1664 | for (enq = 0;; enq++) { |
| 1665 | nexttx: |
| 1666 | /* Grab a paquet for output */ |
| 1667 | IFQ_DEQUEUE(&ifp->if_snd, mb_head); |
| 1668 | if (mb_head == NULL) { |
| 1669 | #ifdef JMEDEBUG_TX |
| 1670 | printf("%s: nothing to send\n" , __func__); |
| 1671 | #endif |
| 1672 | break; |
| 1673 | } |
| 1674 | /* try to add this mbuf to the TX ring */ |
| 1675 | if (jme_encap(sc, &mb_head)) { |
| 1676 | if (mb_head == NULL) { |
| 1677 | ifp->if_oerrors++; |
| 1678 | /* packet dropped, try next one */ |
| 1679 | goto nexttx; |
| 1680 | } |
| 1681 | /* resource shortage, try again later */ |
| 1682 | IF_PREPEND(&ifp->if_snd, mb_head); |
| 1683 | ifp->if_flags |= IFF_OACTIVE; |
| 1684 | break; |
| 1685 | } |
| 1686 | /* Pass packet to bpf if there is a listener */ |
| 1687 | bpf_mtap(ifp, mb_head); |
| 1688 | } |
| 1689 | #ifdef JMEDEBUG_TX |
| 1690 | printf("jme_ifstart enq %d\n" , enq); |
| 1691 | #endif |
| 1692 | if (enq) { |
| 1693 | /* |
| 1694 | * Set a 5 second timer just in case we don't hear from |
| 1695 | * the card again. |
| 1696 | */ |
| 1697 | ifp->if_timer = 5; |
| 1698 | /* |
| 1699 | * Reading TXCSR takes very long time under heavy load |
| 1700 | * so cache TXCSR value and writes the ORed value with |
| 1701 | * the kick command to the TXCSR. This saves one register |
| 1702 | * access cycle. |
| 1703 | */ |
| 1704 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, |
| 1705 | sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); |
| 1706 | #ifdef JMEDEBUG_TX |
| 1707 | printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " |
| 1708 | "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " |
| 1709 | "JME_TXTRHD 0x%x\n" , |
| 1710 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), |
| 1711 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), |
| 1712 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), |
| 1713 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), |
| 1714 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), |
| 1715 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), |
| 1716 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), |
| 1717 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); |
| 1718 | #endif |
| 1719 | } |
| 1720 | } |
| 1721 | |
| 1722 | static void |
| 1723 | jme_ifwatchdog(struct ifnet *ifp) |
| 1724 | { |
| 1725 | jme_softc_t *sc = ifp->if_softc; |
| 1726 | |
| 1727 | if ((ifp->if_flags & IFF_RUNNING) == 0) |
| 1728 | return; |
| 1729 | printf("%s: device timeout\n" , device_xname(sc->jme_dev)); |
| 1730 | ifp->if_oerrors++; |
| 1731 | jme_init(ifp, 0); |
| 1732 | } |
| 1733 | |
| 1734 | static int |
| 1735 | jme_mediachange(struct ifnet *ifp) |
| 1736 | { |
| 1737 | int error; |
| 1738 | jme_softc_t *sc = ifp->if_softc; |
| 1739 | |
| 1740 | if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) |
| 1741 | error = 0; |
| 1742 | else if (error != 0) { |
| 1743 | aprint_error_dev(sc->jme_dev, "could not set media\n" ); |
| 1744 | return error; |
| 1745 | } |
| 1746 | return 0; |
| 1747 | } |
| 1748 | |
| 1749 | static void |
| 1750 | jme_ticks(void *v) |
| 1751 | { |
| 1752 | jme_softc_t *sc = v; |
| 1753 | int s = splnet(); |
| 1754 | |
| 1755 | /* Tick the MII. */ |
| 1756 | mii_tick(&sc->jme_mii); |
| 1757 | |
| 1758 | /* every seconds */ |
| 1759 | callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); |
| 1760 | splx(s); |
| 1761 | } |
| 1762 | |
| 1763 | static void |
| 1764 | jme_mac_config(jme_softc_t *sc) |
| 1765 | { |
| 1766 | uint32_t ghc, gpreg, rxmac, txmac, txpause; |
| 1767 | struct mii_data *mii = &sc->jme_mii; |
| 1768 | |
| 1769 | ghc = 0; |
| 1770 | rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); |
| 1771 | rxmac &= ~RXMAC_FC_ENB; |
| 1772 | txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); |
| 1773 | txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); |
| 1774 | txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); |
| 1775 | txpause &= ~TXPFC_PAUSE_ENB; |
| 1776 | |
| 1777 | if (mii->mii_media_active & IFM_FDX) { |
| 1778 | ghc |= GHC_FULL_DUPLEX; |
| 1779 | rxmac &= ~RXMAC_COLL_DET_ENB; |
| 1780 | txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | |
| 1781 | TXMAC_BACKOFF | TXMAC_CARRIER_EXT | |
| 1782 | TXMAC_FRAME_BURST); |
| 1783 | /* Disable retry transmit timer/retry limit. */ |
| 1784 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, |
| 1785 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) |
| 1786 | & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); |
| 1787 | } else { |
| 1788 | rxmac |= RXMAC_COLL_DET_ENB; |
| 1789 | txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; |
| 1790 | /* Enable retry transmit timer/retry limit. */ |
| 1791 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, |
| 1792 | bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); |
| 1793 | } |
| 1794 | /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ |
| 1795 | switch (IFM_SUBTYPE(mii->mii_media_active)) { |
| 1796 | case IFM_10_T: |
| 1797 | ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; |
| 1798 | break; |
| 1799 | case IFM_100_TX: |
| 1800 | ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; |
| 1801 | break; |
| 1802 | case IFM_1000_T: |
| 1803 | ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; |
| 1804 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) |
| 1805 | txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; |
| 1806 | break; |
| 1807 | default: |
| 1808 | break; |
| 1809 | } |
| 1810 | if ((sc->jme_flags & JME_FLAG_GIGA) && |
| 1811 | sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { |
| 1812 | /* |
| 1813 | * Workaround occasional packet loss issue of JMC250 A2 |
| 1814 | * when it runs on half-duplex media. |
| 1815 | */ |
| 1816 | #ifdef JMEDEBUG |
| 1817 | printf("JME250 A2 workaround\n" ); |
| 1818 | #endif |
| 1819 | gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1820 | JME_GPREG1); |
| 1821 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) |
| 1822 | gpreg &= ~GPREG1_HDPX_FIX; |
| 1823 | else |
| 1824 | gpreg |= GPREG1_HDPX_FIX; |
| 1825 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, |
| 1826 | JME_GPREG1, gpreg); |
| 1827 | /* Workaround CRC errors at 100Mbps on JMC250 A2. */ |
| 1828 | if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { |
| 1829 | /* Extend interface FIFO depth. */ |
| 1830 | jme_mii_write(sc->jme_dev, sc->jme_phyaddr, |
| 1831 | 0x1B, 0x0000); |
| 1832 | } else { |
| 1833 | /* Select default interface FIFO depth. */ |
| 1834 | jme_mii_write(sc->jme_dev, sc->jme_phyaddr, |
| 1835 | 0x1B, 0x0004); |
| 1836 | } |
| 1837 | } |
| 1838 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); |
| 1839 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); |
| 1840 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); |
| 1841 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); |
| 1842 | } |
| 1843 | |
| 1844 | static void |
| 1845 | jme_set_filter(jme_softc_t *sc) |
| 1846 | { |
| 1847 | struct ifnet *ifp = &sc->jme_if; |
| 1848 | struct ether_multistep step; |
| 1849 | struct ether_multi *enm; |
| 1850 | uint32_t hash[2] = {0, 0}; |
| 1851 | int i; |
| 1852 | uint32_t rxcfg; |
| 1853 | |
| 1854 | rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); |
| 1855 | rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | |
| 1856 | RXMAC_ALLMULTI); |
| 1857 | /* Always accept frames destined to our station address. */ |
| 1858 | rxcfg |= RXMAC_UNICAST; |
| 1859 | if ((ifp->if_flags & IFF_BROADCAST) != 0) |
| 1860 | rxcfg |= RXMAC_BROADCAST; |
| 1861 | if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { |
| 1862 | if ((ifp->if_flags & IFF_PROMISC) != 0) |
| 1863 | rxcfg |= RXMAC_PROMISC; |
| 1864 | if ((ifp->if_flags & IFF_ALLMULTI) != 0) |
| 1865 | rxcfg |= RXMAC_ALLMULTI; |
| 1866 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 1867 | JME_MAR0, 0xFFFFFFFF); |
| 1868 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 1869 | JME_MAR1, 0xFFFFFFFF); |
| 1870 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, |
| 1871 | JME_RXMAC, rxcfg); |
| 1872 | return; |
| 1873 | } |
| 1874 | /* |
| 1875 | * Set up the multicast address filter by passing all multicast |
| 1876 | * addresses through a CRC generator, and then using the low-order |
| 1877 | * 6 bits as an index into the 64 bit multicast hash table. The |
| 1878 | * high order bits select the register, while the rest of the bits |
| 1879 | * select the bit within the register. |
| 1880 | */ |
| 1881 | rxcfg |= RXMAC_MULTICAST; |
| 1882 | memset(hash, 0, sizeof(hash)); |
| 1883 | |
| 1884 | ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); |
| 1885 | while (enm != NULL) { |
| 1886 | #ifdef JEMDBUG |
| 1887 | printf("%s: addrs %s %s\n" , __func__, |
| 1888 | ether_sprintf(enm->enm_addrlo), |
| 1889 | ether_sprintf(enm->enm_addrhi)); |
| 1890 | #endif |
| 1891 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { |
| 1892 | i = ether_crc32_be(enm->enm_addrlo, 6); |
| 1893 | /* Just want the 6 least significant bits. */ |
| 1894 | i &= 0x3f; |
| 1895 | hash[i / 32] |= 1 << (i%32); |
| 1896 | } else { |
| 1897 | hash[0] = hash[1] = 0xffffffff; |
| 1898 | sc->jme_if.if_flags |= IFF_ALLMULTI; |
| 1899 | break; |
| 1900 | } |
| 1901 | ETHER_NEXT_MULTI(step, enm); |
| 1902 | } |
| 1903 | #ifdef JMEDEBUG |
| 1904 | printf("%s: hash1 %x has2 %x\n" , __func__, hash[0], hash[1]); |
| 1905 | #endif |
| 1906 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); |
| 1907 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); |
| 1908 | bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); |
| 1909 | } |
| 1910 | |
| 1911 | #if 0 |
| 1912 | static int |
| 1913 | jme_multicast_hash(uint8_t *a) |
| 1914 | { |
| 1915 | int hash; |
| 1916 | |
| 1917 | #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) |
| 1918 | #define xor8(a,b,c,d,e,f,g,h) \ |
| 1919 | (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ |
| 1920 | (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) |
| 1921 | |
| 1922 | hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), |
| 1923 | DA(a,36), DA(a,42)); |
| 1924 | hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), |
| 1925 | DA(a,37), DA(a,43)) << 1; |
| 1926 | hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), |
| 1927 | DA(a,38), DA(a,44)) << 2; |
| 1928 | hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), |
| 1929 | DA(a,39), DA(a,45)) << 3; |
| 1930 | hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), |
| 1931 | DA(a,40), DA(a,46)) << 4; |
| 1932 | hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), |
| 1933 | DA(a,41), DA(a,47)) << 5; |
| 1934 | |
| 1935 | return hash; |
| 1936 | } |
| 1937 | #endif |
| 1938 | |
| 1939 | static int |
| 1940 | jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) |
| 1941 | { |
| 1942 | uint32_t reg; |
| 1943 | int i; |
| 1944 | |
| 1945 | *val = 0; |
| 1946 | for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { |
| 1947 | reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, |
| 1948 | JME_SMBCSR); |
| 1949 | if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) |
| 1950 | break; |
| 1951 | delay(10); |
| 1952 | } |
| 1953 | |
| 1954 | if (i == 0) { |
| 1955 | aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n" ); |
| 1956 | return (ETIMEDOUT); |
| 1957 | } |
| 1958 | |
| 1959 | reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; |
| 1960 | bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, |
| 1961 | JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); |
| 1962 | for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { |
| 1963 | delay(10); |
| 1964 | reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, |
| 1965 | JME_SMBINTF); |
| 1966 | if ((reg & SMBINTF_CMD_TRIGGER) == 0) |
| 1967 | break; |
| 1968 | } |
| 1969 | |
| 1970 | if (i == 0) { |
| 1971 | aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n" ); |
| 1972 | return (ETIMEDOUT); |
| 1973 | } |
| 1974 | |
| 1975 | reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); |
| 1976 | *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; |
| 1977 | return (0); |
| 1978 | } |
| 1979 | |
| 1980 | |
| 1981 | static int |
| 1982 | jme_eeprom_macaddr(struct jme_softc *sc) |
| 1983 | { |
| 1984 | uint8_t eaddr[ETHER_ADDR_LEN]; |
| 1985 | uint8_t fup, reg, val; |
| 1986 | uint32_t offset; |
| 1987 | int match; |
| 1988 | |
| 1989 | offset = 0; |
| 1990 | if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || |
| 1991 | fup != JME_EEPROM_SIG0) |
| 1992 | return (ENOENT); |
| 1993 | if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || |
| 1994 | fup != JME_EEPROM_SIG1) |
| 1995 | return (ENOENT); |
| 1996 | match = 0; |
| 1997 | do { |
| 1998 | if (jme_eeprom_read_byte(sc, offset, &fup) != 0) |
| 1999 | break; |
| 2000 | if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) |
| 2001 | == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { |
| 2002 | if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) |
| 2003 | break; |
| 2004 | if (reg >= JME_PAR0 && |
| 2005 | reg < JME_PAR0 + ETHER_ADDR_LEN) { |
| 2006 | if (jme_eeprom_read_byte(sc, offset + 2, |
| 2007 | &val) != 0) |
| 2008 | break; |
| 2009 | eaddr[reg - JME_PAR0] = val; |
| 2010 | match++; |
| 2011 | } |
| 2012 | } |
| 2013 | if (fup & JME_EEPROM_DESC_END) |
| 2014 | break; |
| 2015 | |
| 2016 | /* Try next eeprom descriptor. */ |
| 2017 | offset += JME_EEPROM_DESC_BYTES; |
| 2018 | } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); |
| 2019 | |
| 2020 | if (match == ETHER_ADDR_LEN) { |
| 2021 | memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); |
| 2022 | return (0); |
| 2023 | } |
| 2024 | |
| 2025 | return (ENOENT); |
| 2026 | } |
| 2027 | |
| 2028 | static int |
| 2029 | jme_reg_macaddr(struct jme_softc *sc) |
| 2030 | { |
| 2031 | uint32_t par0, par1; |
| 2032 | |
| 2033 | par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); |
| 2034 | par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); |
| 2035 | par1 &= 0xffff; |
| 2036 | if ((par0 == 0 && par1 == 0) || |
| 2037 | (par0 == 0xffffffff && par1 == 0xffff)) { |
| 2038 | return (ENOENT); |
| 2039 | } else { |
| 2040 | sc->jme_enaddr[0] = (par0 >> 0) & 0xff; |
| 2041 | sc->jme_enaddr[1] = (par0 >> 8) & 0xff; |
| 2042 | sc->jme_enaddr[2] = (par0 >> 16) & 0xff; |
| 2043 | sc->jme_enaddr[3] = (par0 >> 24) & 0xff; |
| 2044 | sc->jme_enaddr[4] = (par1 >> 0) & 0xff; |
| 2045 | sc->jme_enaddr[5] = (par1 >> 8) & 0xff; |
| 2046 | } |
| 2047 | return (0); |
| 2048 | } |
| 2049 | |
| 2050 | /* |
| 2051 | * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be |
| 2052 | * set up in jme_pci_attach() |
| 2053 | */ |
| 2054 | SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup" ) |
| 2055 | { |
| 2056 | int rc; |
| 2057 | const struct sysctlnode *node; |
| 2058 | |
| 2059 | if ((rc = sysctl_createv(clog, 0, NULL, &node, |
| 2060 | 0, CTLTYPE_NODE, "jme" , |
| 2061 | SYSCTL_DESCR("jme interface controls" ), |
| 2062 | NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { |
| 2063 | goto err; |
| 2064 | } |
| 2065 | |
| 2066 | jme_root_num = node->sysctl_num; |
| 2067 | return; |
| 2068 | |
| 2069 | err: |
| 2070 | aprint_error("%s: syctl_createv failed (rc = %d)\n" , __func__, rc); |
| 2071 | } |
| 2072 | |
| 2073 | static int |
| 2074 | jme_sysctl_intrxto(SYSCTLFN_ARGS) |
| 2075 | { |
| 2076 | int error, t; |
| 2077 | struct sysctlnode node; |
| 2078 | struct jme_softc *sc; |
| 2079 | uint32_t reg; |
| 2080 | |
| 2081 | node = *rnode; |
| 2082 | sc = node.sysctl_data; |
| 2083 | t = sc->jme_intrxto; |
| 2084 | node.sysctl_data = &t; |
| 2085 | error = sysctl_lookup(SYSCTLFN_CALL(&node)); |
| 2086 | if (error || newp == NULL) |
| 2087 | return error; |
| 2088 | |
| 2089 | if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) |
| 2090 | return EINVAL; |
| 2091 | |
| 2092 | /* |
| 2093 | * update the softc with sysctl-changed value, and mark |
| 2094 | * for hardware update |
| 2095 | */ |
| 2096 | sc->jme_intrxto = t; |
| 2097 | /* Configure Rx queue 0 packet completion coalescing. */ |
| 2098 | reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; |
| 2099 | reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; |
| 2100 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); |
| 2101 | return 0; |
| 2102 | } |
| 2103 | |
| 2104 | static int |
| 2105 | jme_sysctl_intrxct(SYSCTLFN_ARGS) |
| 2106 | { |
| 2107 | int error, t; |
| 2108 | struct sysctlnode node; |
| 2109 | struct jme_softc *sc; |
| 2110 | uint32_t reg; |
| 2111 | |
| 2112 | node = *rnode; |
| 2113 | sc = node.sysctl_data; |
| 2114 | t = sc->jme_intrxct; |
| 2115 | node.sysctl_data = &t; |
| 2116 | error = sysctl_lookup(SYSCTLFN_CALL(&node)); |
| 2117 | if (error || newp == NULL) |
| 2118 | return error; |
| 2119 | |
| 2120 | if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) |
| 2121 | return EINVAL; |
| 2122 | |
| 2123 | /* |
| 2124 | * update the softc with sysctl-changed value, and mark |
| 2125 | * for hardware update |
| 2126 | */ |
| 2127 | sc->jme_intrxct = t; |
| 2128 | /* Configure Rx queue 0 packet completion coalescing. */ |
| 2129 | reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; |
| 2130 | reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; |
| 2131 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); |
| 2132 | return 0; |
| 2133 | } |
| 2134 | |
| 2135 | static int |
| 2136 | jme_sysctl_inttxto(SYSCTLFN_ARGS) |
| 2137 | { |
| 2138 | int error, t; |
| 2139 | struct sysctlnode node; |
| 2140 | struct jme_softc *sc; |
| 2141 | uint32_t reg; |
| 2142 | |
| 2143 | node = *rnode; |
| 2144 | sc = node.sysctl_data; |
| 2145 | t = sc->jme_inttxto; |
| 2146 | node.sysctl_data = &t; |
| 2147 | error = sysctl_lookup(SYSCTLFN_CALL(&node)); |
| 2148 | if (error || newp == NULL) |
| 2149 | return error; |
| 2150 | |
| 2151 | if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) |
| 2152 | return EINVAL; |
| 2153 | |
| 2154 | /* |
| 2155 | * update the softc with sysctl-changed value, and mark |
| 2156 | * for hardware update |
| 2157 | */ |
| 2158 | sc->jme_inttxto = t; |
| 2159 | /* Configure Tx queue 0 packet completion coalescing. */ |
| 2160 | reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; |
| 2161 | reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; |
| 2162 | reg |= PCCTX_COAL_TXQ0; |
| 2163 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); |
| 2164 | return 0; |
| 2165 | } |
| 2166 | |
| 2167 | static int |
| 2168 | jme_sysctl_inttxct(SYSCTLFN_ARGS) |
| 2169 | { |
| 2170 | int error, t; |
| 2171 | struct sysctlnode node; |
| 2172 | struct jme_softc *sc; |
| 2173 | uint32_t reg; |
| 2174 | |
| 2175 | node = *rnode; |
| 2176 | sc = node.sysctl_data; |
| 2177 | t = sc->jme_inttxct; |
| 2178 | node.sysctl_data = &t; |
| 2179 | error = sysctl_lookup(SYSCTLFN_CALL(&node)); |
| 2180 | if (error || newp == NULL) |
| 2181 | return error; |
| 2182 | |
| 2183 | if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) |
| 2184 | return EINVAL; |
| 2185 | |
| 2186 | /* |
| 2187 | * update the softc with sysctl-changed value, and mark |
| 2188 | * for hardware update |
| 2189 | */ |
| 2190 | sc->jme_inttxct = t; |
| 2191 | /* Configure Tx queue 0 packet completion coalescing. */ |
| 2192 | reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; |
| 2193 | reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; |
| 2194 | reg |= PCCTX_COAL_TXQ0; |
| 2195 | bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); |
| 2196 | return 0; |
| 2197 | } |
| 2198 | |