| 1 | /* $NetBSD: nouveau_engine_disp_dport.c,v 1.2 2016/10/09 14:52:50 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2013 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_dport.c,v 1.2 2016/10/09 14:52:50 christos Exp $" ); |
| 29 | |
| 30 | #include <subdev/bios.h> |
| 31 | #include <subdev/bios/dcb.h> |
| 32 | #include <subdev/bios/dp.h> |
| 33 | #include <subdev/bios/init.h> |
| 34 | #include <subdev/i2c.h> |
| 35 | |
| 36 | #include <engine/disp.h> |
| 37 | |
| 38 | #include "dport.h" |
| 39 | |
| 40 | #define DBG(fmt, args...) nv_debug(dp->disp, "DP:%04x:%04x: " fmt, \ |
| 41 | dp->outp->hasht, dp->outp->hashm, ##args) |
| 42 | #define ERR(fmt, args...) nv_error(dp->disp, "DP:%04x:%04x: " fmt, \ |
| 43 | dp->outp->hasht, dp->outp->hashm, ##args) |
| 44 | |
| 45 | /****************************************************************************** |
| 46 | * link training |
| 47 | *****************************************************************************/ |
| 48 | struct dp_state { |
| 49 | const struct nouveau_dp_func *func; |
| 50 | struct nouveau_disp *disp; |
| 51 | struct dcb_output *outp; |
| 52 | struct nvbios_dpout info; |
| 53 | u8 version; |
| 54 | struct nouveau_i2c_port *aux; |
| 55 | int head; |
| 56 | u8 dpcd[4]; |
| 57 | int link_nr; |
| 58 | u32 link_bw; |
| 59 | u8 stat[6]; |
| 60 | u8 conf[4]; |
| 61 | }; |
| 62 | |
| 63 | static int |
| 64 | dp_set_link_config(struct dp_state *dp) |
| 65 | { |
| 66 | struct nouveau_disp *disp = dp->disp; |
| 67 | struct nouveau_bios *bios = nouveau_bios(disp); |
| 68 | struct nvbios_init init = { |
| 69 | .subdev = nv_subdev(dp->disp), |
| 70 | .bios = bios, |
| 71 | .offset = 0x0000, |
| 72 | .outp = dp->outp, |
| 73 | .crtc = dp->head, |
| 74 | .execute = 1, |
| 75 | }; |
| 76 | u32 lnkcmp; |
| 77 | u8 sink[2]; |
| 78 | int ret; |
| 79 | |
| 80 | DBG("%d lanes at %d KB/s\n" , dp->link_nr, dp->link_bw); |
| 81 | |
| 82 | /* set desired link configuration on the source */ |
| 83 | if ((lnkcmp = dp->info.lnkcmp)) { |
| 84 | if (dp->version < 0x30) { |
| 85 | while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) |
| 86 | lnkcmp += 4; |
| 87 | init.offset = nv_ro16(bios, lnkcmp + 2); |
| 88 | } else { |
| 89 | while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) |
| 90 | lnkcmp += 3; |
| 91 | init.offset = nv_ro16(bios, lnkcmp + 1); |
| 92 | } |
| 93 | |
| 94 | nvbios_exec(&init); |
| 95 | } |
| 96 | |
| 97 | ret = dp->func->lnk_ctl(dp->disp, dp->outp, dp->head, |
| 98 | dp->link_nr, dp->link_bw / 27000, |
| 99 | dp->dpcd[DPCD_RC02] & |
| 100 | DPCD_RC02_ENHANCED_FRAME_CAP); |
| 101 | if (ret) { |
| 102 | ERR("lnk_ctl failed with %d\n" , ret); |
| 103 | return ret; |
| 104 | } |
| 105 | |
| 106 | /* set desired link configuration on the sink */ |
| 107 | sink[0] = dp->link_bw / 27000; |
| 108 | sink[1] = dp->link_nr; |
| 109 | if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) |
| 110 | sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; |
| 111 | |
| 112 | return nv_wraux(dp->aux, DPCD_LC00, sink, 2); |
| 113 | } |
| 114 | |
| 115 | static void |
| 116 | dp_set_training_pattern(struct dp_state *dp, u8 pattern) |
| 117 | { |
| 118 | u8 sink_tp; |
| 119 | |
| 120 | DBG("training pattern %d\n" , pattern); |
| 121 | dp->func->pattern(dp->disp, dp->outp, dp->head, pattern); |
| 122 | |
| 123 | nv_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1); |
| 124 | sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; |
| 125 | sink_tp |= pattern; |
| 126 | nv_wraux(dp->aux, DPCD_LC02, &sink_tp, 1); |
| 127 | } |
| 128 | |
| 129 | static int |
| 130 | dp_link_train_commit(struct dp_state *dp) |
| 131 | { |
| 132 | int i; |
| 133 | |
| 134 | for (i = 0; i < dp->link_nr; i++) { |
| 135 | u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; |
| 136 | u8 lpre = (lane & 0x0c) >> 2; |
| 137 | u8 lvsw = (lane & 0x03) >> 0; |
| 138 | |
| 139 | dp->conf[i] = (lpre << 3) | lvsw; |
| 140 | if (lvsw == 3) |
| 141 | dp->conf[i] |= DPCD_LC03_MAX_SWING_REACHED; |
| 142 | if (lpre == 3) |
| 143 | dp->conf[i] |= DPCD_LC03_MAX_PRE_EMPHASIS_REACHED; |
| 144 | |
| 145 | DBG("config lane %d %02x\n" , i, dp->conf[i]); |
| 146 | dp->func->drv_ctl(dp->disp, dp->outp, dp->head, i, lvsw, lpre); |
| 147 | } |
| 148 | |
| 149 | return nv_wraux(dp->aux, DPCD_LC03(0), dp->conf, 4); |
| 150 | } |
| 151 | |
| 152 | static int |
| 153 | dp_link_train_update(struct dp_state *dp, u32 delay) |
| 154 | { |
| 155 | int ret; |
| 156 | |
| 157 | udelay(delay); |
| 158 | |
| 159 | ret = nv_rdaux(dp->aux, DPCD_LS02, dp->stat, 6); |
| 160 | if (ret) |
| 161 | return ret; |
| 162 | |
| 163 | DBG("status %6ph\n" , dp->stat); |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static int |
| 168 | dp_link_train_cr(struct dp_state *dp) |
| 169 | { |
| 170 | bool cr_done = false, abort = false; |
| 171 | int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 172 | int tries = 0, i; |
| 173 | |
| 174 | dp_set_training_pattern(dp, 1); |
| 175 | |
| 176 | do { |
| 177 | if (dp_link_train_commit(dp) || |
| 178 | dp_link_train_update(dp, 100)) |
| 179 | break; |
| 180 | |
| 181 | cr_done = true; |
| 182 | for (i = 0; i < dp->link_nr; i++) { |
| 183 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 184 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { |
| 185 | cr_done = false; |
| 186 | if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED) |
| 187 | abort = true; |
| 188 | break; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { |
| 193 | voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 194 | tries = 0; |
| 195 | } |
| 196 | } while (!cr_done && !abort && ++tries < 5); |
| 197 | |
| 198 | return cr_done ? 0 : -1; |
| 199 | } |
| 200 | |
| 201 | static int |
| 202 | dp_link_train_eq(struct dp_state *dp) |
| 203 | { |
| 204 | bool eq_done = false, cr_done = true; |
| 205 | int tries = 0, i; |
| 206 | |
| 207 | dp_set_training_pattern(dp, 2); |
| 208 | |
| 209 | do { |
| 210 | if (dp_link_train_update(dp, 400)) |
| 211 | break; |
| 212 | |
| 213 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); |
| 214 | for (i = 0; i < dp->link_nr && eq_done; i++) { |
| 215 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 216 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) |
| 217 | cr_done = false; |
| 218 | if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || |
| 219 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) |
| 220 | eq_done = false; |
| 221 | } |
| 222 | |
| 223 | if (dp_link_train_commit(dp)) |
| 224 | break; |
| 225 | } while (!eq_done && cr_done && ++tries <= 5); |
| 226 | |
| 227 | return eq_done ? 0 : -1; |
| 228 | } |
| 229 | |
| 230 | static void |
| 231 | dp_link_train_init(struct dp_state *dp, bool spread) |
| 232 | { |
| 233 | struct nvbios_init init = { |
| 234 | .subdev = nv_subdev(dp->disp), |
| 235 | .bios = nouveau_bios(dp->disp), |
| 236 | .outp = dp->outp, |
| 237 | .crtc = dp->head, |
| 238 | .execute = 1, |
| 239 | }; |
| 240 | |
| 241 | /* set desired spread */ |
| 242 | if (spread) |
| 243 | init.offset = dp->info.script[2]; |
| 244 | else |
| 245 | init.offset = dp->info.script[3]; |
| 246 | nvbios_exec(&init); |
| 247 | |
| 248 | /* pre-train script */ |
| 249 | init.offset = dp->info.script[0]; |
| 250 | nvbios_exec(&init); |
| 251 | } |
| 252 | |
| 253 | static void |
| 254 | dp_link_train_fini(struct dp_state *dp) |
| 255 | { |
| 256 | struct nvbios_init init = { |
| 257 | .subdev = nv_subdev(dp->disp), |
| 258 | .bios = nouveau_bios(dp->disp), |
| 259 | .outp = dp->outp, |
| 260 | .crtc = dp->head, |
| 261 | .execute = 1, |
| 262 | }; |
| 263 | |
| 264 | /* post-train script */ |
| 265 | init.offset = dp->info.script[1]; |
| 266 | nvbios_exec(&init); |
| 267 | } |
| 268 | |
| 269 | int |
| 270 | nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func, |
| 271 | struct dcb_output *outp, int head, u32 datarate) |
| 272 | { |
| 273 | struct nouveau_bios *bios = nouveau_bios(disp); |
| 274 | struct nouveau_i2c *i2c = nouveau_i2c(disp); |
| 275 | struct dp_state _dp = { |
| 276 | .disp = disp, |
| 277 | .func = func, |
| 278 | .outp = outp, |
| 279 | .head = head, |
| 280 | }, *dp = &_dp; |
| 281 | const u32 bw_list[] = { 540000, 270000, 162000, 0 }; |
| 282 | const u32 *link_bw = bw_list; |
| 283 | u8 hdr, cnt, len; |
| 284 | u32 data; |
| 285 | int ret; |
| 286 | |
| 287 | /* find the bios displayport data relevant to this output */ |
| 288 | data = nvbios_dpout_match(bios, outp->hasht, outp->hashm, &dp->version, |
| 289 | &hdr, &cnt, &len, &dp->info); |
| 290 | if (!data) { |
| 291 | ERR("bios data not found\n" ); |
| 292 | return -EINVAL; |
| 293 | } |
| 294 | |
| 295 | /* acquire the aux channel and fetch some info about the display */ |
| 296 | if (outp->location) |
| 297 | dp->aux = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(outp->extdev)); |
| 298 | else |
| 299 | dp->aux = i2c->find(i2c, NV_I2C_TYPE_DCBI2C(outp->i2c_index)); |
| 300 | if (!dp->aux) { |
| 301 | ERR("no aux channel?!\n" ); |
| 302 | return -ENODEV; |
| 303 | } |
| 304 | |
| 305 | ret = nv_rdaux(dp->aux, 0x00000, dp->dpcd, sizeof(dp->dpcd)); |
| 306 | if (ret) { |
| 307 | /* it's possible the display has been unplugged before we |
| 308 | * get here. we still need to execute the full set of |
| 309 | * vbios scripts, and program the OR at a high enough |
| 310 | * frequency to satisfy the target mode. failure to do |
| 311 | * so results at best in an UPDATE hanging, and at worst |
| 312 | * with PDISP running away to join the circus. |
| 313 | */ |
| 314 | dp->dpcd[1] = link_bw[0] / 27000; |
| 315 | dp->dpcd[2] = 4; |
| 316 | dp->dpcd[3] = 0x00; |
| 317 | ERR("failed to read DPCD\n" ); |
| 318 | } |
| 319 | |
| 320 | /* bring capabilities within encoder limits */ |
| 321 | if ((dp->dpcd[2] & 0x1f) > dp->outp->dpconf.link_nr) { |
| 322 | dp->dpcd[2] &= ~0x1f; |
| 323 | dp->dpcd[2] |= dp->outp->dpconf.link_nr; |
| 324 | } |
| 325 | if (dp->dpcd[1] > dp->outp->dpconf.link_bw) |
| 326 | dp->dpcd[1] = dp->outp->dpconf.link_bw; |
| 327 | |
| 328 | /* adjust required bandwidth for 8B/10B coding overhead */ |
| 329 | datarate = (datarate / 8) * 10; |
| 330 | |
| 331 | /* enable down-spreading and execute pre-train script from vbios */ |
| 332 | dp_link_train_init(dp, dp->dpcd[3] & 0x01); |
| 333 | |
| 334 | /* start off at highest link rate supported by encoder and display */ |
| 335 | while (*link_bw > (dp->dpcd[1] * 27000)) |
| 336 | link_bw++; |
| 337 | |
| 338 | while ((ret = -EIO) && link_bw[0]) { |
| 339 | /* find minimum required lane count at this link rate */ |
| 340 | dp->link_nr = dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT; |
| 341 | while ((dp->link_nr >> 1) * link_bw[0] > datarate) |
| 342 | dp->link_nr >>= 1; |
| 343 | |
| 344 | /* drop link rate to minimum with this lane count */ |
| 345 | while ((link_bw[1] * dp->link_nr) > datarate) |
| 346 | link_bw++; |
| 347 | dp->link_bw = link_bw[0]; |
| 348 | |
| 349 | /* program selected link configuration */ |
| 350 | ret = dp_set_link_config(dp); |
| 351 | if (ret == 0) { |
| 352 | /* attempt to train the link at this configuration */ |
| 353 | memset(dp->stat, 0x00, sizeof(dp->stat)); |
| 354 | if (!dp_link_train_cr(dp) && |
| 355 | !dp_link_train_eq(dp)) |
| 356 | break; |
| 357 | } else |
| 358 | if (ret) { |
| 359 | /* dp_set_link_config() handled training, or |
| 360 | * we failed to communicate with the sink. |
| 361 | */ |
| 362 | break; |
| 363 | } |
| 364 | |
| 365 | /* retry at lower rate */ |
| 366 | link_bw++; |
| 367 | } |
| 368 | |
| 369 | /* finish link training */ |
| 370 | dp_set_training_pattern(dp, 0); |
| 371 | if (ret < 0) |
| 372 | ERR("link training failed\n" ); |
| 373 | |
| 374 | /* execute post-train script from vbios */ |
| 375 | dp_link_train_fini(dp); |
| 376 | return (ret < 0) ? false : true; |
| 377 | } |
| 378 | |