| 1 | /* |
| 2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
| 3 | * Copyright (c) 2002-2004 Atheros Communications, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | * |
| 17 | * $Id: ar5210phy.h,v 1.1.1.1 2008/12/11 04:46:29 alc Exp $ |
| 18 | */ |
| 19 | #ifndef _DEV_ATH_AR5210PHY_H |
| 20 | #define _DEV_ATH_AR5210PHY_H |
| 21 | |
| 22 | /* |
| 23 | * Definitions for the PHY on the Atheros AR5210 parts. |
| 24 | */ |
| 25 | |
| 26 | /* PHY Registers */ |
| 27 | #define AR_PHY_BASE 0x9800 /* PHY register base */ |
| 28 | #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) |
| 29 | |
| 30 | #define AR_PHY_FRCTL 0x9804 /* PHY frame control */ |
| 31 | #define AR_PHY_TURBO_MODE 0x00000001 /* PHY turbo mode */ |
| 32 | #define AR_PHY_TURBO_SHORT 0x00000002 /* PHY turbo short symbol */ |
| 33 | #define AR_PHY_TIMING_ERR 0x01000000 /* Detect PHY timing error */ |
| 34 | #define AR_PHY_PARITY_ERR 0x02000000 /* Detect signal parity err */ |
| 35 | #define AR_PHY_ILLRATE_ERR 0x04000000 /* Detect PHY illegal rate */ |
| 36 | #define AR_PHY_ILLLEN_ERR 0x08000000 /* Detect PHY illegal length */ |
| 37 | #define AR_PHY_SERVICE_ERR 0x20000000 /* Detect PHY nonzero service */ |
| 38 | #define AR_PHY_TXURN_ERR 0x40000000 /* DetectPHY TX underrun */ |
| 39 | #define AR_PHY_FRCTL_BITS \ |
| 40 | "\20\1TURBO_MODE\2TURBO_SHORT\30TIMING_ERR\31PARITY_ERR\32ILLRATE_ERR"\ |
| 41 | "\33ILLEN_ERR\35SERVICE_ERR\36TXURN_ERR" |
| 42 | |
| 43 | #define AR_PHY_AGC 0x9808 /* PHY AGC command */ |
| 44 | #define AR_PHY_AGC_DISABLE 0x08000000 /* Disable PHY AGC */ |
| 45 | #define AR_PHY_AGC_BITS "\20\33DISABLE" |
| 46 | |
| 47 | #define AR_PHY_CHIPID 0x9818 /* PHY chip revision */ |
| 48 | |
| 49 | #define AR_PHY_ACTIVE 0x981c /* PHY activation */ |
| 50 | #define AR_PHY_ENABLE 0x00000001 /* activate PHY */ |
| 51 | #define AR_PHY_DISABLE 0x00000002 /* deactivate PHY */ |
| 52 | #define AR_PHY_ACTIVE_BITS "\20\1ENABLE\2DISABLE" |
| 53 | |
| 54 | #define AR_PHY_AGCCTL 0x9860 /* PHY calibration and noise floor */ |
| 55 | #define AR_PHY_AGC_CAL 0x00000001 /* PHY internal calibration */ |
| 56 | #define AR_PHY_AGC_NF 0x00000002 /* calc PHY noise-floor */ |
| 57 | #define AR_PHY_AGCCTL_BITS "\20\1CAL\2NF" |
| 58 | |
| 59 | #endif /* _DEV_ATH_AR5210PHY_H */ |
| 60 | |