| 1 | /* $NetBSD: if_skreg.h,v 1.15 2014/10/10 14:23:06 christos Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2003 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 26 | * POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ |
| 29 | /* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */ |
| 30 | /* $OpenBSD: if_skreg.h,v 1.41 2006/11/23 21:56:32 kettenis Exp $ */ |
| 31 | |
| 32 | /* |
| 33 | * Copyright (c) 1997, 1998, 1999, 2000 |
| 34 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * 1. Redistributions of source code must retain the above copyright |
| 40 | * notice, this list of conditions and the following disclaimer. |
| 41 | * 2. Redistributions in binary form must reproduce the above copyright |
| 42 | * notice, this list of conditions and the following disclaimer in the |
| 43 | * documentation and/or other materials provided with the distribution. |
| 44 | * 3. All advertising materials mentioning features or use of this software |
| 45 | * must display the following acknowledgement: |
| 46 | * This product includes software developed by Bill Paul. |
| 47 | * 4. Neither the name of the author nor the names of any co-contributors |
| 48 | * may be used to endorse or promote products derived from this software |
| 49 | * without specific prior written permission. |
| 50 | * |
| 51 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 52 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 53 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 54 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 55 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 56 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 57 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 58 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 59 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 60 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 61 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 62 | * |
| 63 | * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ |
| 64 | * $FreeBSD: /c/ncvs/src/sys/pci/xmaciireg.h,v 1.3 2000/04/22 02:16:37 wpaul Exp $ |
| 65 | */ |
| 66 | |
| 67 | /* |
| 68 | * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> |
| 69 | * |
| 70 | * Permission to use, copy, modify, and distribute this software for any |
| 71 | * purpose with or without fee is hereby granted, provided that the above |
| 72 | * copyright notice and this permission notice appear in all copies. |
| 73 | * |
| 74 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 75 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 76 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 77 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 78 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 79 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 80 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 81 | */ |
| 82 | |
| 83 | #ifndef _DEV_PCI_IF_SKREG_H_ |
| 84 | #define _DEV_PCI_IF_SKREG_H_ |
| 85 | |
| 86 | #include <net/if.h> |
| 87 | #include <net/if_ether.h> |
| 88 | #include <net/if_media.h> |
| 89 | |
| 90 | |
| 91 | /* |
| 92 | * GEnesis registers. The GEnesis chip has a 256-byte I/O window |
| 93 | * but internally it has a 16K register space. This 16K space is |
| 94 | * divided into 128-byte blocks. The first 128 bytes of the I/O |
| 95 | * window represent the first block, which is permanently mapped |
| 96 | * at the start of the window. The other 127 blocks can be mapped |
| 97 | * to the second 128 bytes of the I/O window by setting the desired |
| 98 | * block value in the RAP register in block 0. Not all of the 127 |
| 99 | * blocks are actually used. Most registers are 32 bits wide, but |
| 100 | * there are a few 16-bit and 8-bit ones as well. |
| 101 | */ |
| 102 | |
| 103 | |
| 104 | /* Start of remappable register window. */ |
| 105 | #define SK_WIN_BASE 0x0080 |
| 106 | |
| 107 | /* Size of a window */ |
| 108 | #define SK_WIN_LEN 0x80 |
| 109 | |
| 110 | #define SK_WIN_MASK 0x3F80 |
| 111 | #define SK_REG_MASK 0x7F |
| 112 | |
| 113 | /* Compute the window of a given register (for the RAP register) */ |
| 114 | #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) |
| 115 | |
| 116 | /* Compute the relative offset of a register within the window */ |
| 117 | #define SK_REG(reg) ((reg) & SK_REG_MASK) |
| 118 | |
| 119 | #define SK_PORT_A 0 |
| 120 | #define SK_PORT_B 1 |
| 121 | |
| 122 | /* |
| 123 | * Compute offset of port-specific register. Since there are two |
| 124 | * ports, there are two of some GEnesis modules (e.g. two sets of |
| 125 | * DMA queues, two sets of FIFO control registers, etc...). Normally, |
| 126 | * the block for port 0 is at offset 0x0 and the block for port 1 is |
| 127 | * at offset 0x80 (i.e. the next page over). However for the transmit |
| 128 | * BMUs and RAMbuffers, there are two blocks for each port: one for |
| 129 | * the sync transmit queue and one for the async queue (which we don't |
| 130 | * use). However instead of ordering them like this: |
| 131 | * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 |
| 132 | * SysKonnect has instead ordered them like this: |
| 133 | * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 |
| 134 | * This means that when referencing the TX BMU and RAMbuffer registers, |
| 135 | * we have to double the block offset (0x80 * 2) in order to reach the |
| 136 | * second queue. This prevents us from using the same formula |
| 137 | * (sk_port * 0x80) to compute the offsets for all of the port-specific |
| 138 | * blocks: we need an extra offset for the BMU and RAMbuffer registers. |
| 139 | * The simplest thing is to provide an extra argument to these macros: |
| 140 | * the 'skip' parameter. The 'skip' value is the number of extra pages |
| 141 | * for skip when computing the port0/port1 offsets. For most registers, |
| 142 | * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. |
| 143 | */ |
| 144 | #define SK_IF_READ_4(sc_if, skip, reg) \ |
| 145 | sk_win_read_4(sc_if->sk_softc, reg + \ |
| 146 | ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) |
| 147 | #define SK_IF_READ_2(sc_if, skip, reg) \ |
| 148 | sk_win_read_2(sc_if->sk_softc, reg + \ |
| 149 | ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) |
| 150 | #define SK_IF_READ_1(sc_if, skip, reg) \ |
| 151 | sk_win_read_1(sc_if->sk_softc, reg + \ |
| 152 | ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) |
| 153 | |
| 154 | #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ |
| 155 | sk_win_write_4(sc_if->sk_softc, \ |
| 156 | reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) |
| 157 | #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ |
| 158 | sk_win_write_2(sc_if->sk_softc, \ |
| 159 | reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) |
| 160 | #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ |
| 161 | sk_win_write_1(sc_if->sk_softc, \ |
| 162 | reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) |
| 163 | |
| 164 | /* Block 0 registers, permanently mapped at iobase. */ |
| 165 | #define SK_RAP 0x0000 |
| 166 | #define SK_CSR 0x0004 |
| 167 | #define SK_LED 0x0006 |
| 168 | /* XXX 0x0007 B0_POWER_CTRL */ |
| 169 | #define SK_ISR 0x0008 /* interrupt source */ |
| 170 | #define SK_IMR 0x000C /* interrupt mask */ |
| 171 | #define SK_IESR 0x0010 /* interrupt hardware error source */ |
| 172 | #define SK_IEMR 0x0014 /* interrupt hardware error mask */ |
| 173 | #define SK_ISSR 0x0018 /* special interrupt source */ |
| 174 | #define SK_Y2_ISSR2 0x001C |
| 175 | #define SK_Y2_ISSR3 0x0020 |
| 176 | #define SK_Y2_EISR 0x0024 |
| 177 | #define SK_Y2_LISR 0x0028 |
| 178 | #define SK_Y2_ICR 0x002C |
| 179 | #define SK_XM_IMR0 0x0020 |
| 180 | #define SK_XM_ISR0 0x0028 |
| 181 | #define SK_XM_PHYADDR0 0x0030 |
| 182 | #define SK_XM_PHYDATA0 0x0034 |
| 183 | #define SK_XM_IMR1 0x0040 |
| 184 | #define SK_XM_ISR1 0x0048 |
| 185 | #define SK_XM_PHYADDR1 0x0050 |
| 186 | #define SK_XM_PHYDATA1 0x0054 |
| 187 | #define SK_BMU_RX_CSR0 0x0060 |
| 188 | #define SK_BMU_RX_CSR1 0x0064 |
| 189 | #define SK_BMU_TXS_CSR0 0x0068 |
| 190 | #define SK_BMU_TXA_CSR0 0x006C |
| 191 | #define SK_BMU_TXS_CSR1 0x0070 |
| 192 | #define SK_BMU_TXA_CSR1 0x0074 |
| 193 | |
| 194 | /* SK_CSR register */ |
| 195 | #define SK_CSR_SW_RESET 0x0001 |
| 196 | #define SK_CSR_SW_UNRESET 0x0002 |
| 197 | #define SK_CSR_MASTER_RESET 0x0004 |
| 198 | #define SK_CSR_MASTER_UNRESET 0x0008 |
| 199 | #define SK_CSR_MASTER_STOP 0x0010 |
| 200 | #define SK_CSR_MASTER_DONE 0x0020 |
| 201 | #define SK_CSR_SW_IRQ_CLEAR 0x0040 |
| 202 | #define SK_CSR_SW_IRQ_SET 0x0080 |
| 203 | #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ |
| 204 | #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ |
| 205 | #define SK_CSR_ASF_OFF 0x1000 |
| 206 | #define SK_CSR_ASF_ON 0x2000 |
| 207 | #define SK_CSR_WOL_OFF __BIT(14) |
| 208 | #define SK_CSR_WOL_ON __BIT(15) |
| 209 | |
| 210 | /* SK_LED register */ |
| 211 | #define SK_LED_GREEN_OFF 0x01 |
| 212 | #define SK_LED_GREEN_ON 0x02 |
| 213 | |
| 214 | /* SK_ISR register */ |
| 215 | #define SK_ISR_TX2_AS_CHECK 0x00000001 |
| 216 | #define SK_ISR_TX2_AS_EOF 0x00000002 |
| 217 | #define SK_ISR_TX2_AS_EOB 0x00000004 |
| 218 | #define SK_ISR_TX2_S_CHECK 0x00000008 |
| 219 | #define SK_ISR_TX2_S_EOF 0x00000010 |
| 220 | #define SK_ISR_TX2_S_EOB 0x00000020 |
| 221 | #define SK_ISR_TX1_AS_CHECK 0x00000040 |
| 222 | #define SK_ISR_TX1_AS_EOF 0x00000080 |
| 223 | #define SK_ISR_TX1_AS_EOB 0x00000100 |
| 224 | #define SK_ISR_TX1_S_CHECK 0x00000200 |
| 225 | #define SK_ISR_TX1_S_EOF 0x00000400 |
| 226 | #define SK_ISR_TX1_S_EOB 0x00000800 |
| 227 | #define SK_ISR_RX2_CHECK 0x00001000 |
| 228 | #define SK_ISR_RX2_EOF 0x00002000 |
| 229 | #define SK_ISR_RX2_EOB 0x00004000 |
| 230 | #define SK_ISR_RX1_CHECK 0x00008000 |
| 231 | #define SK_ISR_RX1_EOF 0x00010000 |
| 232 | #define SK_ISR_RX1_EOB 0x00020000 |
| 233 | #define SK_ISR_LINK2_OFLOW 0x00040000 |
| 234 | #define SK_ISR_MAC2 0x00080000 |
| 235 | #define SK_ISR_LINK1_OFLOW 0x00100000 |
| 236 | #define SK_ISR_MAC1 0x00200000 |
| 237 | #define SK_ISR_TIMER 0x00400000 |
| 238 | #define SK_ISR_EXTERNAL_REG 0x00800000 |
| 239 | #define SK_ISR_SW 0x01000000 |
| 240 | #define SK_ISR_I2C_RDY 0x02000000 |
| 241 | #define SK_ISR_TX2_TIMEO 0x04000000 |
| 242 | #define SK_ISR_TX1_TIMEO 0x08000000 |
| 243 | #define SK_ISR_RX2_TIMEO 0x10000000 |
| 244 | #define SK_ISR_RX1_TIMEO 0x20000000 |
| 245 | #define SK_ISR_RSVD 0x40000000 |
| 246 | #define SK_ISR_HWERR 0x80000000 |
| 247 | |
| 248 | /* SK_IMR register */ |
| 249 | #define SK_IMR_TX2_AS_CHECK 0x00000001 |
| 250 | #define SK_IMR_TX2_AS_EOF 0x00000002 |
| 251 | #define SK_IMR_TX2_AS_EOB 0x00000004 |
| 252 | #define SK_IMR_TX2_S_CHECK 0x00000008 |
| 253 | #define SK_IMR_TX2_S_EOF 0x00000010 |
| 254 | #define SK_IMR_TX2_S_EOB 0x00000020 |
| 255 | #define SK_IMR_TX1_AS_CHECK 0x00000040 |
| 256 | #define SK_IMR_TX1_AS_EOF 0x00000080 |
| 257 | #define SK_IMR_TX1_AS_EOB 0x00000100 |
| 258 | #define SK_IMR_TX1_S_CHECK 0x00000200 |
| 259 | #define SK_IMR_TX1_S_EOF 0x00000400 |
| 260 | #define SK_IMR_TX1_S_EOB 0x00000800 |
| 261 | #define SK_IMR_RX2_CHECK 0x00001000 |
| 262 | #define SK_IMR_RX2_EOF 0x00002000 |
| 263 | #define SK_IMR_RX2_EOB 0x00004000 |
| 264 | #define SK_IMR_RX1_CHECK 0x00008000 |
| 265 | #define SK_IMR_RX1_EOF 0x00010000 |
| 266 | #define SK_IMR_RX1_EOB 0x00020000 |
| 267 | #define SK_IMR_LINK2_OFLOW 0x00040000 |
| 268 | #define SK_IMR_MAC2 0x00080000 |
| 269 | #define SK_IMR_LINK1_OFLOW 0x00100000 |
| 270 | #define SK_IMR_MAC1 0x00200000 |
| 271 | #define SK_IMR_TIMER 0x00400000 |
| 272 | #define SK_IMR_EXTERNAL_REG 0x00800000 |
| 273 | #define SK_IMR_SW 0x01000000 |
| 274 | #define SK_IMR_I2C_RDY 0x02000000 |
| 275 | #define SK_IMR_TX2_TIMEO 0x04000000 |
| 276 | #define SK_IMR_TX1_TIMEO 0x08000000 |
| 277 | #define SK_IMR_RX2_TIMEO 0x10000000 |
| 278 | #define SK_IMR_RX1_TIMEO 0x20000000 |
| 279 | #define SK_IMR_RSVD 0x40000000 |
| 280 | #define SK_IMR_HWERR 0x80000000 |
| 281 | |
| 282 | #define SK_INTRS1 \ |
| 283 | (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) |
| 284 | |
| 285 | #define SK_INTRS2 \ |
| 286 | (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) |
| 287 | |
| 288 | #define SK_Y2_IMR_TX1_AS_CHECK 0x00000001 |
| 289 | #define SK_Y2_IMR_TX1_S_CHECK 0x00000002 |
| 290 | #define SK_Y2_IMR_RX1_CHECK 0x00000004 |
| 291 | #define SK_Y2_IMR_MAC1 0x00000008 |
| 292 | #define SK_Y2_IMR_PHY1 0x00000010 |
| 293 | #define SK_Y2_IMR_TX2_AS_CHECK 0x00000100 |
| 294 | #define SK_Y2_IMR_TX2_S_CHECK 0x00000200 |
| 295 | #define SK_Y2_IMR_RX2_CHECK 0x00000400 |
| 296 | #define SK_Y2_IMR_MAC2 0x00000800 |
| 297 | #define SK_Y2_IMR_PHY2 0x00001000 |
| 298 | #define SK_Y2_IMR_TIMER 0x01000000 |
| 299 | #define SK_Y2_IMR_SW 0x02000000 |
| 300 | #define SK_Y2_IMR_ASF 0x20000000 |
| 301 | #define SK_Y2_IMR_BMU 0x40000000 |
| 302 | #define SK_Y2_IMR_HWERR 0x80000000 |
| 303 | |
| 304 | #define SK_Y2_INTRS1 \ |
| 305 | (SK_Y2_IMR_RX1_CHECK|SK_Y2_IMR_TX1_AS_CHECK \ |
| 306 | |SK_Y2_IMR_MAC1|SK_Y2_IMR_PHY1) |
| 307 | |
| 308 | #define SK_Y2_INTRS2 \ |
| 309 | (SK_Y2_IMR_RX2_CHECK|SK_Y2_IMR_TX2_AS_CHECK \ |
| 310 | |SK_Y2_IMR_MAC2|SK_Y2_IMR_PHY2) |
| 311 | |
| 312 | /* SK_IESR register */ |
| 313 | #define SK_IESR_PAR_RX2 0x00000001 |
| 314 | #define SK_IESR_PAR_RX1 0x00000002 |
| 315 | #define SK_IESR_PAR_MAC2 0x00000004 |
| 316 | #define SK_IESR_PAR_MAC1 0x00000008 |
| 317 | #define SK_IESR_PAR_WR_RAM 0x00000010 |
| 318 | #define SK_IESR_PAR_RD_RAM 0x00000020 |
| 319 | #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 |
| 320 | #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 |
| 321 | #define SK_IESR_NO_STS_MAC2 0x00000100 |
| 322 | #define SK_IESR_NO_STS_MAC1 0x00000200 |
| 323 | #define SK_IESR_IRQ_STS 0x00000400 |
| 324 | #define SK_IESR_MASTERERR 0x00000800 |
| 325 | |
| 326 | /* SK_IEMR register */ |
| 327 | #define SK_IEMR_PAR_RX2 0x00000001 |
| 328 | #define SK_IEMR_PAR_RX1 0x00000002 |
| 329 | #define SK_IEMR_PAR_MAC2 0x00000004 |
| 330 | #define SK_IEMR_PAR_MAC1 0x00000008 |
| 331 | #define SK_IEMR_PAR_WR_RAM 0x00000010 |
| 332 | #define SK_IEMR_PAR_RD_RAM 0x00000020 |
| 333 | #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 |
| 334 | #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 |
| 335 | #define SK_IEMR_NO_STS_MAC2 0x00000100 |
| 336 | #define SK_IEMR_NO_STS_MAC1 0x00000200 |
| 337 | #define SK_IEMR_IRQ_STS 0x00000400 |
| 338 | #define SK_IEMR_MASTERERR 0x00000800 |
| 339 | |
| 340 | /* Block 2 */ |
| 341 | #define SK_MAC0_0 0x0100 |
| 342 | #define SK_MAC0_1 0x0104 |
| 343 | #define SK_MAC1_0 0x0108 |
| 344 | #define SK_MAC1_1 0x010C |
| 345 | #define SK_MAC2_0 0x0110 |
| 346 | #define SK_MAC2_1 0x0114 |
| 347 | #define SK_CONNTYPE 0x0118 |
| 348 | #define SK_PMDTYPE 0x0119 |
| 349 | #define SK_CONFIG 0x011A |
| 350 | #define SK_CHIPVER 0x011B |
| 351 | #define SK_EPROM0 0x011C |
| 352 | #define SK_EPROM1 0x011D /* yukon/genesis */ |
| 353 | #define SK_Y2_CLKGATE 0x011D /* yukon 2 */ |
| 354 | #define SK_EPROM2 0x011E /* yukon/genesis */ |
| 355 | #define SK_Y2_HWRES 0x011E /* yukon 2 */ |
| 356 | #define SK_EPROM3 0x011F |
| 357 | #define SK_EP_ADDR 0x0120 |
| 358 | #define SK_EP_DATA 0x0124 |
| 359 | #define SK_EP_LOADCTL 0x0128 |
| 360 | #define SK_EP_LOADTST 0x0129 |
| 361 | #define SK_TIMERINIT 0x0130 |
| 362 | #define SK_TIMER 0x0134 |
| 363 | #define SK_TIMERCTL 0x0138 |
| 364 | #define SK_TIMERTST 0x0139 |
| 365 | #define SK_IMTIMERINIT 0x0140 |
| 366 | #define SK_IMTIMER 0x0144 |
| 367 | #define SK_IMTIMERCTL 0x0148 |
| 368 | #define SK_IMTIMERTST 0x0149 |
| 369 | #define SK_IMMR 0x014C |
| 370 | #define SK_IHWEMR 0x0150 |
| 371 | #define SK_TESTCTL1 0x0158 |
| 372 | #define SK_TESTCTL2 0x0159 |
| 373 | #define SK_GPIO 0x015C |
| 374 | #define SK_I2CHWCTL 0x0160 |
| 375 | #define SK_I2CHWDATA 0x0164 |
| 376 | #define SK_I2CHWIRQ 0x0168 |
| 377 | #define SK_I2CSW 0x016C |
| 378 | #define SK_BLNKINIT 0x0170 |
| 379 | #define SK_BLNKCOUNT 0x0174 |
| 380 | #define SK_BLNKCTL 0x0178 |
| 381 | #define SK_BLNKSTS 0x0179 |
| 382 | #define SK_BLNKTST 0x017A |
| 383 | |
| 384 | /* Values for SK_CHIPVER */ |
| 385 | #define SK_GENESIS 0x0A |
| 386 | #define SK_YUKON 0xB0 |
| 387 | #define SK_YUKON_LITE 0xB1 |
| 388 | #define SK_YUKON_LP 0xB2 |
| 389 | #define SK_YUKON_XL 0xB3 |
| 390 | #define SK_YUKON_EC_U 0xB4 |
| 391 | #define SK_YUKON_EC 0xB6 |
| 392 | #define SK_YUKON_FE 0xB7 |
| 393 | #define SK_YUKON_FE_P 0xB8 |
| 394 | #define SK_YUKON_FAMILY(x) ((x) & 0xB0) |
| 395 | |
| 396 | #define SK_IS_GENESIS(sc) \ |
| 397 | ((sc)->sk_type == SK_GENESIS) |
| 398 | #define SK_IS_YUKON(sc) \ |
| 399 | ((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP) |
| 400 | #define SK_IS_YUKON2(sc) \ |
| 401 | ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE_P) |
| 402 | |
| 403 | /* Known revisions in SK_CONFIG */ |
| 404 | #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach */ |
| 405 | #define SK_YUKON_LITE_REV_A1 0x3 |
| 406 | #define SK_YUKON_LITE_REV_A3 0x7 |
| 407 | |
| 408 | #define SK_YUKON_XL_REV_A0 0x0 |
| 409 | #define SK_YUKON_XL_REV_A1 0x1 |
| 410 | #define SK_YUKON_XL_REV_A2 0x2 |
| 411 | #define SK_YUKON_XL_REV_A3 0x3 |
| 412 | |
| 413 | #define SK_YUKON_EC_REV_A1 0x0 |
| 414 | #define SK_YUKON_EC_REV_A2 0x1 |
| 415 | #define SK_YUKON_EC_REV_A3 0x2 |
| 416 | |
| 417 | #define SK_YUKON_EC_U_REV_A0 0x1 |
| 418 | #define SK_YUKON_EC_U_REV_A1 0x2 |
| 419 | #define SK_YUKON_EC_U_REV_B0 0x3 |
| 420 | |
| 421 | #define SK_YUKON_FE_REV_A1 0x1 |
| 422 | #define SK_YUKON_FE_REV_A2 0x3 |
| 423 | |
| 424 | /* Workaround */ |
| 425 | #define SK_WA_43_418 0x01 |
| 426 | #define SK_WA_4109 0x02 |
| 427 | |
| 428 | #define SK_IMCTL_IRQ_CLEAR 0x01 |
| 429 | #define SK_IMCTL_STOP 0x02 |
| 430 | #define SK_IMCTL_START 0x04 |
| 431 | |
| 432 | /* Number of ticks per usec for interrupt moderation */ |
| 433 | #define SK_IMTIMER_TICKS_GENESIS 53 |
| 434 | #define SK_IMTIMER_TICKS_YUKON 156 |
| 435 | #define SK_IMTIMER_TICKS_YUKON_EC 125 |
| 436 | #define SK_IMTIMER_TICKS_YUKON_FE 100 |
| 437 | #define SK_IMTIMER_TICKS_YUKON_XL 156 |
| 438 | #define SK_IM_USECS(x) ((x) * imtimer_ticks) |
| 439 | |
| 440 | #define SK_IM_MIN 0 |
| 441 | #define SK_IM_DEFAULT 1000 |
| 442 | #define SK_IM_MAX 10000 |
| 443 | /* |
| 444 | * The SK_EPROM0 register contains a byte that describes the |
| 445 | * amount of SRAM mounted on the NIC. The value also tells if |
| 446 | * the chips are 64K or 128K. This affects the RAMbuffer address |
| 447 | * offset that we need to use. |
| 448 | */ |
| 449 | #define SK_RAMSIZE_512K_64 0x1 |
| 450 | #define SK_RAMSIZE_1024K_128 0x2 |
| 451 | #define SK_RAMSIZE_1024K_64 0x3 |
| 452 | #define SK_RAMSIZE_2048K_128 0x4 |
| 453 | |
| 454 | #define SK_RBOFF_0 0x0 |
| 455 | #define SK_RBOFF_80000 0x80000 |
| 456 | |
| 457 | /* |
| 458 | * SK_EEPROM1 contains the PHY type, which may be XMAC for |
| 459 | * fiber-based cards or BCOM for 1000baseT cards with a Broadcom |
| 460 | * PHY. |
| 461 | */ |
| 462 | #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ |
| 463 | #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ |
| 464 | #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ |
| 465 | #define SK_PHYTYPE_NAT 3 /* National DP83891 */ |
| 466 | #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ |
| 467 | #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ |
| 468 | |
| 469 | /* |
| 470 | * PHY addresses. |
| 471 | */ |
| 472 | #define SK_PHYADDR_XMAC 0x0 |
| 473 | #define SK_PHYADDR_BCOM 0x1 |
| 474 | #define SK_PHYADDR_LONE 0x3 |
| 475 | #define SK_PHYADDR_NAT 0x0 |
| 476 | #define SK_PHYADDR_MARV 0x0 |
| 477 | |
| 478 | #define SK_CONFIG_SINGLEMAC 0x01 |
| 479 | #define SK_CONFIG_DIS_DSL_CLK 0x02 |
| 480 | |
| 481 | #define SK_PMD_1000BASETX_ALT 0x31 |
| 482 | #define SK_PMD_1000BASECX 0x43 |
| 483 | #define SK_PMD_1000BASELX 0x4C |
| 484 | #define SK_PMD_1000BASESX 0x53 |
| 485 | #define SK_PMD_1000BASETX 0x54 |
| 486 | |
| 487 | /* GPIO bits */ |
| 488 | #define SK_GPIO_DAT0 0x00000001 |
| 489 | #define SK_GPIO_DAT1 0x00000002 |
| 490 | #define SK_GPIO_DAT2 0x00000004 |
| 491 | #define SK_GPIO_DAT3 0x00000008 |
| 492 | #define SK_GPIO_DAT4 0x00000010 |
| 493 | #define SK_GPIO_DAT5 0x00000020 |
| 494 | #define SK_GPIO_DAT6 0x00000040 |
| 495 | #define SK_GPIO_DAT7 0x00000080 |
| 496 | #define SK_GPIO_DAT8 0x00000100 |
| 497 | #define SK_GPIO_DAT9 0x00000200 |
| 498 | #define SK_GPIO_DIR0 0x00010000 |
| 499 | #define SK_GPIO_DIR1 0x00020000 |
| 500 | #define SK_GPIO_DIR2 0x00040000 |
| 501 | #define SK_GPIO_DIR3 0x00080000 |
| 502 | #define SK_GPIO_DIR4 0x00100000 |
| 503 | #define SK_GPIO_DIR5 0x00200000 |
| 504 | #define SK_GPIO_DIR6 0x00400000 |
| 505 | #define SK_GPIO_DIR7 0x00800000 |
| 506 | #define SK_GPIO_DIR8 0x01000000 |
| 507 | #define SK_GPIO_DIR9 0x02000000 |
| 508 | |
| 509 | #define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */ |
| 510 | #define SK_Y2_CLKGATE_LINK2_GATE_DIS 0x40 /* disable clock gate, 2 */ |
| 511 | #define SK_Y2_CLKGATE_LINK2_CORE_DIS 0x20 /* disable core clock, 2 */ |
| 512 | #define SK_Y2_CLKGATE_LINK2_PCI_DIS 0x10 /* disable pci clock, 2 */ |
| 513 | #define SK_Y2_CLKGATE_LINK1_INACTIVE 0x08 /* port 1 inactive */ |
| 514 | #define SK_Y2_CLKGATE_LINK1_GATE_DIS 0x04 /* disable clock gate, 1 */ |
| 515 | #define SK_Y2_CLKGATE_LINK1_CORE_DIS 0x02 /* disable core clock, 1 */ |
| 516 | #define SK_Y2_CLKGATE_LINK1_PCI_DIS 0x01 /* disable pci clock, 1 */ |
| 517 | |
| 518 | #define SK_Y2_HWRES_LINK_1 0x01 |
| 519 | #define SK_Y2_HWRES_LINK_2 0x02 |
| 520 | #define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) |
| 521 | #define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) |
| 522 | |
| 523 | /* Block 3 Ram interface and MAC arbiter registers */ |
| 524 | #define SK_RAMADDR 0x0180 |
| 525 | #define SK_RAMDATA0 0x0184 |
| 526 | #define SK_RAMDATA1 0x0188 |
| 527 | #define SK_TO0 0x0190 |
| 528 | #define SK_TO1 0x0191 |
| 529 | #define SK_TO2 0x0192 |
| 530 | #define SK_TO3 0x0193 |
| 531 | #define SK_TO4 0x0194 |
| 532 | #define SK_TO5 0x0195 |
| 533 | #define SK_TO6 0x0196 |
| 534 | #define SK_TO7 0x0197 |
| 535 | #define SK_TO8 0x0198 |
| 536 | #define SK_TO9 0x0199 |
| 537 | #define SK_TO10 0x019A |
| 538 | #define SK_TO11 0x019B |
| 539 | #define SK_RITIMEO_TMR 0x019C |
| 540 | #define SK_RAMCTL 0x01A0 |
| 541 | #define SK_RITIMER_TST 0x01A2 |
| 542 | |
| 543 | #define SK_RAMCTL_RESET 0x0001 |
| 544 | #define SK_RAMCTL_UNRESET 0x0002 |
| 545 | #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 |
| 546 | #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 |
| 547 | |
| 548 | /* Mac arbiter registers */ |
| 549 | #define SK_MINIT_RX1 0x01B0 |
| 550 | #define SK_MINIT_RX2 0x01B1 |
| 551 | #define SK_MINIT_TX1 0x01B2 |
| 552 | #define SK_MINIT_TX2 0x01B3 |
| 553 | #define SK_MTIMEO_RX1 0x01B4 |
| 554 | #define SK_MTIMEO_RX2 0x01B5 |
| 555 | #define SK_MTIMEO_TX1 0x01B6 |
| 556 | #define SK_MTIEMO_TX2 0x01B7 |
| 557 | #define SK_MACARB_CTL 0x01B8 |
| 558 | #define SK_MTIMER_TST 0x01BA |
| 559 | #define SK_RCINIT_RX1 0x01C0 |
| 560 | #define SK_RCINIT_RX2 0x01C1 |
| 561 | #define SK_RCINIT_TX1 0x01C2 |
| 562 | #define SK_RCINIT_TX2 0x01C3 |
| 563 | #define SK_RCTIMEO_RX1 0x01C4 |
| 564 | #define SK_RCTIMEO_RX2 0x01C5 |
| 565 | #define SK_RCTIMEO_TX1 0x01C6 |
| 566 | #define SK_RCTIMEO_TX2 0x01C7 |
| 567 | #define SK_RECOVERY_CTL 0x01C8 |
| 568 | #define SK_RCTIMER_TST 0x01CA |
| 569 | |
| 570 | /* Packet arbiter registers */ |
| 571 | #define SK_RXPA1_TINIT 0x01D0 |
| 572 | #define SK_RXPA2_TINIT 0x01D4 |
| 573 | #define SK_TXPA1_TINIT 0x01D8 |
| 574 | #define SK_TXPA2_TINIT 0x01DC |
| 575 | #define SK_RXPA1_TIMEO 0x01E0 |
| 576 | #define SK_RXPA2_TIMEO 0x01E4 |
| 577 | #define SK_TXPA1_TIMEO 0x01E8 |
| 578 | #define SK_TXPA2_TIMEO 0x01EC |
| 579 | #define SK_PKTARB_CTL 0x01F0 |
| 580 | #define SK_PKTATB_TST 0x01F2 |
| 581 | |
| 582 | #define SK_PKTARB_TIMEOUT 0x2000 |
| 583 | |
| 584 | #define SK_PKTARBCTL_RESET 0x0001 |
| 585 | #define SK_PKTARBCTL_UNRESET 0x0002 |
| 586 | #define SK_PKTARBCTL_RXTO1_OFF 0x0004 |
| 587 | #define SK_PKTARBCTL_RXTO1_ON 0x0008 |
| 588 | #define SK_PKTARBCTL_RXTO2_OFF 0x0010 |
| 589 | #define SK_PKTARBCTL_RXTO2_ON 0x0020 |
| 590 | #define SK_PKTARBCTL_TXTO1_OFF 0x0040 |
| 591 | #define SK_PKTARBCTL_TXTO1_ON 0x0080 |
| 592 | #define SK_PKTARBCTL_TXTO2_OFF 0x0100 |
| 593 | #define SK_PKTARBCTL_TXTO2_ON 0x0200 |
| 594 | #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 |
| 595 | #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 |
| 596 | #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 |
| 597 | #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 |
| 598 | |
| 599 | #define SK_MINIT_XMAC_B2 54 |
| 600 | #define SK_MINIT_XMAC_C1 63 |
| 601 | |
| 602 | #define SK_MACARBCTL_RESET 0x0001 |
| 603 | #define SK_MACARBCTL_UNRESET 0x0002 |
| 604 | #define SK_MACARBCTL_FASTOE_OFF 0x0004 |
| 605 | #define SK_MACARBCRL_FASTOE_ON 0x0008 |
| 606 | |
| 607 | #define SK_RCINIT_XMAC_B2 54 |
| 608 | #define SK_RCINIT_XMAC_C1 0 |
| 609 | |
| 610 | #define SK_RECOVERYCTL_RX1_OFF 0x0001 |
| 611 | #define SK_RECOVERYCTL_RX1_ON 0x0002 |
| 612 | #define SK_RECOVERYCTL_RX2_OFF 0x0004 |
| 613 | #define SK_RECOVERYCTL_RX2_ON 0x0008 |
| 614 | #define SK_RECOVERYCTL_TX1_OFF 0x0010 |
| 615 | #define SK_RECOVERYCTL_TX1_ON 0x0020 |
| 616 | #define SK_RECOVERYCTL_TX2_OFF 0x0040 |
| 617 | #define SK_RECOVERYCTL_TX2_ON 0x0080 |
| 618 | |
| 619 | #define SK_RECOVERY_XMAC_B2 \ |
| 620 | (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ |
| 621 | SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) |
| 622 | |
| 623 | #define SK_RECOVERY_XMAC_C1 \ |
| 624 | (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ |
| 625 | SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) |
| 626 | |
| 627 | /* Block 4 -- TX Arbiter MAC 1 */ |
| 628 | #define SK_TXAR1_TIMERINIT 0x0200 |
| 629 | #define SK_TXAR1_TIMERVAL 0x0204 |
| 630 | #define SK_TXAR1_LIMITINIT 0x0208 |
| 631 | #define SK_TXAR1_LIMITCNT 0x020C |
| 632 | #define SK_TXAR1_COUNTERCTL 0x0210 |
| 633 | #define SK_TXAR1_COUNTERTST 0x0212 |
| 634 | #define SK_TXAR1_COUNTERSTS 0x0212 |
| 635 | |
| 636 | /* Block 5 -- TX Arbiter MAC 2 */ |
| 637 | #define SK_TXAR2_TIMERINIT 0x0280 |
| 638 | #define SK_TXAR2_TIMERVAL 0x0284 |
| 639 | #define SK_TXAR2_LIMITINIT 0x0288 |
| 640 | #define SK_TXAR2_LIMITCNT 0x028C |
| 641 | #define SK_TXAR2_COUNTERCTL 0x0290 |
| 642 | #define SK_TXAR2_COUNTERTST 0x0291 |
| 643 | #define SK_TXAR2_COUNTERSTS 0x0292 |
| 644 | |
| 645 | #define SK_TXARCTL_OFF 0x01 |
| 646 | #define SK_TXARCTL_ON 0x02 |
| 647 | #define SK_TXARCTL_RATECTL_OFF 0x04 |
| 648 | #define SK_TXARCTL_RATECTL_ON 0x08 |
| 649 | #define SK_TXARCTL_ALLOC_OFF 0x10 |
| 650 | #define SK_TXARCTL_ALLOC_ON 0x20 |
| 651 | #define SK_TXARCTL_FSYNC_OFF 0x40 |
| 652 | #define SK_TXARCTL_FSYNC_ON 0x80 |
| 653 | |
| 654 | /* Block 6 -- External registers */ |
| 655 | #define SK_EXTREG_BASE 0x300 |
| 656 | #define SK_EXTREG_END 0x37C |
| 657 | |
| 658 | /* Block 7 -- PCI config registers */ |
| 659 | #define SK_PCI_BASE 0x0380 |
| 660 | #define SK_PCI_END 0x03FC |
| 661 | |
| 662 | /* Compute offset of mirrored PCI register */ |
| 663 | #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) |
| 664 | |
| 665 | /* Block 8 -- RX queue 1 */ |
| 666 | #define SK_RXQ1_BUFCNT 0x0400 |
| 667 | #define SK_RXQ1_BUFCTL 0x0402 |
| 668 | #define SK_RXQ1_NEXTDESC 0x0404 |
| 669 | #define SK_RXQ1_RXBUF_LO 0x0408 |
| 670 | #define SK_RXQ1_RXBUF_HI 0x040C |
| 671 | #define SK_RXQ1_RXSTAT 0x0410 |
| 672 | #define SK_RXQ1_TIMESTAMP 0x0414 |
| 673 | #define SK_RXQ1_CSUM1 0x0418 |
| 674 | #define SK_RXQ1_CSUM2 0x041A |
| 675 | #define SK_RXQ1_CSUM1_START 0x041C |
| 676 | #define SK_RXQ1_CSUM2_START 0x041E |
| 677 | #define SK_RXQ1_CURADDR_LO 0x0420 |
| 678 | #define SK_RXQ1_CURADDR_HI 0x0424 |
| 679 | #define SK_RXQ1_CURCNT_LO 0x0428 |
| 680 | #define SK_RXQ1_CURCNT_HI 0x042C |
| 681 | #define SK_RXQ1_CURBYTES 0x0430 |
| 682 | #define SK_RXQ1_BMU_CSR 0x0434 |
| 683 | #define SK_RXQ1_WATERMARK 0x0438 |
| 684 | #define SK_RXQ1_FLAG 0x043A |
| 685 | #define SK_RXQ1_TEST1 0x043C |
| 686 | #define SK_RXQ1_TEST2 0x0440 |
| 687 | #define SK_RXQ1_TEST3 0x0444 |
| 688 | /* yukon-2 only */ |
| 689 | #define SK_RXQ1_Y2_WM 0x0440 |
| 690 | #define SK_RXQ1_Y2_AL 0x0442 |
| 691 | #define SK_RXQ1_Y2_RSP 0x0444 |
| 692 | #define SK_RXQ1_Y2_RSL 0x0446 |
| 693 | #define SK_RXQ1_Y2_RP 0x0448 |
| 694 | #define SK_RXQ1_Y2_RL 0x044A |
| 695 | #define SK_RXQ1_Y2_WP 0x044C |
| 696 | #define SK_RXQ1_Y2_WSP 0x044D |
| 697 | #define SK_RXQ1_Y2_WL 0x044E |
| 698 | #define SK_RXQ1_Y2_WSL 0x044F |
| 699 | /* yukon-2 only (prefetch unit) */ |
| 700 | #define SK_RXQ1_Y2_PREF_CSR 0x0450 |
| 701 | #define SK_RXQ1_Y2_PREF_LIDX 0x0454 |
| 702 | #define SK_RXQ1_Y2_PREF_ADDRLO 0x0458 |
| 703 | #define SK_RXQ1_Y2_PREF_ADDRHI 0x045C |
| 704 | #define SK_RXQ1_Y2_PREF_GETIDX 0x0460 |
| 705 | #define SK_RXQ1_Y2_PREF_PUTIDX 0x0464 |
| 706 | #define SK_RXQ1_Y2_PREF_FIFOWP 0x0470 |
| 707 | #define SK_RXQ1_Y2_PREF_FIFORP 0x0474 |
| 708 | #define SK_RXQ1_Y2_PREF_FIFOWM 0x0478 |
| 709 | #define SK_RXQ1_Y2_PREF_FIFOLV 0x047C |
| 710 | |
| 711 | /* Block 9 -- RX queue 2 */ |
| 712 | #define SK_RXQ2_BUFCNT 0x0480 |
| 713 | #define SK_RXQ2_BUFCTL 0x0482 |
| 714 | #define SK_RXQ2_NEXTDESC 0x0484 |
| 715 | #define SK_RXQ2_RXBUF_LO 0x0488 |
| 716 | #define SK_RXQ2_RXBUF_HI 0x048C |
| 717 | #define SK_RXQ2_RXSTAT 0x0490 |
| 718 | #define SK_RXQ2_TIMESTAMP 0x0494 |
| 719 | #define SK_RXQ2_CSUM1 0x0498 |
| 720 | #define SK_RXQ2_CSUM2 0x049A |
| 721 | #define SK_RXQ2_CSUM1_START 0x049C |
| 722 | #define SK_RXQ2_CSUM2_START 0x049E |
| 723 | #define SK_RXQ2_CURADDR_LO 0x04A0 |
| 724 | #define SK_RXQ2_CURADDR_HI 0x04A4 |
| 725 | #define SK_RXQ2_CURCNT_LO 0x04A8 |
| 726 | #define SK_RXQ2_CURCNT_HI 0x04AC |
| 727 | #define SK_RXQ2_CURBYTES 0x04B0 |
| 728 | #define SK_RXQ2_BMU_CSR 0x04B4 |
| 729 | #define SK_RXQ2_WATERMARK 0x04B8 |
| 730 | #define SK_RXQ2_FLAG 0x04BA |
| 731 | #define SK_RXQ2_TEST1 0x04BC |
| 732 | #define SK_RXQ2_TEST2 0x04C0 |
| 733 | #define SK_RXQ2_TEST3 0x04C4 |
| 734 | /* yukon-2 only */ |
| 735 | #define SK_RXQ2_Y2_WM 0x04C0 |
| 736 | #define SK_RXQ2_Y2_AL 0x04C2 |
| 737 | #define SK_RXQ2_Y2_RSP 0x04C4 |
| 738 | #define SK_RXQ2_Y2_RSL 0x04C6 |
| 739 | #define SK_RXQ2_Y2_RP 0x04C8 |
| 740 | #define SK_RXQ2_Y2_RL 0x04CA |
| 741 | #define SK_RXQ2_Y2_WP 0x04CC |
| 742 | #define SK_RXQ2_Y2_WSP 0x04CD |
| 743 | #define SK_RXQ2_Y2_WL 0x04CE |
| 744 | #define SK_RXQ2_Y2_WSL 0x04CF |
| 745 | /* yukon-2 only (prefetch unit) */ |
| 746 | #define SK_RXQ2_Y2_PREF_CSR 0x04D0 |
| 747 | #define SK_RXQ2_Y2_PREF_LIDX 0x04D4 |
| 748 | #define SK_RXQ2_Y2_PREF_ADDRLO 0x04D8 |
| 749 | #define SK_RXQ2_Y2_PREF_ADDRHI 0x04DC |
| 750 | #define SK_RXQ2_Y2_PREF_GETIDX 0x04E0 |
| 751 | #define SK_RXQ2_Y2_PREF_PUTIDX 0x04E4 |
| 752 | #define SK_RXQ2_Y2_PREF_FIFOWP 0x04F0 |
| 753 | #define SK_RXQ2_Y2_PREF_FIFORP 0x04F4 |
| 754 | #define SK_RXQ2_Y2_PREF_FIFOWM 0x04F8 |
| 755 | #define SK_RXQ2_Y2_PREF_FIFOLV 0x04FC |
| 756 | |
| 757 | #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 |
| 758 | #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 |
| 759 | #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 |
| 760 | #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 |
| 761 | #define SK_RXBMU_RX_START 0x00000010 |
| 762 | #define SK_RXBMU_RX_STOP 0x00000020 |
| 763 | #define SK_RXBMU_POLL_OFF 0x00000040 |
| 764 | #define SK_RXBMU_POLL_ON 0x00000080 |
| 765 | #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 |
| 766 | #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 |
| 767 | #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 |
| 768 | #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 |
| 769 | #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 |
| 770 | #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 |
| 771 | #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 |
| 772 | #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 |
| 773 | #define SK_RXBMU_PFI_SM_RESET 0x00010000 |
| 774 | #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 |
| 775 | #define SK_RXBMU_FIFO_RESET 0x00040000 |
| 776 | #define SK_RXBMU_FIFO_UNRESET 0x00080000 |
| 777 | #define SK_RXBMU_DESC_RESET 0x00100000 |
| 778 | #define SK_RXBMU_DESC_UNRESET 0x00200000 |
| 779 | #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 |
| 780 | |
| 781 | #define SK_RXBMU_ONLINE \ |
| 782 | (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ |
| 783 | SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ |
| 784 | SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ |
| 785 | SK_RXBMU_DESC_UNRESET) |
| 786 | |
| 787 | #define SK_RXBMU_OFFLINE \ |
| 788 | (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ |
| 789 | SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ |
| 790 | SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ |
| 791 | SK_RXBMU_DESC_RESET) |
| 792 | |
| 793 | /* Block 12 -- TX sync queue 1 */ |
| 794 | #define SK_TXQS1_BUFCNT 0x0600 |
| 795 | #define SK_TXQS1_BUFCTL 0x0602 |
| 796 | #define SK_TXQS1_NEXTDESC 0x0604 |
| 797 | #define SK_TXQS1_RXBUF_LO 0x0608 |
| 798 | #define SK_TXQS1_RXBUF_HI 0x060C |
| 799 | #define SK_TXQS1_RXSTAT 0x0610 |
| 800 | #define SK_TXQS1_CSUM_STARTVAL 0x0614 |
| 801 | #define SK_TXQS1_CSUM_STARTPOS 0x0618 |
| 802 | #define SK_TXQS1_CSUM_WRITEPOS 0x061A |
| 803 | #define SK_TXQS1_CURADDR_LO 0x0620 |
| 804 | #define SK_TXQS1_CURADDR_HI 0x0624 |
| 805 | #define SK_TXQS1_CURCNT_LO 0x0628 |
| 806 | #define SK_TXQS1_CURCNT_HI 0x062C |
| 807 | #define SK_TXQS1_CURBYTES 0x0630 |
| 808 | #define SK_TXQS1_BMU_CSR 0x0634 |
| 809 | #define SK_TXQS1_WATERMARK 0x0638 |
| 810 | #define SK_TXQS1_FLAG 0x063A |
| 811 | #define SK_TXQS1_TEST1 0x063C |
| 812 | #define SK_TXQS1_TEST2 0x0640 |
| 813 | #define SK_TXQS1_TEST3 0x0644 |
| 814 | /* yukon-2 only (prefetch unit) */ |
| 815 | #define SK_TXQS1_Y2_PREF_CSR 0x0650 |
| 816 | #define SK_TXQS1_Y2_PREF_LIDX 0x0654 |
| 817 | #define SK_TXQS1_Y2_PREF_ADDRLO 0x0658 |
| 818 | #define SK_TXQS1_Y2_PREF_ADDRHI 0x065C |
| 819 | #define SK_TXQS1_Y2_PREF_GETIDX 0x0660 |
| 820 | #define SK_TXQS1_Y2_PREF_PUTIDX 0x0664 |
| 821 | #define SK_TXQS1_Y2_PREF_FIFOWP 0x0670 |
| 822 | #define SK_TXQS1_Y2_PREF_FIFORP 0x0674 |
| 823 | #define SK_TXQS1_Y2_PREF_FIFOWM 0x0678 |
| 824 | #define SK_TXQS1_Y2_PREF_FIFOLV 0x067C |
| 825 | |
| 826 | /* Block 13 -- TX async queue 1 */ |
| 827 | #define SK_TXQA1_BUFCNT 0x0680 |
| 828 | #define SK_TXQA1_BUFCTL 0x0682 |
| 829 | #define SK_TXQA1_NEXTDESC 0x0684 |
| 830 | #define SK_TXQA1_RXBUF_LO 0x0688 |
| 831 | #define SK_TXQA1_RXBUF_HI 0x068C |
| 832 | #define SK_TXQA1_RXSTAT 0x0690 |
| 833 | #define SK_TXQA1_CSUM_STARTVAL 0x0694 |
| 834 | #define SK_TXQA1_CSUM_STARTPOS 0x0698 |
| 835 | #define SK_TXQA1_CSUM_WRITEPOS 0x069A |
| 836 | #define SK_TXQA1_CURADDR_LO 0x06A0 |
| 837 | #define SK_TXQA1_CURADDR_HI 0x06A4 |
| 838 | #define SK_TXQA1_CURCNT_LO 0x06A8 |
| 839 | #define SK_TXQA1_CURCNT_HI 0x06AC |
| 840 | #define SK_TXQA1_CURBYTES 0x06B0 |
| 841 | #define SK_TXQA1_BMU_CSR 0x06B4 |
| 842 | #define SK_TXQA1_WATERMARK 0x06B8 |
| 843 | #define SK_TXQA1_FLAG 0x06BA |
| 844 | #define SK_TXQA1_TEST1 0x06BC |
| 845 | #define SK_TXQA1_TEST2 0x06C0 |
| 846 | #define SK_TXQA1_TEST3 0x06C4 |
| 847 | /* yukon-2 only */ |
| 848 | #define SK_TXQA1_Y2_WM 0x06C0 |
| 849 | #define SK_TXQA1_Y2_AL 0x06C2 |
| 850 | #define SK_TXQA1_Y2_RSP 0x06C4 |
| 851 | #define SK_TXQA1_Y2_RSL 0x06C6 |
| 852 | #define SK_TXQA1_Y2_RP 0x06C8 |
| 853 | #define SK_TXQA1_Y2_RL 0x06CA |
| 854 | #define SK_TXQA1_Y2_WP 0x06CC |
| 855 | #define SK_TXQA1_Y2_WSP 0x06CD |
| 856 | #define SK_TXQA1_Y2_WL 0x06CE |
| 857 | #define SK_TXQA1_Y2_WSL 0x06CF |
| 858 | /* yukon-2 only (prefetch unit) */ |
| 859 | #define SK_TXQA1_Y2_PREF_CSR 0x06D0 |
| 860 | #define SK_TXQA1_Y2_PREF_LIDX 0x06D4 |
| 861 | #define SK_TXQA1_Y2_PREF_ADDRLO 0x06D8 |
| 862 | #define SK_TXQA1_Y2_PREF_ADDRHI 0x06DC |
| 863 | #define SK_TXQA1_Y2_PREF_GETIDX 0x06E0 |
| 864 | #define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4 |
| 865 | #define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0 |
| 866 | #define SK_TXQA1_Y2_PREF_FIFORP 0x06F4 |
| 867 | #define SK_TXQA1_Y2_PREF_FIFOWM 0x06F8 |
| 868 | #define SK_TXQA1_Y2_PREF_FIFOLV 0x06FC |
| 869 | |
| 870 | /* Block 14 -- TX sync queue 2 */ |
| 871 | #define SK_TXQS2_BUFCNT 0x0700 |
| 872 | #define SK_TXQS2_BUFCTL 0x0702 |
| 873 | #define SK_TXQS2_NEXTDESC 0x0704 |
| 874 | #define SK_TXQS2_RXBUF_LO 0x0708 |
| 875 | #define SK_TXQS2_RXBUF_HI 0x070C |
| 876 | #define SK_TXQS2_RXSTAT 0x0710 |
| 877 | #define SK_TXQS2_CSUM_STARTVAL 0x0714 |
| 878 | #define SK_TXQS2_CSUM_STARTPOS 0x0718 |
| 879 | #define SK_TXQS2_CSUM_WRITEPOS 0x071A |
| 880 | #define SK_TXQS2_CURADDR_LO 0x0720 |
| 881 | #define SK_TXQS2_CURADDR_HI 0x0724 |
| 882 | #define SK_TXQS2_CURCNT_LO 0x0728 |
| 883 | #define SK_TXQS2_CURCNT_HI 0x072C |
| 884 | #define SK_TXQS2_CURBYTES 0x0730 |
| 885 | #define SK_TXQS2_BMU_CSR 0x0734 |
| 886 | #define SK_TXQS2_WATERMARK 0x0738 |
| 887 | #define SK_TXQS2_FLAG 0x073A |
| 888 | #define SK_TXQS2_TEST1 0x073C |
| 889 | #define SK_TXQS2_TEST2 0x0740 |
| 890 | #define SK_TXQS2_TEST3 0x0744 |
| 891 | /* yukon-2 only */ |
| 892 | #define SK_TXQS2_Y2_WM 0x0740 |
| 893 | #define SK_TXQS2_Y2_AL 0x0742 |
| 894 | #define SK_TXQS2_Y2_RSP 0x0744 |
| 895 | #define SK_TXQS2_Y2_RSL 0x0746 |
| 896 | #define SK_TXQS2_Y2_RP 0x0748 |
| 897 | #define SK_TXQS2_Y2_RL 0x074A |
| 898 | #define SK_TXQS2_Y2_WP 0x074C |
| 899 | #define SK_TXQS2_Y2_WSP 0x074D |
| 900 | #define SK_TXQS2_Y2_WL 0x074E |
| 901 | #define SK_TXQS2_Y2_WSL 0x074F |
| 902 | /* yukon-2 only (prefetch unit) */ |
| 903 | #define SK_TXQS2_Y2_PREF_CSR 0x0750 |
| 904 | #define SK_TXQS2_Y2_PREF_LIDX 0x0754 |
| 905 | #define SK_TXQS2_Y2_PREF_ADDRLO 0x0758 |
| 906 | #define SK_TXQS2_Y2_PREF_ADDRHI 0x075C |
| 907 | #define SK_TXQS2_Y2_PREF_GETIDX 0x0760 |
| 908 | #define SK_TXQS2_Y2_PREF_PUTIDX 0x0764 |
| 909 | #define SK_TXQS2_Y2_PREF_FIFOWP 0x0770 |
| 910 | #define SK_TXQS2_Y2_PREF_FIFORP 0x0774 |
| 911 | #define SK_TXQS2_Y2_PREF_FIFOWM 0x0778 |
| 912 | #define SK_TXQS2_Y2_PREF_FIFOLV 0x077C |
| 913 | |
| 914 | /* Block 15 -- TX async queue 2 */ |
| 915 | #define SK_TXQA2_BUFCNT 0x0780 |
| 916 | #define SK_TXQA2_BUFCTL 0x0782 |
| 917 | #define SK_TXQA2_NEXTDESC 0x0784 |
| 918 | #define SK_TXQA2_RXBUF_LO 0x0788 |
| 919 | #define SK_TXQA2_RXBUF_HI 0x078C |
| 920 | #define SK_TXQA2_RXSTAT 0x0790 |
| 921 | #define SK_TXQA2_CSUM_STARTVAL 0x0794 |
| 922 | #define SK_TXQA2_CSUM_STARTPOS 0x0798 |
| 923 | #define SK_TXQA2_CSUM_WRITEPOS 0x079A |
| 924 | #define SK_TXQA2_CURADDR_LO 0x07A0 |
| 925 | #define SK_TXQA2_CURADDR_HI 0x07A4 |
| 926 | #define SK_TXQA2_CURCNT_LO 0x07A8 |
| 927 | #define SK_TXQA2_CURCNT_HI 0x07AC |
| 928 | #define SK_TXQA2_CURBYTES 0x07B0 |
| 929 | #define SK_TXQA2_BMU_CSR 0x07B4 |
| 930 | #define SK_TXQA2_WATERMARK 0x07B8 |
| 931 | #define SK_TXQA2_FLAG 0x07BA |
| 932 | #define SK_TXQA2_TEST1 0x07BC |
| 933 | #define SK_TXQA2_TEST2 0x07C0 |
| 934 | #define SK_TXQA2_TEST3 0x07C4 |
| 935 | /* yukon-2 only */ |
| 936 | #define SK_TXQA2_Y2_WM 0x07C0 |
| 937 | #define SK_TXQA2_Y2_AL 0x07C2 |
| 938 | #define SK_TXQA2_Y2_RSP 0x07C4 |
| 939 | #define SK_TXQA2_Y2_RSL 0x07C6 |
| 940 | #define SK_TXQA2_Y2_RP 0x07C8 |
| 941 | #define SK_TXQA2_Y2_RL 0x07CA |
| 942 | #define SK_TXQA2_Y2_WP 0x07CC |
| 943 | #define SK_TXQA2_Y2_WSP 0x07CD |
| 944 | #define SK_TXQA2_Y2_WL 0x07CE |
| 945 | #define SK_TXQA2_Y2_WSL 0x07CF |
| 946 | /* yukon-2 only (prefetch unit) */ |
| 947 | #define SK_TXQA2_Y2_PREF_CSR 0x07D0 |
| 948 | #define SK_TXQA2_Y2_PREF_LIDX 0x07D4 |
| 949 | #define SK_TXQA2_Y2_PREF_ADDRLO 0x07D8 |
| 950 | #define SK_TXQA2_Y2_PREF_ADDRHI 0x07DC |
| 951 | #define SK_TXQA2_Y2_PREF_GETIDX 0x07E0 |
| 952 | #define SK_TXQA2_Y2_PREF_PUTIDX 0x07E4 |
| 953 | #define SK_TXQA2_Y2_PREF_FIFOWP 0x07F0 |
| 954 | #define SK_TXQA2_Y2_PREF_FIFORP 0x07F4 |
| 955 | #define SK_TXQA2_Y2_PREF_FIFOWM 0x07F8 |
| 956 | #define SK_TXQA2_Y2_PREF_FIFOLV 0x07FC |
| 957 | |
| 958 | #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 |
| 959 | #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 |
| 960 | #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 |
| 961 | #define SK_TXBMU_TX_START 0x00000010 |
| 962 | #define SK_TXBMU_TX_STOP 0x00000020 |
| 963 | #define SK_TXBMU_POLL_OFF 0x00000040 |
| 964 | #define SK_TXBMU_POLL_ON 0x00000080 |
| 965 | #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 |
| 966 | #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 |
| 967 | #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 |
| 968 | #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 |
| 969 | #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 |
| 970 | #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 |
| 971 | #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 |
| 972 | #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 |
| 973 | #define SK_TXBMU_PFI_SM_RESET 0x00010000 |
| 974 | #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 |
| 975 | #define SK_TXBMU_FIFO_RESET 0x00040000 |
| 976 | #define SK_TXBMU_FIFO_UNRESET 0x00080000 |
| 977 | #define SK_TXBMU_DESC_RESET 0x00100000 |
| 978 | #define SK_TXBMU_DESC_UNRESET 0x00200000 |
| 979 | #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 |
| 980 | |
| 981 | #define SK_TXBMU_ONLINE \ |
| 982 | (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ |
| 983 | SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ |
| 984 | SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ |
| 985 | SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) |
| 986 | |
| 987 | #define SK_TXBMU_OFFLINE \ |
| 988 | (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ |
| 989 | SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ |
| 990 | SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ |
| 991 | SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) |
| 992 | |
| 993 | /* Block 16 -- Receive RAMbuffer 1 */ |
| 994 | #define SK_RXRB1_START 0x0800 |
| 995 | #define SK_RXRB1_END 0x0804 |
| 996 | #define SK_RXRB1_WR_PTR 0x0808 |
| 997 | #define SK_RXRB1_RD_PTR 0x080C |
| 998 | #define SK_RXRB1_UTHR_PAUSE 0x0810 |
| 999 | #define SK_RXRB1_LTHR_PAUSE 0x0814 |
| 1000 | #define SK_RXRB1_UTHR_HIPRIO 0x0818 |
| 1001 | #define SK_RXRB1_UTHR_LOPRIO 0x081C |
| 1002 | #define SK_RXRB1_PKTCNT 0x0820 |
| 1003 | #define SK_RXRB1_LVL 0x0824 |
| 1004 | #define SK_RXRB1_CTLTST 0x0828 |
| 1005 | |
| 1006 | /* Block 17 -- Receive RAMbuffer 2 */ |
| 1007 | #define SK_RXRB2_START 0x0880 |
| 1008 | #define SK_RXRB2_END 0x0884 |
| 1009 | #define SK_RXRB2_WR_PTR 0x0888 |
| 1010 | #define SK_RXRB2_RD_PTR 0x088C |
| 1011 | #define SK_RXRB2_UTHR_PAUSE 0x0890 |
| 1012 | #define SK_RXRB2_LTHR_PAUSE 0x0894 |
| 1013 | #define SK_RXRB2_UTHR_HIPRIO 0x0898 |
| 1014 | #define SK_RXRB2_UTHR_LOPRIO 0x089C |
| 1015 | #define SK_RXRB2_PKTCNT 0x08A0 |
| 1016 | #define SK_RXRB2_LVL 0x08A4 |
| 1017 | #define SK_RXRB2_CTLTST 0x08A8 |
| 1018 | |
| 1019 | /* Block 20 -- Sync. Transmit RAMbuffer 1 */ |
| 1020 | #define SK_TXRBS1_START 0x0A00 |
| 1021 | #define SK_TXRBS1_END 0x0A04 |
| 1022 | #define SK_TXRBS1_WR_PTR 0x0A08 |
| 1023 | #define SK_TXRBS1_RD_PTR 0x0A0C |
| 1024 | #define SK_TXRBS1_PKTCNT 0x0A20 |
| 1025 | #define SK_TXRBS1_LVL 0x0A24 |
| 1026 | #define SK_TXRBS1_CTLTST 0x0A28 |
| 1027 | |
| 1028 | /* Block 21 -- Async. Transmit RAMbuffer 1 */ |
| 1029 | #define SK_TXRBA1_START 0x0A80 |
| 1030 | #define SK_TXRBA1_END 0x0A84 |
| 1031 | #define SK_TXRBA1_WR_PTR 0x0A88 |
| 1032 | #define SK_TXRBA1_RD_PTR 0x0A8C |
| 1033 | #define SK_TXRBA1_PKTCNT 0x0AA0 |
| 1034 | #define SK_TXRBA1_LVL 0x0AA4 |
| 1035 | #define SK_TXRBA1_CTLTST 0x0AA8 |
| 1036 | |
| 1037 | /* Block 22 -- Sync. Transmit RAMbuffer 2 */ |
| 1038 | #define SK_TXRBS2_START 0x0B00 |
| 1039 | #define SK_TXRBS2_END 0x0B04 |
| 1040 | #define SK_TXRBS2_WR_PTR 0x0B08 |
| 1041 | #define SK_TXRBS2_RD_PTR 0x0B0C |
| 1042 | #define SK_TXRBS2_PKTCNT 0x0B20 |
| 1043 | #define SK_TXRBS2_LVL 0x0B24 |
| 1044 | #define SK_TXRBS2_CTLTST 0x0B28 |
| 1045 | |
| 1046 | /* Block 23 -- Async. Transmit RAMbuffer 2 */ |
| 1047 | #define SK_TXRBA2_START 0x0B80 |
| 1048 | #define SK_TXRBA2_END 0x0B84 |
| 1049 | #define SK_TXRBA2_WR_PTR 0x0B88 |
| 1050 | #define SK_TXRBA2_RD_PTR 0x0B8C |
| 1051 | #define SK_TXRBA2_PKTCNT 0x0BA0 |
| 1052 | #define SK_TXRBA2_LVL 0x0BA4 |
| 1053 | #define SK_TXRBA2_CTLTST 0x0BA8 |
| 1054 | |
| 1055 | #define SK_RBCTL_RESET 0x01 |
| 1056 | #define SK_RBCTL_UNRESET 0x02 |
| 1057 | #define SK_RBCTL_OFF 0x04 |
| 1058 | #define SK_RBCTL_ON 0x08 |
| 1059 | #define SK_RBCTL_STORENFWD_OFF 0x10 |
| 1060 | #define SK_RBCTL_STORENFWD_ON 0x20 |
| 1061 | |
| 1062 | /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ |
| 1063 | #define SK_RXF1_END 0x0C00 |
| 1064 | #define SK_RXF1_WPTR 0x0C04 |
| 1065 | #define SK_RXF1_RPTR 0x0C0C |
| 1066 | #define SK_RXF1_PKTCNT 0x0C10 |
| 1067 | #define SK_RXF1_LVL 0x0C14 |
| 1068 | #define SK_RXF1_MACCTL 0x0C18 |
| 1069 | #define SK_RXF1_CTL 0x0C1C |
| 1070 | #define SK_RXLED1_CNTINIT 0x0C20 |
| 1071 | #define SK_RXLED1_COUNTER 0x0C24 |
| 1072 | #define SK_RXLED1_CTL 0x0C28 |
| 1073 | #define SK_RXLED1_TST 0x0C29 |
| 1074 | #define SK_LINK_SYNC1_CINIT 0x0C30 |
| 1075 | #define SK_LINK_SYNC1_COUNTER 0x0C34 |
| 1076 | #define SK_LINK_SYNC1_CTL 0x0C38 |
| 1077 | #define SK_LINK_SYNC1_TST 0x0C39 |
| 1078 | #define SK_LINKLED1_CTL 0x0C3C |
| 1079 | |
| 1080 | #define SK_FIFO_END 0x3F |
| 1081 | |
| 1082 | /* Receive MAC FIFO 1 (Yukon Only) */ |
| 1083 | #define SK_RXMF1_END 0x0C40 |
| 1084 | #define SK_RXMF1_THRESHOLD 0x0C44 |
| 1085 | #define SK_RXMF1_CTRL_TEST 0x0C48 |
| 1086 | #define SK_RXMF1_FLUSH_MASK 0x0C4C |
| 1087 | #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 |
| 1088 | #define SK_RXMF1_WRITE_PTR 0x0C60 |
| 1089 | #define SK_RXMF1_WRITE_LEVEL 0x0C68 |
| 1090 | #define SK_RXMF1_READ_PTR 0x0C70 |
| 1091 | #define SK_RXMF1_READ_LEVEL 0x0C78 |
| 1092 | |
| 1093 | /* Receive MAC FIFO 1 Control/Test */ |
| 1094 | #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ |
| 1095 | #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ |
| 1096 | #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ |
| 1097 | #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ |
| 1098 | #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ |
| 1099 | #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ |
| 1100 | #define SK_RFCTL_FIFO_FLUSH_ON 0x00000080 /* RX FIFO Flush mode on */ |
| 1101 | #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000040 /* RX FIFO Flsuh mode off */ |
| 1102 | #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ |
| 1103 | #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ |
| 1104 | #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ |
| 1105 | #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ |
| 1106 | #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ |
| 1107 | #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ |
| 1108 | |
| 1109 | #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ |
| 1110 | |
| 1111 | /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ |
| 1112 | #define SK_RXF2_END 0x0C80 |
| 1113 | #define SK_RXF2_WPTR 0x0C84 |
| 1114 | #define SK_RXF2_RPTR 0x0C8C |
| 1115 | #define SK_RXF2_PKTCNT 0x0C90 |
| 1116 | #define SK_RXF2_LVL 0x0C94 |
| 1117 | #define SK_RXF2_MACCTL 0x0C98 |
| 1118 | #define SK_RXF2_CTL 0x0C9C |
| 1119 | #define SK_RXLED2_CNTINIT 0x0CA0 |
| 1120 | #define SK_RXLED2_COUNTER 0x0CA4 |
| 1121 | #define SK_RXLED2_CTL 0x0CA8 |
| 1122 | #define SK_RXLED2_TST 0x0CA9 |
| 1123 | #define SK_LINK_SYNC2_CINIT 0x0CB0 |
| 1124 | #define SK_LINK_SYNC2_COUNTER 0x0CB4 |
| 1125 | #define SK_LINK_SYNC2_CTL 0x0CB8 |
| 1126 | #define SK_LINK_SYNC2_TST 0x0CB9 |
| 1127 | #define SK_LINKLED2_CTL 0x0CBC |
| 1128 | |
| 1129 | #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 |
| 1130 | #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 |
| 1131 | #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 |
| 1132 | #define SK_RXMACCTL_RSTAMP_ON 0x00000008 |
| 1133 | #define SK_RXMACCTL_FLUSH_OFF 0x00000010 |
| 1134 | #define SK_RXMACCTL_FLUSH_ON 0x00000020 |
| 1135 | #define SK_RXMACCTL_PAUSE_OFF 0x00000040 |
| 1136 | #define SK_RXMACCTL_PAUSE_ON 0x00000080 |
| 1137 | #define SK_RXMACCTL_AFULL_OFF 0x00000100 |
| 1138 | #define SK_RXMACCTL_AFULL_ON 0x00000200 |
| 1139 | #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 |
| 1140 | #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 |
| 1141 | #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 |
| 1142 | #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 |
| 1143 | #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 |
| 1144 | #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 |
| 1145 | |
| 1146 | #define SK_RXLEDCTL_ENABLE 0x0001 |
| 1147 | #define SK_RXLEDCTL_COUNTER_STOP 0x0002 |
| 1148 | #define SK_RXLEDCTL_COUNTER_START 0x0004 |
| 1149 | |
| 1150 | #define SK_LINKLED_OFF 0x0001 |
| 1151 | #define SK_LINKLED_ON 0x0002 |
| 1152 | #define SK_LINKLED_LINKSYNC_OFF 0x0004 |
| 1153 | #define SK_LINKLED_LINKSYNC_ON 0x0008 |
| 1154 | #define SK_LINKLED_BLINK_OFF 0x0010 |
| 1155 | #define SK_LINKLED_BLINK_ON 0x0020 |
| 1156 | |
| 1157 | /* Block 26 -- TX MAC FIFO 1 regisrers */ |
| 1158 | #define SK_TXF1_END 0x0D00 |
| 1159 | #define SK_TXF1_WPTR 0x0D04 |
| 1160 | #define SK_TXF1_RPTR 0x0D0C |
| 1161 | #define SK_TXF1_PKTCNT 0x0D10 |
| 1162 | #define SK_TXF1_LVL 0x0D14 |
| 1163 | #define SK_TXF1_MACCTL 0x0D18 |
| 1164 | #define SK_TXF1_CTL 0x0D1C |
| 1165 | #define SK_TXLED1_CNTINIT 0x0D20 |
| 1166 | #define SK_TXLED1_COUNTER 0x0D24 |
| 1167 | #define SK_TXLED1_CTL 0x0D28 |
| 1168 | #define SK_TXLED1_TST 0x0D29 |
| 1169 | |
| 1170 | /* Transmit MAC FIFO 1 (Yukon Only) */ |
| 1171 | #define SK_TXMF1_END 0x0D40 |
| 1172 | #define SK_TXMF1_THRESHOLD 0x0D44 |
| 1173 | #define SK_TXMF1_CTRL_TEST 0x0D48 |
| 1174 | #define SK_TXMF1_WRITE_PTR 0x0D60 |
| 1175 | #define SK_TXMF1_WRITE_SHADOW 0x0D64 |
| 1176 | #define SK_TXMF1_WRITE_LEVEL 0x0D68 |
| 1177 | #define SK_TXMF1_READ_PTR 0x0D70 |
| 1178 | #define SK_TXMF1_RESTART_PTR 0x0D74 |
| 1179 | #define SK_TXMF1_READ_LEVEL 0x0D78 |
| 1180 | |
| 1181 | /* Transmit MAC FIFO Control/Test */ |
| 1182 | #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ |
| 1183 | #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ |
| 1184 | #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ |
| 1185 | #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ |
| 1186 | #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ |
| 1187 | #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ |
| 1188 | #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ |
| 1189 | #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ |
| 1190 | #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ |
| 1191 | #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ |
| 1192 | #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ |
| 1193 | #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ |
| 1194 | #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ |
| 1195 | |
| 1196 | /* Block 27 -- TX MAC FIFO 2 regisrers */ |
| 1197 | #define SK_TXF2_END 0x0D80 |
| 1198 | #define SK_TXF2_WPTR 0x0D84 |
| 1199 | #define SK_TXF2_RPTR 0x0D8C |
| 1200 | #define SK_TXF2_PKTCNT 0x0D90 |
| 1201 | #define SK_TXF2_LVL 0x0D94 |
| 1202 | #define SK_TXF2_MACCTL 0x0D98 |
| 1203 | #define SK_TXF2_CTL 0x0D9C |
| 1204 | #define SK_TXLED2_CNTINIT 0x0DA0 |
| 1205 | #define SK_TXLED2_COUNTER 0x0DA4 |
| 1206 | #define SK_TXLED2_CTL 0x0DA8 |
| 1207 | #define SK_TXLED2_TST 0x0DA9 |
| 1208 | |
| 1209 | #define SK_TXMACCTL_XMAC_RESET 0x00000001 |
| 1210 | #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 |
| 1211 | #define SK_TXMACCTL_LOOP_OFF 0x00000004 |
| 1212 | #define SK_TXMACCTL_LOOP_ON 0x00000008 |
| 1213 | #define SK_TXMACCTL_FLUSH_OFF 0x00000010 |
| 1214 | #define SK_TXMACCTL_FLUSH_ON 0x00000020 |
| 1215 | #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 |
| 1216 | #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 |
| 1217 | #define SK_TXMACCTL_AFULL_OFF 0x00000100 |
| 1218 | #define SK_TXMACCTL_AFULL_ON 0x00000200 |
| 1219 | #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 |
| 1220 | #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 |
| 1221 | #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 |
| 1222 | #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 |
| 1223 | #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 |
| 1224 | #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 |
| 1225 | |
| 1226 | #define SK_TXLEDCTL_ENABLE 0x0001 |
| 1227 | #define SK_TXLEDCTL_COUNTER_STOP 0x0002 |
| 1228 | #define SK_TXLEDCTL_COUNTER_START 0x0004 |
| 1229 | |
| 1230 | #define SK_FIFO_RESET 0x00000001 |
| 1231 | #define SK_FIFO_UNRESET 0x00000002 |
| 1232 | #define SK_FIFO_OFF 0x00000004 |
| 1233 | #define SK_FIFO_ON 0x00000008 |
| 1234 | |
| 1235 | /* Block 28 -- Descriptor Poll Timer */ |
| 1236 | #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ |
| 1237 | #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ |
| 1238 | |
| 1239 | #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ |
| 1240 | |
| 1241 | #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 8 bits */ |
| 1242 | #define SK_DPT_TCTL_STOP 0x01 /* Stop Timer */ |
| 1243 | #define SK_DPT_TCTL_START 0x02 /* Start Timer */ |
| 1244 | |
| 1245 | #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ |
| 1246 | #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ |
| 1247 | #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ |
| 1248 | #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ |
| 1249 | |
| 1250 | #define SK_TSTAMP_COUNT 0x0e14 |
| 1251 | #define SK_TSTAMP_CTL 0x0e18 |
| 1252 | |
| 1253 | #define SK_TSTAMP_IRQ_CLEAR 0x01 |
| 1254 | #define SK_TSTAMP_STOP 0x02 |
| 1255 | #define SK_TSTAMP_START 0x04 |
| 1256 | |
| 1257 | #define SK_Y2_ASF_CSR 0x0e68 |
| 1258 | |
| 1259 | #define SK_Y2_ASF_RESET 0x08 |
| 1260 | |
| 1261 | #define SK_Y2_LEV_ITIMERINIT 0x0eb0 |
| 1262 | #define SK_Y2_LEV_ITIMERCTL 0x0eb8 |
| 1263 | #define SK_Y2_TX_ITIMERINIT 0x0ec0 |
| 1264 | #define SK_Y2_TX_ITIMERCTL 0x0ec8 |
| 1265 | #define SK_Y2_ISR_ITIMERINIT 0x0ed0 |
| 1266 | #define SK_Y2_ISR_ITIMERCTL 0x0ed8 |
| 1267 | |
| 1268 | /* Block 29 -- Status BMU (Yukon-2 only) */ |
| 1269 | #define SK_STAT_BMU_CSR 0x0e80 |
| 1270 | #define SK_STAT_BMU_LIDX 0x0e84 |
| 1271 | #define SK_STAT_BMU_ADDRLO 0x0e88 |
| 1272 | #define SK_STAT_BMU_ADDRHI 0x0e8c |
| 1273 | #define SK_STAT_BMU_TXA1_RIDX 0x0e90 |
| 1274 | #define SK_STAT_BMU_TXS1_RIDX 0x0e92 |
| 1275 | #define SK_STAT_BMU_TXA2_RIDX 0x0e94 |
| 1276 | #define SK_STAT_BMU_TXS2_RIDX 0x0e96 |
| 1277 | #define SK_STAT_BMU_TX_THRESH 0x0e98 |
| 1278 | #define SK_STAT_BMU_PUTIDX 0x0e9c |
| 1279 | #define SK_STAT_BMU_FIFOWP 0x0ea0 |
| 1280 | #define SK_STAT_BMU_FIFORP 0x0ea4 |
| 1281 | #define SK_STAT_BMU_FIFORSP 0x0ea6 |
| 1282 | #define SK_STAT_BMU_FIFOLV 0x0ea8 |
| 1283 | #define SK_STAT_BMU_FIFOSLV 0x0eaa |
| 1284 | #define SK_STAT_BMU_FIFOWM 0x0eac |
| 1285 | #define SK_STAT_BMU_FIFOIWM 0x0ead |
| 1286 | |
| 1287 | #define SK_STAT_BMU_RESET 0x00000001 |
| 1288 | #define SK_STAT_BMU_UNRESET 0x00000002 |
| 1289 | #define SK_STAT_BMU_OFF 0x00000004 |
| 1290 | #define SK_STAT_BMU_ON 0x00000008 |
| 1291 | #define SK_STAT_BMU_IRQ_CLEAR 0x00000010 |
| 1292 | |
| 1293 | #define SK_STAT_BMU_TXTHIDX_MSK 0x0fff |
| 1294 | |
| 1295 | /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ |
| 1296 | #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ |
| 1297 | #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ |
| 1298 | #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ |
| 1299 | #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ |
| 1300 | #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ |
| 1301 | #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ |
| 1302 | #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ |
| 1303 | #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ |
| 1304 | #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ |
| 1305 | #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ |
| 1306 | #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ |
| 1307 | #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ |
| 1308 | #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ |
| 1309 | #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ |
| 1310 | #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ |
| 1311 | #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ |
| 1312 | #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ |
| 1313 | #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ |
| 1314 | #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ |
| 1315 | #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ |
| 1316 | #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ |
| 1317 | #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ |
| 1318 | #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ |
| 1319 | #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ |
| 1320 | #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ |
| 1321 | #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ |
| 1322 | #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ |
| 1323 | #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ |
| 1324 | #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ |
| 1325 | |
| 1326 | #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ |
| 1327 | #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ |
| 1328 | #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ |
| 1329 | #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ |
| 1330 | #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ |
| 1331 | #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ |
| 1332 | |
| 1333 | #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ |
| 1334 | #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ |
| 1335 | #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ |
| 1336 | #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ |
| 1337 | #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ |
| 1338 | #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ |
| 1339 | #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ |
| 1340 | #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ |
| 1341 | #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ |
| 1342 | #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ |
| 1343 | #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ |
| 1344 | #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ |
| 1345 | #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ |
| 1346 | #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ |
| 1347 | #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ |
| 1348 | #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ |
| 1349 | #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ |
| 1350 | #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ |
| 1351 | #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ |
| 1352 | #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ |
| 1353 | #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ |
| 1354 | #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ |
| 1355 | #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ |
| 1356 | |
| 1357 | #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ |
| 1358 | SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) |
| 1359 | #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ |
| 1360 | SK_GPHY_HWCFG_M_2 ) |
| 1361 | #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ |
| 1362 | SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) |
| 1363 | |
| 1364 | #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ |
| 1365 | #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ |
| 1366 | #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ |
| 1367 | #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ |
| 1368 | #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ |
| 1369 | #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ |
| 1370 | |
| 1371 | #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ |
| 1372 | #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ |
| 1373 | |
| 1374 | /* Block 31 -- reserved */ |
| 1375 | |
| 1376 | /* Block 32-33 -- Pattern Ram */ |
| 1377 | #define SK_WOL_PRAM 0x1000 |
| 1378 | |
| 1379 | /* Block 0x22 - 0x37 -- reserved */ |
| 1380 | |
| 1381 | /* Block 0x38 -- Y2 PCI config registers */ |
| 1382 | #define SK_Y2_PCI_BASE 0x1c00 |
| 1383 | |
| 1384 | /* Compute offset of mirrored PCI register */ |
| 1385 | #define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE) |
| 1386 | |
| 1387 | /* Block 0x39 - 0x3f -- reserved */ |
| 1388 | |
| 1389 | /* Block 0x40 to 0x4F -- XMAC 1 registers */ |
| 1390 | #define SK_XMAC1_BASE 0x2000 |
| 1391 | |
| 1392 | /* Block 0x50 to 0x5F -- MARV 1 registers */ |
| 1393 | #define SK_MARV1_BASE 0x2800 |
| 1394 | |
| 1395 | /* Block 0x60 to 0x6F -- XMAC 2 registers */ |
| 1396 | #define SK_XMAC2_BASE 0x3000 |
| 1397 | |
| 1398 | /* Block 0x70 to 0x7F -- MARV 2 registers */ |
| 1399 | #define SK_MARV2_BASE 0x3800 |
| 1400 | |
| 1401 | /* Compute relative offset of an XMAC register in the XMAC window(s). */ |
| 1402 | #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ |
| 1403 | (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) |
| 1404 | |
| 1405 | #if 0 |
| 1406 | #define SK_XM_READ_4(sc, reg) \ |
| 1407 | ((sk_win_read_2(sc->sk_softc, \ |
| 1408 | SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ |
| 1409 | ((sk_win_read_2(sc->sk_softc, \ |
| 1410 | SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) |
| 1411 | |
| 1412 | #define SK_XM_WRITE_4(sc, reg, val) \ |
| 1413 | sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ |
| 1414 | ((val) & 0xFFFF)); \ |
| 1415 | sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ |
| 1416 | ((val) >> 16) & 0xFFFF) |
| 1417 | #else |
| 1418 | #define SK_XM_READ_4(sc, reg) \ |
| 1419 | sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) |
| 1420 | |
| 1421 | #define SK_XM_WRITE_4(sc, reg, val) \ |
| 1422 | sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) |
| 1423 | #endif |
| 1424 | |
| 1425 | #define SK_XM_READ_2(sc, reg) \ |
| 1426 | sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) |
| 1427 | |
| 1428 | #define SK_XM_WRITE_2(sc, reg, val) \ |
| 1429 | sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) |
| 1430 | |
| 1431 | #define SK_XM_SETBIT_4(sc, reg, x) \ |
| 1432 | SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) |
| 1433 | |
| 1434 | #define SK_XM_CLRBIT_4(sc, reg, x) \ |
| 1435 | SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) |
| 1436 | |
| 1437 | #define SK_XM_SETBIT_2(sc, reg, x) \ |
| 1438 | SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) |
| 1439 | |
| 1440 | #define SK_XM_CLRBIT_2(sc, reg, x) \ |
| 1441 | SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) |
| 1442 | |
| 1443 | /* Compute relative offset of an MARV register in the MARV window(s). */ |
| 1444 | #define SK_YU_REG(sc, reg) \ |
| 1445 | ((reg) + SK_MARV1_BASE + \ |
| 1446 | (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) |
| 1447 | |
| 1448 | #define SK_YU_READ_4(sc, reg) \ |
| 1449 | sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) |
| 1450 | |
| 1451 | #define SK_YU_READ_2(sc, reg) \ |
| 1452 | sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) |
| 1453 | |
| 1454 | #define SK_YU_WRITE_4(sc, reg, val) \ |
| 1455 | sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) |
| 1456 | |
| 1457 | #define SK_YU_WRITE_2(sc, reg, val) \ |
| 1458 | sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) |
| 1459 | |
| 1460 | #define SK_YU_SETBIT_4(sc, reg, x) \ |
| 1461 | SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) |
| 1462 | |
| 1463 | #define SK_YU_CLRBIT_4(sc, reg, x) \ |
| 1464 | SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) |
| 1465 | |
| 1466 | #define SK_YU_SETBIT_2(sc, reg, x) \ |
| 1467 | SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) |
| 1468 | |
| 1469 | #define SK_YU_CLRBIT_2(sc, reg, x) \ |
| 1470 | SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) |
| 1471 | |
| 1472 | /* |
| 1473 | * The default FIFO threshold on the XMAC II is 4 bytes. On |
| 1474 | * dual port NICs, this often leads to transmit underruns, so we |
| 1475 | * bump the threshold a little. |
| 1476 | */ |
| 1477 | #define SK_XM_TX_FIFOTHRESH 512 |
| 1478 | |
| 1479 | #define SK_PCI_VENDOR_ID 0x0000 |
| 1480 | #define SK_PCI_DEVICE_ID 0x0002 |
| 1481 | #define SK_PCI_COMMAND 0x0004 |
| 1482 | #define SK_PCI_STATUS 0x0006 |
| 1483 | #define SK_PCI_REVID 0x0008 |
| 1484 | #define SK_PCI_CLASSCODE 0x0009 |
| 1485 | #define SK_PCI_CACHELEN 0x000C |
| 1486 | #define SK_PCI_LATENCY_TIMER 0x000D |
| 1487 | #define 0x000E |
| 1488 | #define SK_PCI_LOMEM 0x0010 |
| 1489 | #define SK_PCI_LOIO 0x0014 |
| 1490 | #define SK_PCI_SUBVEN_ID 0x002C |
| 1491 | #define SK_PCI_SYBSYS_ID 0x002E |
| 1492 | #define SK_PCI_BIOSROM 0x0030 |
| 1493 | #define SK_PCI_INTLINE 0x003C |
| 1494 | #define SK_PCI_INTPIN 0x003D |
| 1495 | #define SK_PCI_MINGNT 0x003E |
| 1496 | #define SK_PCI_MINLAT 0x003F |
| 1497 | |
| 1498 | /* device specific PCI registers */ |
| 1499 | #define SK_PCI_OURREG1 0x0040 |
| 1500 | #define SK_PCI_OURREG2 0x0044 |
| 1501 | #define SK_PCI_CAPID 0x0048 /* 8 bits */ |
| 1502 | #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ |
| 1503 | #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ |
| 1504 | #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ |
| 1505 | #define SK_PCI_PME_EVENT 0x004F |
| 1506 | #define SK_PCI_VPD_CAPID 0x0050 |
| 1507 | #define SK_PCI_VPD_NEXTPTR 0x0051 |
| 1508 | #define SK_PCI_VPD_ADDR 0x0052 |
| 1509 | #define SK_PCI_VPD_DATA 0x0054 |
| 1510 | #define SK_PCI_OURREG3 0x0080 /* Yukon EC U */ |
| 1511 | #define SK_PCI_OURREG4 0x0084 |
| 1512 | #define SK_PCI_OURREG5 0x0088 |
| 1513 | |
| 1514 | #define SK_Y2_REG1_PHY1_COMA 0x10000000 |
| 1515 | #define SK_Y2_REG1_PHY2_COMA 0x20000000 |
| 1516 | |
| 1517 | /* SK_PCI_OURREG2 32bits */ |
| 1518 | #define SK_REG2_REV_DESC 0x00000004 /* revert byte order in descriptor */ |
| 1519 | |
| 1520 | /* SK_PCI_OURREG4 32bits (Yukon-ECU only) */ |
| 1521 | #define SK_Y2_REG4_TIMER_VALUE_MSK (0xff << 16) |
| 1522 | #define SK_Y2_REG4_FORCE_ASPM_REQUEST __BIT(15) |
| 1523 | #define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN __BIT(14) |
| 1524 | #define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY __BIT(13) |
| 1525 | #define SK_Y2_REG4_ASPM_CLKRUN_REQUEST __BIT(12) |
| 1526 | #define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA __BIT(4) |
| 1527 | #define SK_Y2_REG4_ASPM_CLKREQ_PAD __BIT(3) |
| 1528 | #define SK_Y2_REG4_ASPM_A1_MODE_SELECT __BIT(2) |
| 1529 | #define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA __BIT(1) |
| 1530 | #define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA __BIT(0) |
| 1531 | |
| 1532 | #define SK_PSTATE_MASK 0x0003 |
| 1533 | #define SK_PSTATE_D0 0x0000 |
| 1534 | #define SK_PSTATE_D1 0x0001 |
| 1535 | #define SK_PSTATE_D2 0x0002 |
| 1536 | #define SK_PSTATE_D3 0x0003 |
| 1537 | #define SK_PME_EN 0x0010 |
| 1538 | #define SK_PME_STATUS 0x8000 |
| 1539 | |
| 1540 | /* |
| 1541 | * VPD flag bit. Set to 0 to initiate a read, will become 1 when |
| 1542 | * read is complete. Set to 1 to initiate a write, will become 0 |
| 1543 | * when write is finished. |
| 1544 | */ |
| 1545 | #define SK_VPD_FLAG 0x8000 |
| 1546 | |
| 1547 | /* VPD structures */ |
| 1548 | struct vpd_res { |
| 1549 | u_int8_t vr_id; |
| 1550 | u_int8_t vr_len; |
| 1551 | u_int8_t vr_pad; |
| 1552 | }; |
| 1553 | |
| 1554 | struct vpd_key { |
| 1555 | char vk_key[2]; |
| 1556 | u_int8_t vk_len; |
| 1557 | }; |
| 1558 | |
| 1559 | #define VPD_RES_ID 0x82 /* ID string */ |
| 1560 | #define VPD_RES_READ 0x90 /* start of read only area */ |
| 1561 | #define VPD_RES_WRITE 0x81 /* start of read/write area */ |
| 1562 | #define VPD_RES_END 0x78 /* end tag */ |
| 1563 | |
| 1564 | #define CSR_WRITE_4(sc, reg, val) \ |
| 1565 | bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) |
| 1566 | #define CSR_WRITE_2(sc, reg, val) \ |
| 1567 | bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) |
| 1568 | #define CSR_WRITE_1(sc, reg, val) \ |
| 1569 | bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) |
| 1570 | |
| 1571 | #define CSR_READ_4(sc, reg) \ |
| 1572 | bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) |
| 1573 | #define CSR_READ_2(sc, reg) \ |
| 1574 | bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) |
| 1575 | #define CSR_READ_1(sc, reg) \ |
| 1576 | bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) |
| 1577 | |
| 1578 | struct sk_type { |
| 1579 | u_int16_t sk_vid; |
| 1580 | u_int16_t sk_did; |
| 1581 | const char *sk_name; |
| 1582 | }; |
| 1583 | |
| 1584 | #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) |
| 1585 | #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) |
| 1586 | |
| 1587 | #define SK_RING_ALIGN 64 |
| 1588 | |
| 1589 | #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) |
| 1590 | #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) |
| 1591 | |
| 1592 | #define SK_RING_ALIGN 64 |
| 1593 | |
| 1594 | /* RX queue descriptor data structure */ |
| 1595 | struct sk_rx_desc { |
| 1596 | u_int32_t sk_ctl; |
| 1597 | u_int32_t sk_next; |
| 1598 | u_int32_t sk_data_lo; |
| 1599 | u_int32_t sk_data_hi; |
| 1600 | u_int32_t sk_xmac_rxstat; |
| 1601 | u_int32_t sk_timestamp; |
| 1602 | u_int16_t sk_csum2; |
| 1603 | u_int16_t sk_csum1; |
| 1604 | u_int16_t sk_csum2_start; |
| 1605 | u_int16_t sk_csum1_start; |
| 1606 | }; |
| 1607 | |
| 1608 | #define SK_OPCODE_DEFAULT 0x00550000 |
| 1609 | #define SK_OPCODE_CSUM 0x00560000 |
| 1610 | |
| 1611 | #define SK_RXCTL_LEN 0x0000FFFF |
| 1612 | #define SK_RXCTL_OPCODE 0x00FF0000 |
| 1613 | #define SK_RXCTL_TSTAMP_VALID 0x01000000 |
| 1614 | #define SK_RXCTL_STATUS_VALID 0x02000000 |
| 1615 | #define SK_RXCTL_DEV0 0x04000000 |
| 1616 | #define SK_RXCTL_EOF_INTR 0x08000000 |
| 1617 | #define SK_RXCTL_EOB_INTR 0x10000000 |
| 1618 | #define SK_RXCTL_LASTFRAG 0x20000000 |
| 1619 | #define SK_RXCTL_FIRSTFRAG 0x40000000 |
| 1620 | #define SK_RXCTL_OWN 0x80000000 |
| 1621 | |
| 1622 | #define SK_RXSTAT \ |
| 1623 | (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ |
| 1624 | SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) |
| 1625 | |
| 1626 | struct sk_tx_desc { |
| 1627 | u_int32_t sk_ctl; |
| 1628 | u_int32_t sk_next; |
| 1629 | u_int32_t sk_data_lo; |
| 1630 | u_int32_t sk_data_hi; |
| 1631 | u_int32_t sk_xmac_txstat; |
| 1632 | u_int16_t sk_rsvd0; |
| 1633 | u_int16_t sk_csum_startval; |
| 1634 | u_int16_t sk_csum_startpos; |
| 1635 | u_int16_t sk_csum_writepos; |
| 1636 | u_int32_t sk_rsvd1; |
| 1637 | }; |
| 1638 | |
| 1639 | #define SK_TXCTL_LEN 0x0000FFFF |
| 1640 | #define SK_TXCTL_OPCODE 0x00FF0000 |
| 1641 | #define SK_TXCTL_SW 0x01000000 |
| 1642 | #define SK_TXCTL_NOCRC 0x02000000 |
| 1643 | #define SK_TXCTL_STORENFWD 0x04000000 |
| 1644 | #define SK_TXCTL_EOF_INTR 0x08000000 |
| 1645 | #define SK_TXCTL_EOB_INTR 0x10000000 |
| 1646 | #define SK_TXCTL_LASTFRAG 0x20000000 |
| 1647 | #define SK_TXCTL_FIRSTFRAG 0x40000000 |
| 1648 | #define SK_TXCTL_OWN 0x80000000 |
| 1649 | |
| 1650 | #define SK_TXSTAT \ |
| 1651 | (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) |
| 1652 | |
| 1653 | #define SK_RXBYTES(x) ((x) & 0x0000FFFF); |
| 1654 | #define SK_TXBYTES SK_RXBYTES |
| 1655 | |
| 1656 | #define SK_TX_RING_CNT 512 |
| 1657 | #define SK_RX_RING_CNT 256 |
| 1658 | |
| 1659 | struct msk_rx_desc { |
| 1660 | u_int32_t sk_addr; |
| 1661 | u_int16_t sk_len; |
| 1662 | u_int8_t sk_ctl; |
| 1663 | u_int8_t sk_opcode; |
| 1664 | } __packed; |
| 1665 | |
| 1666 | #define SK_Y2_RXOPC_BUFFER 0x40 |
| 1667 | #define SK_Y2_RXOPC_PACKET 0x41 |
| 1668 | #define SK_Y2_RXOPC_OWN 0x80 |
| 1669 | |
| 1670 | struct msk_tx_desc { |
| 1671 | u_int32_t sk_addr; |
| 1672 | u_int16_t sk_len; |
| 1673 | u_int8_t sk_ctl; |
| 1674 | u_int8_t sk_opcode; |
| 1675 | } __packed; |
| 1676 | |
| 1677 | #define SK_Y2_TXCTL_LASTFRAG 0x80 |
| 1678 | |
| 1679 | #define SK_Y2_TXOPC_BUFFER 0x40 |
| 1680 | #define SK_Y2_TXOPC_PACKET 0x41 |
| 1681 | #define SK_Y2_TXOPC_OWN 0x80 |
| 1682 | |
| 1683 | struct msk_status_desc { |
| 1684 | u_int32_t sk_status; |
| 1685 | u_int16_t sk_len; |
| 1686 | u_int8_t sk_link; |
| 1687 | u_int8_t sk_opcode; |
| 1688 | } __packed; |
| 1689 | |
| 1690 | #define SK_Y2_STOPC_RXSTAT 0x60 |
| 1691 | #define SK_Y2_STOPC_TXSTAT 0x68 |
| 1692 | #define SK_Y2_STOPC_OWN 0x80 |
| 1693 | |
| 1694 | #define SK_Y2_ST_TXA1_MSKL 0x00000fff |
| 1695 | #define SK_Y2_ST_TXA1_SHIFT 0 |
| 1696 | |
| 1697 | #define SK_Y2_ST_TXA2_MSKL 0xff000000 |
| 1698 | #define SK_Y2_ST_TXA2_SHIFTL 24 |
| 1699 | #define SK_Y2_ST_TXA2_MSKH 0x000f |
| 1700 | #define SK_Y2_ST_TXA2_SHIFTH 8 |
| 1701 | |
| 1702 | #define SK_Y2_ST_TXA1_MSKL 0x00000fff |
| 1703 | #define SK_Y2_ST_TXA1_SHIFT 0 |
| 1704 | |
| 1705 | #define SK_Y2_ST_TXA2_MSKL 0xff000000 |
| 1706 | #define SK_Y2_ST_TXA2_SHIFTL 24 |
| 1707 | #define SK_Y2_ST_TXA2_MSKH 0x000f |
| 1708 | #define SK_Y2_ST_TXA2_SHIFTH 8 |
| 1709 | |
| 1710 | #define MSK_TX_RING_CNT 512 |
| 1711 | #define MSK_RX_RING_CNT 512 |
| 1712 | #define MSK_STATUS_RING_CNT 2048 |
| 1713 | |
| 1714 | /* |
| 1715 | * Jumbo buffer stuff. Note that we must allocate more jumbo |
| 1716 | * buffers than there are descriptors in the receive ring. This |
| 1717 | * is because we don't know how long it will take for a packet |
| 1718 | * to be released after we hand it off to the upper protocol |
| 1719 | * layers. To be safe, we allocate 1.5 times the number of |
| 1720 | * receive descriptors. |
| 1721 | */ |
| 1722 | #define SK_JUMBO_FRAMELEN 9018 |
| 1723 | #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
| 1724 | #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) |
| 1725 | #define SK_JSLOTS 384 |
| 1726 | |
| 1727 | #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) |
| 1728 | #define SK_JLEN SK_JRAWLEN |
| 1729 | #define SK_MCLBYTES SK_JLEN |
| 1730 | #define SK_JPAGESZ PAGE_SIZE |
| 1731 | #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) |
| 1732 | #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) |
| 1733 | |
| 1734 | #define MSK_JSLOTS ((MSK_RX_RING_CNT / 2) * 3) |
| 1735 | |
| 1736 | #define MSK_RESID (SK_JPAGESZ - (SK_JLEN * MSK_JSLOTS) % SK_JPAGESZ) |
| 1737 | #define MSK_JMEM ((SK_JLEN * MSK_JSLOTS) + MSK_RESID) |
| 1738 | |
| 1739 | #define SK_MAXUNIT 256 |
| 1740 | #define SK_TIMEOUT 1000 |
| 1741 | #define ETHER_ALIGN 2 |
| 1742 | |
| 1743 | /* YUKON registers */ |
| 1744 | |
| 1745 | /* General Purpose Status Register (GPSR) */ |
| 1746 | #define YUKON_GPSR 0x0000 |
| 1747 | |
| 1748 | #define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ |
| 1749 | #define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ |
| 1750 | #define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */ |
| 1751 | #define YU_GPSR_LINK 0x1000 /* link status (down/up) */ |
| 1752 | #define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ |
| 1753 | #define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ |
| 1754 | #define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ |
| 1755 | #define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ |
| 1756 | #define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ |
| 1757 | #define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ |
| 1758 | #define YU_GPSR_PARTITION 0x0008 /* partition mode */ |
| 1759 | #define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */ |
| 1760 | #define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */ |
| 1761 | |
| 1762 | /* General Purpose Control Register (GPCR) */ |
| 1763 | #define YUKON_GPCR 0x0004 |
| 1764 | |
| 1765 | #define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */ |
| 1766 | #define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ |
| 1767 | #define YU_GPCR_RXEN 0x0800 /* Receive Enable */ |
| 1768 | #define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */ |
| 1769 | #define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */ |
| 1770 | #define YU_GPCR_PAR 0x0100 /* Partition Enable */ |
| 1771 | #define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */ |
| 1772 | #define YU_GPCR_FLP 0x0040 /* Force Link Pass */ |
| 1773 | #define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ |
| 1774 | #define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */ |
| 1775 | #define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */ |
| 1776 | #define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */ |
| 1777 | #define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */ |
| 1778 | #define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */ |
| 1779 | |
| 1780 | /* Transmit Control Register (TCR) */ |
| 1781 | #define YUKON_TCR 0x0008 |
| 1782 | |
| 1783 | #define YU_TCR_FJ 0x8000 /* force jam / flow control */ |
| 1784 | #define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ |
| 1785 | #define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ |
| 1786 | #define YU_TCR_COLTH 0x1c00 /* collision threshold */ |
| 1787 | |
| 1788 | /* Receive Control Register (RCR) */ |
| 1789 | #define YUKON_RCR 0x000c |
| 1790 | |
| 1791 | #define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ |
| 1792 | #define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ |
| 1793 | #define YU_RCR_CRCR 0x2000 /* remove CRC */ |
| 1794 | #define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ |
| 1795 | |
| 1796 | /* Transmit Flow Control Register (TFCR) */ |
| 1797 | #define YUKON_TFCR 0x0010 /* Pause Time */ |
| 1798 | |
| 1799 | /* Transmit Parameter Register (TPR) */ |
| 1800 | #define YUKON_TPR 0x0014 |
| 1801 | |
| 1802 | #define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) |
| 1803 | #define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) |
| 1804 | #define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) |
| 1805 | |
| 1806 | /* Serial Mode Register (SMR) */ |
| 1807 | #define YUKON_SMR 0x0018 |
| 1808 | |
| 1809 | #define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) |
| 1810 | #define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ |
| 1811 | #define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ |
| 1812 | #define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ |
| 1813 | #define YU_SMR_IPG_DATA(x) ((x) & 0x1f) |
| 1814 | |
| 1815 | /* Source Address Low #1 (SAL1) */ |
| 1816 | #define YUKON_SAL1 0x001c /* SA1[15:0] */ |
| 1817 | |
| 1818 | /* Source Address Middle #1 (SAM1) */ |
| 1819 | #define YUKON_SAM1 0x0020 /* SA1[31:16] */ |
| 1820 | |
| 1821 | /* Source Address High #1 (SAH1) */ |
| 1822 | #define YUKON_SAH1 0x0024 /* SA1[47:32] */ |
| 1823 | |
| 1824 | /* Source Address Low #2 (SAL2) */ |
| 1825 | #define YUKON_SAL2 0x0028 /* SA2[15:0] */ |
| 1826 | |
| 1827 | /* Source Address Middle #2 (SAM2) */ |
| 1828 | #define YUKON_SAM2 0x002c /* SA2[31:16] */ |
| 1829 | |
| 1830 | /* Source Address High #2 (SAH2) */ |
| 1831 | #define YUKON_SAH2 0x0030 /* SA2[47:32] */ |
| 1832 | |
| 1833 | /* Multicatst Address Hash Register 1 (MCAH1) */ |
| 1834 | #define YUKON_MCAH1 0x0034 |
| 1835 | |
| 1836 | /* Multicatst Address Hash Register 2 (MCAH2) */ |
| 1837 | #define YUKON_MCAH2 0x0038 |
| 1838 | |
| 1839 | /* Multicatst Address Hash Register 3 (MCAH3) */ |
| 1840 | #define YUKON_MCAH3 0x003c |
| 1841 | |
| 1842 | /* Multicatst Address Hash Register 4 (MCAH4) */ |
| 1843 | #define YUKON_MCAH4 0x0040 |
| 1844 | |
| 1845 | /* Transmit Interrupt Register (TIR) */ |
| 1846 | #define YUKON_TIR 0x0044 |
| 1847 | |
| 1848 | #define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ |
| 1849 | #define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ |
| 1850 | #define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ |
| 1851 | #define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ |
| 1852 | #define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ |
| 1853 | #define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1854 | #define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1855 | #define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1856 | #define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1857 | #define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1858 | #define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1859 | #define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ |
| 1860 | #define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ |
| 1861 | #define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ |
| 1862 | #define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ |
| 1863 | |
| 1864 | /* Receive Interrupt Register (RIR) */ |
| 1865 | #define YUKON_RIR 0x0048 |
| 1866 | |
| 1867 | /* Transmit and Receive Interrupt Register (TRIR) */ |
| 1868 | #define YUKON_TRIR 0x004c |
| 1869 | |
| 1870 | /* Transmit Interrupt Mask Register (TIMR) */ |
| 1871 | #define YUKON_TIMR 0x0050 |
| 1872 | |
| 1873 | /* Receive Interrupt Mask Register (RIMR) */ |
| 1874 | #define YUKON_RIMR 0x0054 |
| 1875 | |
| 1876 | /* Transmit and Receive Interrupt Mask Register (TRIMR) */ |
| 1877 | #define YUKON_TRIMR 0x0058 |
| 1878 | |
| 1879 | /* SMI Control Register (SMICR) */ |
| 1880 | #define YUKON_SMICR 0x0080 |
| 1881 | |
| 1882 | #define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) |
| 1883 | #define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) |
| 1884 | #define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ |
| 1885 | #define YU_SMICR_OP_READ 0x0020 /* opcode read */ |
| 1886 | #define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ |
| 1887 | #define YU_SMICR_READ_VALID 0x0010 /* read valid */ |
| 1888 | #define YU_SMICR_BUSY 0x0008 /* busy (writing) */ |
| 1889 | |
| 1890 | /* SMI Data Register (SMIDR) */ |
| 1891 | #define YUKON_SMIDR 0x0084 |
| 1892 | |
| 1893 | /* PHY Addres Register (PAR) */ |
| 1894 | #define YUKON_PAR 0x0088 |
| 1895 | |
| 1896 | #define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ |
| 1897 | #define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ |
| 1898 | |
| 1899 | /* Receive status */ |
| 1900 | #define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */ |
| 1901 | #define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */ |
| 1902 | #define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */ |
| 1903 | #define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */ |
| 1904 | #define YU_RXSTAT_MIIERR 0x00000020 /* MII error */ |
| 1905 | #define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */ |
| 1906 | #define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */ |
| 1907 | #define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */ |
| 1908 | #define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */ |
| 1909 | #define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */ |
| 1910 | #define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */ |
| 1911 | #define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */ |
| 1912 | #define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */ |
| 1913 | #define YU_RXSTAT_LENSHIFT 16 |
| 1914 | |
| 1915 | #define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT) |
| 1916 | |
| 1917 | /* Receive status */ |
| 1918 | #define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */ |
| 1919 | #define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */ |
| 1920 | #define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */ |
| 1921 | #define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */ |
| 1922 | #define YU_RXSTAT_MIIERR 0x00000020 /* MII error */ |
| 1923 | #define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */ |
| 1924 | #define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */ |
| 1925 | #define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */ |
| 1926 | #define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */ |
| 1927 | #define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */ |
| 1928 | #define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */ |
| 1929 | #define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */ |
| 1930 | #define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */ |
| 1931 | #define YU_RXSTAT_LENSHIFT 16 |
| 1932 | |
| 1933 | #define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT) |
| 1934 | |
| 1935 | /* Receive status */ |
| 1936 | #define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */ |
| 1937 | #define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */ |
| 1938 | #define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */ |
| 1939 | #define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */ |
| 1940 | #define YU_RXSTAT_MIIERR 0x00000020 /* MII error */ |
| 1941 | #define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */ |
| 1942 | #define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */ |
| 1943 | #define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */ |
| 1944 | #define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */ |
| 1945 | #define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */ |
| 1946 | #define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */ |
| 1947 | #define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */ |
| 1948 | #define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */ |
| 1949 | #define YU_RXSTAT_LENSHIFT 16 |
| 1950 | |
| 1951 | #define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT) |
| 1952 | |
| 1953 | /* |
| 1954 | * Registers and data structures for the XaQti Corporation XMAC II |
| 1955 | * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com. |
| 1956 | * The XMAC can be programmed for 16-bit or 32-bit register access modes. |
| 1957 | * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's |
| 1958 | * how the registers are laid out here. |
| 1959 | */ |
| 1960 | |
| 1961 | #define XM_DEVICEID 0x00E0AE20 |
| 1962 | #define XM_XAQTI_OUI 0x00E0AE |
| 1963 | |
| 1964 | #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5) |
| 1965 | |
| 1966 | #define XM_XMAC_REV_B2 0x0 |
| 1967 | #define XM_XMAC_REV_C1 0x1 |
| 1968 | |
| 1969 | #define XM_MMUCMD 0x0000 |
| 1970 | #define XM_POFF 0x0008 |
| 1971 | #define XM_BURST 0x000C |
| 1972 | #define XM_VLAN_TAGLEV1 0x0010 |
| 1973 | #define XM_VLAN_TAGLEV2 0x0014 |
| 1974 | #define XM_TXCMD 0x0020 |
| 1975 | #define XM_TX_RETRYLIMIT 0x0024 |
| 1976 | #define XM_TX_SLOTTIME 0x0028 |
| 1977 | #define XM_TX_IPG 0x003C |
| 1978 | #define XM_RXCMD 0x0030 |
| 1979 | #define XM_PHY_ADDR 0x0034 |
| 1980 | #define XM_PHY_DATA 0x0038 |
| 1981 | #define XM_GPIO 0x0040 |
| 1982 | #define XM_IMR 0x0044 |
| 1983 | #define XM_ISR 0x0048 |
| 1984 | #define XM_HWCFG 0x004C |
| 1985 | #define XM_TX_LOWAT 0x0060 |
| 1986 | #define XM_TX_HIWAT 0x0062 |
| 1987 | #define XM_TX_REQTHRESH_LO 0x0064 |
| 1988 | #define XM_TX_REQTHRESH_HI 0x0066 |
| 1989 | #define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO |
| 1990 | #define XM_PAUSEDST0 0x0068 |
| 1991 | #define XM_PAUSEDST1 0x006A |
| 1992 | #define XM_PAUSEDST2 0x006C |
| 1993 | #define XM_CTLPARM_LO 0x0070 |
| 1994 | #define XM_CTLPARM_HI 0x0072 |
| 1995 | #define XM_CTLPARM XM_CTLPARM_LO |
| 1996 | #define XM_OPCODE_PAUSE_TIMER 0x0074 |
| 1997 | #define XM_TXSTAT_LIFO 0x0078 |
| 1998 | |
| 1999 | /* |
| 2000 | * Perfect filter registers. The XMAC has a table of 16 perfect |
| 2001 | * filter entries, spaced 8 bytes apart. This is in addition to |
| 2002 | * the station address registers, which appear below. |
| 2003 | */ |
| 2004 | #define XM_RXFILT_BASE 0x0080 |
| 2005 | #define XM_RXFILT_END 0x0107 |
| 2006 | #define XM_RXFILT_MAX 16 |
| 2007 | #define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8))) |
| 2008 | |
| 2009 | /* Primary station address. */ |
| 2010 | #define XM_PAR0 0x0108 |
| 2011 | #define XM_PAR1 0x010A |
| 2012 | #define XM_PAR2 0x010C |
| 2013 | |
| 2014 | /* 64-bit multicast hash table registers */ |
| 2015 | #define XM_MAR0 0x0110 |
| 2016 | #define XM_MAR1 0x0112 |
| 2017 | #define XM_MAR2 0x0114 |
| 2018 | #define XM_MAR3 0x0116 |
| 2019 | #define XM_RX_LOWAT 0x0118 |
| 2020 | #define XM_RX_HIWAT 0x011A |
| 2021 | #define XM_RX_REQTHRESH_LO 0x011C |
| 2022 | #define XM_RX_REQTHRESH_HI 0x011E |
| 2023 | #define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO |
| 2024 | #define XM_DEVID_LO 0x0120 |
| 2025 | #define XM_DEVID_HI 0x0122 |
| 2026 | #define XM_DEVID XM_DEVID_LO |
| 2027 | #define XM_MODE_LO 0x0124 |
| 2028 | #define XM_MODE_HI 0x0126 |
| 2029 | #define XM_MODE XM_MODE_LO |
| 2030 | #define XM_LASTSRC0 0x0128 |
| 2031 | #define XM_LASTSRC1 0x012A |
| 2032 | #define XM_LASTSRC2 0x012C |
| 2033 | #define XM_TSTAMP_READ 0x0130 |
| 2034 | #define XM_TSTAMP_LOAD 0x0134 |
| 2035 | #define XM_STATS_CMD 0x0200 |
| 2036 | #define XM_RXCNT_EVENT_LO 0x0204 |
| 2037 | #define XM_RXCNT_EVENT_HI 0x0206 |
| 2038 | #define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO |
| 2039 | #define XM_TXCNT_EVENT_LO 0x0208 |
| 2040 | #define XM_TXCNT_EVENT_HI 0x020A |
| 2041 | #define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO |
| 2042 | #define XM_RXCNT_EVMASK_LO 0x020C |
| 2043 | #define XM_RXCNT_EVMASK_HI 0x020E |
| 2044 | #define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO |
| 2045 | #define XM_TXCNT_EVMASK_LO 0x0210 |
| 2046 | #define XM_TXCNT_EVMASK_HI 0x0212 |
| 2047 | #define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO |
| 2048 | |
| 2049 | /* Statistics command register */ |
| 2050 | #define XM_STATCMD_CLR_TX 0x0001 |
| 2051 | #define XM_STATCMD_CLR_RX 0x0002 |
| 2052 | #define XM_STATCMD_COPY_TX 0x0004 |
| 2053 | #define XM_STATCMD_COPY_RX 0x0008 |
| 2054 | #define XM_STATCMD_SNAP_TX 0x0010 |
| 2055 | #define XM_STATCMD_SNAP_RX 0x0020 |
| 2056 | |
| 2057 | /* TX statistics registers */ |
| 2058 | #define XM_TXSTATS_PKTSOK 0x280 |
| 2059 | #define XM_TXSTATS_BYTESOK_HI 0x284 |
| 2060 | #define XM_TXSTATS_BYTESOK_LO 0x288 |
| 2061 | #define XM_TXSTATS_BCASTSOK 0x28C |
| 2062 | #define XM_TXSTATS_MCASTSOK 0x290 |
| 2063 | #define XM_TXSTATS_UCASTSOK 0x294 |
| 2064 | #define XM_TXSTATS_GIANTS 0x298 |
| 2065 | #define XM_TXSTATS_BURSTCNT 0x29C |
| 2066 | #define XM_TXSTATS_PAUSEPKTS 0x2A0 |
| 2067 | #define XM_TXSTATS_MACCTLPKTS 0x2A4 |
| 2068 | #define XM_TXSTATS_SINGLECOLS 0x2A8 |
| 2069 | #define XM_TXSTATS_MULTICOLS 0x2AC |
| 2070 | #define XM_TXSTATS_EXCESSCOLS 0x2B0 |
| 2071 | #define XM_TXSTATS_LATECOLS 0x2B4 |
| 2072 | #define XM_TXSTATS_DEFER 0x2B8 |
| 2073 | #define XM_TXSTATS_EXCESSDEFER 0x2BC |
| 2074 | #define XM_TXSTATS_UNDERRUN 0x2C0 |
| 2075 | #define XM_TXSTATS_CARRIERSENSE 0x2C4 |
| 2076 | #define XM_TXSTATS_UTILIZATION 0x2C8 |
| 2077 | #define XM_TXSTATS_64 0x2D0 |
| 2078 | #define XM_TXSTATS_65_127 0x2D4 |
| 2079 | #define XM_TXSTATS_128_255 0x2D8 |
| 2080 | #define XM_TXSTATS_256_511 0x2DC |
| 2081 | #define XM_TXSTATS_512_1023 0x2E0 |
| 2082 | #define XM_TXSTATS_1024_MAX 0x2E4 |
| 2083 | |
| 2084 | /* RX statistics registers */ |
| 2085 | #define XM_RXSTATS_PKTSOK 0x300 |
| 2086 | #define XM_RXSTATS_BYTESOK_HI 0x304 |
| 2087 | #define XM_RXSTATS_BYTESOK_LO 0x308 |
| 2088 | #define XM_RXSTATS_BCASTSOK 0x30C |
| 2089 | #define XM_RXSTATS_MCASTSOK 0x310 |
| 2090 | #define XM_RXSTATS_UCASTSOK 0x314 |
| 2091 | #define XM_RXSTATS_PAUSEPKTS 0x318 |
| 2092 | #define XM_RXSTATS_MACCTLPKTS 0x31C |
| 2093 | #define XM_RXSTATS_BADPAUSEPKTS 0x320 |
| 2094 | #define XM_RXSTATS_BADMACCTLPKTS 0x324 |
| 2095 | #define XM_RXSTATS_BURSTCNT 0x328 |
| 2096 | #define XM_RXSTATS_MISSEDPKTS 0x32C |
| 2097 | #define XM_RXSTATS_FRAMEERRS 0x330 |
| 2098 | #define XM_RXSTATS_OVERRUN 0x334 |
| 2099 | #define XM_RXSTATS_JABBER 0x338 |
| 2100 | #define XM_RXSTATS_CARRLOSS 0x33C |
| 2101 | #define XM_RXSTATS_INRNGLENERR 0x340 |
| 2102 | #define XM_RXSTATS_SYMERR 0x344 |
| 2103 | #define XM_RXSTATS_SHORTEVENT 0x348 |
| 2104 | #define XM_RXSTATS_RUNTS 0x34C |
| 2105 | #define XM_RXSTATS_GIANTS 0x350 |
| 2106 | #define XM_RXSTATS_CRCERRS 0x354 |
| 2107 | #define XM_RXSTATS_CEXTERRS 0x35C |
| 2108 | #define XM_RXSTATS_UTILIZATION 0x360 |
| 2109 | #define XM_RXSTATS_64 0x368 |
| 2110 | #define XM_RXSTATS_65_127 0x36C |
| 2111 | #define XM_RXSTATS_128_255 0x370 |
| 2112 | #define XM_RXSTATS_256_511 0x374 |
| 2113 | #define XM_RXSTATS_512_1023 0x378 |
| 2114 | #define XM_RXSTATS_1024_MAX 0x37C |
| 2115 | |
| 2116 | #define XM_MMUCMD_TX_ENB 0x0001 |
| 2117 | #define XM_MMUCMD_RX_ENB 0x0002 |
| 2118 | #define XM_MMUCMD_GMIILOOP 0x0004 |
| 2119 | #define XM_MMUCMD_RATECTL 0x0008 |
| 2120 | #define XM_MMUCMD_GMIIFDX 0x0010 |
| 2121 | #define XM_MMUCMD_NO_MGMT_PRMB 0x0020 |
| 2122 | #define XM_MMUCMD_SIMCOL 0x0040 |
| 2123 | #define XM_MMUCMD_FORCETX 0x0080 |
| 2124 | #define XM_MMUCMD_LOOPENB 0x0200 |
| 2125 | #define XM_MMUCMD_IGNPAUSE 0x0400 |
| 2126 | #define XM_MMUCMD_PHYBUSY 0x0800 |
| 2127 | #define XM_MMUCMD_PHYDATARDY 0x1000 |
| 2128 | |
| 2129 | #define XM_TXCMD_AUTOPAD 0x0001 |
| 2130 | #define XM_TXCMD_NOCRC 0x0002 |
| 2131 | #define XM_TXCMD_NOPREAMBLE 0x0004 |
| 2132 | #define XM_TXCMD_NOGIGAMODE 0x0008 |
| 2133 | #define XM_TXCMD_SAMPLELINE 0x0010 |
| 2134 | #define XM_TXCMD_ENCBYPASS 0x0020 |
| 2135 | #define XM_TXCMD_XMITBK2BK 0x0040 |
| 2136 | #define XM_TXCMD_FAIRSHARE 0x0080 |
| 2137 | |
| 2138 | #define XM_RXCMD_DISABLE_CEXT 0x0001 |
| 2139 | #define XM_RXCMD_STRIPPAD 0x0002 |
| 2140 | #define XM_RXCMD_SAMPLELINE 0x0004 |
| 2141 | #define XM_RXCMD_SELFRX 0x0008 |
| 2142 | #define XM_RXCMD_STRIPFCS 0x0010 |
| 2143 | #define XM_RXCMD_TRANSPARENT 0x0020 |
| 2144 | #define XM_RXCMD_IPGCAPTURE 0x0040 |
| 2145 | #define XM_RXCMD_BIGPKTOK 0x0080 |
| 2146 | #define XM_RXCMD_LENERROK 0x0100 |
| 2147 | |
| 2148 | #define XM_GPIO_GP0_SET 0x0001 |
| 2149 | #define XM_GPIO_RESETSTATS 0x0004 |
| 2150 | #define XM_GPIO_RESETMAC 0x0008 |
| 2151 | #define XM_GPIO_FORCEINT 0x0020 |
| 2152 | #define XM_GPIO_ANEGINPROG 0x0040 |
| 2153 | |
| 2154 | #define XM_IMR_RX_EOF 0x0001 |
| 2155 | #define XM_IMR_TX_EOF 0x0002 |
| 2156 | #define XM_IMR_TX_UNDERRUN 0x0004 |
| 2157 | #define XM_IMR_RX_OVERRUN 0x0008 |
| 2158 | #define XM_IMR_TX_STATS_OFLOW 0x0010 |
| 2159 | #define XM_IMR_RX_STATS_OFLOW 0x0020 |
| 2160 | #define XM_IMR_TSTAMP_OFLOW 0x0040 |
| 2161 | #define XM_IMR_AUTONEG_DONE 0x0080 |
| 2162 | #define XM_IMR_NEXTPAGE_RDY 0x0100 |
| 2163 | #define XM_IMR_PAGE_RECEIVED 0x0200 |
| 2164 | #define XM_IMR_LP_REQCFG 0x0400 |
| 2165 | #define XM_IMR_GP0_SET 0x0800 |
| 2166 | #define XM_IMR_FORCEINTR 0x1000 |
| 2167 | #define XM_IMR_TX_ABORT 0x2000 |
| 2168 | #define XM_IMR_LINKEVENT 0x4000 |
| 2169 | |
| 2170 | #define XM_INTRS \ |
| 2171 | (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN)) |
| 2172 | |
| 2173 | #define XM_ISR_RX_EOF 0x0001 |
| 2174 | #define XM_ISR_TX_EOF 0x0002 |
| 2175 | #define XM_ISR_TX_UNDERRUN 0x0004 |
| 2176 | #define XM_ISR_RX_OVERRUN 0x0008 |
| 2177 | #define XM_ISR_TX_STATS_OFLOW 0x0010 |
| 2178 | #define XM_ISR_RX_STATS_OFLOW 0x0020 |
| 2179 | #define XM_ISR_TSTAMP_OFLOW 0x0040 |
| 2180 | #define XM_ISR_AUTONEG_DONE 0x0080 |
| 2181 | #define XM_ISR_NEXTPAGE_RDY 0x0100 |
| 2182 | #define XM_ISR_PAGE_RECEIVED 0x0200 |
| 2183 | #define XM_ISR_LP_REQCFG 0x0400 |
| 2184 | #define XM_ISR_GP0_SET 0x0800 |
| 2185 | #define XM_ISR_FORCEINTR 0x1000 |
| 2186 | #define XM_ISR_TX_ABORT 0x2000 |
| 2187 | #define XM_ISR_LINKEVENT 0x4000 |
| 2188 | |
| 2189 | #define XM_HWCFG_GENEOP 0x0008 |
| 2190 | #define XM_HWCFG_SIGSTATCKH 0x0004 |
| 2191 | #define XM_HWCFG_GMIIMODE 0x0001 |
| 2192 | |
| 2193 | #define XM_MODE_FLUSH_RXFIFO 0x00000001 |
| 2194 | #define XM_MODE_FLUSH_TXFIFO 0x00000002 |
| 2195 | #define XM_MODE_BIGENDIAN 0x00000004 |
| 2196 | #define XM_MODE_RX_PROMISC 0x00000008 |
| 2197 | #define XM_MODE_RX_NOBROAD 0x00000010 |
| 2198 | #define XM_MODE_RX_NOMULTI 0x00000020 |
| 2199 | #define XM_MODE_RX_NOUNI 0x00000040 |
| 2200 | #define XM_MODE_RX_BADFRAMES 0x00000080 |
| 2201 | #define XM_MODE_RX_CRCERRS 0x00000100 |
| 2202 | #define XM_MODE_RX_GIANTS 0x00000200 |
| 2203 | #define XM_MODE_RX_INRANGELEN 0x00000400 |
| 2204 | #define XM_MODE_RX_RUNTS 0x00000800 |
| 2205 | #define XM_MODE_RX_MACCTL 0x00001000 |
| 2206 | #define XM_MODE_RX_USE_PERFECT 0x00002000 |
| 2207 | #define XM_MODE_RX_USE_STATION 0x00004000 |
| 2208 | #define XM_MODE_RX_USE_HASH 0x00008000 |
| 2209 | #define XM_MODE_RX_ADDRPAIR 0x00010000 |
| 2210 | #define XM_MODE_PAUSEONHI 0x00020000 |
| 2211 | #define XM_MODE_PAUSEONLO 0x00040000 |
| 2212 | #define XM_MODE_TIMESTAMP 0x00080000 |
| 2213 | #define XM_MODE_SENDPAUSE 0x00100000 |
| 2214 | #define XM_MODE_SENDCONTINUOUS 0x00200000 |
| 2215 | #define XM_MODE_LE_STATUSWORD 0x00400000 |
| 2216 | #define XM_MODE_AUTOFIFOPAUSE 0x00800000 |
| 2217 | #define XM_MODE_EXPAUSEGEN 0x02000000 |
| 2218 | #define XM_MODE_RX_INVERSE 0x04000000 |
| 2219 | |
| 2220 | #define XM_RXSTAT_MACCTL 0x00000001 |
| 2221 | #define XM_RXSTAT_ERRFRAME 0x00000002 |
| 2222 | #define XM_RXSTAT_CRCERR 0x00000004 |
| 2223 | #define XM_RXSTAT_GIANT 0x00000008 |
| 2224 | #define XM_RXSTAT_RUNT 0x00000010 |
| 2225 | #define XM_RXSTAT_FRAMEERR 0x00000020 |
| 2226 | #define XM_RXSTAT_INRANGEERR 0x00000040 |
| 2227 | #define XM_RXSTAT_CARRIERERR 0x00000080 |
| 2228 | #define XM_RXSTAT_COLLERR 0x00000100 |
| 2229 | #define XM_RXSTAT_802_3 0x00000200 |
| 2230 | #define XM_RXSTAT_CARREXTERR 0x00000400 |
| 2231 | #define XM_RXSTAT_BURSTMODE 0x00000800 |
| 2232 | #define XM_RXSTAT_UNICAST 0x00002000 |
| 2233 | #define XM_RXSTAT_MULTICAST 0x00004000 |
| 2234 | #define XM_RXSTAT_BROADCAST 0x00008000 |
| 2235 | #define XM_RXSTAT_VLAN_LEV1 0x00010000 |
| 2236 | #define XM_RXSTAT_VLAN_LEV2 0x00020000 |
| 2237 | #define XM_RXSTAT_LEN 0xFFFC0000 |
| 2238 | #define XM_RXSTAT_LENSHIFT 18 |
| 2239 | |
| 2240 | #define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT) |
| 2241 | |
| 2242 | /* |
| 2243 | * XMAC PHY registers, indirectly accessed through |
| 2244 | * XM_PHY_ADDR and XM_PHY_REG. |
| 2245 | */ |
| 2246 | |
| 2247 | #define XM_PHY_BMCR 0x0000 /* control */ |
| 2248 | #define XM_PHY_BMSR 0x0001 /* status */ |
| 2249 | #define XM_PHY_VENID 0x0002 /* vendor id */ |
| 2250 | #define XM_PHY_DEVID 0x0003 /* device id */ |
| 2251 | #define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */ |
| 2252 | #define XM_PHY_LPAR 0x0005 /* link partner ability */ |
| 2253 | #define XM_PHY_ANEXP 0x0006 /* autoneg expansion */ |
| 2254 | #define XM_PHY_NEXTP 0x0007 /* nextpage */ |
| 2255 | #define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */ |
| 2256 | #define XM_PHY_EXTSTS 0x000F /* extented status */ |
| 2257 | #define XM_PHY_RESAB 0x0010 /* resolved ability */ |
| 2258 | |
| 2259 | #define XM_BMCR_DUPLEX 0x0100 |
| 2260 | #define XM_BMCR_RENEGOTIATE 0x0200 |
| 2261 | #define XM_BMCR_AUTONEGENBL 0x1000 |
| 2262 | #define XM_BMCR_LOOPBACK 0x4000 |
| 2263 | #define XM_BMCR_RESET 0x8000 |
| 2264 | |
| 2265 | #define XM_BMSR_EXTCAP 0x0001 |
| 2266 | #define XM_BMSR_LINKSTAT 0x0004 |
| 2267 | #define XM_BMSR_AUTONEGABLE 0x0008 |
| 2268 | #define XM_BMSR_REMFAULT 0x0010 |
| 2269 | #define XM_BMSR_AUTONEGDONE 0x0020 |
| 2270 | #define XM_BMSR_EXTSTAT 0x0100 |
| 2271 | |
| 2272 | #define XM_VENID_XAQTI 0xD14C |
| 2273 | #define XM_DEVID_XMAC 0x0002 |
| 2274 | |
| 2275 | #define XM_ANAR_FULLDUPLEX 0x0020 |
| 2276 | #define XM_ANAR_HALFDUPLEX 0x0040 |
| 2277 | #define XM_ANAR_PAUSEBITS 0x0180 |
| 2278 | #define XM_ANAR_REMFAULTBITS 0x1800 |
| 2279 | #define XM_ANAR_ACK 0x4000 |
| 2280 | #define XM_ANAR_NEXTPAGE 0x8000 |
| 2281 | |
| 2282 | #define XM_LPAR_FULLDUPLEX 0x0020 |
| 2283 | #define XM_LPAR_HALFDUPLEX 0x0040 |
| 2284 | #define XM_LPAR_PAUSEBITS 0x0180 |
| 2285 | #define XM_LPAR_REMFAULTBITS 0x1800 |
| 2286 | #define XM_LPAR_ACK 0x4000 |
| 2287 | #define XM_LPAR_NEXTPAGE 0x8000 |
| 2288 | |
| 2289 | #define XM_PAUSE_NOPAUSE 0x0000 |
| 2290 | #define XM_PAUSE_SYMPAUSE 0x0080 |
| 2291 | #define XM_PAUSE_ASYMPAUSE 0x0100 |
| 2292 | #define XM_PAUSE_BOTH 0x0180 |
| 2293 | |
| 2294 | #define XM_REMFAULT_LINKOK 0x0000 |
| 2295 | #define XM_REMFAULT_LINKFAIL 0x0800 |
| 2296 | #define XM_REMFAULT_OFFLINE 0x1000 |
| 2297 | #define XM_REMFAULT_ANEGERR 0x1800 |
| 2298 | |
| 2299 | #define XM_ANEXP_GOTPAGE 0x0002 |
| 2300 | #define XM_ANEXP_NEXTPAGE_SELF 0x0004 |
| 2301 | #define XM_ANEXP_NEXTPAGE_LP 0x0008 |
| 2302 | |
| 2303 | #define XM_NEXTP_MESSAGE 0x07FF |
| 2304 | #define XM_NEXTP_TOGGLE 0x0800 |
| 2305 | #define XM_NEXTP_ACK2 0x1000 |
| 2306 | #define XM_NEXTP_MPAGE 0x2000 |
| 2307 | #define XM_NEXTP_ACK1 0x4000 |
| 2308 | #define XM_NEXTP_NPAGE 0x8000 |
| 2309 | |
| 2310 | #define XM_LPNEXTP_MESSAGE 0x07FF |
| 2311 | #define XM_LPNEXTP_TOGGLE 0x0800 |
| 2312 | #define XM_LPNEXTP_ACK2 0x1000 |
| 2313 | #define XM_LPNEXTP_MPAGE 0x2000 |
| 2314 | #define XM_LPNEXTP_ACK1 0x4000 |
| 2315 | #define XM_LPNEXTP_NPAGE 0x8000 |
| 2316 | |
| 2317 | #define XM_EXTSTS_HALFDUPLEX 0x4000 |
| 2318 | #define XM_EXTSTS_FULLDUPLEX 0x8000 |
| 2319 | |
| 2320 | #define XM_RESAB_PAUSEMISMATCH 0x0008 |
| 2321 | #define XM_RESAB_ABLMISMATCH 0x0010 |
| 2322 | #define XM_RESAB_FDMODESEL 0x0020 |
| 2323 | #define XM_RESAB_HDMODESEL 0x0040 |
| 2324 | #define XM_RESAB_PAUSEBITS 0x0180 |
| 2325 | #endif /* _DEV_PCI_IF_SKREG_H_ */ |
| 2326 | |