| 1 | /* $NetBSD: iophyreg.h,v 1.2 1999/09/16 05:58:18 soren Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 1998, 1999 Soren S. Jorvang. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _DEV_MII_IOPHYREG_H_ |
| 30 | #define _DEV_MII_IOPHYREG_H_ |
| 31 | |
| 32 | /* |
| 33 | * Intel 82553 PHY registers |
| 34 | */ |
| 35 | |
| 36 | #define MII_IOPHY_EXT0 0x10 /* Extended Register 0 */ |
| 37 | #define EXT0_JABDIS 0x8000 /* jabber disabled */ |
| 38 | #define EXT0_LINKDIS 0x4000 /* link integrity disable */ |
| 39 | #define EXT0_TEST4 0x2000 |
| 40 | #define EXT0_TEST3 0x1000 |
| 41 | #define EXT0_TEST2 0x0800 |
| 42 | #define EXT0_TEST1 0x0400 |
| 43 | #define EXT0_TEST0 0x0200 |
| 44 | #define EXT0_FORCE100 0x0100 /* force 100 Mbps operation */ |
| 45 | #define EXT0_REVMASK 0x00e0 /* 82553 chip revision */ |
| 46 | #define EXT0_HSQ 0x0010 |
| 47 | #define EXT0_LSQ 0x0008 |
| 48 | #define EXT0_WAKEUP 0x0004 /* disable auto power-down */ |
| 49 | #define EXT0_SPEED 0x0002 /* current speed 10/100 */ |
| 50 | #define EXT0_DUPLEX 0x0001 /* current duplex setting */ |
| 51 | |
| 52 | #define MII_IOPHY_EXT1 0x14 /* Extended Register 1 */ |
| 53 | #define EXT1_PAIR_SKEW_ERR 0x8000 /* pair skew error */ |
| 54 | #define EXT1_DC_BALANCE_ERR 0x4000 /* DC balance error */ |
| 55 | #define EXT1_INVALID_CODE_ERR 0x2000 /* invalid code error */ |
| 56 | #define EXT1_BAD_CODE_ERR 0x1000 /* bad code error */ |
| 57 | #define EXT1_EOP_ERR 0x0800 /* EOP error */ |
| 58 | #define EXT1_MANCHESTER_ERR 0x0400 /* Manchester code error */ |
| 59 | #define EXT1_CH2_EOF_ERR 0x0200 /* channel 2 EOF detection error */ |
| 60 | #define EXT1_DTE_MODE_SEL 0x0100 /* external DTE mode */ |
| 61 | #define EXT1_LINE_RPTR_MODE_SEL 0x0080 /* line repeater mode */ |
| 62 | #define EXT1_EXT_TEST_MODE_SEL 0x0040 /* external test mode */ |
| 63 | #define EXT1_MII_RPTR_MODE_SEL 0x0020 /* MII repeater mode */ |
| 64 | #define EXT1_CH2_POLARITY_ERR 0x0010 /* channel 2 polarity error */ |
| 65 | #define EXT1_CH3_POLARITY_ERR 0x0008 /* channel 3 polarity error */ |
| 66 | #define EXT1_CH4_POLARITY_ERR 0x0004 /* channel 4 polarity error */ |
| 67 | #define EXT1_CH2_SFD_DETECT_ERR 0x0002 /* channel 2 SFD not found */ |
| 68 | |
| 69 | #define MII_IOPHY_EXT2 0x15 /* Extended Register 2 (C step only) */ |
| 70 | #define EXT2_AUTONEG_SEL 0x8000 /* autonegotiation selected */ |
| 71 | #define EXT2_CH3_SFD_ERR 0x4000 /* channel 3 SFD not found */ |
| 72 | #define EXT2_CH4_SFD_ERR 0x2000 /* channel 4 SFD not found */ |
| 73 | |
| 74 | #endif /* _DEV_MII_IOPHYREG_H_ */ |
| 75 | |