| 1 | /* $NetBSD: twareg.h,v 1.11 2010/11/22 23:02:16 dholland Exp $ */ |
| 2 | /* $wasabi: twareg.h,v 1.14 2006/07/28 18:29:51 wrstuden Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2003-04 3ware, Inc. |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | * |
| 29 | * $FreeBSD: src/sys/dev/twa/twa_reg.h,v 1.2 2004/08/18 16:14:44 vkashyap Exp $ |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * 3ware driver for 9000 series storage controllers. |
| 34 | * |
| 35 | * Author: Vinod Kashyap |
| 36 | */ |
| 37 | |
| 38 | #ifndef _PCI_TWAREG_H_ |
| 39 | #define _PCI_TWAREG_H_ |
| 40 | |
| 41 | #if defined(_KERNEL) |
| 42 | #include <sys/bus.h> |
| 43 | |
| 44 | /* |
| 45 | * The following macro has no business being in twa_reg.h. It should probably |
| 46 | * be defined in twa_includes.h, before the #include twa_reg.h.... But that |
| 47 | * causes the API to run into build errors. Will leave it here for now... |
| 48 | */ |
| 49 | #define TWA_64BIT_ADDRESSES ((sizeof(bus_addr_t) == 8) ? 1 : 0) |
| 50 | |
| 51 | /* |
| 52 | * Define the following here since it relies on TWA_64BIT_ADDRESSES which |
| 53 | * depends on sizeof(bus_addr_t), which is not exported to userland. |
| 54 | * The userland API shouldn't care about the kernel's bus_addr_t. |
| 55 | * For the userland API, use the array size that we would use for 32-bit |
| 56 | * addresses since that's what we use in the sg structure definition. |
| 57 | * The userland API does not actually appear to use the array, but it |
| 58 | * does include the array in various command structures. |
| 59 | */ |
| 60 | #define TWA_MAX_SG_ELEMENTS (TWA_64BIT_ADDRESSES ? 70 : 105) |
| 61 | #else |
| 62 | #define TWA_MAX_SG_ELEMENTS 105 |
| 63 | #endif |
| 64 | |
| 65 | #define TWAQ_FREE 0 |
| 66 | #define TWAQ_BUSY 1 |
| 67 | #define TWAQ_PENDING 2 |
| 68 | #define TWAQ_COMPLETE 3 |
| 69 | #define TWAQ_IO_PENDING 4 |
| 70 | #define TWAQ_COUNT 5 /* total number of queues */ |
| 71 | |
| 72 | #define TWA_DRIVER_VERSION_STRING "1.00.00.000" |
| 73 | |
| 74 | #define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ |
| 75 | |
| 76 | #define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3 |
| 77 | |
| 78 | /* Register offsets from base address. */ |
| 79 | #define TWA_CONTROL_REGISTER_OFFSET 0x0 |
| 80 | #define TWA_STATUS_REGISTER_OFFSET 0x4 |
| 81 | #define TWA_COMMAND_QUEUE_OFFSET 0x8 |
| 82 | #define TWA_RESPONSE_QUEUE_OFFSET 0xC |
| 83 | #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 |
| 84 | #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 |
| 85 | #define TWA_RESPONSE_QUEUE_LARGE_OFFSET 0x30 |
| 86 | |
| 87 | #if defined(_KERNEL) |
| 88 | #define TWA_WRITE_REGISTER(sc, offset, val) \ |
| 89 | bus_space_write_4(sc->twa_bus_iot, sc->twa_bus_ioh, offset, (uint32_t)val) |
| 90 | |
| 91 | #define TWA_WRITE_COMMAND_QUEUE(sc, val) \ |
| 92 | do { \ |
| 93 | if (TWA_64BIT_ADDRESSES) { \ |
| 94 | /* First write the low 4 bytes, then the high 4. */ \ |
| 95 | TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \ |
| 96 | (uint32_t)(val)); \ |
| 97 | TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ |
| 98 | (uint32_t)(((uint64_t)val)>>32)); \ |
| 99 | } else \ |
| 100 | TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\ |
| 101 | (uint32_t)(val)); \ |
| 102 | } while (0) |
| 103 | #endif |
| 104 | |
| 105 | #define TWA_WRITE_COMMAND_QUEUE_HIGH(sc, val) \ |
| 106 | do { \ |
| 107 | TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH, \ |
| 108 | (uint32_t)(((uint64_t)val)>>32)); \ |
| 109 | } while (0) |
| 110 | |
| 111 | #define TWA_WRITE_COMMAND_QUEUE_LOW(sc, val) \ |
| 112 | do { \ |
| 113 | TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \ |
| 114 | (uint32_t)(val)); \ |
| 115 | } while (0) |
| 116 | |
| 117 | /* Control register bit definitions. */ |
| 118 | #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 |
| 119 | #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 |
| 120 | #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 |
| 121 | #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 |
| 122 | #define TWA_CONTROL_CLEAR_ERROR_STATUS 0x00000200 |
| 123 | #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 |
| 124 | #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 |
| 125 | #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 |
| 126 | #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 |
| 127 | #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 |
| 128 | #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 |
| 129 | #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 |
| 130 | #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 |
| 131 | #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 |
| 132 | |
| 133 | /* Status register bit definitions. */ |
| 134 | #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 |
| 135 | #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 |
| 136 | #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 |
| 137 | #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 |
| 138 | #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 |
| 139 | #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 |
| 140 | #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 |
| 141 | #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 |
| 142 | #define TWA_STATUS_HOST_INTERRUPT 0x00080000 |
| 143 | #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 |
| 144 | #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 |
| 145 | #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 |
| 146 | #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 |
| 147 | #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 |
| 148 | #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 |
| 149 | |
| 150 | #define TWA_STATUS_EXPECTED_BITS 0x00002000 |
| 151 | #define TWA_STATUS_UNEXPECTED_BITS 0x00F00000 |
| 152 | |
| 153 | /* For use with the %b printf format. */ |
| 154 | #define TWA_STATUS_BITS_DESCRIPTION \ |
| 155 | "\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n" |
| 156 | |
| 157 | /* Detect inconsistencies in the status register. */ |
| 158 | #define TWA_STATUS_ERRORS(x) \ |
| 159 | ((x & TWA_STATUS_UNEXPECTED_BITS) && \ |
| 160 | (x & TWA_STATUS_MICROCONTROLLER_READY)) |
| 161 | |
| 162 | /* PCI related defines. */ |
| 163 | #define TWA_IO_CONFIG_REG 0x10 |
| 164 | #define TWA_DEVICE_NAME "3ware 9000 series Storage Controller" |
| 165 | #define TWA_VENDOR_ID 0x13C1 |
| 166 | #define TWA_DEVICE_ID_9K 0x1002 |
| 167 | |
| 168 | #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 |
| 169 | #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 |
| 170 | #define TWA_9550SX_DRAIN_COMPLETE 0xffff |
| 171 | |
| 172 | /* Command packet opcodes. */ |
| 173 | #define TWA_OP_NOP 0x00 |
| 174 | #define TWA_OP_INIT_CONNECTION 0x01 |
| 175 | #define TWA_OP_READ 0x02 |
| 176 | #define TWA_OP_WRITE 0x03 |
| 177 | #define TWA_OP_READVERIFY 0x04 |
| 178 | #define TWA_OP_VERIFY 0x05 |
| 179 | #define TWA_OP_ZEROUNIT 0x08 |
| 180 | #define TWA_OP_REPLACEUNIT 0x09 |
| 181 | #define TWA_OP_HOTSWAP 0x0A |
| 182 | #define TWA_OP_SELFTESTS 0x0B |
| 183 | #define TWA_OP_SYNC_PARAM 0x0C |
| 184 | #define TWA_OP_REORDER_UNITS 0x0D |
| 185 | #define TWA_OP_FLUSH 0x0E |
| 186 | #define TWA_OP_EXECUTE_SCSI_COMMAND 0x10 |
| 187 | #define TWA_OP_ATA_PASSTHROUGH 0x11 |
| 188 | #define TWA_OP_GET_PARAM 0x12 |
| 189 | #define TWA_OP_SET_PARAM 0x13 |
| 190 | #define TWA_OP_CREATEUNIT 0x14 |
| 191 | #define TWA_OP_DELETEUNIT 0x15 |
| 192 | #define TWA_OP_DOWNLOAD_FIRMWARE 0x16 |
| 193 | #define TWA_OP_REBUILDUNIT 0x17 |
| 194 | #define TWA_OP_POWER_MANAGEMENT 0x18 |
| 195 | |
| 196 | #define TWA_OP_REMOTE_PRINT 0x1B |
| 197 | #define TWA_OP_RESET_FIRMWARE 0x1C |
| 198 | #define TWA_OP_DEBUG 0x1D |
| 199 | |
| 200 | #define TWA_OP_DIAGNOSTICS 0x1F |
| 201 | |
| 202 | /* Misc defines. */ |
| 203 | #define TWA_ALIGNMENT 0x4 |
| 204 | #define TWA_MAX_UNITS 16 |
| 205 | #define TWA_9650_MAX_UNITS 32 |
| 206 | #define TWA_9690_MAX_UNITS 32 |
| 207 | #define TWA_INIT_MESSAGE_CREDITS 0x100 |
| 208 | #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 |
| 209 | #define TWA_64BIT_SG_ADDRESSES 0x00000001 |
| 210 | #define TWA_EXTENDED_INIT_CONNECT 0x00000002 |
| 211 | #define TWA_BASE_MODE 1 |
| 212 | #define TWA_BASE_FW_SRL 24 |
| 213 | #define TWA_BASE_FW_BRANCH 0 |
| 214 | #define TWA_BASE_FW_BUILD 1 |
| 215 | #define TWA_CURRENT_FW_SRL 28 |
| 216 | #define TWA_CURRENT_FW_BRANCH 4 |
| 217 | #define TWA_CURRENT_FW_BUILD 9 |
| 218 | #define TWA_9000_ARCH_ID 0x5 /* 9000 series controllers */ |
| 219 | #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 |
| 220 | #define TWA_CTLR_FW_COMPATIBLE 0x00000002 |
| 221 | #define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004 |
| 222 | #define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008 |
| 223 | #define NUM_FW_IMAGE_CHUNKS 5 |
| 224 | #define TWA_MAX_IO_SIZE 0x20000 /* 128K */ |
| 225 | /* #define TWA_MAX_SG_ELEMENTS defined above */ |
| 226 | #define TWA_MAX_ATA_SG_ELEMENTS 60 |
| 227 | #define TWA_Q_LENGTH TWA_INIT_MESSAGE_CREDITS |
| 228 | #define TWA_MAX_RESET_TRIES 3 |
| 229 | #define TWA_SECTOR_SIZE 0x200 /* generic I/O bufffer */ |
| 230 | #define TWA_SENSE_DATA_LENGTH 18 |
| 231 | #define TWA_MICROSECOND 1000000 |
| 232 | #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a |
| 233 | #define TWA_ERROR_UNIT_OFFLINE 0x0128 |
| 234 | #define TWA_ERROR_MORE_DATA 0x0231 |
| 235 | |
| 236 | /* Scatter/Gather list entry. */ |
| 237 | struct twa_sg { |
| 238 | #if defined(_KERNEL) |
| 239 | bus_addr_t address; |
| 240 | #else |
| 241 | uint32_t xx_address_xx; /* Fail if userland tries to use this */ |
| 242 | #endif |
| 243 | uint32_t length; |
| 244 | } __packed; |
| 245 | |
| 246 | |
| 247 | /* 7000 structures. */ |
| 248 | struct twa_command_init_connect { |
| 249 | uint8_t opcode:5; /* TWA_OP_INITCONNECTION */ |
| 250 | uint8_t res1:3; |
| 251 | uint8_t size; |
| 252 | uint8_t request_id; |
| 253 | uint8_t res2; |
| 254 | uint8_t status; |
| 255 | uint8_t flags; |
| 256 | uint16_t message_credits; |
| 257 | uint32_t features; |
| 258 | uint16_t fw_srl; |
| 259 | uint16_t fw_arch_id; |
| 260 | uint16_t fw_branch; |
| 261 | uint16_t fw_build; |
| 262 | uint32_t result; |
| 263 | }__packed; |
| 264 | |
| 265 | struct twa_command_download_firmware { |
| 266 | uint8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */ |
| 267 | uint8_t sgl_offset:3; |
| 268 | uint8_t size; |
| 269 | uint8_t request_id; |
| 270 | uint8_t unit; |
| 271 | uint8_t status; |
| 272 | uint8_t flags; |
| 273 | uint16_t param; |
| 274 | uint8_t sgl[1]; |
| 275 | } __packed; |
| 276 | |
| 277 | |
| 278 | struct twa_command_reset_firmware { |
| 279 | uint8_t opcode:5; /* TWA_OP_RESET_FIRMWARE */ |
| 280 | uint8_t res1:3; |
| 281 | uint8_t size; |
| 282 | uint8_t request_id; |
| 283 | uint8_t unit; |
| 284 | uint8_t status; |
| 285 | uint8_t flags; |
| 286 | uint8_t res2; |
| 287 | uint8_t param; |
| 288 | } __packed; |
| 289 | |
| 290 | |
| 291 | struct twa_command_io { |
| 292 | uint8_t opcode:5; /* TWA_OP_READ/TWA_OP_WRITE */ |
| 293 | uint8_t sgl_offset:3; |
| 294 | uint8_t size; |
| 295 | uint8_t request_id; |
| 296 | uint8_t unit:4; |
| 297 | uint8_t host_id:4; |
| 298 | uint8_t status; |
| 299 | uint8_t flags; |
| 300 | uint16_t block_count; |
| 301 | uint32_t lba; |
| 302 | struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; |
| 303 | } __packed; |
| 304 | |
| 305 | |
| 306 | struct twa_command_hotswap { |
| 307 | uint8_t opcode:5; /* TWA_OP_HOTSWAP */ |
| 308 | uint8_t res1:3; |
| 309 | uint8_t size; |
| 310 | uint8_t request_id; |
| 311 | uint8_t unit:4; |
| 312 | uint8_t host_id:4; |
| 313 | uint8_t status; |
| 314 | uint8_t flags; |
| 315 | uint8_t action; |
| 316 | #define TWA_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */ |
| 317 | #define TWA_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */ |
| 318 | #define TWA_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */ |
| 319 | uint8_t aport; |
| 320 | } __packed; |
| 321 | |
| 322 | |
| 323 | struct twa_command_param { |
| 324 | uint8_t opcode:5; /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */ |
| 325 | uint8_t sgl_offset:3; |
| 326 | uint8_t size; |
| 327 | uint8_t request_id; |
| 328 | uint8_t unit:4; |
| 329 | uint8_t host_id:4; |
| 330 | uint8_t status; |
| 331 | uint8_t flags; |
| 332 | uint16_t param_count; |
| 333 | uint8_t sgl[1]; |
| 334 | } __packed; |
| 335 | |
| 336 | |
| 337 | struct twa_command_rebuildunit { |
| 338 | uint8_t opcode:5; /* TWA_OP_REBUILDUNIT */ |
| 339 | uint8_t res1:3; |
| 340 | uint8_t size; |
| 341 | uint8_t request_id; |
| 342 | uint8_t src_unit:4; |
| 343 | uint8_t host_id:4; |
| 344 | uint8_t status; |
| 345 | uint8_t flags; |
| 346 | uint8_t action:7; |
| 347 | #define TWA_OP_REBUILDUNIT_NOP 0 |
| 348 | #define TWA_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */ |
| 349 | #define TWA_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */ |
| 350 | #define TWA_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */ |
| 351 | uint8_t cs:1; /* request state change on src_unit */ |
| 352 | uint8_t logical_subunit; /* for RAID10 rebuild of logical subunit */ |
| 353 | } __packed; |
| 354 | |
| 355 | |
| 356 | struct twa_command_ata { |
| 357 | uint8_t opcode:5; /* TWA_OP_ATA_PASSTHROUGH */ |
| 358 | uint8_t sgl_offset:3; |
| 359 | uint8_t size; |
| 360 | uint8_t request_id; |
| 361 | uint8_t unit:4; |
| 362 | uint8_t host_id:4; |
| 363 | uint8_t status; |
| 364 | uint8_t flags; |
| 365 | uint16_t param; |
| 366 | uint16_t features; |
| 367 | uint16_t sector_count; |
| 368 | uint16_t sector_num; |
| 369 | uint16_t cylinder_lo; |
| 370 | uint16_t cylinder_hi; |
| 371 | uint8_t drive_head; |
| 372 | uint8_t command; |
| 373 | struct twa_sg sgl[TWA_MAX_ATA_SG_ELEMENTS]; |
| 374 | } __packed; |
| 375 | |
| 376 | |
| 377 | struct twa_command_generic { |
| 378 | uint8_t opcode:5; |
| 379 | uint8_t sgl_offset:3; |
| 380 | uint8_t size; |
| 381 | uint8_t request_id; |
| 382 | uint8_t unit:4; |
| 383 | uint8_t host_id:4; |
| 384 | uint8_t status; |
| 385 | uint8_t flags; |
| 386 | #define TWA_FLAGS_SUCCESS 0x00 |
| 387 | #define TWA_FLAGS_INFORMATIONAL 0x01 |
| 388 | #define TWA_FLAGS_WARNING 0x02 |
| 389 | #define TWA_FLAGS_FATAL 0x03 |
| 390 | #define TWA_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ |
| 391 | uint16_t count; /* block count, parameter count, message credits */ |
| 392 | } __packed; |
| 393 | |
| 394 | /* Command packet header. */ |
| 395 | #pragma pack(1) |
| 396 | struct twa_command_header { |
| 397 | uint8_t sense_data[TWA_SENSE_DATA_LENGTH]; |
| 398 | struct { |
| 399 | int8_t reserved[4]; |
| 400 | uint16_t error; |
| 401 | uint8_t padding; |
| 402 | struct { |
| 403 | uint8_t severity:3; |
| 404 | uint8_t reserved:5; |
| 405 | } substatus_block; |
| 406 | } status_block; |
| 407 | uint8_t err_specific_desc[98]; |
| 408 | struct { |
| 409 | uint8_t size_header; |
| 410 | uint16_t reserved; |
| 411 | uint8_t size_sense; |
| 412 | } header_desc; |
| 413 | } __packed; |
| 414 | #pragma pack() |
| 415 | |
| 416 | |
| 417 | /* Command packet - must be TWA_ALIGNMENT aligned. */ |
| 418 | union twa_command_7k { |
| 419 | struct twa_command_init_connect init_connect; |
| 420 | struct twa_command_download_firmware download_fw; |
| 421 | struct twa_command_reset_firmware reset_fw; |
| 422 | struct twa_command_param param; |
| 423 | struct twa_command_generic generic; |
| 424 | uint8_t padding[1024 - sizeof(struct twa_command_header)]; |
| 425 | } __packed; |
| 426 | |
| 427 | |
| 428 | /* 9000 structures. */ |
| 429 | |
| 430 | /* Command Packet. */ |
| 431 | struct twa_command_9k { |
| 432 | struct { |
| 433 | uint8_t opcode:5; |
| 434 | uint8_t reserved:3; |
| 435 | } command; |
| 436 | uint8_t unit; |
| 437 | uint16_t request_id; |
| 438 | uint8_t status; |
| 439 | uint8_t sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */ |
| 440 | uint16_t sgl_entries; |
| 441 | uint8_t cdb[16]; |
| 442 | struct twa_sg sg_list[TWA_MAX_SG_ELEMENTS]; |
| 443 | uint8_t padding[32]; |
| 444 | } __packed; |
| 445 | |
| 446 | |
| 447 | |
| 448 | /* Full command packet. */ |
| 449 | struct twa_command_packet { |
| 450 | struct twa_command_header cmd_hdr; |
| 451 | union { |
| 452 | union twa_command_7k cmd_pkt_7k; |
| 453 | struct twa_command_9k cmd_pkt_9k; |
| 454 | } command; |
| 455 | } __packed; |
| 456 | |
| 457 | |
| 458 | /* Response queue entry. */ |
| 459 | union twa_response_queue { |
| 460 | struct { |
| 461 | uint32_t undefined_1:4; |
| 462 | uint32_t response_id:8; |
| 463 | uint32_t undefined_2:20; |
| 464 | } u; |
| 465 | uint32_t value; |
| 466 | } __packed; |
| 467 | |
| 468 | |
| 469 | #define TWA_AEN_QUEUE_EMPTY 0x00 |
| 470 | #define TWA_AEN_SOFT_RESET 0x01 |
| 471 | #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 |
| 472 | #define TWA_AEN_SEVERITY_ERROR 0x1 |
| 473 | #define TWA_AEN_SEVERITY_WARNING 0x2 |
| 474 | #define TWA_AEN_SEVERITY_INFO 0x3 |
| 475 | #define TWA_AEN_SEVERITY_DEBUG 0x4 |
| 476 | |
| 477 | #define TWA_PARAM_DRIVESUMMARY 0x0002 |
| 478 | #define TWA_PARAM_DRIVESTATUS 3 |
| 479 | |
| 480 | #define TWA_DRIVE_DETECTED 0x80 |
| 481 | |
| 482 | #define TWA_PARAM_DRIVE_TABLE 0x0200 |
| 483 | #define TWA_PARAM_DRIVESIZEINDEX 2 |
| 484 | #define TWA_PARAM_DRIVEMODELINDEX 3 |
| 485 | |
| 486 | #define TWA_PARAM_DRIVESIZE_LENGTH 4 |
| 487 | #define TWA_PARAM_DRIVEMODEL_LENGTH 40 |
| 488 | |
| 489 | |
| 490 | #define TWA_PARAM_VERSION 0x0402 |
| 491 | #define TWA_PARAM_VERSION_Mon 2 /* monitor version [16] */ |
| 492 | #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ |
| 493 | #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ |
| 494 | #define TWA_PARAM_VERSION_PCBA 5 /* PCB version [8] */ |
| 495 | #define TWA_PARAM_VERSION_ATA 6 /* A-chip version [8] */ |
| 496 | #define TWA_PARAM_VERSION_PCI 7 /* P-chip version [8] */ |
| 497 | |
| 498 | #define TWA_PARAM_CONTROLLER 0x0403 |
| 499 | #define TWA_PARAM_CONTROLLER_PortCount 3 /* number of ports [1] */ |
| 500 | |
| 501 | #define TWA_PARAM_TIME_TABLE 0x40A |
| 502 | #define TWA_PARAM_TIME_SchedulerTime 0x3 |
| 503 | |
| 504 | #define TWA_9K_PARAM_DESCRIPTOR 0x8000 |
| 505 | |
| 506 | |
| 507 | struct twa_param_9k { |
| 508 | uint16_t table_id; |
| 509 | uint8_t parameter_id; |
| 510 | uint8_t reserved; |
| 511 | uint16_t parameter_size_bytes; |
| 512 | uint16_t parameter_actual_size_bytes; |
| 513 | uint8_t data[1]; |
| 514 | } __packed; |
| 515 | |
| 516 | #endif /* !_PCI_TWAREG_H_ */ |
| 517 | |