| 1 | /* $NetBSD: ninjaata32reg.h,v 1.4 2011/02/21 02:32:00 itohy Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2006 ITOH Yasufumi. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 18 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 26 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _NJATA32REG_H_ |
| 30 | #define _NJATA32REG_H_ |
| 31 | |
| 32 | /* |
| 33 | * Workbit NinjaATA (32bit versions), IDE Controller with Busmastering PIO: |
| 34 | * NinjaATA-32Bi PCMCIA/CardBus dual mode device ("DuoATA") |
| 35 | * (CardBus mode only) |
| 36 | * NPATA-32 CardBus device |
| 37 | */ |
| 38 | |
| 39 | /* |
| 40 | * CAVEAT |
| 41 | * The names and the functions of the registers are probably incorrect |
| 42 | * since no programming information is available in the public. |
| 43 | */ |
| 44 | |
| 45 | #define NJATA32_REGSIZE 32 /* size of register set */ |
| 46 | #define NJATA32_MEMOFFSET_REG 0x860 /* offset of memory mapped register */ |
| 47 | |
| 48 | #define NJATA32_REG_IRQ_STAT 0x00 /* len=1 RO */ |
| 49 | #define NJATA32_REG_IRQ_SELECT 0x01 /* len=1 WO */ |
| 50 | # define NJATA32_IRQ_XFER 0x01 |
| 51 | # define NJATA32_IRQ_DEV 0x04 |
| 52 | |
| 53 | #define NJATA32_REG_IOBM 0x02 /* len=1 WO */ |
| 54 | # define NJATA32_IOBM_01 0x01 |
| 55 | # define NJATA32_IOBM_02 0x02 |
| 56 | # define NJATA32_IOBM_MMENBL 0x08 |
| 57 | # define NJATA32_IOBM_BURST 0x10 |
| 58 | # define NJATA32_IOBM_NO_BMSTART0 0x20 |
| 59 | # define NJATA32_IOBM_80 0x80 |
| 60 | |
| 61 | # define NJATA32_IOBM_DEFAULT (NJATA32_IOBM_01 | NJATA32_IOBM_02 | \ |
| 62 | NJATA32_IOBM_BURST | NJATA32_IOBM_NO_BMSTART0 | NJATA32_IOBM_80) |
| 63 | |
| 64 | #define NJATA32_REG_AS 0x04 /* len=1 WO */ |
| 65 | # define NJATA32_AS_START 0x01 /* 0: PIO BM, 1: DMA BM */ |
| 66 | # define NJATA32_AS_WAIT0 0x00 |
| 67 | # define NJATA32_AS_WAIT1 0x04 |
| 68 | # define NJATA32_AS_WAIT2 0x08 |
| 69 | # define NJATA32_AS_WAIT3 0x0c |
| 70 | # define NJATA32_AS_BUS_RESET 0x80 |
| 71 | |
| 72 | #define NJATA32_REG_DMAADDR 0x08 /* len=4 R/W */ |
| 73 | #define NJATA32_REG_DMALENGTH 0x0c /* len=4 R/W */ |
| 74 | |
| 75 | /* |
| 76 | * WDC registers |
| 77 | */ |
| 78 | #define NJATA32_OFFSET_WDCREGS 0x10 |
| 79 | |
| 80 | #define NJATA32_REG_WD_DATA 0x10 /* len=1/2/4 R/W */ |
| 81 | #define NJATA32_REG_WD_ERROR 0x11 /* len=1 RO */ |
| 82 | #define NJATA32_REG_WD_FEATURES 0x11 /* len=1 WO */ |
| 83 | #define NJATA32_REG_WD_SECCNT 0x12 /* len=1 R/W */ |
| 84 | #define NJATA32_REG_WD_IREASON 0x12 /* len=1 R/W (ATAPI) */ |
| 85 | #define NJATA32_REG_WD_SECTOR 0x13 /* len=1 R/W */ |
| 86 | #define NJATA32_REG_WD_LBA_LO 0x13 /* len=1 R/W */ |
| 87 | #define NJATA32_REG_WD_CYL_LO 0x14 /* len=1 R/W */ |
| 88 | #define NJATA32_REG_WD_LBA_MI 0x14 /* len=1 R/W */ |
| 89 | #define NJATA32_REG_WD_CYL_HI 0x15 /* len=1 R/W */ |
| 90 | #define NJATA32_REG_WD_LBA_HI 0x15 /* len=1 R/W */ |
| 91 | #define NJATA32_REG_WD_SDH 0x16 /* len=1 R/W */ |
| 92 | #define NJATA32_REG_WD_COMMAND 0x17 /* len=1 WO */ |
| 93 | #define NJATA32_REG_WD_STATUS 0x17 /* len=1 RO */ |
| 94 | |
| 95 | #if 0 /* these registers seem to show the busmaster status */ |
| 96 | /* ? */ |
| 97 | #define NJATA32_REG_18 0x18 /* len=4 RO */ |
| 98 | /* ? */ |
| 99 | #define NJATA32_REG_1c 0x1c /* len=1 RO */ |
| 100 | #endif |
| 101 | |
| 102 | #define NJATA32_REG_BM 0x1d /* len=1 R/W */ |
| 103 | # define NJATA32_BM_EN 0x01 |
| 104 | # define NJATA32_BM_RD 0x02 /* 0: write, 1: read */ |
| 105 | # define NJATA32_BM_SG 0x04 /* 1: use scatter/gather tbl */ |
| 106 | # define NJATA32_BM_GO 0x08 |
| 107 | # define NJATA32_BM_WAIT0 0x00 |
| 108 | # define NJATA32_BM_WAIT1 0x10 |
| 109 | # define NJATA32_BM_WAIT2 0x20 |
| 110 | # define NJATA32_BM_WAIT3 0x30 |
| 111 | # define NJATA32_BM_WAIT_MASK 0x30 |
| 112 | # define NJATA32_BM_WAIT_SHIFT 4 |
| 113 | # define NJATA32_BM_DONE 0x80 /* ? */ |
| 114 | |
| 115 | #define NJATA32_REG_WD_ALTSTATUS 0x1e /* len=1 R */ |
| 116 | |
| 117 | #define NJATA32_REG_TIMING 0x1f /* len=1 W */ |
| 118 | /* timing values for PIO transfer */ |
| 119 | # define NJATA32_TIMING_PIO0 0xd6 |
| 120 | # define NJATA32_TIMING_PIO1 0x85 |
| 121 | # define NJATA32_TIMING_PIO2 0x44 |
| 122 | # define NJATA32_TIMING_PIO3 0x33 |
| 123 | # define NJATA32_TIMING_PIO4 0x13 |
| 124 | # define NJATA32_TIMING_PIO4_ 0x14 /* for timing tweak */ |
| 125 | # define NJATA32_TIMING_PIO4__ 0x24 /* for timing tweak */ |
| 126 | /* timing values for multiword DMA transfer */ |
| 127 | # define NJATA32_TIMING_DMA0 0x88 |
| 128 | # define NJATA32_TIMING_DMA1 0x23 |
| 129 | # define NJATA32_TIMING_DMA2 0x13 |
| 130 | /* timing values for obsolete singleword DMA transfer */ |
| 131 | # define NJATA32_TIMING_SMDMA0 0xff |
| 132 | # define NJATA32_TIMING_SMDMA1 0x88 |
| 133 | # define NJATA32_TIMING_SMDMA2 0x44 |
| 134 | |
| 135 | /* |
| 136 | * DMA data structure |
| 137 | */ |
| 138 | |
| 139 | /* scatter/gather transfer table entry (8 bytes) */ |
| 140 | struct njata32_sgtable { |
| 141 | uint32_t sg_addr; /* transfer address (little endian) */ |
| 142 | uint32_t sg_len; /* transfer length (little endian) */ |
| 143 | #define NJATA32_SGT_ENDMARK 0x80000000 |
| 144 | #define NJATA32_SGT_MAXSEGLEN 0x10000 |
| 145 | }; |
| 146 | #define NJATA32_SGT_MAXENTRY 18 |
| 147 | |
| 148 | /* |
| 149 | * device specific constants |
| 150 | */ |
| 151 | #define NJATA32_MODE_MAX_DMA 2 |
| 152 | #define NJATA32_MODE_MAX_PIO 4 |
| 153 | |
| 154 | #endif /* _NJATA32REG_H_ */ |
| 155 | |