| 1 | /* $NetBSD: nouveau_engine_disp_nve0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2012 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_nve0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
| 29 | |
| 30 | #include <engine/software.h> |
| 31 | #include <engine/disp.h> |
| 32 | |
| 33 | #include <core/class.h> |
| 34 | |
| 35 | #include "nv50.h" |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * EVO master channel object |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | static const struct nv50_disp_mthd_list |
| 42 | nve0_disp_mast_mthd_head = { |
| 43 | .mthd = 0x0300, |
| 44 | .addr = 0x000300, |
| 45 | .data = { |
| 46 | { 0x0400, 0x660400 }, |
| 47 | { 0x0404, 0x660404 }, |
| 48 | { 0x0408, 0x660408 }, |
| 49 | { 0x040c, 0x66040c }, |
| 50 | { 0x0410, 0x660410 }, |
| 51 | { 0x0414, 0x660414 }, |
| 52 | { 0x0418, 0x660418 }, |
| 53 | { 0x041c, 0x66041c }, |
| 54 | { 0x0420, 0x660420 }, |
| 55 | { 0x0424, 0x660424 }, |
| 56 | { 0x0428, 0x660428 }, |
| 57 | { 0x042c, 0x66042c }, |
| 58 | { 0x0430, 0x660430 }, |
| 59 | { 0x0434, 0x660434 }, |
| 60 | { 0x0438, 0x660438 }, |
| 61 | { 0x0440, 0x660440 }, |
| 62 | { 0x0444, 0x660444 }, |
| 63 | { 0x0448, 0x660448 }, |
| 64 | { 0x044c, 0x66044c }, |
| 65 | { 0x0450, 0x660450 }, |
| 66 | { 0x0454, 0x660454 }, |
| 67 | { 0x0458, 0x660458 }, |
| 68 | { 0x045c, 0x66045c }, |
| 69 | { 0x0460, 0x660460 }, |
| 70 | { 0x0468, 0x660468 }, |
| 71 | { 0x046c, 0x66046c }, |
| 72 | { 0x0470, 0x660470 }, |
| 73 | { 0x0474, 0x660474 }, |
| 74 | { 0x047c, 0x66047c }, |
| 75 | { 0x0480, 0x660480 }, |
| 76 | { 0x0484, 0x660484 }, |
| 77 | { 0x0488, 0x660488 }, |
| 78 | { 0x048c, 0x66048c }, |
| 79 | { 0x0490, 0x660490 }, |
| 80 | { 0x0494, 0x660494 }, |
| 81 | { 0x0498, 0x660498 }, |
| 82 | { 0x04a0, 0x6604a0 }, |
| 83 | { 0x04b0, 0x6604b0 }, |
| 84 | { 0x04b8, 0x6604b8 }, |
| 85 | { 0x04bc, 0x6604bc }, |
| 86 | { 0x04c0, 0x6604c0 }, |
| 87 | { 0x04c4, 0x6604c4 }, |
| 88 | { 0x04c8, 0x6604c8 }, |
| 89 | { 0x04d0, 0x6604d0 }, |
| 90 | { 0x04d4, 0x6604d4 }, |
| 91 | { 0x04e0, 0x6604e0 }, |
| 92 | { 0x04e4, 0x6604e4 }, |
| 93 | { 0x04e8, 0x6604e8 }, |
| 94 | { 0x04ec, 0x6604ec }, |
| 95 | { 0x04f0, 0x6604f0 }, |
| 96 | { 0x04f4, 0x6604f4 }, |
| 97 | { 0x04f8, 0x6604f8 }, |
| 98 | { 0x04fc, 0x6604fc }, |
| 99 | { 0x0500, 0x660500 }, |
| 100 | { 0x0504, 0x660504 }, |
| 101 | { 0x0508, 0x660508 }, |
| 102 | { 0x050c, 0x66050c }, |
| 103 | { 0x0510, 0x660510 }, |
| 104 | { 0x0514, 0x660514 }, |
| 105 | { 0x0518, 0x660518 }, |
| 106 | { 0x051c, 0x66051c }, |
| 107 | { 0x0520, 0x660520 }, |
| 108 | { 0x0524, 0x660524 }, |
| 109 | { 0x052c, 0x66052c }, |
| 110 | { 0x0530, 0x660530 }, |
| 111 | { 0x054c, 0x66054c }, |
| 112 | { 0x0550, 0x660550 }, |
| 113 | { 0x0554, 0x660554 }, |
| 114 | { 0x0558, 0x660558 }, |
| 115 | { 0x055c, 0x66055c }, |
| 116 | {} |
| 117 | } |
| 118 | }; |
| 119 | |
| 120 | const struct nv50_disp_mthd_chan |
| 121 | nve0_disp_mast_mthd_chan = { |
| 122 | .name = "Core" , |
| 123 | .addr = 0x000000, |
| 124 | .data = { |
| 125 | { "Global" , 1, &nvd0_disp_mast_mthd_base }, |
| 126 | { "DAC" , 3, &nvd0_disp_mast_mthd_dac }, |
| 127 | { "SOR" , 8, &nvd0_disp_mast_mthd_sor }, |
| 128 | { "PIOR" , 4, &nvd0_disp_mast_mthd_pior }, |
| 129 | { "HEAD" , 4, &nve0_disp_mast_mthd_head }, |
| 130 | {} |
| 131 | } |
| 132 | }; |
| 133 | |
| 134 | /******************************************************************************* |
| 135 | * EVO overlay channel objects |
| 136 | ******************************************************************************/ |
| 137 | |
| 138 | static const struct nv50_disp_mthd_list |
| 139 | nve0_disp_ovly_mthd_base = { |
| 140 | .mthd = 0x0000, |
| 141 | .data = { |
| 142 | { 0x0080, 0x665080 }, |
| 143 | { 0x0084, 0x665084 }, |
| 144 | { 0x0088, 0x665088 }, |
| 145 | { 0x008c, 0x66508c }, |
| 146 | { 0x0090, 0x665090 }, |
| 147 | { 0x0094, 0x665094 }, |
| 148 | { 0x00a0, 0x6650a0 }, |
| 149 | { 0x00a4, 0x6650a4 }, |
| 150 | { 0x00b0, 0x6650b0 }, |
| 151 | { 0x00b4, 0x6650b4 }, |
| 152 | { 0x00b8, 0x6650b8 }, |
| 153 | { 0x00c0, 0x6650c0 }, |
| 154 | { 0x00c4, 0x6650c4 }, |
| 155 | { 0x00e0, 0x6650e0 }, |
| 156 | { 0x00e4, 0x6650e4 }, |
| 157 | { 0x00e8, 0x6650e8 }, |
| 158 | { 0x0100, 0x665100 }, |
| 159 | { 0x0104, 0x665104 }, |
| 160 | { 0x0108, 0x665108 }, |
| 161 | { 0x010c, 0x66510c }, |
| 162 | { 0x0110, 0x665110 }, |
| 163 | { 0x0118, 0x665118 }, |
| 164 | { 0x011c, 0x66511c }, |
| 165 | { 0x0120, 0x665120 }, |
| 166 | { 0x0124, 0x665124 }, |
| 167 | { 0x0130, 0x665130 }, |
| 168 | { 0x0134, 0x665134 }, |
| 169 | { 0x0138, 0x665138 }, |
| 170 | { 0x013c, 0x66513c }, |
| 171 | { 0x0140, 0x665140 }, |
| 172 | { 0x0144, 0x665144 }, |
| 173 | { 0x0148, 0x665148 }, |
| 174 | { 0x014c, 0x66514c }, |
| 175 | { 0x0150, 0x665150 }, |
| 176 | { 0x0154, 0x665154 }, |
| 177 | { 0x0158, 0x665158 }, |
| 178 | { 0x015c, 0x66515c }, |
| 179 | { 0x0160, 0x665160 }, |
| 180 | { 0x0164, 0x665164 }, |
| 181 | { 0x0168, 0x665168 }, |
| 182 | { 0x016c, 0x66516c }, |
| 183 | { 0x0400, 0x665400 }, |
| 184 | { 0x0404, 0x665404 }, |
| 185 | { 0x0408, 0x665408 }, |
| 186 | { 0x040c, 0x66540c }, |
| 187 | { 0x0410, 0x665410 }, |
| 188 | {} |
| 189 | } |
| 190 | }; |
| 191 | |
| 192 | const struct nv50_disp_mthd_chan |
| 193 | nve0_disp_ovly_mthd_chan = { |
| 194 | .name = "Overlay" , |
| 195 | .addr = 0x001000, |
| 196 | .data = { |
| 197 | { "Global" , 1, &nve0_disp_ovly_mthd_base }, |
| 198 | {} |
| 199 | } |
| 200 | }; |
| 201 | |
| 202 | /******************************************************************************* |
| 203 | * Base display object |
| 204 | ******************************************************************************/ |
| 205 | |
| 206 | static struct nouveau_oclass |
| 207 | nve0_disp_sclass[] = { |
| 208 | { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, |
| 209 | { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, |
| 210 | { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, |
| 211 | { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, |
| 212 | { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, |
| 213 | {} |
| 214 | }; |
| 215 | |
| 216 | static struct nouveau_oclass |
| 217 | nve0_disp_base_oclass[] = { |
| 218 | { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nvd0_disp_base_omthds }, |
| 219 | {} |
| 220 | }; |
| 221 | |
| 222 | /******************************************************************************* |
| 223 | * Display engine implementation |
| 224 | ******************************************************************************/ |
| 225 | |
| 226 | static int |
| 227 | nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 228 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 229 | struct nouveau_object **pobject) |
| 230 | { |
| 231 | struct nv50_disp_priv *priv; |
| 232 | int heads = nv_rd32(parent, 0x022448); |
| 233 | int ret; |
| 234 | |
| 235 | ret = nouveau_disp_create(parent, engine, oclass, heads, |
| 236 | "PDISP" , "display" , &priv); |
| 237 | *pobject = nv_object(priv); |
| 238 | if (ret) |
| 239 | return ret; |
| 240 | |
| 241 | nv_engine(priv)->sclass = nve0_disp_base_oclass; |
| 242 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
| 243 | nv_subdev(priv)->intr = nvd0_disp_intr; |
| 244 | INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); |
| 245 | priv->sclass = nve0_disp_sclass; |
| 246 | priv->head.nr = heads; |
| 247 | priv->dac.nr = 3; |
| 248 | priv->sor.nr = 4; |
| 249 | priv->dac.power = nv50_dac_power; |
| 250 | priv->dac.sense = nv50_dac_sense; |
| 251 | priv->sor.power = nv50_sor_power; |
| 252 | priv->sor.hda_eld = nvd0_hda_eld; |
| 253 | priv->sor.hdmi = nvd0_hdmi_ctrl; |
| 254 | priv->sor.dp = &nvd0_sor_dp_func; |
| 255 | return 0; |
| 256 | } |
| 257 | |
| 258 | struct nouveau_oclass * |
| 259 | nve0_disp_oclass = &(struct nv50_disp_impl) { |
| 260 | .base.base.handle = NV_ENGINE(DISP, 0x91), |
| 261 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
| 262 | .ctor = nve0_disp_ctor, |
| 263 | .dtor = _nouveau_disp_dtor, |
| 264 | .init = _nouveau_disp_init, |
| 265 | .fini = _nouveau_disp_fini, |
| 266 | }, |
| 267 | .mthd.core = &nve0_disp_mast_mthd_chan, |
| 268 | .mthd.base = &nvd0_disp_sync_mthd_chan, |
| 269 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, |
| 270 | .mthd.prev = -0x020000, |
| 271 | }.base.base; |
| 272 | |