| 1 | /* |
| 2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
| 3 | * Copyright (c) 2002-2006 Atheros Communications, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | * |
| 17 | * $Id: ar5211_interrupts.c,v 1.1.1.1 2008/12/11 04:46:31 alc Exp $ |
| 18 | */ |
| 19 | #include "opt_ah.h" |
| 20 | |
| 21 | #include "ah.h" |
| 22 | #include "ah_internal.h" |
| 23 | |
| 24 | #include "ar5211/ar5211.h" |
| 25 | #include "ar5211/ar5211reg.h" |
| 26 | |
| 27 | /* |
| 28 | * Checks to see if an interrupt is pending on our NIC |
| 29 | * |
| 30 | * Returns: TRUE if an interrupt is pending |
| 31 | * FALSE if not |
| 32 | */ |
| 33 | HAL_BOOL |
| 34 | ar5211IsInterruptPending(struct ath_hal *ah) |
| 35 | { |
| 36 | return OS_REG_READ(ah, AR_INTPEND) != 0; |
| 37 | } |
| 38 | |
| 39 | /* |
| 40 | * Reads the Interrupt Status Register value from the NIC, thus deasserting |
| 41 | * the interrupt line, and returns both the masked and unmasked mapped ISR |
| 42 | * values. The value returned is mapped to abstract the hw-specific bit |
| 43 | * locations in the Interrupt Status Register. |
| 44 | * |
| 45 | * Returns: A hardware-abstracted bitmap of all non-masked-out |
| 46 | * interrupts pending, as well as an unmasked value |
| 47 | */ |
| 48 | HAL_BOOL |
| 49 | ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) |
| 50 | { |
| 51 | uint32_t isr; |
| 52 | |
| 53 | isr = OS_REG_READ(ah, AR_ISR_RAC); |
| 54 | if (isr == 0xffffffff) { |
| 55 | *masked = 0; |
| 56 | return AH_FALSE; |
| 57 | } |
| 58 | |
| 59 | *masked = isr & HAL_INT_COMMON; |
| 60 | |
| 61 | if (isr & AR_ISR_HIUERR) |
| 62 | *masked |= HAL_INT_FATAL; |
| 63 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) |
| 64 | *masked |= HAL_INT_RX; |
| 65 | if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) |
| 66 | *masked |= HAL_INT_TX; |
| 67 | /* |
| 68 | * Receive overrun is usually non-fatal on Oahu/Spirit. |
| 69 | * BUT on some parts rx could fail and the chip must be reset. |
| 70 | * So we force a hardware reset in all cases. |
| 71 | */ |
| 72 | if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { |
| 73 | HALDEBUG(ah, HAL_DEBUG_ANY, |
| 74 | "%s: receive FIFO overrun interrupt\n" , __func__); |
| 75 | *masked |= HAL_INT_FATAL; |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * On fatal errors collect ISR state for debugging. |
| 80 | */ |
| 81 | if (*masked & HAL_INT_FATAL) { |
| 82 | AH_PRIVATE(ah)->ah_fatalState[0] = isr; |
| 83 | AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); |
| 84 | AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); |
| 85 | AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); |
| 86 | AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); |
| 87 | AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); |
| 88 | HALDEBUG(ah, HAL_DEBUG_ANY, |
| 89 | "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n" , |
| 90 | __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); |
| 91 | } |
| 92 | return AH_TRUE; |
| 93 | } |
| 94 | |
| 95 | HAL_INT |
| 96 | ar5211GetInterrupts(struct ath_hal *ah) |
| 97 | { |
| 98 | return AH5211(ah)->ah_maskReg; |
| 99 | } |
| 100 | |
| 101 | /* |
| 102 | * Atomically enables NIC interrupts. Interrupts are passed in |
| 103 | * via the enumerated bitmask in ints. |
| 104 | */ |
| 105 | HAL_INT |
| 106 | ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints) |
| 107 | { |
| 108 | struct ath_hal_5211 *ahp = AH5211(ah); |
| 109 | uint32_t omask = ahp->ah_maskReg; |
| 110 | uint32_t mask; |
| 111 | |
| 112 | HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n" , |
| 113 | __func__, omask, ints); |
| 114 | |
| 115 | /* |
| 116 | * Disable interrupts here before reading & modifying |
| 117 | * the mask so that the ISR does not modify the mask |
| 118 | * out from under us. |
| 119 | */ |
| 120 | if (omask & HAL_INT_GLOBAL) { |
| 121 | HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n" , __func__); |
| 122 | OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
| 123 | /* XXX??? */ |
| 124 | (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ |
| 125 | } |
| 126 | |
| 127 | mask = ints & HAL_INT_COMMON; |
| 128 | if (ints & HAL_INT_TX) { |
| 129 | if (ahp->ah_txOkInterruptMask) |
| 130 | mask |= AR_IMR_TXOK; |
| 131 | if (ahp->ah_txErrInterruptMask) |
| 132 | mask |= AR_IMR_TXERR; |
| 133 | if (ahp->ah_txDescInterruptMask) |
| 134 | mask |= AR_IMR_TXDESC; |
| 135 | if (ahp->ah_txEolInterruptMask) |
| 136 | mask |= AR_IMR_TXEOL; |
| 137 | } |
| 138 | if (ints & HAL_INT_RX) |
| 139 | mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; |
| 140 | if (ints & HAL_INT_FATAL) { |
| 141 | /* |
| 142 | * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 |
| 143 | * so enabling HIUERR enables delivery. |
| 144 | */ |
| 145 | mask |= AR_IMR_HIUERR; |
| 146 | } |
| 147 | |
| 148 | /* Write the new IMR and store off our SW copy. */ |
| 149 | HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n" , __func__, mask); |
| 150 | OS_REG_WRITE(ah, AR_IMR, mask); |
| 151 | ahp->ah_maskReg = ints; |
| 152 | |
| 153 | /* Re-enable interrupts as appropriate. */ |
| 154 | if (ints & HAL_INT_GLOBAL) { |
| 155 | HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n" , __func__); |
| 156 | OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
| 157 | } |
| 158 | |
| 159 | return omask; |
| 160 | } |
| 161 | |