| 1 | /* $NetBSD: mlxreg.h,v 1.8 2008/09/08 23:36:54 gmcgarry Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Andrew Doran. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | /*- |
| 33 | * Copyright (c) 1999 Michael Smith |
| 34 | * All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * 1. Redistributions of source code must retain the above copyright |
| 40 | * notice, this list of conditions and the following disclaimer. |
| 41 | * 2. Redistributions in binary form must reproduce the above copyright |
| 42 | * notice, this list of conditions and the following disclaimer in the |
| 43 | * documentation and/or other materials provided with the distribution. |
| 44 | * |
| 45 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 46 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 55 | * SUCH DAMAGE. |
| 56 | * |
| 57 | * from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp |
| 58 | */ |
| 59 | |
| 60 | #ifndef _IC_MLXREG_H_ |
| 61 | #define _IC_MLXREG_H_ |
| 62 | |
| 63 | #define MLX_SECTOR_SIZE 512 |
| 64 | |
| 65 | /* |
| 66 | * Selected command codes. |
| 67 | */ |
| 68 | #define MLX_CMD_ENQUIRY_OLD 0x05 |
| 69 | #define MLX_CMD_ENQUIRY 0x53 |
| 70 | #define MLX_CMD_ENQUIRY2 0x1c |
| 71 | #define MLX_CMD_ENQSYSDRIVE 0x19 |
| 72 | #define MLX_CMD_READSG 0xb6 |
| 73 | #define MLX_CMD_WRITESG 0xb7 |
| 74 | #define MLX_CMD_READSG_OLD 0x82 |
| 75 | #define MLX_CMD_WRITESG_OLD 0x83 |
| 76 | #define MLX_CMD_FLUSH 0x0a |
| 77 | #define MLX_CMD_LOGOP 0x72 |
| 78 | #define MLX_CMD_REBUILDASYNC 0x16 |
| 79 | #define MLX_CMD_CHECKASYNC 0x1e |
| 80 | #define MLX_CMD_REBUILDSTAT 0x0c |
| 81 | #define MLX_CMD_STOPCHANNEL 0x13 |
| 82 | #define MLX_CMD_STARTCHANNEL 0x12 |
| 83 | #define MLX_CMD_READ_CONFIG 0x4e |
| 84 | #define MLX_CMD_WRITE_CONFIG 0x4f |
| 85 | #define MLX_CMD_READ_DK_CONFIG 0x4a |
| 86 | #define MLX_CMD_WRITE_DK_CONFIG 0x4b |
| 87 | #define MLX_CMD_DIRECT_CDB 0x04 |
| 88 | #define MLX_CMD_DEVICE_STATE 0x50 |
| 89 | #define MLX_CMD_READ_CONFIG2 0x3d |
| 90 | #define MLX_CMD_WRITE_CONFIG2 0x3c |
| 91 | |
| 92 | #ifdef _KERNEL |
| 93 | |
| 94 | /* |
| 95 | * Status values. |
| 96 | */ |
| 97 | #define MLX_STATUS_OK 0x0000 |
| 98 | #define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */ |
| 99 | #define MLX_STATUS_WEDGED 0xdeaf /* controller not listening */ |
| 100 | #define MLX_STATUS_LOST 0xdead /* never came back */ |
| 101 | #define MLX_STATUS_BUSY 0xbabe /* command is in controller */ |
| 102 | |
| 103 | /* |
| 104 | * V1 (EISA) interface. |
| 105 | */ |
| 106 | #define MLX_V1REG_IE 0x09 |
| 107 | #define MLX_V1REG_IDB 0x0d |
| 108 | #define MLX_V1REG_ODB_EN 0x0e |
| 109 | #define MLX_V1REG_ODB 0x0f |
| 110 | #define MLX_V1REG_MAILBOX 0x10 |
| 111 | |
| 112 | #define MLX_V1_IDB_FULL 0x01 /* mailbox is full */ |
| 113 | #define MLX_V1_IDB_INIT_BUSY 0x02 /* init in progress */ |
| 114 | |
| 115 | #define MLX_V1_IDB_SACK 0x02 /* acknowledge status read */ |
| 116 | #define MLX_V1_IDB_RESET 0x10 /* reset controller */ |
| 117 | |
| 118 | #define MLX_V1_ODB_SAVAIL 0x01 /* status is available */ |
| 119 | #define MLX_V1_ODB_RESET 0x02 /* reset controller */ |
| 120 | |
| 121 | #define MLX_V1_FWERROR_PEND 0x04 /* firmware error pending */ |
| 122 | |
| 123 | /* |
| 124 | * V2/V3 interface. |
| 125 | */ |
| 126 | #define MLX_V3REG_MAILBOX 0x00 |
| 127 | #define MLX_V3REG_STATUS_IDENT 0x0d |
| 128 | #define MLX_V3REG_STATUS 0x0e |
| 129 | #define MLX_V3REG_IDB 0x40 |
| 130 | #define MLX_V3REG_ODB 0x41 |
| 131 | #define MLX_V3REG_IE 0x43 |
| 132 | #define MLX_V3REG_FWERROR 0x3f |
| 133 | #define MLX_V3REG_FWERROR_PARAM1 0x00 |
| 134 | #define MLX_V3REG_FWERROR_PARAM2 0x01 |
| 135 | |
| 136 | #define MLX_V3_IDB_FULL 0x01 /* mailbox is full */ |
| 137 | #define MLX_V3_IDB_INIT_BUSY 0x02 /* init in progress */ |
| 138 | |
| 139 | #define MLX_V3_IDB_SACK 0x02 /* acknowledge status read */ |
| 140 | #define MLX_V3_IDB_RESET 0x08 /* reset controller */ |
| 141 | |
| 142 | #define MLX_V3_ODB_SAVAIL 0x01 /* status is available */ |
| 143 | |
| 144 | #define MLX_V3_FWERROR_PEND 0x04 /* firmware error pending */ |
| 145 | |
| 146 | /* |
| 147 | * V4 interface. |
| 148 | */ |
| 149 | #define MLX_V4REG_MAILBOX 0x1000 |
| 150 | #define MLX_V4REG_STATUS_IDENT 0x1018 |
| 151 | #define MLX_V4REG_STATUS 0x101a |
| 152 | #define MLX_V4REG_IDB 0x0020 |
| 153 | #define MLX_V4REG_ODB 0x002c |
| 154 | #define MLX_V4REG_IE 0x0034 |
| 155 | #define MLX_V4REG_FWERROR 0x103f |
| 156 | #define MLX_V4REG_FWERROR_PARAM1 0x1000 |
| 157 | #define MLX_V4REG_FWERROR_PARAM2 0x1001 |
| 158 | |
| 159 | #define MLX_V4_IDB_FULL 0x01 /* mailbox is full */ |
| 160 | #define MLX_V4_IDB_INIT_BUSY 0x02 /* initialisation in progress */ |
| 161 | |
| 162 | #define MLX_V4_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ |
| 163 | #define MLX_V4_IDB_SACK 0x02 /* acknowledge status read */ |
| 164 | #define MLX_V4_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ |
| 165 | |
| 166 | #define MLX_V4_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ |
| 167 | #define MLX_V4_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ |
| 168 | |
| 169 | #define MLX_V4_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ |
| 170 | #define MLX_V4_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ |
| 171 | |
| 172 | #define MLX_V4_IE_MASK 0xfb /* message unit interrupt mask */ |
| 173 | #define MLX_V4_IE_DISINT 0x04 /* interrupt disable bit */ |
| 174 | |
| 175 | #define MLX_V4_FWERROR_PEND 0x04 /* firmware error pending */ |
| 176 | |
| 177 | /* |
| 178 | * V5 interface. |
| 179 | */ |
| 180 | #define MLX_V5REG_MAILBOX 0x50 |
| 181 | #define MLX_V5REG_STATUS_IDENT 0x5d |
| 182 | #define MLX_V5REG_STATUS 0x5e |
| 183 | #define MLX_V5REG_IDB 0x60 |
| 184 | #define MLX_V5REG_ODB 0x61 |
| 185 | #define MLX_V5REG_IE 0x34 |
| 186 | #define MLX_V5REG_FWERROR 0x63 |
| 187 | #define MLX_V5REG_FWERROR_PARAM1 0x50 |
| 188 | #define MLX_V5REG_FWERROR_PARAM2 0x51 |
| 189 | |
| 190 | #define MLX_V5_IDB_EMPTY 0x01 /* mailbox is empty */ |
| 191 | #define MLX_V5_IDB_INIT_DONE 0x02 /* initialisation has completed */ |
| 192 | |
| 193 | #define MLX_V5_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */ |
| 194 | #define MLX_V5_IDB_SACK 0x02 /* acknowledge status read */ |
| 195 | #define MLX_V5_IDB_RESET 0x08 /* reset request */ |
| 196 | #define MLX_V5_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */ |
| 197 | |
| 198 | #define MLX_V5_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */ |
| 199 | #define MLX_V5_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */ |
| 200 | |
| 201 | #define MLX_V5_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */ |
| 202 | #define MLX_V5_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */ |
| 203 | |
| 204 | #define MLX_V5_IE_DISINT 0x04 /* interrupt disable bit */ |
| 205 | |
| 206 | #define MLX_V5_FWERROR_PEND 0x04 /* firmware error pending */ |
| 207 | |
| 208 | #endif /* _KERNEL */ |
| 209 | |
| 210 | /* |
| 211 | * Scatter-gather list format, type 1, kind 00. |
| 212 | */ |
| 213 | struct mlx_sgentry { |
| 214 | u_int32_t sge_addr; |
| 215 | u_int32_t sge_count; |
| 216 | } __packed; |
| 217 | |
| 218 | /* |
| 219 | * Command result buffers, as placed in system memory by the controller. |
| 220 | */ |
| 221 | struct mlx_enquiry_old { |
| 222 | u_int8_t me_num_sys_drvs; |
| 223 | u_int8_t me_res1[3]; |
| 224 | u_int32_t me_drvsize[8]; |
| 225 | u_int16_t me_flash_age; |
| 226 | u_int8_t me_status_flags; |
| 227 | u_int8_t me_free_state_change_count; |
| 228 | u_int8_t me_fwminor; |
| 229 | u_int8_t me_fwmajor; |
| 230 | u_int8_t me_rebuild_flag; |
| 231 | u_int8_t me_max_commands; |
| 232 | u_int8_t me_offline_sd_count; |
| 233 | u_int8_t me_res3; |
| 234 | u_int8_t me_critical_sd_count; |
| 235 | u_int8_t me_res4[3]; |
| 236 | u_int8_t me_dead_count; |
| 237 | u_int8_t me_res5; |
| 238 | u_int8_t me_rebuild_count; |
| 239 | u_int8_t me_misc_flags; |
| 240 | struct { |
| 241 | u_int8_t dd_targ; |
| 242 | u_int8_t dd_chan; |
| 243 | } __packed me_dead[20]; |
| 244 | } __packed; |
| 245 | |
| 246 | struct mlx_enquiry { |
| 247 | u_int8_t me_num_sys_drvs; |
| 248 | u_int8_t me_res1[3]; |
| 249 | u_int32_t me_drvsize[32]; |
| 250 | u_int16_t me_flash_age; |
| 251 | u_int8_t me_status_flags; |
| 252 | #define MLX_ENQ_SFLAG_DEFWRERR 0x01 /* deferred write error indicator */ |
| 253 | #define MLX_ENQ_SFLAG_BATTLOW 0x02 /* battery low */ |
| 254 | u_int8_t me_res2; |
| 255 | u_int8_t me_fwminor; |
| 256 | u_int8_t me_fwmajor; |
| 257 | u_int8_t me_rebuild_flag; |
| 258 | u_int8_t me_max_commands; |
| 259 | u_int8_t me_offline_sd_count; |
| 260 | u_int8_t me_res3; |
| 261 | u_int16_t me_event_log_seq_num; |
| 262 | u_int8_t me_critical_sd_count; |
| 263 | u_int8_t me_res4[3]; |
| 264 | u_int8_t me_dead_count; |
| 265 | u_int8_t me_res5; |
| 266 | u_int8_t me_rebuild_count; |
| 267 | u_int8_t me_misc_flags; |
| 268 | #define MLX_ENQ_MISC_BBU 0x08 /* battery backup present */ |
| 269 | struct { |
| 270 | u_int8_t dd_targ; |
| 271 | u_int8_t dd_chan; |
| 272 | } __packed me_dead[20]; |
| 273 | } __packed; |
| 274 | |
| 275 | struct mlx_enquiry2 { |
| 276 | u_int8_t me_hardware_id[4]; |
| 277 | u_int8_t me_firmware_id[4]; |
| 278 | u_int32_t me_res1; |
| 279 | u_int8_t me_configured_channels; |
| 280 | u_int8_t me_actual_channels; |
| 281 | u_int8_t me_max_targets; |
| 282 | u_int8_t me_max_tags; |
| 283 | u_int8_t me_max_sys_drives; |
| 284 | u_int8_t me_max_arms; |
| 285 | u_int8_t me_max_spans; |
| 286 | u_int8_t me_res2; |
| 287 | u_int32_t me_res3; |
| 288 | u_int32_t me_mem_size; |
| 289 | u_int32_t me_cache_size; |
| 290 | u_int32_t me_flash_size; |
| 291 | u_int32_t me_nvram_size; |
| 292 | u_int16_t me_mem_type; |
| 293 | u_int16_t me_clock_speed; |
| 294 | u_int16_t me_mem_speed; |
| 295 | u_int16_t me_hardware_speed; |
| 296 | u_int8_t me_res4[12]; |
| 297 | u_int16_t me_max_commands; |
| 298 | u_int16_t me_max_sg; |
| 299 | u_int16_t me_max_dp; |
| 300 | u_int16_t me_max_iod; |
| 301 | u_int16_t me_max_comb; |
| 302 | u_int8_t me_latency; |
| 303 | u_int8_t me_res5; |
| 304 | u_int8_t me_scsi_timeout; |
| 305 | u_int8_t me_res6; |
| 306 | u_int16_t me_min_freelines; |
| 307 | u_int8_t me_res7[8]; |
| 308 | u_int8_t me_rate_const; |
| 309 | u_int8_t me_res8[11]; |
| 310 | u_int16_t me_physblk; |
| 311 | u_int16_t me_logblk; |
| 312 | u_int16_t me_maxblk; |
| 313 | u_int16_t me_blocking_factor; |
| 314 | u_int16_t me_cacheline; |
| 315 | u_int8_t me_scsi_cap; |
| 316 | u_int8_t me_res9[5]; |
| 317 | u_int16_t me_firmware_build; |
| 318 | u_int8_t me_fault_mgmt_type; |
| 319 | u_int8_t me_res10; |
| 320 | u_int32_t me_firmware_features; |
| 321 | u_int8_t me_res11[8]; |
| 322 | } __packed; |
| 323 | |
| 324 | /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */ |
| 325 | struct mlx_enq_sys_drive { |
| 326 | u_int32_t sd_size; |
| 327 | u_int8_t sd_state; |
| 328 | u_int8_t sd_raidlevel; |
| 329 | u_int16_t sd_res1; |
| 330 | } __packed; |
| 331 | |
| 332 | /* |
| 333 | * MLX_CMD_LOGOP/MLX_LOGOP_GET |
| 334 | * |
| 335 | * Bitfields: |
| 336 | * |
| 337 | * 0-4 el_target SCSI target |
| 338 | * 5-7 el_target SCSI channel |
| 339 | * 0-6 el_errorcode error code |
| 340 | * 7-7 el_errorcode validity (?) |
| 341 | * 0-3 el_sense sense key |
| 342 | * 4-4 el_sense reserved |
| 343 | * 5-5 el_sense ILI |
| 344 | * 6-6 el_sense EOM |
| 345 | * 7-7 el_sense filemark |
| 346 | */ |
| 347 | struct mlx_eventlog_entry { |
| 348 | u_int8_t el_type; |
| 349 | u_int8_t el_length; |
| 350 | u_int8_t el_target; |
| 351 | u_int8_t el_lun; |
| 352 | u_int16_t el_seqno; |
| 353 | u_int8_t el_errorcode; |
| 354 | u_int8_t el_segment; |
| 355 | u_int8_t el_sense; |
| 356 | u_int8_t el_information[4]; |
| 357 | u_int8_t el_addsense; |
| 358 | u_int8_t el_csi[4]; |
| 359 | u_int8_t el_asc; |
| 360 | u_int8_t el_asq; |
| 361 | u_int8_t el_res3[12]; |
| 362 | } __packed; |
| 363 | |
| 364 | #define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */ |
| 365 | #define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */ |
| 366 | |
| 367 | struct mlx_rebuild_stat { |
| 368 | u_int32_t rb_drive; |
| 369 | u_int32_t rb_size; |
| 370 | u_int32_t rb_remaining; |
| 371 | } __packed; |
| 372 | |
| 373 | struct mlx_config { |
| 374 | u_int16_t cf_flags1; |
| 375 | #define MLX_CF2_ACTV_NEG 0x0002 |
| 376 | #define MLX_CF2_NORSTRTRY 0x0080 |
| 377 | #define MLX_CF2_STRGWRK 0x0100 |
| 378 | #define MLX_CF2_HPSUPP 0x0200 |
| 379 | #define MLX_CF2_NODISCN 0x0400 |
| 380 | #define MLX_CF2_ARM 0x2000 |
| 381 | #define MLX_CF2_OFM 0x8000 |
| 382 | #define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM) |
| 383 | u_int8_t cf_oemid; |
| 384 | u_int8_t cf_oem_model; |
| 385 | u_int8_t cf_physical_sector; |
| 386 | u_int8_t cf_logical_sector; |
| 387 | u_int8_t cf_blockfactor; |
| 388 | u_int8_t cf_flags2; |
| 389 | #define MLX_CF2_READAH 0x01 |
| 390 | #define MLX_CF2_BIOSDLY 0x02 |
| 391 | #define MLX_CF2_REASS1S 0x10 |
| 392 | #define MLX_CF2_FUAENABL 0x40 |
| 393 | #define MLX_CF2_R5ALLS 0x80 |
| 394 | u_int8_t cf_rcrate; |
| 395 | u_int8_t cf_res1; |
| 396 | u_int8_t cf_blocks_per_cache_line; |
| 397 | u_int8_t cf_blocks_per_stripe; |
| 398 | u_int8_t cf_scsi_param_0; |
| 399 | u_int8_t cf_scsi_param_1; |
| 400 | u_int8_t cf_scsi_param_2; |
| 401 | u_int8_t cf_scsi_param_3; |
| 402 | u_int8_t cf_scsi_param_4; |
| 403 | u_int8_t cf_scsi_param_5; |
| 404 | u_int8_t cf_scsi_initiator_id; |
| 405 | u_int8_t cf_res2; |
| 406 | u_int8_t cf_startup_mode; |
| 407 | u_int8_t cf_simultaneous_spinup_devices; |
| 408 | u_int8_t cf_delay_between_spinups; |
| 409 | u_int8_t cf_res3; |
| 410 | u_int16_t cf_checksum; |
| 411 | } __packed; |
| 412 | |
| 413 | struct mlx_config2 { |
| 414 | struct mlx_config cf2_cf; |
| 415 | u_int8_t cf2_reserved0[26]; |
| 416 | u_int8_t cf2_flags; |
| 417 | #define MLX_CF2_BIOS_DIS 0x01 |
| 418 | #define MLX_CF2_CDROM_DIS 0x02 |
| 419 | #define MLX_CF2_GEOM_255 0x20 |
| 420 | u_int8_t cf2_reserved1[9]; |
| 421 | u_int16_t cf2_checksum; |
| 422 | } __packed; |
| 423 | |
| 424 | struct mlx_sys_drv_span { |
| 425 | u_int32_t sp_start_lba; |
| 426 | u_int32_t sp_nblks; |
| 427 | u_int8_t sp_arm[8]; |
| 428 | } __packed; |
| 429 | |
| 430 | struct mlx_sys_drv { |
| 431 | u_int8_t sd_status; |
| 432 | u_int8_t sd_ext_status; |
| 433 | u_int8_t sd_mod1; |
| 434 | u_int8_t sd_mod2; |
| 435 | u_int8_t sd_raidlevel; |
| 436 | #define MLX_SYS_DRV_WRITEBACK (1<<7) |
| 437 | #define MLX_SYS_DRV_RAID0 0 |
| 438 | #define MLX_SYS_DRV_RAID1 1 |
| 439 | #define MLX_SYS_DRV_RAID3 3 |
| 440 | #define MLX_SYS_DRV_RAID5 5 |
| 441 | #define MLX_SYS_DRV_RAID6 6 |
| 442 | #define MLX_SYS_DRV_JBOD 7 |
| 443 | u_int8_t sd_valid_arms; |
| 444 | u_int8_t sd_valid_spans; |
| 445 | u_int8_t sd_init_state; |
| 446 | #define MLX_SYS_DRV_INITTED 0x81; |
| 447 | struct mlx_sys_drv_span sd_span[4]; |
| 448 | } __packed; |
| 449 | |
| 450 | struct mlx_phys_drv { |
| 451 | u_int8_t pd_flags1; |
| 452 | #define MLX_PHYS_DRV_PRESENT 0x01 |
| 453 | u_int8_t pd_flags2; |
| 454 | #define MLX_PHYS_DRV_OTHER 0x00 |
| 455 | #define MLX_PHYS_DRV_DISK 0x01 |
| 456 | #define MLX_PHYS_DRV_SEQUENTIAL 0x02 |
| 457 | #define MLX_PHYS_DRV_CDROM 0x03 |
| 458 | #define MLX_PHYS_DRV_FAST20 0x08 |
| 459 | #define MLX_PHYS_DRV_SYNC 0x10 |
| 460 | #define MLX_PHYS_DRV_FAST 0x20 |
| 461 | #define MLX_PHYS_DRV_WIDE 0x40 |
| 462 | #define MLX_PHYS_DRV_TAG 0x80 |
| 463 | u_int8_t pd_status; |
| 464 | #define MLX_PHYS_DRV_DEAD 0x00 |
| 465 | #define MLX_PHYS_DRV_WRONLY 0x02 |
| 466 | #define MLX_PHYS_DRV_ONLINE 0x03 |
| 467 | #define MLX_PHYS_DRV_STANDBY 0x10 |
| 468 | u_int8_t pd_res1; |
| 469 | u_int8_t pd_period; |
| 470 | u_int8_t pd_offset; |
| 471 | u_int32_t pd_config_size; |
| 472 | } __packed; |
| 473 | |
| 474 | struct mlx_core_cfg { |
| 475 | u_int8_t cc_num_sys_drives; |
| 476 | u_int8_t cc_res1[3]; |
| 477 | struct mlx_sys_drv cc_sys_drives[32]; |
| 478 | struct mlx_phys_drv cc_phys_drives[5 * 16]; |
| 479 | } __packed; |
| 480 | |
| 481 | /* |
| 482 | * Bitfields: |
| 483 | * |
| 484 | * 0-3 dcdb_target SCSI target |
| 485 | * 4-7 dcdb_target SCSI channel |
| 486 | * 0-3 dcdb_length CDB length |
| 487 | * 4-7 dcdb_length high 4 bits of `datasize' |
| 488 | */ |
| 489 | struct mlx_dcdb { |
| 490 | u_int8_t dcdb_target; |
| 491 | u_int8_t dcdb_flags; |
| 492 | #define MLX_DCDB_NO_DATA 0x00 |
| 493 | #define MLX_DCDB_DATA_IN 0x01 |
| 494 | #define MLX_DCDB_DATA_OUT 0x02 |
| 495 | #define MLX_DCDB_EARLY_STATUS 0x04 |
| 496 | #define MLX_DCDB_TIMEOUT_10S 0x10 /* This lot is wrong? [ad] */ |
| 497 | #define MLX_DCDB_TIMEOUT_60S 0x20 |
| 498 | #define MLX_DCDB_TIMEOUT_20M 0x30 |
| 499 | #define MLX_DCDB_TIMEOUT_24H 0x40 |
| 500 | #define MLX_DCDB_NO_AUTO_SENSE 0x40 /* XXX ?? */ |
| 501 | #define MLX_DCDB_DISCONNECT 0x80 |
| 502 | u_int16_t dcdb_datasize; |
| 503 | u_int32_t dcdb_physaddr; |
| 504 | u_int8_t dcdb_length; |
| 505 | u_int8_t dcdb_sense_length; |
| 506 | u_int8_t dcdb_cdb[12]; |
| 507 | u_int8_t dcdb_sense[64]; |
| 508 | u_int8_t dcdb_status; |
| 509 | u_int8_t res1; |
| 510 | } __packed; |
| 511 | |
| 512 | struct mlx_bbtable_entry { |
| 513 | u_int32_t bbt_block_number; |
| 514 | u_int8_t bbt_extent; |
| 515 | u_int8_t bbt_res1; |
| 516 | u_int8_t bbt_entry_type; |
| 517 | u_int8_t bbt_system_drive; /* high 3 bits reserved */ |
| 518 | } __packed; |
| 519 | |
| 520 | #endif /* !_IC_MLXREG_H_ */ |
| 521 | |