| 1 | /* $NetBSD: if_alcreg.h,v 1.5 2015/11/24 23:30:04 leot Exp $ */ |
| 2 | /* $OpenBSD: if_alcreg.h,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ |
| 3 | /*- |
| 4 | * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice unmodified, this list of conditions, and the following |
| 12 | * disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMATE. |
| 28 | * |
| 29 | * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ |
| 30 | */ |
| 31 | |
| 32 | #ifndef _IF_ALCREG_H |
| 33 | #define _IF_ALCREG_H |
| 34 | |
| 35 | #define ALC_PCIR_BAR 0x10 |
| 36 | |
| 37 | #define ATHEROS_AR8152_B_V10 0xC0 |
| 38 | #define ATHEROS_AR8152_B_V11 0xC1 |
| 39 | |
| 40 | /* |
| 41 | * Atheros AR816x/AR817x revisions |
| 42 | */ |
| 43 | #define AR816X_REV_A0 0 |
| 44 | #define AR816X_REV_A1 1 |
| 45 | #define AR816X_REV_B0 2 |
| 46 | #define AR816X_REV_C0 3 |
| 47 | |
| 48 | #define AR816X_REV_SHIFT 3 |
| 49 | #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) |
| 50 | |
| 51 | /* 0x0000 - 0x02FF : PCIe configuration space */ |
| 52 | |
| 53 | #define ALC_PEX_UNC_ERR_SEV 0x10C |
| 54 | #define PEX_UNC_ERR_SEV_TRN 0x00000001 |
| 55 | #define PEX_UNC_ERR_SEV_DLP 0x00000010 |
| 56 | #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 |
| 57 | #define PEX_UNC_ERR_SEV_FCP 0x00002000 |
| 58 | #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 |
| 59 | #define PEX_UNC_ERR_SEV_CA 0x00008000 |
| 60 | #define PEX_UNC_ERR_SEV_UC 0x00010000 |
| 61 | #define PEX_UNC_ERR_SEV_ROV 0x00020000 |
| 62 | #define PEX_UNC_ERR_SEV_MLFP 0x00040000 |
| 63 | #define PEX_UNC_ERR_SEV_ECRC 0x00080000 |
| 64 | #define PEX_UNC_ERR_SEV_UR 0x00100000 |
| 65 | |
| 66 | #define ALC_EEPROM_LD 0x204 /* AR816x */ |
| 67 | #define EEPROM_LD_START 0x00000001 |
| 68 | #define EEPROM_LD_IDLE 0x00000010 |
| 69 | #define EEPROM_LD_DONE 0x00000000 |
| 70 | #define EEPROM_LD_PROGRESS 0x00000020 |
| 71 | #define EEPROM_LD_EXIST 0x00000100 |
| 72 | #define EEPROM_LD_EEPROM_EXIST 0x00000200 |
| 73 | #define EEPROM_LD_FLASH_EXIST 0x00000400 |
| 74 | #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 |
| 75 | #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 |
| 76 | |
| 77 | #define ALC_TWSI_CFG 0x218 |
| 78 | #define TWSI_CFG_SW_LD_START 0x00000800 |
| 79 | #define TWSI_CFG_HW_LD_START 0x00001000 |
| 80 | #define TWSI_CFG_LD_EXIST 0x00400000 |
| 81 | |
| 82 | #define ALC_SLD 0x218 /* AR816x */ |
| 83 | #define SLD_START 0x00000800 |
| 84 | #define SLD_PROGRESS 0x00001000 |
| 85 | #define SLD_IDLE 0x00002000 |
| 86 | #define SLD_SLVADDR_MASK 0x007F0000 |
| 87 | #define SLD_EXIST 0x00800000 |
| 88 | #define SLD_FREQ_MASK 0x03000000 |
| 89 | #define SLD_FREQ_100K 0x00000000 |
| 90 | #define SLD_FREQ_200K 0x01000000 |
| 91 | #define SLD_FREQ_300K 0x02000000 |
| 92 | #define SLD_FREQ_400K 0x03000000 |
| 93 | |
| 94 | #define ALC_PCIE_PHYMISC 0x1000 |
| 95 | #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 |
| 96 | |
| 97 | #define ALC_PCIE_PHYMISC2 0x1004 |
| 98 | #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 |
| 99 | #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 |
| 100 | #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 |
| 101 | #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 |
| 102 | |
| 103 | #define ALC_TWSI_DEBUG 0x1108 |
| 104 | #define TWSI_DEBUG_DEV_EXIST 0x20000000 |
| 105 | |
| 106 | #define ALC_PDLL_TRNS1 0x1104 |
| 107 | #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 |
| 108 | |
| 109 | #define ALC_EEPROM_CFG 0x12C0 |
| 110 | #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF |
| 111 | #define EEPROM_CFG_ADDR_MASK 0x03FF0000 |
| 112 | #define EEPROM_CFG_ACK 0x40000000 |
| 113 | #define EEPROM_CFG_RW 0x80000000 |
| 114 | #define EEPROM_CFG_DATA_HI_SHIFT 0 |
| 115 | #define EEPROM_CFG_ADDR_SHIFT 16 |
| 116 | |
| 117 | #define ALC_EEPROM_DATA_LO 0x12C4 |
| 118 | |
| 119 | #define ALC_OPT_CFG 0x12F0 |
| 120 | #define OPT_CFG_CLK_ENB 0x00000002 |
| 121 | |
| 122 | #define ALC_PM_CFG 0x12F8 |
| 123 | #define PM_CFG_SERDES_ENB 0x00000001 |
| 124 | #define PM_CFG_RBER_ENB 0x00000002 |
| 125 | #define PM_CFG_CLK_REQ_ENB 0x00000004 |
| 126 | #define PM_CFG_ASPM_L1_ENB 0x00000008 |
| 127 | #define PM_CFG_SERDES_L1_ENB 0x00000010 |
| 128 | #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 |
| 129 | #define PM_CFG_SERDES_PD_EX_L1 0x00000040 |
| 130 | #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 |
| 131 | #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 |
| 132 | #define PM_CFG_RX_L1_AFTER_L0S 0x00000800 |
| 133 | #define PM_CFG_ASPM_L0S_ENB 0x00001000 |
| 134 | #define PM_CFG_CLK_SWH_L1 0x00002000 |
| 135 | #define PM_CFG_CLK_PWM_VER1_1 0x00004000 |
| 136 | #define PM_CFG_PCIE_RECV 0x00008000 |
| 137 | #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 |
| 138 | #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 |
| 139 | #define PM_CFG_TX_L1_AFTER_L0S 0x00080000 |
| 140 | #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 |
| 141 | #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 |
| 142 | #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 |
| 143 | #define PM_CFG_SA_DLY_ENB 0x20000000 |
| 144 | #define PM_CFG_MAC_ASPM_CHK 0x40000000 |
| 145 | #define PM_CFG_HOTRST 0x80000000 |
| 146 | #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 |
| 147 | #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 |
| 148 | #define PM_CFG_PM_REQ_TIMER_SHIFT 20 |
| 149 | #define PM_CFG_LCKDET_TIMER_SHIFT 24 |
| 150 | |
| 151 | #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 |
| 152 | #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 |
| 153 | #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 |
| 154 | #define PM_CFG_LCKDET_TIMER_DEFAULT 12 |
| 155 | #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 |
| 156 | #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 |
| 157 | |
| 158 | #define ALC_LTSSM_ID_CFG 0x12FC |
| 159 | #define LTSSM_ID_WRO_ENB 0x00001000 |
| 160 | |
| 161 | #define ALC_MASTER_CFG 0x1400 |
| 162 | #define MASTER_RESET 0x00000001 |
| 163 | #define MASTER_TEST_MODE_MASK 0x0000000C |
| 164 | #define MASTER_BERT_START 0x00000010 |
| 165 | #define MASTER_WAKEN_25M 0x00000020 |
| 166 | #define MASTER_OOB_DIS_OFF 0x00000040 |
| 167 | #define MASTER_SA_TIMER_ENB 0x00000080 |
| 168 | #define MASTER_MTIMER_ENB 0x00000100 |
| 169 | #define MASTER_MANUAL_INTR_ENB 0x00000200 |
| 170 | #define MASTER_IM_TX_TIMER_ENB 0x00000400 |
| 171 | #define MASTER_IM_RX_TIMER_ENB 0x00000800 |
| 172 | #define MASTER_CLK_SEL_DIS 0x00001000 |
| 173 | #define MASTER_CLK_SWH_MODE 0x00002000 |
| 174 | #define MASTER_INTR_RD_CLR 0x00004000 |
| 175 | #define MASTER_CHIP_REV_MASK 0x00FF0000 |
| 176 | #define MASTER_CHIP_ID_MASK 0x7F000000 |
| 177 | #define MASTER_OTP_SEL 0x80000000 |
| 178 | #define MASTER_TEST_MODE_SHIFT 2 |
| 179 | #define MASTER_CHIP_REV_SHIFT 16 |
| 180 | #define MASTER_CHIP_ID_SHIFT 24 |
| 181 | |
| 182 | /* Number of ticks per usec for AR813x/AR815x. */ |
| 183 | #define ALC_TICK_USECS 2 |
| 184 | #define ALC_USECS(x) ((x) / ALC_TICK_USECS) |
| 185 | |
| 186 | #define ALC_MANUAL_TIMER 0x1404 |
| 187 | |
| 188 | #define ALC_IM_TIMER 0x1408 |
| 189 | #define IM_TIMER_TX_MASK 0x0000FFFF |
| 190 | #define IM_TIMER_RX_MASK 0xFFFF0000 |
| 191 | #define IM_TIMER_TX_SHIFT 0 |
| 192 | #define IM_TIMER_RX_SHIFT 16 |
| 193 | #define ALC_IM_TIMER_MIN 0 |
| 194 | #define ALC_IM_TIMER_MAX 130000 /* 130ms */ |
| 195 | /* |
| 196 | * 100us will ensure alc(4) wouldn't generate more than 10000 Rx |
| 197 | * interrupts in a second. |
| 198 | */ |
| 199 | #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ |
| 200 | /* |
| 201 | * alc(4) does not rely on Tx completion interrupts, so set it |
| 202 | * somewhat large value to reduce Tx completion interrupts. |
| 203 | */ |
| 204 | #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ |
| 205 | |
| 206 | #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ |
| 207 | #define GPHY_CFG_EXT_RESET 0x0001 |
| 208 | #define GPHY_CFG_RTL_MODE 0x0002 |
| 209 | #define GPHY_CFG_LED_MODE 0x0004 |
| 210 | #define GPHY_CFG_ANEG_NOW 0x0008 |
| 211 | #define GPHY_CFG_RECV_ANEG 0x0010 |
| 212 | #define GPHY_CFG_GATE_25M_ENB 0x0020 |
| 213 | #define GPHY_CFG_LPW_EXIT 0x0040 |
| 214 | #define GPHY_CFG_PHY_IDDQ 0x0080 |
| 215 | #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 |
| 216 | #define GPHY_CFG_PCLK_SEL_DIS 0x0200 |
| 217 | #define GPHY_CFG_HIB_EN 0x0400 |
| 218 | #define GPHY_CFG_HIB_PULSE 0x0800 |
| 219 | #define GPHY_CFG_SEL_ANA_RESET 0x1000 |
| 220 | #define GPHY_CFG_PHY_PLL_ON 0x2000 |
| 221 | #define GPHY_CFG_PWDOWN_HW 0x4000 |
| 222 | #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 |
| 223 | #define GPHY_CFG_100AB_ENB 0x00020000 |
| 224 | |
| 225 | #define ALC_IDLE_STATUS 0x1410 |
| 226 | #define IDLE_STATUS_RXMAC 0x00000001 |
| 227 | #define IDLE_STATUS_TXMAC 0x00000002 |
| 228 | #define IDLE_STATUS_RXQ 0x00000004 |
| 229 | #define IDLE_STATUS_TXQ 0x00000008 |
| 230 | #define IDLE_STATUS_DMARD 0x00000010 |
| 231 | #define IDLE_STATUS_DMAWR 0x00000020 |
| 232 | #define IDLE_STATUS_SMB 0x00000040 |
| 233 | #define IDLE_STATUS_CMB 0x00000080 |
| 234 | |
| 235 | #define ALC_MDIO 0x1414 |
| 236 | #define MDIO_DATA_MASK 0x0000FFFF |
| 237 | #define MDIO_REG_ADDR_MASK 0x001F0000 |
| 238 | #define MDIO_OP_READ 0x00200000 |
| 239 | #define MDIO_OP_WRITE 0x00000000 |
| 240 | #define MDIO_SUP_PREAMBLE 0x00400000 |
| 241 | #define MDIO_OP_EXECUTE 0x00800000 |
| 242 | #define MDIO_CLK_25_4 0x00000000 |
| 243 | #define MDIO_CLK_25_6 0x02000000 |
| 244 | #define MDIO_CLK_25_8 0x03000000 |
| 245 | #define MDIO_CLK_25_10 0x04000000 |
| 246 | #define MDIO_CLK_25_14 0x05000000 |
| 247 | #define MDIO_CLK_25_20 0x06000000 |
| 248 | #define MDIO_CLK_25_128 0x07000000 |
| 249 | #define MDIO_OP_BUSY 0x08000000 |
| 250 | #define MDIO_AP_ENB 0x10000000 |
| 251 | #define MDIO_MODE_EXT 0x40000000 |
| 252 | #define MDIO_DATA_SHIFT 0 |
| 253 | #define MDIO_REG_ADDR_SHIFT 16 |
| 254 | |
| 255 | #define MDIO_REG_ADDR(x) \ |
| 256 | (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) |
| 257 | /* Default PHY address. */ |
| 258 | #define ALC_PHY_ADDR 0 |
| 259 | |
| 260 | #define ALC_PHY_STATUS 0x1418 |
| 261 | #define PHY_STATUS_RECV_ENB 0x00000001 |
| 262 | #define PHY_STATUS_GENERAL_MASK 0x0000FFFF |
| 263 | #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 |
| 264 | #define PHY_STATUS_LPW_STATE 0x80000000 |
| 265 | #define PHY_STATIS_OE_PWSP_SHIFT 16 |
| 266 | |
| 267 | /* Packet memory BIST. */ |
| 268 | #define ALC_BIST0 0x141C |
| 269 | #define BIST0_ENB 0x00000001 |
| 270 | #define BIST0_SRAM_FAIL 0x00000002 |
| 271 | #define BIST0_FUSE_FLAG 0x00000004 |
| 272 | |
| 273 | /* PCIe retry buffer BIST. */ |
| 274 | #define ALC_BIST1 0x1420 |
| 275 | #define BIST1_ENB 0x00000001 |
| 276 | #define BIST1_SRAM_FAIL 0x00000002 |
| 277 | #define BIST1_FUSE_FLAG 0x00000004 |
| 278 | |
| 279 | #define ALC_SERDES_LOCK 0x1424 |
| 280 | #define SERDES_LOCK_DET 0x00000001 |
| 281 | #define SERDES_LOCK_DET_ENB 0x00000002 |
| 282 | #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 |
| 283 | #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 |
| 284 | |
| 285 | #define ALC_LPI_CTL 0x1440 |
| 286 | #define LPI_CTL_ENB 0x00000001 |
| 287 | |
| 288 | #define ALC_EXT_MDIO 0x1448 |
| 289 | #define EXT_MDIO_REG_MASK 0x0000FFFF |
| 290 | #define EXT_MDIO_DEVADDR_MASK 0x001F0000 |
| 291 | #define EXT_MDIO_REG_SHIFT 0 |
| 292 | #define EXT_MDIO_DEVADDR_SHIFT 16 |
| 293 | |
| 294 | #define EXT_MDIO_REG(x) \ |
| 295 | (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) |
| 296 | #define EXT_MDIO_DEVADDR(x) \ |
| 297 | (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) |
| 298 | |
| 299 | #define ALC_IDLE_DECISN_TIMER 0x1474 |
| 300 | #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 |
| 301 | |
| 302 | #define ALC_MAC_CFG 0x1480 |
| 303 | #define MAC_CFG_TX_ENB 0x00000001 |
| 304 | #define MAC_CFG_RX_ENB 0x00000002 |
| 305 | #define MAC_CFG_TX_FC 0x00000004 |
| 306 | #define MAC_CFG_RX_FC 0x00000008 |
| 307 | #define MAC_CFG_LOOP 0x00000010 |
| 308 | #define MAC_CFG_FULL_DUPLEX 0x00000020 |
| 309 | #define MAC_CFG_TX_CRC_ENB 0x00000040 |
| 310 | #define MAC_CFG_TX_AUTO_PAD 0x00000080 |
| 311 | #define MAC_CFG_TX_LENCHK 0x00000100 |
| 312 | #define MAC_CFG_RX_JUMBO_ENB 0x00000200 |
| 313 | #define MAC_CFG_PREAMBLE_MASK 0x00003C00 |
| 314 | #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 |
| 315 | #define MAC_CFG_PROMISC 0x00008000 |
| 316 | #define MAC_CFG_TX_PAUSE 0x00010000 |
| 317 | #define MAC_CFG_SCNT 0x00020000 |
| 318 | #define MAC_CFG_SYNC_RST_TX 0x00040000 |
| 319 | #define MAC_CFG_SIM_RST_TX 0x00080000 |
| 320 | #define MAC_CFG_SPEED_MASK 0x00300000 |
| 321 | #define MAC_CFG_SPEED_10_100 0x00100000 |
| 322 | #define MAC_CFG_SPEED_1000 0x00200000 |
| 323 | #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 |
| 324 | #define MAC_CFG_TX_JUMBO_ENB 0x00800000 |
| 325 | #define MAC_CFG_RXCSUM_ENB 0x01000000 |
| 326 | #define MAC_CFG_ALLMULTI 0x02000000 |
| 327 | #define MAC_CFG_BCAST 0x04000000 |
| 328 | #define MAC_CFG_DBG 0x08000000 |
| 329 | #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 |
| 330 | #define MAC_CFG_HASH_ALG_CRC32 0x20000000 |
| 331 | #define MAC_CFG_SPEED_MODE_SW 0x40000000 |
| 332 | #define MAC_CFG_FAST_PAUSE 0x80000000 |
| 333 | #define MAC_CFG_PREAMBLE_SHIFT 10 |
| 334 | #define MAC_CFG_PREAMBLE_DEFAULT 7 |
| 335 | |
| 336 | #define ALC_IPG_IFG_CFG 0x1484 |
| 337 | #define IPG_IFG_IPGT_MASK 0x0000007F |
| 338 | #define IPG_IFG_MIFG_MASK 0x0000FF00 |
| 339 | #define IPG_IFG_IPG1_MASK 0x007F0000 |
| 340 | #define IPG_IFG_IPG2_MASK 0x7F000000 |
| 341 | #define IPG_IFG_IPGT_SHIFT 0 |
| 342 | #define IPG_IFG_IPGT_DEFAULT 0x60 |
| 343 | #define IPG_IFG_MIFG_SHIFT 8 |
| 344 | #define IPG_IFG_MIFG_DEFAULT 0x50 |
| 345 | #define IPG_IFG_IPG1_SHIFT 16 |
| 346 | #define IPG_IFG_IPG1_DEFAULT 0x40 |
| 347 | #define IPG_IFG_IPG2_SHIFT 24 |
| 348 | #define IPG_IFG_IPG2_DEFAULT 0x60 |
| 349 | |
| 350 | /* Station address. */ |
| 351 | #define ALC_PAR0 0x1488 |
| 352 | #define ALC_PAR1 0x148C |
| 353 | |
| 354 | /* 64bit multicast hash register. */ |
| 355 | #define ALC_MAR0 0x1490 |
| 356 | #define ALC_MAR1 0x1494 |
| 357 | |
| 358 | /* half-duplex parameter configuration. */ |
| 359 | #define ALC_HDPX_CFG 0x1498 |
| 360 | #define HDPX_CFG_LCOL_MASK 0x000003FF |
| 361 | #define HDPX_CFG_RETRY_MASK 0x0000F000 |
| 362 | #define HDPX_CFG_EXC_DEF_EN 0x00010000 |
| 363 | #define HDPX_CFG_NO_BACK_C 0x00020000 |
| 364 | #define HDPX_CFG_NO_BACK_P 0x00040000 |
| 365 | #define HDPX_CFG_ABEBE 0x00080000 |
| 366 | #define HDPX_CFG_ABEBT_MASK 0x00F00000 |
| 367 | #define HDPX_CFG_JAMIPG_MASK 0x0F000000 |
| 368 | #define HDPX_CFG_LCOL_SHIFT 0 |
| 369 | #define HDPX_CFG_LCOL_DEFAULT 0x37 |
| 370 | #define HDPX_CFG_RETRY_SHIFT 12 |
| 371 | #define HDPX_CFG_RETRY_DEFAULT 0x0F |
| 372 | #define HDPX_CFG_ABEBT_SHIFT 20 |
| 373 | #define HDPX_CFG_ABEBT_DEFAULT 0x0A |
| 374 | #define HDPX_CFG_JAMIPG_SHIFT 24 |
| 375 | #define HDPX_CFG_JAMIPG_DEFAULT 0x07 |
| 376 | |
| 377 | #define ALC_FRAME_SIZE 0x149C |
| 378 | |
| 379 | #define ALC_WOL_CFG 0x14A0 |
| 380 | #define WOL_CFG_PATTERN 0x00000001 |
| 381 | #define WOL_CFG_PATTERN_ENB 0x00000002 |
| 382 | #define WOL_CFG_MAGIC 0x00000004 |
| 383 | #define WOL_CFG_MAGIC_ENB 0x00000008 |
| 384 | #define WOL_CFG_LINK_CHG 0x00000010 |
| 385 | #define WOL_CFG_LINK_CHG_ENB 0x00000020 |
| 386 | #define WOL_CFG_PATTERN_DET 0x00000100 |
| 387 | #define WOL_CFG_MAGIC_DET 0x00000200 |
| 388 | #define WOL_CFG_LINK_CHG_DET 0x00000400 |
| 389 | #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 |
| 390 | #define WOL_CFG_PATTERN0 0x00010000 |
| 391 | #define WOL_CFG_PATTERN1 0x00020000 |
| 392 | #define WOL_CFG_PATTERN2 0x00040000 |
| 393 | #define WOL_CFG_PATTERN3 0x00080000 |
| 394 | #define WOL_CFG_PATTERN4 0x00100000 |
| 395 | #define WOL_CFG_PATTERN5 0x00200000 |
| 396 | #define WOL_CFG_PATTERN6 0x00400000 |
| 397 | |
| 398 | /* WOL pattern length. */ |
| 399 | #define ALC_PATTERN_CFG0 0x14A4 |
| 400 | #define PATTERN_CFG_0_LEN_MASK 0x0000007F |
| 401 | #define PATTERN_CFG_1_LEN_MASK 0x00007F00 |
| 402 | #define PATTERN_CFG_2_LEN_MASK 0x007F0000 |
| 403 | #define PATTERN_CFG_3_LEN_MASK 0x7F000000 |
| 404 | |
| 405 | #define ALC_PATTERN_CFG1 0x14A8 |
| 406 | #define PATTERN_CFG_4_LEN_MASK 0x0000007F |
| 407 | #define PATTERN_CFG_5_LEN_MASK 0x00007F00 |
| 408 | #define PATTERN_CFG_6_LEN_MASK 0x007F0000 |
| 409 | |
| 410 | /* RSS */ |
| 411 | #define 0x14B0 |
| 412 | |
| 413 | #define 0x14B4 |
| 414 | |
| 415 | #define 0x14B8 |
| 416 | |
| 417 | #define 0x14BC |
| 418 | |
| 419 | #define 0x14C0 |
| 420 | |
| 421 | #define 0x14C4 |
| 422 | |
| 423 | #define 0x14C8 |
| 424 | |
| 425 | #define 0x14CC |
| 426 | |
| 427 | #define 0x14D0 |
| 428 | |
| 429 | #define 0x14D4 |
| 430 | |
| 431 | #define 0x14E0 |
| 432 | |
| 433 | #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ |
| 434 | |
| 435 | #define 0x14E4 |
| 436 | |
| 437 | #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ |
| 438 | |
| 439 | #define 0x14E8 |
| 440 | |
| 441 | #define 0x14EC |
| 442 | |
| 443 | #define 0x14F0 |
| 444 | |
| 445 | #define 0x14F4 |
| 446 | |
| 447 | #define 0x14F8 |
| 448 | |
| 449 | #define 0x14FC |
| 450 | |
| 451 | #define ALC_SRAM_RD0_ADDR 0x1500 |
| 452 | |
| 453 | #define ALC_SRAM_RD1_ADDR 0x1504 |
| 454 | |
| 455 | #define ALC_SRAM_RD2_ADDR 0x1508 |
| 456 | |
| 457 | #define ALC_SRAM_RD3_ADDR 0x150C |
| 458 | |
| 459 | #define RD_HEAD_ADDR_MASK 0x000003FF |
| 460 | #define RD_TAIL_ADDR_MASK 0x03FF0000 |
| 461 | #define RD_HEAD_ADDR_SHIFT 0 |
| 462 | #define RD_TAIL_ADDR_SHIFT 16 |
| 463 | |
| 464 | #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ |
| 465 | #define RD_NIC_LEN_MASK 0x000003FF |
| 466 | |
| 467 | #define ALC_RD_NIC_LEN1 0x1514 |
| 468 | |
| 469 | #define ALC_SRAM_TD_ADDR 0x1518 |
| 470 | #define TD_HEAD_ADDR_MASK 0x000003FF |
| 471 | #define TD_TAIL_ADDR_MASK 0x03FF0000 |
| 472 | #define TD_HEAD_ADDR_SHIFT 0 |
| 473 | #define TD_TAIL_ADDR_SHIFT 16 |
| 474 | |
| 475 | #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ |
| 476 | #define SRAM_TD_LEN_MASK 0x000003FF |
| 477 | |
| 478 | #define ALC_SRAM_RX_FIFO_ADDR 0x1520 |
| 479 | |
| 480 | #define ALC_SRAM_RX_FIFO_LEN 0x1524 |
| 481 | #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF |
| 482 | #define SRAM_RX_FIFO_LEN_SHIFT 0 |
| 483 | |
| 484 | #define ALC_SRAM_TX_FIFO_ADDR 0x1528 |
| 485 | |
| 486 | #define ALC_SRAM_TX_FIFO_LEN 0x152C |
| 487 | |
| 488 | #define ALC_SRAM_TCPH_ADDR 0x1530 |
| 489 | #define SRAM_TCPH_ADDR_MASK 0x00000FFF |
| 490 | #define SRAM_PATH_ADDR_MASK 0x0FFF0000 |
| 491 | #define SRAM_TCPH_ADDR_SHIFT 0 |
| 492 | #define SRAM_PKTH_ADDR_SHIFT 16 |
| 493 | |
| 494 | #define ALC_DMA_BLOCK 0x1534 |
| 495 | #define DMA_BLOCK_LOAD 0x00000001 |
| 496 | |
| 497 | #define ALC_RX_BASE_ADDR_HI 0x1540 |
| 498 | |
| 499 | #define ALC_TX_BASE_ADDR_HI 0x1544 |
| 500 | |
| 501 | #define ALC_SMB_BASE_ADDR_HI 0x1548 |
| 502 | |
| 503 | #define ALC_SMB_BASE_ADDR_LO 0x154C |
| 504 | |
| 505 | #define ALC_RD0_HEAD_ADDR_LO 0x1550 |
| 506 | |
| 507 | #define ALC_RD1_HEAD_ADDR_LO 0x1554 |
| 508 | |
| 509 | #define ALC_RD2_HEAD_ADDR_LO 0x1558 |
| 510 | |
| 511 | #define ALC_RD3_HEAD_ADDR_LO 0x155C |
| 512 | |
| 513 | #define ALC_RD_RING_CNT 0x1560 |
| 514 | #define RD_RING_CNT_MASK 0x00000FFF |
| 515 | #define RD_RING_CNT_SHIFT 0 |
| 516 | |
| 517 | #define ALC_RX_BUF_SIZE 0x1564 |
| 518 | #define RX_BUF_SIZE_MASK 0x0000FFFF |
| 519 | /* |
| 520 | * If larger buffer size than 1536 is specified the controller |
| 521 | * will be locked up. This is hardware limitation. |
| 522 | */ |
| 523 | #define RX_BUF_SIZE_MAX 1536 |
| 524 | |
| 525 | #define ALC_RRD0_HEAD_ADDR_LO 0x1568 |
| 526 | |
| 527 | #define ALC_RRD1_HEAD_ADDR_LO 0x156C |
| 528 | |
| 529 | #define ALC_RRD2_HEAD_ADDR_LO 0x1570 |
| 530 | |
| 531 | #define ALC_RRD3_HEAD_ADDR_LO 0x1574 |
| 532 | |
| 533 | #define ALC_RRD_RING_CNT 0x1578 |
| 534 | #define RRD_RING_CNT_MASK 0x00000FFF |
| 535 | #define RRD_RING_CNT_SHIFT 0 |
| 536 | |
| 537 | #define ALC_TDH_HEAD_ADDR_LO 0x157C |
| 538 | |
| 539 | #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ |
| 540 | |
| 541 | #define ALC_TDL_HEAD_ADDR_LO 0x1580 |
| 542 | |
| 543 | #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ |
| 544 | |
| 545 | #define ALC_TD_RING_CNT 0x1584 |
| 546 | #define TD_RING_CNT_MASK 0x0000FFFF |
| 547 | #define TD_RING_CNT_SHIFT 0 |
| 548 | |
| 549 | #define ALC_CMB_BASE_ADDR_LO 0x1588 |
| 550 | |
| 551 | #define ALC_TXQ_CFG 0x1590 |
| 552 | #define TXQ_CFG_TD_BURST_MASK 0x0000000F |
| 553 | #define TXQ_CFG_IP_OPTION_ENB 0x00000010 |
| 554 | #define TXQ_CFG_ENB 0x00000020 |
| 555 | #define TXQ_CFG_ENHANCED_MODE 0x00000040 |
| 556 | #define TXQ_CFG_8023_ENB 0x00000080 |
| 557 | #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 |
| 558 | #define TXQ_CFG_TD_BURST_SHIFT 0 |
| 559 | #define TXQ_CFG_TD_BURST_DEFAULT 5 |
| 560 | #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 |
| 561 | |
| 562 | #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ |
| 563 | #define TSO_OFFLOAD_THRESH_MASK 0x000007FF |
| 564 | #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 |
| 565 | #define TSO_OFFLOAD_THRESH_SHIFT 0 |
| 566 | #define TSO_OFFLOAD_THRESH_UNIT 8 |
| 567 | #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 |
| 568 | |
| 569 | #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ |
| 570 | #define TXF_WATER_MARK_HI_MASK 0x00000FFF |
| 571 | #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 |
| 572 | #define TXF_WATER_MARK_BURST_ENB 0x80000000 |
| 573 | #define TXF_WATER_MARK_LO_SHIFT 0 |
| 574 | #define TXF_WATER_MARK_HI_SHIFT 16 |
| 575 | |
| 576 | #define ALC_THROUGHPUT_MON 0x159C |
| 577 | #define THROUGHPUT_MON_RATE_MASK 0x00000003 |
| 578 | #define THROUGHPUT_MON_ENB 0x00000080 |
| 579 | #define THROUGHPUT_MON_RATE_SHIFT 0 |
| 580 | |
| 581 | #define ALC_RXQ_CFG 0x15A0 |
| 582 | #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 |
| 583 | #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 |
| 584 | #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 |
| 585 | #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 |
| 586 | #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 |
| 587 | #define RXQ_CFG_QUEUE1_ENB 0x00000010 |
| 588 | #define RXQ_CFG_QUEUE2_ENB 0x00000020 |
| 589 | #define RXQ_CFG_QUEUE3_ENB 0x00000040 |
| 590 | #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 |
| 591 | #define 0x0000FF00 |
| 592 | #define 0x00010000 |
| 593 | #define 0x00020000 |
| 594 | #define 0x00040000 |
| 595 | #define 0x00080000 |
| 596 | #define RXQ_CFG_RD_BURST_MASK 0x03F00000 |
| 597 | #define 0x00000000 |
| 598 | #define 0x04000000 |
| 599 | #define 0x08000000 |
| 600 | #define 0x0C000000 |
| 601 | #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 |
| 602 | #define 0x20000000 |
| 603 | #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 |
| 604 | #define RXQ_CFG_QUEUE0_ENB 0x80000000 |
| 605 | #define 8 |
| 606 | #define RXQ_CFG_RD_BURST_DEFAULT 8 |
| 607 | #define RXQ_CFG_RD_BURST_SHIFT 20 |
| 608 | #define RXQ_CFG_ENB \ |
| 609 | (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ |
| 610 | RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) |
| 611 | |
| 612 | /* AR816x specific bits */ |
| 613 | #define 0x00000004 |
| 614 | #define 0x00000008 |
| 615 | #define 0x00000010 |
| 616 | #define 0x00000020 |
| 617 | #define 0x0000003C |
| 618 | #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 |
| 619 | #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 |
| 620 | #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 |
| 621 | #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 |
| 622 | |
| 623 | #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ |
| 624 | #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F |
| 625 | #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 |
| 626 | #define RX_RD_FREE_THRESH_HI_SHIFT 0 |
| 627 | #define RX_RD_FREE_THRESH_LO_SHIFT 6 |
| 628 | #define RX_RD_FREE_THRESH_HI_DEFAULT 16 |
| 629 | #define RX_RD_FREE_THRESH_LO_DEFAULT 8 |
| 630 | |
| 631 | #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 |
| 632 | #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF |
| 633 | #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 |
| 634 | #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 |
| 635 | #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 |
| 636 | /* |
| 637 | * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + |
| 638 | * rx-packet(1522) + delay-of-link(64) |
| 639 | * = 3212. |
| 640 | */ |
| 641 | #define RX_FIFO_PAUSE_816X_RSVD 3212 |
| 642 | |
| 643 | #define ALC_RD_DMA_CFG 0x15AC |
| 644 | #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ |
| 645 | #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 |
| 646 | #define RD_DMA_CFG_THRESH_SHIFT 0 |
| 647 | #define RD_DMA_CFG_TIMER_SHIFT 16 |
| 648 | #define RD_DMA_CFG_THRESH_DEFAULT 0x100 |
| 649 | #define RD_DMA_CFG_TIMER_DEFAULT 0 |
| 650 | #define RD_DMA_CFG_TICK_USECS 8 |
| 651 | #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) |
| 652 | |
| 653 | #define 0x15B0 |
| 654 | |
| 655 | #define 0x15B4 |
| 656 | |
| 657 | #define 0x15B8 |
| 658 | |
| 659 | #define ALC_DMA_CFG 0x15C0 |
| 660 | #define DMA_CFG_IN_ORDER 0x00000001 |
| 661 | #define DMA_CFG_ENH_ORDER 0x00000002 |
| 662 | #define DMA_CFG_OUT_ORDER 0x00000004 |
| 663 | #define DMA_CFG_RCB_64 0x00000000 |
| 664 | #define DMA_CFG_RCB_128 0x00000008 |
| 665 | #define DMA_CFG_PEND_AUTO_RST 0x00000008 |
| 666 | #define DMA_CFG_RD_BURST_128 0x00000000 |
| 667 | #define DMA_CFG_RD_BURST_256 0x00000010 |
| 668 | #define DMA_CFG_RD_BURST_512 0x00000020 |
| 669 | #define DMA_CFG_RD_BURST_1024 0x00000030 |
| 670 | #define DMA_CFG_RD_BURST_2048 0x00000040 |
| 671 | #define DMA_CFG_RD_BURST_4096 0x00000050 |
| 672 | #define DMA_CFG_WR_BURST_128 0x00000000 |
| 673 | #define DMA_CFG_WR_BURST_256 0x00000080 |
| 674 | #define DMA_CFG_WR_BURST_512 0x00000100 |
| 675 | #define DMA_CFG_WR_BURST_1024 0x00000180 |
| 676 | #define DMA_CFG_WR_BURST_2048 0x00000200 |
| 677 | #define DMA_CFG_WR_BURST_4096 0x00000280 |
| 678 | #define DMA_CFG_RD_REQ_PRI 0x00000400 |
| 679 | #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 |
| 680 | #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 |
| 681 | #define DMA_CFG_CMB_ENB 0x00100000 |
| 682 | #define DMA_CFG_SMB_ENB 0x00200000 |
| 683 | #define DMA_CFG_CMB_NOW 0x00400000 |
| 684 | #define DMA_CFG_SMB_DIS 0x01000000 |
| 685 | #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 |
| 686 | #define DMA_CFG_RD_CHNL_SEL_1 0x00000000 |
| 687 | #define DMA_CFG_RD_CHNL_SEL_2 0x04000000 |
| 688 | #define DMA_CFG_RD_CHNL_SEL_3 0x08000000 |
| 689 | #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 |
| 690 | #define DMA_CFG_WSRAM_RDCTL 0x10000000 |
| 691 | #define DMA_CFG_RD_PEND_CLR 0x20000000 |
| 692 | #define DMA_CFG_WR_PEND_CLR 0x40000000 |
| 693 | #define DMA_CFG_SMB_NOW 0x80000000 |
| 694 | #define DMA_CFG_RD_BURST_MASK 0x07 |
| 695 | #define DMA_CFG_RD_BURST_SHIFT 4 |
| 696 | #define DMA_CFG_WR_BURST_MASK 0x07 |
| 697 | #define DMA_CFG_WR_BURST_SHIFT 7 |
| 698 | #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 |
| 699 | #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 |
| 700 | #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 |
| 701 | #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 |
| 702 | |
| 703 | #define ALC_SMB_STAT_TIMER 0x15C4 |
| 704 | #define SMB_STAT_TIMER_MASK 0x00FFFFFF |
| 705 | #define SMB_STAT_TIMER_SHIFT 0 |
| 706 | |
| 707 | #define ALC_CMB_TD_THRESH 0x15C8 |
| 708 | #define CMB_TD_THRESH_MASK 0x0000FFFF |
| 709 | #define CMB_TD_THRESH_SHIFT 0 |
| 710 | |
| 711 | #define ALC_CMB_TX_TIMER 0x15CC |
| 712 | #define CMB_TX_TIMER_MASK 0x0000FFFF |
| 713 | #define CMB_TX_TIMER_SHIFT 0 |
| 714 | |
| 715 | #define ALC_MSI_MAP_TBL1 0x15D0 |
| 716 | |
| 717 | #define ALC_MSI_ID_MAP 0x15D4 |
| 718 | |
| 719 | #define ALC_MSI_MAP_TBL2 0x15D8 |
| 720 | |
| 721 | #define ALC_MBOX_RD0_PROD_IDX 0x15E0 |
| 722 | |
| 723 | #define ALC_MBOX_RD1_PROD_IDX 0x15E4 |
| 724 | |
| 725 | #define ALC_MBOX_RD2_PROD_IDX 0x15E8 |
| 726 | |
| 727 | #define ALC_MBOX_RD3_PROD_IDX 0x15EC |
| 728 | |
| 729 | #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF |
| 730 | #define MBOX_RD_PROD_SHIFT 0 |
| 731 | |
| 732 | #define ALC_MBOX_TD_PROD_IDX 0x15F0 |
| 733 | #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF |
| 734 | #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 |
| 735 | #define MBOX_TD_PROD_HI_IDX_SHIFT 0 |
| 736 | #define MBOX_TD_PROD_LO_IDX_SHIFT 16 |
| 737 | |
| 738 | #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ |
| 739 | |
| 740 | #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ |
| 741 | |
| 742 | #define ALC_MBOX_TD_CONS_IDX 0x15F4 |
| 743 | #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF |
| 744 | #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 |
| 745 | #define MBOX_TD_CONS_HI_IDX_SHIFT 0 |
| 746 | #define MBOX_TD_CONS_LO_IDX_SHIFT 16 |
| 747 | |
| 748 | #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ |
| 749 | |
| 750 | #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ |
| 751 | |
| 752 | #define ALC_MBOX_RD01_CONS_IDX 0x15F8 |
| 753 | #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF |
| 754 | #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 |
| 755 | #define MBOX_RD0_CONS_IDX_SHIFT 0 |
| 756 | #define MBOX_RD1_CONS_IDX_SHIFT 16 |
| 757 | |
| 758 | #define ALC_MBOX_RD23_CONS_IDX 0x15FC |
| 759 | #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF |
| 760 | #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 |
| 761 | #define MBOX_RD2_CONS_IDX_SHIFT 0 |
| 762 | #define MBOX_RD3_CONS_IDX_SHIFT 16 |
| 763 | |
| 764 | #define ALC_INTR_STATUS 0x1600 |
| 765 | #define INTR_SMB 0x00000001 |
| 766 | #define INTR_TIMER 0x00000002 |
| 767 | #define INTR_MANUAL_TIMER 0x00000004 |
| 768 | #define INTR_RX_FIFO_OFLOW 0x00000008 |
| 769 | #define INTR_RD0_UNDERRUN 0x00000010 |
| 770 | #define INTR_RD1_UNDERRUN 0x00000020 |
| 771 | #define INTR_RD2_UNDERRUN 0x00000040 |
| 772 | #define INTR_RD3_UNDERRUN 0x00000080 |
| 773 | #define INTR_TX_FIFO_UNDERRUN 0x00000100 |
| 774 | #define INTR_DMA_RD_TO_RST 0x00000200 |
| 775 | #define INTR_DMA_WR_TO_RST 0x00000400 |
| 776 | #define INTR_TX_CREDIT 0x00000800 |
| 777 | #define INTR_GPHY 0x00001000 |
| 778 | #define INTR_GPHY_LOW_PW 0x00002000 |
| 779 | #define INTR_TXQ_TO_RST 0x00004000 |
| 780 | #define INTR_TX_PKT0 0x00008000 |
| 781 | #define INTR_RX_PKT0 0x00010000 |
| 782 | #define INTR_RX_PKT1 0x00020000 |
| 783 | #define INTR_RX_PKT2 0x00040000 |
| 784 | #define INTR_RX_PKT3 0x00080000 |
| 785 | #define INTR_MAC_RX 0x00100000 |
| 786 | #define INTR_MAC_TX 0x00200000 |
| 787 | #define INTR_UNDERRUN 0x00400000 |
| 788 | #define INTR_FRAME_ERROR 0x00800000 |
| 789 | #define INTR_FRAME_OK 0x01000000 |
| 790 | #define INTR_CSUM_ERROR 0x02000000 |
| 791 | #define INTR_PHY_LINK_DOWN 0x04000000 |
| 792 | #define INTR_DIS_INT 0x80000000 |
| 793 | |
| 794 | /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ |
| 795 | #define INTR_TX_PKT1 0x00000020 |
| 796 | #define INTR_TX_PKT2 0x00000040 |
| 797 | #define INTR_TX_PKT3 0x00000080 |
| 798 | #define INTR_RX_PKT4 0x08000000 |
| 799 | #define INTR_RX_PKT5 0x10000000 |
| 800 | #define INTR_RX_PKT6 0x20000000 |
| 801 | #define INTR_RX_PKT7 0x40000000 |
| 802 | |
| 803 | /* Interrupt Mask Register */ |
| 804 | #define ALC_INTR_MASK 0x1604 |
| 805 | |
| 806 | #ifdef notyet |
| 807 | #define INTR_RX_PKT \ |
| 808 | (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ |
| 809 | INTR_RX_PKT3) |
| 810 | #define INTR_RD_UNDERRUN \ |
| 811 | (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ |
| 812 | INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) |
| 813 | #else |
| 814 | #define INTR_TX_PKT INTR_TX_PKT0 |
| 815 | #define INTR_RX_PKT INTR_RX_PKT0 |
| 816 | #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN |
| 817 | #endif |
| 818 | |
| 819 | #define ALC_INTRS \ |
| 820 | (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ |
| 821 | INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ |
| 822 | INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ |
| 823 | INTR_TX_FIFO_UNDERRUN) |
| 824 | |
| 825 | #define ALC_INTR_RETRIG_TIMER 0x1608 |
| 826 | #define INTR_RETRIG_TIMER_MASK 0x0000FFFF |
| 827 | #define INTR_RETRIG_TIMER_SHIFT 0 |
| 828 | |
| 829 | #define ALC_HDS_CFG 0x160C |
| 830 | #define HDS_CFG_ENB 0x00000001 |
| 831 | #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 |
| 832 | #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 |
| 833 | #define HDS_CFG_BACKFILLSIZE_SHIFT 8 |
| 834 | #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 |
| 835 | |
| 836 | #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ |
| 837 | |
| 838 | #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ |
| 839 | |
| 840 | #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ |
| 841 | |
| 842 | #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ |
| 843 | |
| 844 | /* AR813x/AR815x registers for MAC statistics */ |
| 845 | #define ALC_RX_MIB_BASE 0x1700 |
| 846 | |
| 847 | #define ALC_TX_MIB_BASE 0x1760 |
| 848 | |
| 849 | #define ALC_DRV 0x1804 /* AR816x */ |
| 850 | #define DRV_ASPM_SPD10LMT_1M 0x00000000 |
| 851 | #define DRV_ASPM_SPD10LMT_10M 0x00000001 |
| 852 | #define DRV_ASPM_SPD10LMT_100M 0x00000002 |
| 853 | #define DRV_ASPM_SPD10LMT_NO 0x00000003 |
| 854 | #define DRV_ASPM_SPD10LMT_MASK 0x00000003 |
| 855 | #define DRV_ASPM_SPD100LMT_1M 0x00000000 |
| 856 | #define DRV_ASPM_SPD100LMT_10M 0x00000004 |
| 857 | #define DRV_ASPM_SPD100LMT_100M 0x00000008 |
| 858 | #define DRV_ASPM_SPD100LMT_NO 0x0000000C |
| 859 | #define DRV_ASPM_SPD100LMT_MASK 0x0000000C |
| 860 | #define DRV_ASPM_SPD1000LMT_100M 0x00000000 |
| 861 | #define DRV_ASPM_SPD1000LMT_NO 0x00000010 |
| 862 | #define DRV_ASPM_SPD1000LMT_1M 0x00000020 |
| 863 | #define DRV_ASPM_SPD1000LMT_10M 0x00000030 |
| 864 | #define DRV_ASPM_SPD1000LMT_MASK 0x00000000 |
| 865 | #define DRV_WOLCAP_BIOS_EN 0x00000100 |
| 866 | #define DRV_WOLMAGIC_EN 0x00000200 |
| 867 | #define DRV_WOLLINKUP_EN 0x00000400 |
| 868 | #define DRV_WOLPATTERN_EN 0x00000800 |
| 869 | #define DRV_AZ_EN 0x00001000 |
| 870 | #define DRV_WOLS5_BIOS_EN 0x00010000 |
| 871 | #define DRV_WOLS5_EN 0x00020000 |
| 872 | #define DRV_DISABLE 0x00040000 |
| 873 | #define DRV_PHY_MASK 0x1FE00000 |
| 874 | #define DRV_PHY_EEE 0x00200000 |
| 875 | #define DRV_PHY_APAUSE 0x00400000 |
| 876 | #define DRV_PHY_PAUSE 0x00800000 |
| 877 | #define DRV_PHY_DUPLEX 0x01000000 |
| 878 | #define DRV_PHY_10 0x02000000 |
| 879 | #define DRV_PHY_100 0x04000000 |
| 880 | #define DRV_PHY_1000 0x08000000 |
| 881 | #define DRV_PHY_AUTO 0x10000000 |
| 882 | #define DRV_PHY_SHIFT 21 |
| 883 | |
| 884 | #define ALC_CLK_GATING_CFG 0x1814 |
| 885 | #define CLK_GATING_DMAW_ENB 0x0001 |
| 886 | #define CLK_GATING_DMAR_ENB 0x0002 |
| 887 | #define CLK_GATING_TXQ_ENB 0x0004 |
| 888 | #define CLK_GATING_RXQ_ENB 0x0008 |
| 889 | #define CLK_GATING_TXMAC_ENB 0x0010 |
| 890 | #define CLK_GATING_RXMAC_ENB 0x0020 |
| 891 | |
| 892 | #define ALC_DEBUG_DATA0 0x1900 |
| 893 | |
| 894 | #define ALC_DEBUG_DATA1 0x1904 |
| 895 | |
| 896 | #define ALC_MSI_RETRANS_TIMER 0x1920 |
| 897 | #define MSI_RETRANS_TIMER_MASK 0x0000FFFF |
| 898 | #define MSI_RETRANS_MASK_SEL_STD 0x00000000 |
| 899 | #define MSI_RETRANS_MASK_SEL_LINE 0x00010000 |
| 900 | #define MSI_RETRANS_TIMER_SHIFT 0 |
| 901 | |
| 902 | #define ALC_WRR 0x1938 |
| 903 | #define WRR_PRI0_MASK 0x0000001F |
| 904 | #define WRR_PRI1_MASK 0x00001F00 |
| 905 | #define WRR_PRI2_MASK 0x001F0000 |
| 906 | #define WRR_PRI3_MASK 0x1F000000 |
| 907 | #define WRR_PRI_RESTRICT_MASK 0x60000000 |
| 908 | #define WRR_PRI_RESTRICT_ALL 0x00000000 |
| 909 | #define WRR_PRI_RESTRICT_HI 0x20000000 |
| 910 | #define WRR_PRI_RESTRICT_HI2 0x40000000 |
| 911 | #define WRR_PRI_RESTRICT_NONE 0x60000000 |
| 912 | #define WRR_PRI0_SHIFT 0 |
| 913 | #define WRR_PRI1_SHIFT 8 |
| 914 | #define WRR_PRI2_SHIFT 16 |
| 915 | #define WRR_PRI3_SHIFT 24 |
| 916 | #define WRR_PRI_DEFAULT 4 |
| 917 | #define WRR_PRI_RESTRICT_SHIFT 29 |
| 918 | |
| 919 | #define ALC_HQTD_CFG 0x193C |
| 920 | #define HQTD_CFG_Q1_BURST_MASK 0x0000000F |
| 921 | #define HQTD_CFG_Q2_BURST_MASK 0x000000F0 |
| 922 | #define HQTD_CFG_Q3_BURST_MASK 0x00000F00 |
| 923 | #define HQTD_CFG_BURST_ENB 0x80000000 |
| 924 | #define HQTD_CFG_Q1_BURST_SHIFT 0 |
| 925 | #define HQTD_CFG_Q2_BURST_SHIFT 4 |
| 926 | #define HQTD_CFG_Q3_BURST_SHIFT 8 |
| 927 | |
| 928 | #define ALC_MISC 0x19C0 |
| 929 | #define MISC_INTNLOSC_OPEN 0x00000008 |
| 930 | #define MISC_ISO_ENB 0x00001000 |
| 931 | #define MISC_PSW_OCP_MASK 0x00E00000 |
| 932 | #define MISC_PSW_OCP_SHIFT 21 |
| 933 | #define MISC_PSW_OCP_DEFAULT 7 |
| 934 | |
| 935 | #define ALC_MISC2 0x19C8 |
| 936 | #define MISC2_CALB_START 0x00000001 |
| 937 | |
| 938 | #define ALC_MISC3 0x19CC |
| 939 | #define MISC3_25M_NOTO_INTNL 0x00000001 |
| 940 | #define MISC3_25M_BY_SW 0x00000002 |
| 941 | |
| 942 | #define ALC_MII_DBG_ADDR 0x1D |
| 943 | #define ALC_MII_DBG_DATA 0x1E |
| 944 | |
| 945 | #define MII_ANA_CFG0 0x00 |
| 946 | #define ANA_RESTART_CAL 0x0001 |
| 947 | #define ANA_MANUL_SWICH_ON_MASK 0x001E |
| 948 | #define ANA_MAN_ENABLE 0x0020 |
| 949 | #define ANA_SEL_HSP 0x0040 |
| 950 | #define ANA_EN_HB 0x0080 |
| 951 | #define ANA_EN_HBIAS 0x0100 |
| 952 | #define ANA_OEN_125M 0x0200 |
| 953 | #define ANA_EN_LCKDT 0x0400 |
| 954 | #define ANA_LCKDT_PHY 0x0800 |
| 955 | #define ANA_AFE_MODE 0x1000 |
| 956 | #define ANA_VCO_SLOW 0x2000 |
| 957 | #define ANA_VCO_FAST 0x4000 |
| 958 | #define ANA_SEL_CLK125M_DSP 0x8000 |
| 959 | #define ANA_MANUL_SWICH_ON_SHIFT 1 |
| 960 | |
| 961 | #define MII_DBG_ANACTL 0x00 |
| 962 | #define DBG_ANACTL_DEFAULT 0x02EF |
| 963 | |
| 964 | #define MII_ANA_CFG4 0x04 |
| 965 | #define ANA_IECHO_ADJ_MASK 0x0F |
| 966 | #define ANA_IECHO_ADJ_3_MASK 0x000F |
| 967 | #define ANA_IECHO_ADJ_2_MASK 0x00F0 |
| 968 | #define ANA_IECHO_ADJ_1_MASK 0x0F00 |
| 969 | #define ANA_IECHO_ADJ_0_MASK 0xF000 |
| 970 | #define ANA_IECHO_ADJ_3_SHIFT 0 |
| 971 | #define ANA_IECHO_ADJ_2_SHIFT 4 |
| 972 | #define ANA_IECHO_ADJ_1_SHIFT 8 |
| 973 | #define ANA_IECHO_ADJ_0_SHIFT 12 |
| 974 | |
| 975 | #define MII_DBG_SYSMODCTL 0x04 |
| 976 | #define DBG_SYSMODCTL_DEFAULT 0xBB8B |
| 977 | |
| 978 | #define MII_ANA_CFG5 0x05 |
| 979 | #define ANA_SERDES_CDR_BW_MASK 0x0003 |
| 980 | #define ANA_MS_PAD_DBG 0x0004 |
| 981 | #define ANA_SPEEDUP_DBG 0x0008 |
| 982 | #define ANA_SERDES_TH_LOS_MASK 0x0030 |
| 983 | #define ANA_SERDES_EN_DEEM 0x0040 |
| 984 | #define ANA_SERDES_TXELECIDLE 0x0080 |
| 985 | #define ANA_SERDES_BEACON 0x0100 |
| 986 | #define ANA_SERDES_HALFTXDR 0x0200 |
| 987 | #define ANA_SERDES_SEL_HSP 0x0400 |
| 988 | #define ANA_SERDES_EN_PLL 0x0800 |
| 989 | #define ANA_SERDES_EN 0x1000 |
| 990 | #define ANA_SERDES_EN_LCKDT 0x2000 |
| 991 | #define ANA_SERDES_CDR_BW_SHIFT 0 |
| 992 | #define ANA_SERDES_TH_LOS_SHIFT 4 |
| 993 | |
| 994 | #define MII_DBG_SRDSYSMOD 0x05 |
| 995 | #define DBG_SRDSYSMOD_DEFAULT 0x2C46 |
| 996 | |
| 997 | #define MII_ANA_CFG11 0x0B |
| 998 | #define ANA_PS_HIB_EN 0x8000 |
| 999 | |
| 1000 | #define MII_DBG_HIBNEG 0x0B |
| 1001 | #define DBG_HIBNEG_HIB_PULSE 0x1000 |
| 1002 | #define DBG_HIBNEG_PSHIB_EN 0x8000 |
| 1003 | #define DBG_HIBNEG_DEFAULT 0xBC40 |
| 1004 | |
| 1005 | #define MII_ANA_CFG18 0x12 |
| 1006 | #define ANA_TEST_MODE_10BT_01MASK 0x0003 |
| 1007 | #define ANA_LOOP_SEL_10BT 0x0004 |
| 1008 | #define ANA_RGMII_MODE_SW 0x0008 |
| 1009 | #define ANA_EN_LONGECABLE 0x0010 |
| 1010 | #define ANA_TEST_MODE_10BT_2 0x0020 |
| 1011 | #define ANA_EN_10BT_IDLE 0x0400 |
| 1012 | #define ANA_EN_MASK_TB 0x0800 |
| 1013 | #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 |
| 1014 | #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 |
| 1015 | #define ANA_TEST_MODE_10BT_01SHIFT 0 |
| 1016 | #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 |
| 1017 | #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 |
| 1018 | |
| 1019 | #define MII_DBG_TST10BTCFG 0x12 |
| 1020 | #define DBG_TST10BTCFG_DEFAULT 0x4C04 |
| 1021 | |
| 1022 | #define MII_DBG_AZ_ANADECT 0x15 |
| 1023 | #define DBG_AZ_ANADECT_DEFAULT 0x3220 |
| 1024 | #define DBG_AZ_ANADECT_LONG 0x3210 |
| 1025 | |
| 1026 | #define MII_DBG_MSE16DB 0x18 |
| 1027 | #define DBG_MSE16DB_UP 0x05EA |
| 1028 | #define DBG_MSE16DB_DOWN 0x02EA |
| 1029 | |
| 1030 | #define MII_DBG_MSE20DB 0x1C |
| 1031 | #define DBG_MSE20DB_TH_MASK 0x01FC |
| 1032 | #define DBG_MSE20DB_TH_DEFAULT 0x2E |
| 1033 | #define DBG_MSE20DB_TH_HI 0x54 |
| 1034 | #define DBG_MSE20DB_TH_SHIFT 2 |
| 1035 | |
| 1036 | #define MII_DBG_AGC 0x23 |
| 1037 | #define DBG_AGC_2_VGA_MASK 0x3F00 |
| 1038 | #define DBG_AGC_2_VGA_SHIFT 8 |
| 1039 | #define DBG_AGC_LONG1G_LIMT 40 |
| 1040 | #define DBG_AGC_LONG100M_LIMT 44 |
| 1041 | |
| 1042 | #define MII_ANA_CFG41 0x29 |
| 1043 | #define ANA_TOP_PS_EN 0x8000 |
| 1044 | |
| 1045 | #define MII_DBG_LEGCYPS 0x29 |
| 1046 | #define DBG_LEGCYPS_ENB 0x8000 |
| 1047 | #define DBG_LEGCYPS_DEFAULT 0x129D |
| 1048 | |
| 1049 | #define MII_ANA_CFG54 0x36 |
| 1050 | #define ANA_LONG_CABLE_TH_100_MASK 0x003F |
| 1051 | #define ANA_DESERVED 0x0040 |
| 1052 | #define ANA_EN_LIT_CH 0x0080 |
| 1053 | #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 |
| 1054 | #define ANA_BP_BAD_LINK_ACCUM 0x4000 |
| 1055 | #define ANA_BP_SMALL_BW 0x8000 |
| 1056 | #define ANA_LONG_CABLE_TH_100_SHIFT 0 |
| 1057 | #define ANA_SHORT_CABLE_TH_100_SHIFT 8 |
| 1058 | |
| 1059 | #define MII_DBG_TST100BTCFG 0x36 |
| 1060 | #define DBG_TST100BTCFG_DEFAULT 0xE12C |
| 1061 | |
| 1062 | #define MII_DBG_GREENCFG 0x3B |
| 1063 | #define DBG_GREENCFG_DEFAULT 0x7078 |
| 1064 | |
| 1065 | #define MII_DBG_GREENCFG2 0x3D |
| 1066 | #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 |
| 1067 | #define DBG_GREENCFG2_BP_GREEN 0x8000 |
| 1068 | |
| 1069 | /* Device addr 3 */ |
| 1070 | #define MII_EXT_PCS 3 |
| 1071 | |
| 1072 | #define MII_EXT_CLDCTL3 0x8003 |
| 1073 | #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 |
| 1074 | |
| 1075 | #define MII_EXT_CLDCTL5 0x8005 |
| 1076 | #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 |
| 1077 | |
| 1078 | #define MII_EXT_CLDCTL6 0x8006 |
| 1079 | #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF |
| 1080 | #define EXT_CLDCTL6_CAB_LEN_SHIFT 0 |
| 1081 | #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 |
| 1082 | #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 |
| 1083 | |
| 1084 | #define MII_EXT_VDRVBIAS 0x8062 |
| 1085 | #define EXT_VDRVBIAS_DEFAULT 3 |
| 1086 | |
| 1087 | /* Device addr 7 */ |
| 1088 | #define MII_EXT_ANEG 7 |
| 1089 | |
| 1090 | #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C |
| 1091 | #define ANEG_LOCA_EEEADV_100BT 0x0002 |
| 1092 | #define ANEG_LOCA_EEEADV_1000BT 0x0004 |
| 1093 | |
| 1094 | #define MII_EXT_ANEG_AFE 0x801A |
| 1095 | #define ANEG_AFEE_10BT_100M_TH 0x0040 |
| 1096 | |
| 1097 | #define MII_EXT_ANEG_S3DIG10 0x8023 |
| 1098 | #define ANEG_S3DIG10_SL 0x0001 |
| 1099 | #define ANEG_S3DIG10_DEFAULT 0 |
| 1100 | |
| 1101 | #define MII_EXT_ANEG_NLP78 0x8027 |
| 1102 | #define ANEG_NLP78_120M_DEFAULT 0x8A05 |
| 1103 | |
| 1104 | /* Statistics counters collected by the MAC. */ |
| 1105 | struct smb { |
| 1106 | /* Rx stats. */ |
| 1107 | uint32_t rx_frames; |
| 1108 | uint32_t rx_bcast_frames; |
| 1109 | uint32_t rx_mcast_frames; |
| 1110 | uint32_t rx_pause_frames; |
| 1111 | uint32_t rx_control_frames; |
| 1112 | uint32_t rx_crcerrs; |
| 1113 | uint32_t rx_lenerrs; |
| 1114 | uint32_t rx_bytes; |
| 1115 | uint32_t rx_runts; |
| 1116 | uint32_t rx_fragments; |
| 1117 | uint32_t rx_pkts_64; |
| 1118 | uint32_t rx_pkts_65_127; |
| 1119 | uint32_t rx_pkts_128_255; |
| 1120 | uint32_t rx_pkts_256_511; |
| 1121 | uint32_t rx_pkts_512_1023; |
| 1122 | uint32_t rx_pkts_1024_1518; |
| 1123 | uint32_t rx_pkts_1519_max; |
| 1124 | uint32_t rx_pkts_truncated; |
| 1125 | uint32_t rx_fifo_oflows; |
| 1126 | uint32_t rx_rrs_errs; |
| 1127 | uint32_t rx_alignerrs; |
| 1128 | uint32_t rx_bcast_bytes; |
| 1129 | uint32_t rx_mcast_bytes; |
| 1130 | uint32_t rx_pkts_filtered; |
| 1131 | /* Tx stats. */ |
| 1132 | uint32_t tx_frames; |
| 1133 | uint32_t tx_bcast_frames; |
| 1134 | uint32_t tx_mcast_frames; |
| 1135 | uint32_t tx_pause_frames; |
| 1136 | uint32_t tx_excess_defer; |
| 1137 | uint32_t tx_control_frames; |
| 1138 | uint32_t tx_deferred; |
| 1139 | uint32_t tx_bytes; |
| 1140 | uint32_t tx_pkts_64; |
| 1141 | uint32_t tx_pkts_65_127; |
| 1142 | uint32_t tx_pkts_128_255; |
| 1143 | uint32_t tx_pkts_256_511; |
| 1144 | uint32_t tx_pkts_512_1023; |
| 1145 | uint32_t tx_pkts_1024_1518; |
| 1146 | uint32_t tx_pkts_1519_max; |
| 1147 | uint32_t tx_single_colls; |
| 1148 | uint32_t tx_multi_colls; |
| 1149 | uint32_t tx_late_colls; |
| 1150 | uint32_t tx_excess_colls; |
| 1151 | uint32_t tx_underrun; |
| 1152 | uint32_t tx_desc_underrun; |
| 1153 | uint32_t tx_lenerrs; |
| 1154 | uint32_t tx_pkts_truncated; |
| 1155 | uint32_t tx_bcast_bytes; |
| 1156 | uint32_t tx_mcast_bytes; |
| 1157 | uint32_t updated; |
| 1158 | }; |
| 1159 | |
| 1160 | /* CMB(Coalesing message block) */ |
| 1161 | struct cmb { |
| 1162 | uint32_t cons; |
| 1163 | }; |
| 1164 | |
| 1165 | /* Rx free descriptor */ |
| 1166 | struct rx_desc { |
| 1167 | uint64_t addr; |
| 1168 | }; |
| 1169 | |
| 1170 | /* Rx return descriptor */ |
| 1171 | struct rx_rdesc { |
| 1172 | uint32_t rdinfo; |
| 1173 | #define RRD_CSUM_MASK 0x0000FFFF |
| 1174 | #define RRD_RD_CNT_MASK 0x000F0000 |
| 1175 | #define RRD_RD_IDX_MASK 0xFFF00000 |
| 1176 | #define RRD_CSUM_SHIFT 0 |
| 1177 | #define RRD_RD_CNT_SHIFT 16 |
| 1178 | #define RRD_RD_IDX_SHIFT 20 |
| 1179 | #define RRD_CSUM(x) \ |
| 1180 | (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) |
| 1181 | #define RRD_RD_CNT(x) \ |
| 1182 | (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) |
| 1183 | #define RRD_RD_IDX(x) \ |
| 1184 | (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) |
| 1185 | uint32_t ; |
| 1186 | uint32_t vtag; |
| 1187 | #define RRD_VLAN_MASK 0x0000FFFF |
| 1188 | #define RRD_HEAD_LEN_MASK 0x00FF0000 |
| 1189 | #define RRD_HDS_MASK 0x03000000 |
| 1190 | #define RRD_HDS_NONE 0x00000000 |
| 1191 | #define RRD_HDS_HEAD 0x01000000 |
| 1192 | #define RRD_HDS_DATA 0x02000000 |
| 1193 | #define RRD_CPU_MASK 0x0C000000 |
| 1194 | #define RRD_HASH_FLAG_MASK 0xF0000000 |
| 1195 | #define RRD_VLAN_SHIFT 0 |
| 1196 | #define RRD_HEAD_LEN_SHIFT 16 |
| 1197 | #define RRD_HDS_SHIFT 24 |
| 1198 | #define RRD_CPU_SHIFT 26 |
| 1199 | #define RRD_HASH_FLAG_SHIFT 28 |
| 1200 | #define RRD_VLAN(x) \ |
| 1201 | (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) |
| 1202 | #define RRD_HEAD_LEN(x) \ |
| 1203 | (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) |
| 1204 | #define RRD_CPU(x) \ |
| 1205 | (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) |
| 1206 | uint32_t status; |
| 1207 | #define RRD_LEN_MASK 0x00003FFF |
| 1208 | #define RRD_LEN_SHIFT 0 |
| 1209 | #define RRD_TCP_UDPCSUM_NOK 0x00004000 |
| 1210 | #define RRD_IPCSUM_NOK 0x00008000 |
| 1211 | #define RRD_VLAN_TAG 0x00010000 |
| 1212 | #define RRD_PROTO_MASK 0x000E0000 |
| 1213 | #define RRD_PROTO_IPV4 0x00020000 |
| 1214 | #define RRD_PROTO_IPV6 0x000C0000 |
| 1215 | #define RRD_ERR_SUM 0x00100000 |
| 1216 | #define RRD_ERR_CRC 0x00200000 |
| 1217 | #define RRD_ERR_ALIGN 0x00400000 |
| 1218 | #define RRD_ERR_TRUNC 0x00800000 |
| 1219 | #define RRD_ERR_RUNT 0x01000000 |
| 1220 | #define RRD_ERR_ICMP 0x02000000 |
| 1221 | #define RRD_BCAST 0x04000000 |
| 1222 | #define RRD_MCAST 0x08000000 |
| 1223 | #define RRD_SNAP_LLC 0x10000000 |
| 1224 | #define RRD_ETHER 0x00000000 |
| 1225 | #define RRD_FIFO_FULL 0x20000000 |
| 1226 | #define RRD_ERR_LENGTH 0x40000000 |
| 1227 | #define RRD_VALID 0x80000000 |
| 1228 | #define RRD_BYTES(x) \ |
| 1229 | (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) |
| 1230 | #define RRD_IPV4(x) \ |
| 1231 | (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) |
| 1232 | }; |
| 1233 | |
| 1234 | /* Tx descriptor */ |
| 1235 | struct tx_desc { |
| 1236 | uint32_t len; |
| 1237 | #define TD_BUFLEN_MASK 0x00003FFF |
| 1238 | #define TD_VLAN_MASK 0xFFFF0000 |
| 1239 | #define TD_BUFLEN_SHIFT 0 |
| 1240 | #define TX_BYTES(x) \ |
| 1241 | (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) |
| 1242 | #define TD_VLAN_SHIFT 16 |
| 1243 | uint32_t flags; |
| 1244 | #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ |
| 1245 | #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ |
| 1246 | #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ |
| 1247 | #define TD_CUSTOM_CSUM 0x00000100 |
| 1248 | #define TD_IPCSUM 0x00000200 |
| 1249 | #define TD_TCPCSUM 0x00000400 |
| 1250 | #define TD_UDPCSUM 0x00000800 |
| 1251 | #define TD_TSO 0x00001000 |
| 1252 | #define TD_TSO_DESCV1 0x00000000 |
| 1253 | #define TD_TSO_DESCV2 0x00002000 |
| 1254 | #define TD_CON_VLAN_TAG 0x00004000 |
| 1255 | #define TD_INS_VLAN_TAG 0x00008000 |
| 1256 | #define TD_IPV4_DESCV2 0x00010000 |
| 1257 | #define TD_LLC_SNAP 0x00020000 |
| 1258 | #define TD_ETHERNET 0x00000000 |
| 1259 | #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ |
| 1260 | #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 |
| 1261 | #define TD_MSS_MASK 0x7FFC0000 |
| 1262 | #define TD_EOP 0x80000000 |
| 1263 | #define TD_L4HDR_OFFSET_SHIFT 0 |
| 1264 | #define TD_TCPHDR_OFFSET_SHIFT 0 |
| 1265 | #define TD_PLOAD_OFFSET_SHIFT 0 |
| 1266 | #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 |
| 1267 | #define TD_MSS_SHIFT 18 |
| 1268 | uint64_t addr; |
| 1269 | }; |
| 1270 | |
| 1271 | #define ALC_TX_RING_CNT 256 |
| 1272 | #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) |
| 1273 | #define ALC_RX_RING_CNT 256 |
| 1274 | #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) |
| 1275 | #define ALC_RX_BUF_ALIGN 4 |
| 1276 | #define ALC_RR_RING_CNT ALC_RX_RING_CNT |
| 1277 | #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) |
| 1278 | #define ALC_CMB_ALIGN 8 |
| 1279 | #define ALC_SMB_ALIGN 8 |
| 1280 | |
| 1281 | #define ALC_TSO_MAXSEGSIZE 4096 |
| 1282 | #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) |
| 1283 | #define ALC_MAXTXSEGS 32 |
| 1284 | |
| 1285 | #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) |
| 1286 | #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) |
| 1287 | |
| 1288 | #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) |
| 1289 | |
| 1290 | /* Water mark to kick reclaiming Tx buffers. */ |
| 1291 | #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) |
| 1292 | |
| 1293 | /* |
| 1294 | * AR816x controllers support up to 16 messages but this driver |
| 1295 | * uses single message. |
| 1296 | */ |
| 1297 | #define ALC_MSI_MESSAGES 1 |
| 1298 | #define ALC_MSIX_MESSAGES 1 |
| 1299 | |
| 1300 | #define ALC_TX_RING_SZ \ |
| 1301 | (sizeof(struct tx_desc) * ALC_TX_RING_CNT) |
| 1302 | #define ALC_RX_RING_SZ \ |
| 1303 | (sizeof(struct rx_desc) * ALC_RX_RING_CNT) |
| 1304 | #define ALC_RR_RING_SZ \ |
| 1305 | (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) |
| 1306 | #define ALC_CMB_SZ (sizeof(struct cmb)) |
| 1307 | #define ALC_SMB_SZ (sizeof(struct smb)) |
| 1308 | |
| 1309 | #define ALC_PROC_MIN 16 |
| 1310 | #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) |
| 1311 | #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) |
| 1312 | |
| 1313 | /* |
| 1314 | * The number of bits reserved for MSS in AR813x/AR815x controllers |
| 1315 | * are 13 bits. This limits the maximum interface MTU size in TSO |
| 1316 | * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper |
| 1317 | * stack should not generate TCP segments with MSS greater than the |
| 1318 | * limit. Also Atheros says that maximum MTU for TSO is 6KB. |
| 1319 | */ |
| 1320 | #define ALC_TSO_MTU (6 * 1024) |
| 1321 | |
| 1322 | struct alc_rxdesc { |
| 1323 | struct mbuf *rx_m; |
| 1324 | bus_dmamap_t rx_dmamap; |
| 1325 | struct rx_desc *rx_desc; |
| 1326 | }; |
| 1327 | |
| 1328 | struct alc_txdesc { |
| 1329 | struct mbuf *tx_m; |
| 1330 | bus_dmamap_t tx_dmamap; |
| 1331 | }; |
| 1332 | |
| 1333 | struct alc_ring_data { |
| 1334 | struct tx_desc *alc_tx_ring; |
| 1335 | bus_dma_segment_t alc_tx_ring_seg; |
| 1336 | bus_addr_t alc_tx_ring_paddr; |
| 1337 | struct rx_desc *alc_rx_ring; |
| 1338 | bus_dma_segment_t alc_rx_ring_seg; |
| 1339 | bus_addr_t alc_rx_ring_paddr; |
| 1340 | struct rx_rdesc *alc_rr_ring; |
| 1341 | bus_dma_segment_t alc_rr_ring_seg; |
| 1342 | bus_addr_t alc_rr_ring_paddr; |
| 1343 | struct cmb *alc_cmb; |
| 1344 | bus_dma_segment_t alc_cmb_seg; |
| 1345 | bus_addr_t alc_cmb_paddr; |
| 1346 | struct smb *alc_smb; |
| 1347 | bus_dma_segment_t alc_smb_seg; |
| 1348 | bus_addr_t alc_smb_paddr; |
| 1349 | }; |
| 1350 | |
| 1351 | struct alc_chain_data { |
| 1352 | struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; |
| 1353 | struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; |
| 1354 | bus_dmamap_t alc_tx_ring_map; |
| 1355 | bus_dma_segment_t alc_tx_ring_seg; |
| 1356 | bus_dmamap_t alc_rx_ring_map; |
| 1357 | bus_dma_segment_t alc_rx_ring_seg; |
| 1358 | bus_dmamap_t alc_rr_ring_map; |
| 1359 | bus_dma_segment_t alc_rr_ring_seg; |
| 1360 | bus_dmamap_t alc_rx_sparemap; |
| 1361 | bus_dmamap_t alc_cmb_map; |
| 1362 | bus_dma_segment_t alc_cmb_seg; |
| 1363 | bus_dmamap_t alc_smb_map; |
| 1364 | bus_dma_segment_t alc_smb_seg; |
| 1365 | |
| 1366 | int alc_tx_prod; |
| 1367 | int alc_tx_cons; |
| 1368 | int alc_tx_cnt; |
| 1369 | int alc_rx_cons; |
| 1370 | int alc_rr_cons; |
| 1371 | int alc_rxlen; |
| 1372 | |
| 1373 | struct mbuf *alc_rxhead; |
| 1374 | struct mbuf *alc_rxtail; |
| 1375 | struct mbuf *alc_rxprev_tail; |
| 1376 | }; |
| 1377 | |
| 1378 | struct alc_hw_stats { |
| 1379 | /* Rx stats. */ |
| 1380 | uint32_t rx_frames; |
| 1381 | uint32_t rx_bcast_frames; |
| 1382 | uint32_t rx_mcast_frames; |
| 1383 | uint32_t rx_pause_frames; |
| 1384 | uint32_t rx_control_frames; |
| 1385 | uint32_t rx_crcerrs; |
| 1386 | uint32_t rx_lenerrs; |
| 1387 | uint64_t rx_bytes; |
| 1388 | uint32_t rx_runts; |
| 1389 | uint32_t rx_fragments; |
| 1390 | uint32_t rx_pkts_64; |
| 1391 | uint32_t rx_pkts_65_127; |
| 1392 | uint32_t rx_pkts_128_255; |
| 1393 | uint32_t rx_pkts_256_511; |
| 1394 | uint32_t rx_pkts_512_1023; |
| 1395 | uint32_t rx_pkts_1024_1518; |
| 1396 | uint32_t rx_pkts_1519_max; |
| 1397 | uint32_t rx_pkts_truncated; |
| 1398 | uint32_t rx_fifo_oflows; |
| 1399 | uint32_t rx_rrs_errs; |
| 1400 | uint32_t rx_alignerrs; |
| 1401 | uint64_t rx_bcast_bytes; |
| 1402 | uint64_t rx_mcast_bytes; |
| 1403 | uint32_t rx_pkts_filtered; |
| 1404 | /* Tx stats. */ |
| 1405 | uint32_t tx_frames; |
| 1406 | uint32_t tx_bcast_frames; |
| 1407 | uint32_t tx_mcast_frames; |
| 1408 | uint32_t tx_pause_frames; |
| 1409 | uint32_t tx_excess_defer; |
| 1410 | uint32_t tx_control_frames; |
| 1411 | uint32_t tx_deferred; |
| 1412 | uint64_t tx_bytes; |
| 1413 | uint32_t tx_pkts_64; |
| 1414 | uint32_t tx_pkts_65_127; |
| 1415 | uint32_t tx_pkts_128_255; |
| 1416 | uint32_t tx_pkts_256_511; |
| 1417 | uint32_t tx_pkts_512_1023; |
| 1418 | uint32_t tx_pkts_1024_1518; |
| 1419 | uint32_t tx_pkts_1519_max; |
| 1420 | uint32_t tx_single_colls; |
| 1421 | uint32_t tx_multi_colls; |
| 1422 | uint32_t tx_late_colls; |
| 1423 | uint32_t tx_excess_colls; |
| 1424 | uint32_t tx_underrun; |
| 1425 | uint32_t tx_desc_underrun; |
| 1426 | uint32_t tx_lenerrs; |
| 1427 | uint32_t tx_pkts_truncated; |
| 1428 | uint64_t tx_bcast_bytes; |
| 1429 | uint64_t tx_mcast_bytes; |
| 1430 | }; |
| 1431 | |
| 1432 | struct alc_ident { |
| 1433 | uint16_t vendorid; |
| 1434 | uint16_t deviceid; |
| 1435 | uint32_t max_framelen; |
| 1436 | const char *name; |
| 1437 | }; |
| 1438 | |
| 1439 | /* |
| 1440 | * Software state per device. |
| 1441 | */ |
| 1442 | struct alc_softc { |
| 1443 | device_t sc_dev; |
| 1444 | struct ethercom sc_ec; |
| 1445 | |
| 1446 | bus_space_tag_t sc_mem_bt; |
| 1447 | bus_space_handle_t sc_mem_bh; |
| 1448 | bus_size_t sc_mem_size; |
| 1449 | bus_dma_tag_t sc_dmat; |
| 1450 | pci_chipset_tag_t sc_pct; |
| 1451 | pcitag_t sc_pcitag; |
| 1452 | |
| 1453 | void *sc_irq_handle; |
| 1454 | struct alc_ident *alc_ident; |
| 1455 | struct mii_data sc_miibus; |
| 1456 | int alc_rev; |
| 1457 | int alc_expcap; |
| 1458 | int alc_chip_rev; |
| 1459 | int alc_phyaddr; |
| 1460 | uint8_t alc_eaddr[ETHER_ADDR_LEN]; |
| 1461 | uint32_t alc_dma_rd_burst; |
| 1462 | uint32_t alc_dma_wr_burst; |
| 1463 | uint32_t alc_rcb; |
| 1464 | int alc_flags; |
| 1465 | #define ALC_FLAG_PCIE 0x0001 |
| 1466 | #define ALC_FLAG_PCIX 0x0002 |
| 1467 | #define ALC_FLAG_MSI 0x0004 |
| 1468 | #define ALC_FLAG_MSIX 0x0008 |
| 1469 | #define ALC_FLAG_FASTETHER 0x0020 |
| 1470 | #define ALC_FLAG_JUMBO 0x0040 |
| 1471 | #define ALC_FLAG_CMB_BUG 0x0100 |
| 1472 | #define ALC_FLAG_SMB_BUG 0x0200 |
| 1473 | #define ALC_FLAG_L0S 0x0400 |
| 1474 | #define ALC_FLAG_L1S 0x0800 |
| 1475 | #define ALC_FLAG_APS 0x1000 |
| 1476 | #define ALC_FLAG_AR816X_FAMILY 0x2000 |
| 1477 | #define ALC_FLAG_LINK_WAR 0x4000 |
| 1478 | #define ALC_FLAG_LINK 0x8000 |
| 1479 | |
| 1480 | callout_t sc_tick_ch; |
| 1481 | struct alc_hw_stats alc_stats; |
| 1482 | struct alc_chain_data alc_cdata; |
| 1483 | struct alc_ring_data alc_rdata; |
| 1484 | int alc_int_rx_mod; |
| 1485 | int alc_int_tx_mod; |
| 1486 | int alc_buf_size; |
| 1487 | }; |
| 1488 | |
| 1489 | /* Register access macros. */ |
| 1490 | #define CSR_WRITE_4(_sc, reg, val) \ |
| 1491 | bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 1492 | #define CSR_WRITE_2(_sc, reg, val) \ |
| 1493 | bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 1494 | #define CSR_WRITE_1(_sc, reg, val) \ |
| 1495 | bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) |
| 1496 | #define CSR_READ_2(_sc, reg) \ |
| 1497 | bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) |
| 1498 | #define CSR_READ_4(_sc, reg) \ |
| 1499 | bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) |
| 1500 | |
| 1501 | #define ALC_RXCHAIN_RESET(_sc) \ |
| 1502 | do { \ |
| 1503 | (_sc)->alc_cdata.alc_rxhead = NULL; \ |
| 1504 | (_sc)->alc_cdata.alc_rxtail = NULL; \ |
| 1505 | (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ |
| 1506 | (_sc)->alc_cdata.alc_rxlen = 0; \ |
| 1507 | } while (0) |
| 1508 | |
| 1509 | #define ALC_TX_TIMEOUT 5 |
| 1510 | #define ALC_RESET_TIMEOUT 100 |
| 1511 | #define ALC_TIMEOUT 1000 |
| 1512 | #define ALC_PHY_TIMEOUT 1000 |
| 1513 | |
| 1514 | /* For compatibility with FreeBSD */ |
| 1515 | #define IFM_UNKNOWN 31 |
| 1516 | |
| 1517 | #endif /* _IF_ALCREG_H */ |
| 1518 | |