| 1 | /* $NetBSD: if_rumreg.h,v 1.5 2016/04/23 10:15:31 skrll Exp $ */ |
| 2 | /* $OpenBSD: if_rumreg.h,v 1.14 2009/08/10 18:04:56 damien Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2005, 2006 Damien Bergamini <damien.bergamini@free.fr> |
| 6 | * Copyright (c) 2006 Niall O'Higgins <niallo@openbsd.org> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #define RT2573_TX_DESC_SIZE (sizeof(struct rum_tx_desc)) |
| 22 | #define RT2573_RX_DESC_SIZE (sizeof(struct rum_rx_desc)) |
| 23 | |
| 24 | #define RT2573_CONFIG_NO 1 |
| 25 | #define RT2573_IFACE_INDEX 0 |
| 26 | |
| 27 | #define RT2573_MCU_CNTL 0x01 |
| 28 | #define RT2573_WRITE_MAC 0x02 |
| 29 | #define RT2573_READ_MAC 0x03 |
| 30 | #define RT2573_WRITE_MULTI_MAC 0x06 |
| 31 | #define RT2573_READ_MULTI_MAC 0x07 |
| 32 | #define RT2573_READ_EEPROM 0x09 |
| 33 | #define RT2573_WRITE_LED 0x0a |
| 34 | |
| 35 | /* |
| 36 | * Control and status registers. |
| 37 | */ |
| 38 | #define RT2573_AIFSN_CSR 0x0400 |
| 39 | #define RT2573_CWMIN_CSR 0x0404 |
| 40 | #define RT2573_CWMAX_CSR 0x0408 |
| 41 | #define RT2573_MCU_CODE_BASE 0x0800 |
| 42 | #define RT2573_HW_BEACON_BASE0 0x2400 |
| 43 | #define RT2573_HW_BEACON_BASE1 0x2500 |
| 44 | #define RT2573_HW_BEACON_BASE2 0x2600 |
| 45 | #define RT2573_HW_BEACON_BASE3 0x2700 |
| 46 | #define RT2573_MAC_CSR0 0x3000 |
| 47 | #define RT2573_MAC_CSR1 0x3004 |
| 48 | #define RT2573_MAC_CSR2 0x3008 |
| 49 | #define RT2573_MAC_CSR3 0x300c |
| 50 | #define RT2573_MAC_CSR4 0x3010 |
| 51 | #define RT2573_MAC_CSR5 0x3014 |
| 52 | #define RT2573_MAC_CSR6 0x3018 |
| 53 | #define RT2573_MAC_CSR7 0x301c |
| 54 | #define RT2573_MAC_CSR8 0x3020 |
| 55 | #define RT2573_MAC_CSR9 0x3024 |
| 56 | #define RT2573_MAC_CSR10 0x3028 |
| 57 | #define RT2573_MAC_CSR11 0x302c |
| 58 | #define RT2573_MAC_CSR12 0x3030 |
| 59 | #define RT2573_MAC_CSR13 0x3034 |
| 60 | #define RT2573_MAC_CSR14 0x3038 |
| 61 | #define RT2573_MAC_CSR15 0x303c |
| 62 | #define RT2573_TXRX_CSR0 0x3040 |
| 63 | #define RT2573_TXRX_CSR1 0x3044 |
| 64 | #define RT2573_TXRX_CSR2 0x3048 |
| 65 | #define RT2573_TXRX_CSR3 0x304c |
| 66 | #define RT2573_TXRX_CSR4 0x3050 |
| 67 | #define RT2573_TXRX_CSR5 0x3054 |
| 68 | #define RT2573_TXRX_CSR6 0x3058 |
| 69 | #define RT2573_TXRX_CSR7 0x305c |
| 70 | #define RT2573_TXRX_CSR8 0x3060 |
| 71 | #define RT2573_TXRX_CSR9 0x3064 |
| 72 | #define RT2573_TXRX_CSR10 0x3068 |
| 73 | #define RT2573_TXRX_CSR11 0x306c |
| 74 | #define RT2573_TXRX_CSR12 0x3070 |
| 75 | #define RT2573_TXRX_CSR13 0x3074 |
| 76 | #define RT2573_TXRX_CSR14 0x3078 |
| 77 | #define RT2573_TXRX_CSR15 0x307c |
| 78 | #define RT2573_PHY_CSR0 0x3080 |
| 79 | #define RT2573_PHY_CSR1 0x3084 |
| 80 | #define RT2573_PHY_CSR2 0x3088 |
| 81 | #define RT2573_PHY_CSR3 0x308c |
| 82 | #define RT2573_PHY_CSR4 0x3090 |
| 83 | #define RT2573_PHY_CSR5 0x3094 |
| 84 | #define RT2573_PHY_CSR6 0x3098 |
| 85 | #define RT2573_PHY_CSR7 0x309c |
| 86 | #define RT2573_SEC_CSR0 0x30a0 |
| 87 | #define RT2573_SEC_CSR1 0x30a4 |
| 88 | #define RT2573_SEC_CSR2 0x30a8 |
| 89 | #define RT2573_SEC_CSR3 0x30ac |
| 90 | #define RT2573_SEC_CSR4 0x30b0 |
| 91 | #define RT2573_SEC_CSR5 0x30b4 |
| 92 | #define RT2573_STA_CSR0 0x30c0 |
| 93 | #define RT2573_STA_CSR1 0x30c4 |
| 94 | #define RT2573_STA_CSR2 0x30c8 |
| 95 | #define RT2573_STA_CSR3 0x30cc |
| 96 | #define RT2573_STA_CSR4 0x30d0 |
| 97 | #define RT2573_STA_CSR5 0x30d4 |
| 98 | |
| 99 | |
| 100 | /* possible flags for register RT2573_MAC_CSR1 */ |
| 101 | #define RT2573_RESET_ASIC (1 << 0) |
| 102 | #define RT2573_RESET_BBP (1 << 1) |
| 103 | #define RT2573_HOST_READY (1 << 2) |
| 104 | |
| 105 | /* possible flags for register MAC_CSR5 */ |
| 106 | #define RT2573_ONE_BSSID 3 |
| 107 | |
| 108 | /* possible flags for register TXRX_CSR0 */ |
| 109 | /* Tx filter flags are in the low 16 bits */ |
| 110 | #define RT2573_AUTO_TX_SEQ (1 << 15) |
| 111 | /* Rx filter flags are in the high 16 bits */ |
| 112 | #define RT2573_DISABLE_RX (1 << 16) |
| 113 | #define RT2573_DROP_CRC_ERROR (1 << 17) |
| 114 | #define RT2573_DROP_PHY_ERROR (1 << 18) |
| 115 | #define RT2573_DROP_CTL (1 << 19) |
| 116 | #define RT2573_DROP_NOT_TO_ME (1 << 20) |
| 117 | #define RT2573_DROP_TODS (1 << 21) |
| 118 | #define RT2573_DROP_VER_ERROR (1 << 22) |
| 119 | #define RT2573_DROP_MULTICAST (1 << 23) |
| 120 | #define RT2573_DROP_BROADCAST (1 << 24) |
| 121 | #define RT2573_DROP_ACKCTS (1 << 25) |
| 122 | |
| 123 | /* possible flags for register TXRX_CSR4 */ |
| 124 | #define RT2573_SHORT_PREAMBLE (1 << 18) |
| 125 | #define RT2573_MRR_ENABLED (1 << 19) |
| 126 | #define RT2573_MRR_CCK_FALLBACK (1 << 22) |
| 127 | |
| 128 | /* possible flags for register TXRX_CSR9 */ |
| 129 | #define RT2573_TSF_TICKING (1 << 16) |
| 130 | #define RT2573_TSF_MODE(x) (((x) & 0x3) << 17) |
| 131 | /* TBTT stands for Target Beacon Transmission Time */ |
| 132 | #define RT2573_ENABLE_TBTT (1 << 19) |
| 133 | #define RT2573_GENERATE_BEACON (1 << 20) |
| 134 | |
| 135 | /* possible flags for register PHY_CSR0 */ |
| 136 | #define RT2573_PA_PE_2GHZ (1 << 16) |
| 137 | #define RT2573_PA_PE_5GHZ (1 << 17) |
| 138 | |
| 139 | /* possible flags for register PHY_CSR3 */ |
| 140 | #define RT2573_BBP_READ (1 << 15) |
| 141 | #define RT2573_BBP_BUSY (1 << 16) |
| 142 | /* possible flags for register PHY_CSR4 */ |
| 143 | #define RT2573_RF_20BIT (20 << 24) |
| 144 | #define RT2573_RF_BUSY (1 << 31) |
| 145 | |
| 146 | /* LED values */ |
| 147 | #define RT2573_LED_RADIO (1 << 8) |
| 148 | #define RT2573_LED_G (1 << 9) |
| 149 | #define RT2573_LED_A (1 << 10) |
| 150 | #define RT2573_LED_ON 0x1e1e |
| 151 | #define RT2573_LED_OFF 0x0 |
| 152 | |
| 153 | #define RT2573_MCU_RUN (1 << 3) |
| 154 | |
| 155 | #define RT2573_SMART_MODE (1 << 0) |
| 156 | |
| 157 | #define RT2573_BBPR94_DEFAULT 6 |
| 158 | |
| 159 | #define RT2573_BBP_WRITE (1 << 15) |
| 160 | |
| 161 | /* dual-band RF */ |
| 162 | #define RT2573_RF_5226 1 |
| 163 | #define RT2573_RF_5225 3 |
| 164 | /* single-band RF */ |
| 165 | #define RT2573_RF_2528 2 |
| 166 | #define RT2573_RF_2527 4 |
| 167 | |
| 168 | #define RT2573_BBP_VERSION 0 |
| 169 | |
| 170 | struct rum_tx_desc { |
| 171 | uint32_t flags; |
| 172 | #define RT2573_TX_BURST (1 << 0) |
| 173 | #define RT2573_TX_VALID (1 << 1) |
| 174 | #define RT2573_TX_MORE_FRAG (1 << 2) |
| 175 | #define RT2573_TX_NEED_ACK (1 << 3) |
| 176 | #define RT2573_TX_TIMESTAMP (1 << 4) |
| 177 | #define RT2573_TX_OFDM (1 << 5) |
| 178 | #define RT2573_TX_IFS_SIFS (1 << 6) |
| 179 | #define RT2573_TX_LONG_RETRY (1 << 7) |
| 180 | |
| 181 | uint16_t wme; |
| 182 | #define RT2573_QID(v) (v) |
| 183 | #define RT2573_AIFSN(v) ((v) << 4) |
| 184 | #define RT2573_LOGCWMIN(v) ((v) << 8) |
| 185 | #define RT2573_LOGCWMAX(v) ((v) << 12) |
| 186 | |
| 187 | uint16_t xflags; |
| 188 | #define RT2573_TX_HWSEQ (1 << 12) |
| 189 | |
| 190 | uint8_t plcp_signal; |
| 191 | uint8_t plcp_service; |
| 192 | #define RT2573_PLCP_LENGEXT 0x80 |
| 193 | |
| 194 | uint8_t plcp_length_lo; |
| 195 | uint8_t plcp_length_hi; |
| 196 | |
| 197 | uint32_t iv; |
| 198 | uint32_t eiv; |
| 199 | |
| 200 | uint8_t offset; |
| 201 | uint8_t qid; |
| 202 | uint8_t txpower; |
| 203 | #define RT2573_DEFAULT_TXPOWER 0 |
| 204 | |
| 205 | uint8_t reserved; |
| 206 | } __packed; |
| 207 | |
| 208 | struct rum_rx_desc { |
| 209 | uint32_t flags; |
| 210 | #define RT2573_RX_BUSY (1 << 0) |
| 211 | #define RT2573_RX_DROP (1 << 1) |
| 212 | #define RT2573_RX_CRC_ERROR (1 << 6) |
| 213 | #define RT2573_RX_OFDM (1 << 7) |
| 214 | |
| 215 | uint8_t rate; |
| 216 | uint8_t ; |
| 217 | uint8_t reserved1; |
| 218 | uint8_t offset; |
| 219 | uint32_t iv; |
| 220 | uint32_t eiv; |
| 221 | uint32_t reserved2[2]; |
| 222 | } __packed; |
| 223 | |
| 224 | #define RT2573_RF1 0 |
| 225 | #define RT2573_RF2 2 |
| 226 | #define RT2573_RF3 1 |
| 227 | #define RT2573_RF4 3 |
| 228 | |
| 229 | #define RT2573_EEPROM_MACBBP 0x0000 |
| 230 | #define RT2573_EEPROM_ADDRESS 0x0004 |
| 231 | #define RT2573_EEPROM_ANTENNA 0x0020 |
| 232 | #define RT2573_EEPROM_CONFIG2 0x0022 |
| 233 | #define RT2573_EEPROM_BBP_BASE 0x0026 |
| 234 | #define RT2573_EEPROM_TXPOWER 0x0046 |
| 235 | #define RT2573_EEPROM_FREQ_OFFSET 0x005e |
| 236 | #define 0x009a |
| 237 | #define 0x009c |
| 238 | |
| 239 | /* |
| 240 | * Default values for MAC registers; values taken from the reference driver. |
| 241 | */ |
| 242 | #define RT2573_DEF_MAC \ |
| 243 | { RT2573_TXRX_CSR0, 0x025fb032 }, \ |
| 244 | { RT2573_TXRX_CSR1, 0x9eaa9eaf }, \ |
| 245 | { RT2573_TXRX_CSR2, 0x8a8b8c8d }, \ |
| 246 | { RT2573_TXRX_CSR3, 0x00858687 }, \ |
| 247 | { RT2573_TXRX_CSR7, 0x2e31353b }, \ |
| 248 | { RT2573_TXRX_CSR8, 0x2a2a2a2c }, \ |
| 249 | { RT2573_TXRX_CSR15, 0x0000000f }, \ |
| 250 | { RT2573_MAC_CSR6, 0x00000fff }, \ |
| 251 | { RT2573_MAC_CSR8, 0x016c030a }, \ |
| 252 | { RT2573_MAC_CSR10, 0x00000718 }, \ |
| 253 | { RT2573_MAC_CSR12, 0x00000004 }, \ |
| 254 | { RT2573_MAC_CSR13, 0x00007f00 }, \ |
| 255 | { RT2573_SEC_CSR0, 0x00000000 }, \ |
| 256 | { RT2573_SEC_CSR1, 0x00000000 }, \ |
| 257 | { RT2573_SEC_CSR5, 0x00000000 }, \ |
| 258 | { RT2573_PHY_CSR1, 0x000023b0 }, \ |
| 259 | { RT2573_PHY_CSR5, 0x00040a06 }, \ |
| 260 | { RT2573_PHY_CSR6, 0x00080606 }, \ |
| 261 | { RT2573_PHY_CSR7, 0x00000408 }, \ |
| 262 | { RT2573_AIFSN_CSR, 0x00002273 }, \ |
| 263 | { RT2573_CWMIN_CSR, 0x00002344 }, \ |
| 264 | { RT2573_CWMAX_CSR, 0x000034aa }, \ |
| 265 | { RT2573_HW_BEACON_BASE0, 0x00000000 }, \ |
| 266 | { RT2573_HW_BEACON_BASE1, 0x00000000 }, \ |
| 267 | { RT2573_HW_BEACON_BASE2, 0x00000000 }, \ |
| 268 | { RT2573_HW_BEACON_BASE3, 0x00000000 } |
| 269 | |
| 270 | /* |
| 271 | * Default values for BBP registers; values taken from the reference driver. |
| 272 | */ |
| 273 | #define RT2573_DEF_BBP \ |
| 274 | { 3, 0x80 }, \ |
| 275 | { 15, 0x30 }, \ |
| 276 | { 17, 0x20 }, \ |
| 277 | { 21, 0xc8 }, \ |
| 278 | { 22, 0x38 }, \ |
| 279 | { 23, 0x06 }, \ |
| 280 | { 24, 0xfe }, \ |
| 281 | { 25, 0x0a }, \ |
| 282 | { 26, 0x0d }, \ |
| 283 | { 32, 0x0b }, \ |
| 284 | { 34, 0x12 }, \ |
| 285 | { 37, 0x07 }, \ |
| 286 | { 39, 0xf8 }, \ |
| 287 | { 41, 0x60 }, \ |
| 288 | { 53, 0x10 }, \ |
| 289 | { 54, 0x18 }, \ |
| 290 | { 60, 0x10 }, \ |
| 291 | { 61, 0x04 }, \ |
| 292 | { 62, 0x04 }, \ |
| 293 | { 75, 0xfe }, \ |
| 294 | { 86, 0xfe }, \ |
| 295 | { 88, 0xfe }, \ |
| 296 | { 90, 0x0f }, \ |
| 297 | { 99, 0x00 }, \ |
| 298 | { 102, 0x16 }, \ |
| 299 | { 107, 0x04 } |
| 300 | |
| 301 | /* |
| 302 | * Default settings for RF registers; values taken from the reference driver. |
| 303 | */ |
| 304 | #define RT2573_RF5226 \ |
| 305 | { 1, 0x00b03, 0x001e1, 0x1a014, 0x30282 }, \ |
| 306 | { 2, 0x00b03, 0x001e1, 0x1a014, 0x30287 }, \ |
| 307 | { 3, 0x00b03, 0x001e2, 0x1a014, 0x30282 }, \ |
| 308 | { 4, 0x00b03, 0x001e2, 0x1a014, 0x30287 }, \ |
| 309 | { 5, 0x00b03, 0x001e3, 0x1a014, 0x30282 }, \ |
| 310 | { 6, 0x00b03, 0x001e3, 0x1a014, 0x30287 }, \ |
| 311 | { 7, 0x00b03, 0x001e4, 0x1a014, 0x30282 }, \ |
| 312 | { 8, 0x00b03, 0x001e4, 0x1a014, 0x30287 }, \ |
| 313 | { 9, 0x00b03, 0x001e5, 0x1a014, 0x30282 }, \ |
| 314 | { 10, 0x00b03, 0x001e5, 0x1a014, 0x30287 }, \ |
| 315 | { 11, 0x00b03, 0x001e6, 0x1a014, 0x30282 }, \ |
| 316 | { 12, 0x00b03, 0x001e6, 0x1a014, 0x30287 }, \ |
| 317 | { 13, 0x00b03, 0x001e7, 0x1a014, 0x30282 }, \ |
| 318 | { 14, 0x00b03, 0x001e8, 0x1a014, 0x30284 }, \ |
| 319 | \ |
| 320 | { 34, 0x00b03, 0x20266, 0x36014, 0x30282 }, \ |
| 321 | { 38, 0x00b03, 0x20267, 0x36014, 0x30284 }, \ |
| 322 | { 42, 0x00b03, 0x20268, 0x36014, 0x30286 }, \ |
| 323 | { 46, 0x00b03, 0x20269, 0x36014, 0x30288 }, \ |
| 324 | \ |
| 325 | { 36, 0x00b03, 0x00266, 0x26014, 0x30288 }, \ |
| 326 | { 40, 0x00b03, 0x00268, 0x26014, 0x30280 }, \ |
| 327 | { 44, 0x00b03, 0x00269, 0x26014, 0x30282 }, \ |
| 328 | { 48, 0x00b03, 0x0026a, 0x26014, 0x30284 }, \ |
| 329 | { 52, 0x00b03, 0x0026b, 0x26014, 0x30286 }, \ |
| 330 | { 56, 0x00b03, 0x0026c, 0x26014, 0x30288 }, \ |
| 331 | { 60, 0x00b03, 0x0026e, 0x26014, 0x30280 }, \ |
| 332 | { 64, 0x00b03, 0x0026f, 0x26014, 0x30282 }, \ |
| 333 | \ |
| 334 | { 100, 0x00b03, 0x0028a, 0x2e014, 0x30280 }, \ |
| 335 | { 104, 0x00b03, 0x0028b, 0x2e014, 0x30282 }, \ |
| 336 | { 108, 0x00b03, 0x0028c, 0x2e014, 0x30284 }, \ |
| 337 | { 112, 0x00b03, 0x0028d, 0x2e014, 0x30286 }, \ |
| 338 | { 116, 0x00b03, 0x0028e, 0x2e014, 0x30288 }, \ |
| 339 | { 120, 0x00b03, 0x002a0, 0x2e014, 0x30280 }, \ |
| 340 | { 124, 0x00b03, 0x002a1, 0x2e014, 0x30282 }, \ |
| 341 | { 128, 0x00b03, 0x002a2, 0x2e014, 0x30284 }, \ |
| 342 | { 132, 0x00b03, 0x002a3, 0x2e014, 0x30286 }, \ |
| 343 | { 136, 0x00b03, 0x002a4, 0x2e014, 0x30288 }, \ |
| 344 | { 140, 0x00b03, 0x002a6, 0x2e014, 0x30280 }, \ |
| 345 | \ |
| 346 | { 149, 0x00b03, 0x002a8, 0x2e014, 0x30287 }, \ |
| 347 | { 153, 0x00b03, 0x002a9, 0x2e014, 0x30289 }, \ |
| 348 | { 157, 0x00b03, 0x002ab, 0x2e014, 0x30281 }, \ |
| 349 | { 161, 0x00b03, 0x002ac, 0x2e014, 0x30283 }, \ |
| 350 | { 165, 0x00b03, 0x002ad, 0x2e014, 0x30285 } |
| 351 | |
| 352 | #define RT2573_RF5225 \ |
| 353 | { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ |
| 354 | { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ |
| 355 | { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ |
| 356 | { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ |
| 357 | { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ |
| 358 | { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ |
| 359 | { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ |
| 360 | { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ |
| 361 | { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ |
| 362 | { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ |
| 363 | { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ |
| 364 | { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ |
| 365 | { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ |
| 366 | { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ |
| 367 | \ |
| 368 | { 34, 0x00b33, 0x01266, 0x26014, 0x30282 }, \ |
| 369 | { 38, 0x00b33, 0x01267, 0x26014, 0x30284 }, \ |
| 370 | { 42, 0x00b33, 0x01268, 0x26014, 0x30286 }, \ |
| 371 | { 46, 0x00b33, 0x01269, 0x26014, 0x30288 }, \ |
| 372 | \ |
| 373 | { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ |
| 374 | { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ |
| 375 | { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ |
| 376 | { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ |
| 377 | { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ |
| 378 | { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ |
| 379 | { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ |
| 380 | { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ |
| 381 | \ |
| 382 | { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ |
| 383 | { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ |
| 384 | { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ |
| 385 | { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ |
| 386 | { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ |
| 387 | { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ |
| 388 | { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ |
| 389 | { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ |
| 390 | { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ |
| 391 | { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ |
| 392 | { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ |
| 393 | \ |
| 394 | { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ |
| 395 | { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ |
| 396 | { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ |
| 397 | { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ |
| 398 | { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } |
| 399 | |