| 1 | /* $NetBSD: if_iwnreg.h,v 1.15 2014/11/09 14:40:54 nonaka Exp $ */ |
| 2 | /* $OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2007, 2008 |
| 6 | * Damien Bergamini <damien.bergamini@free.fr> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #include <sys/endian.h> |
| 22 | |
| 23 | /* XXX Added for NetBSD */ |
| 24 | #define IEEE80211_TKIP_MICLEN 8 |
| 25 | |
| 26 | #define IWN_TX_RING_COUNT 256 |
| 27 | #define IWN_TX_RING_LOMARK 192 |
| 28 | #define IWN_TX_RING_HIMARK 224 |
| 29 | #define IWN_RX_RING_COUNT_LOG 6 |
| 30 | #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) |
| 31 | |
| 32 | #define IWN4965_NTXQUEUES 16 |
| 33 | #define IWN5000_NTXQUEUES 20 |
| 34 | |
| 35 | #define IWN4965_NDMACHNLS 7 |
| 36 | #define IWN5000_NDMACHNLS 8 |
| 37 | |
| 38 | #define IWN_SRVC_DMACHNL 9 |
| 39 | |
| 40 | #define IWN_ICT_SIZE 4096 |
| 41 | #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) |
| 42 | |
| 43 | /* Maximum number of DMA segments for TX. */ |
| 44 | #define IWN_MAX_SCATTER 20 |
| 45 | |
| 46 | /* RX buffers must be large enough to hold a full 4K A-MPDU. */ |
| 47 | #define IWN_RBUF_SIZE (4 * 1024) |
| 48 | |
| 49 | #if defined(__LP64__) |
| 50 | /* HW supports 36-bit DMA addresses. */ |
| 51 | #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) |
| 52 | #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) |
| 53 | #else |
| 54 | #define IWN_LOADDR(paddr) (paddr) |
| 55 | #define IWN_HIADDR(paddr) (0) |
| 56 | #endif |
| 57 | |
| 58 | /* Base Address Register. */ |
| 59 | #define IWN_PCI_BAR0 PCI_MAPREG_START |
| 60 | |
| 61 | /* |
| 62 | * Control and status registers. |
| 63 | */ |
| 64 | #define IWN_HW_IF_CONFIG 0x000 |
| 65 | #define IWN_INT_COALESCING 0x004 |
| 66 | #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ |
| 67 | #define IWN_INT 0x008 |
| 68 | #define IWN_INT_MASK 0x00c |
| 69 | #define IWN_FH_INT 0x010 |
| 70 | #define IWN_RESET 0x020 |
| 71 | #define IWN_GP_CNTRL 0x024 |
| 72 | #define IWN_HW_REV 0x028 |
| 73 | #define IWN_EEPROM 0x02c |
| 74 | #define IWN_EEPROM_GP 0x030 |
| 75 | #define IWN_OTP_GP 0x034 |
| 76 | #define IWN_GIO 0x03c |
| 77 | #define IWN_GP_DRIVER 0x050 |
| 78 | #define IWN_UCODE_GP1_CLR 0x05c |
| 79 | #define IWN_LED 0x094 |
| 80 | #define IWN_DRAM_INT_TBL 0x0a0 |
| 81 | #define IWN_SHADOW_REG_CTRL 0x0a8 |
| 82 | #define IWN_GIO_CHICKEN 0x100 |
| 83 | #define IWN_ANA_PLL 0x20c |
| 84 | #define IWN_HW_REV_WA 0x22c |
| 85 | #define IWN_DBG_HPET_MEM 0x240 |
| 86 | #define IWN_DBG_LINK_PWR_MGMT 0x250 |
| 87 | #define IWN_MEM_RADDR 0x40c |
| 88 | #define IWN_MEM_WADDR 0x410 |
| 89 | #define IWN_MEM_WDATA 0x418 |
| 90 | #define IWN_MEM_RDATA 0x41c |
| 91 | #define IWN_PRPH_WADDR 0x444 |
| 92 | #define IWN_PRPH_RADDR 0x448 |
| 93 | #define IWN_PRPH_WDATA 0x44c |
| 94 | #define IWN_PRPH_RDATA 0x450 |
| 95 | #define IWN_HBUS_TARG_WRPTR 0x460 |
| 96 | |
| 97 | /* |
| 98 | * Flow-Handler registers. |
| 99 | */ |
| 100 | #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) |
| 101 | #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) |
| 102 | #define IWN_FH_KW_ADDR 0x197c |
| 103 | #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) |
| 104 | #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) |
| 105 | #define IWN_FH_STATUS_WPTR 0x1bc0 |
| 106 | #define IWN_FH_RX_BASE 0x1bc4 |
| 107 | #define IWN_FH_RX_WPTR 0x1bc8 |
| 108 | #define IWN_FH_RX_CONFIG 0x1c00 |
| 109 | #define IWN_FH_RX_STATUS 0x1c44 |
| 110 | #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) |
| 111 | #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) |
| 112 | #define IWN_FH_TX_CHICKEN 0x1e98 |
| 113 | #define IWN_FH_TX_STATUS 0x1eb0 |
| 114 | |
| 115 | /* |
| 116 | * TX scheduler registers. |
| 117 | */ |
| 118 | #define IWN_SCHED_BASE 0xa02c00 |
| 119 | #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) |
| 120 | #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) |
| 121 | #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) |
| 122 | #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) |
| 123 | #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) |
| 124 | #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) |
| 125 | #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) |
| 126 | #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) |
| 127 | #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) |
| 128 | #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) |
| 129 | #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) |
| 130 | #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) |
| 131 | #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) |
| 132 | #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) |
| 133 | |
| 134 | /* |
| 135 | * Offsets in TX scheduler's SRAM. |
| 136 | */ |
| 137 | #define IWN4965_SCHED_CTX_OFF 0x380 |
| 138 | #define IWN4965_SCHED_CTX_LEN 416 |
| 139 | #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) |
| 140 | #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) |
| 141 | #define IWN5000_SCHED_CTX_OFF 0x600 |
| 142 | #define IWN5000_SCHED_CTX_LEN 520 |
| 143 | #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) |
| 144 | #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) |
| 145 | |
| 146 | /* |
| 147 | * NIC internal memory offsets. |
| 148 | */ |
| 149 | #define IWN_APMG_CLK_CTRL 0x3000 |
| 150 | #define IWN_APMG_CLK_EN 0x3004 |
| 151 | #define IWN_APMG_CLK_DIS 0x3008 |
| 152 | #define IWN_APMG_PS 0x300c |
| 153 | #define IWN_APMG_DIGITAL_SVR 0x3058 |
| 154 | #define IWN_APMG_ANALOG_SVR 0x306c |
| 155 | #define IWN_APMG_PCI_STT 0x3010 |
| 156 | #define IWN_BSM_WR_CTRL 0x3400 |
| 157 | #define IWN_BSM_WR_MEM_SRC 0x3404 |
| 158 | #define IWN_BSM_WR_MEM_DST 0x3408 |
| 159 | #define IWN_BSM_WR_DWCOUNT 0x340c |
| 160 | #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 |
| 161 | #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 |
| 162 | #define IWN_BSM_DRAM_DATA_ADDR 0x3498 |
| 163 | #define IWN_BSM_DRAM_DATA_SIZE 0x349c |
| 164 | #define IWN_BSM_SRAM_BASE 0x3800 |
| 165 | |
| 166 | /* Possible flags for register IWN_HW_IF_CONFIG. */ |
| 167 | #define IWN_HW_IF_CONFIG_4965_R (1 << 4) |
| 168 | #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) |
| 169 | #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) |
| 170 | #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) |
| 171 | #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) |
| 172 | #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) |
| 173 | #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) |
| 174 | #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) |
| 175 | |
| 176 | /* Possible values for register IWN_INT_PERIODIC. */ |
| 177 | #define IWN_INT_PERIODIC_DIS 0x00 |
| 178 | #define IWN_INT_PERIODIC_ENA 0xff |
| 179 | |
| 180 | /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ |
| 181 | #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) |
| 182 | |
| 183 | /* Possible values for IWN_BSM_WR_MEM_DST. */ |
| 184 | #define IWN_FW_TEXT_BASE 0x00000000 |
| 185 | #define IWN_FW_DATA_BASE 0x00800000 |
| 186 | |
| 187 | /* Possible flags for register IWN_RESET. */ |
| 188 | #define IWN_RESET_NEVO (1U << 0) |
| 189 | #define IWN_RESET_SW (1U << 7) |
| 190 | #define IWN_RESET_MASTER_DISABLED (1U << 8) |
| 191 | #define IWN_RESET_STOP_MASTER (1U << 9) |
| 192 | #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) |
| 193 | |
| 194 | /* Possible flags for register IWN_GP_CNTRL. */ |
| 195 | #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) |
| 196 | #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) |
| 197 | #define IWN_GP_CNTRL_INIT_DONE (1 << 2) |
| 198 | #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) |
| 199 | #define IWN_GP_CNTRL_SLEEP (1 << 4) |
| 200 | #define IWN_GP_CNTRL_RFKILL (1 << 27) |
| 201 | |
| 202 | /* Possible flags for register IWN_HW_REV. */ |
| 203 | #define IWN_HW_REV_TYPE_SHIFT 4 |
| 204 | #define IWN_HW_REV_TYPE_MASK 0x000001f0 |
| 205 | #define IWN_HW_REV_TYPE_4965 0 |
| 206 | #define IWN_HW_REV_TYPE_5300 2 |
| 207 | #define IWN_HW_REV_TYPE_5350 3 |
| 208 | #define IWN_HW_REV_TYPE_5150 4 |
| 209 | #define IWN_HW_REV_TYPE_5100 5 |
| 210 | #define IWN_HW_REV_TYPE_1000 6 |
| 211 | #define IWN_HW_REV_TYPE_6000 7 |
| 212 | #define IWN_HW_REV_TYPE_6050 8 |
| 213 | #define IWN_HW_REV_TYPE_6005 11 |
| 214 | /* Types 6030 and 6035 also return 11 */ |
| 215 | #define IWN_HW_REV_TYPE_2030 12 |
| 216 | #define IWN_HW_REV_TYPE_2000 16 |
| 217 | #define IWN_HW_REV_TYPE_105 17 |
| 218 | #define IWN_HW_REV_TYPE_135 18 |
| 219 | |
| 220 | /* Possible flags for register IWN_GIO_CHICKEN. */ |
| 221 | #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) |
| 222 | #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) |
| 223 | |
| 224 | /* Possible flags for register IWN_GIO. */ |
| 225 | #define IWN_GIO_L0S_ENA (1 << 1) |
| 226 | |
| 227 | /* Possible flags for register IWN_GP_DRIVER. */ |
| 228 | #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) |
| 229 | #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) |
| 230 | #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) |
| 231 | #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) |
| 232 | #define IWN_GP_DRIVER_6050_1X2 (1 << 3) |
| 233 | #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) |
| 234 | |
| 235 | /* Possible flags for register IWN_UCODE_GP1_CLR. */ |
| 236 | #define IWN_UCODE_GP1_RFKILL (1 << 1) |
| 237 | #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) |
| 238 | #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) |
| 239 | |
| 240 | /* Possible flags/values for register IWN_LED. */ |
| 241 | #define IWN_LED_BSM_CTRL (1 << 5) |
| 242 | #define IWN_LED_OFF 0x00000038 |
| 243 | #define IWN_LED_ON 0x00000078 |
| 244 | |
| 245 | /* Possible flags for register IWN_DRAM_INT_TBL. */ |
| 246 | #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) |
| 247 | #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) |
| 248 | |
| 249 | /* Possible values for register IWN_ANA_PLL. */ |
| 250 | #define IWN_ANA_PLL_INIT 0x00880300 |
| 251 | |
| 252 | /* Possible flags for register IWN_FH_RX_STATUS. */ |
| 253 | #define IWN_FH_RX_STATUS_IDLE (1 << 24) |
| 254 | |
| 255 | /* Possible flags for register IWN_BSM_WR_CTRL. */ |
| 256 | #define IWN_BSM_WR_CTRL_START_EN (1 << 30) |
| 257 | #define IWN_BSM_WR_CTRL_START (1 << 31) |
| 258 | |
| 259 | /* Possible flags for register IWN_INT. */ |
| 260 | #define IWN_INT_ALIVE (1 << 0) |
| 261 | #define IWN_INT_WAKEUP (1 << 1) |
| 262 | #define IWN_INT_SW_RX (1 << 3) |
| 263 | #define IWN_INT_CT_REACHED (1 << 6) |
| 264 | #define IWN_INT_RF_TOGGLED (1 << 7) |
| 265 | #define IWN_INT_SW_ERR (1 << 25) |
| 266 | #define IWN_INT_SCHED (1 << 26) |
| 267 | #define IWN_INT_FH_TX (1 << 27) |
| 268 | #define IWN_INT_RX_PERIODIC (1 << 28) |
| 269 | #define IWN_INT_HW_ERR (1 << 29) |
| 270 | #define IWN_INT_FH_RX (1 << 31) |
| 271 | |
| 272 | /* Shortcut. */ |
| 273 | #define IWN_INT_MASK_DEF \ |
| 274 | (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ |
| 275 | IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ |
| 276 | IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) |
| 277 | |
| 278 | /* Possible flags for register IWN_FH_INT. */ |
| 279 | #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) |
| 280 | #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) |
| 281 | #define IWN_FH_INT_HI_PRIOR (1 << 30) |
| 282 | /* Shortcuts for the above. */ |
| 283 | #define IWN_FH_INT_TX \ |
| 284 | (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) |
| 285 | #define IWN_FH_INT_RX \ |
| 286 | (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) |
| 287 | |
| 288 | /* Possible flags/values for register IWN_FH_TX_CONFIG. */ |
| 289 | #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 |
| 290 | #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) |
| 291 | #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) |
| 292 | |
| 293 | /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ |
| 294 | #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) |
| 295 | #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) |
| 296 | #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 |
| 297 | |
| 298 | /* Possible flags for register IWN_FH_TX_CHICKEN. */ |
| 299 | #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) |
| 300 | |
| 301 | /* Possible flags for register IWN_FH_TX_STATUS. */ |
| 302 | #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) |
| 303 | |
| 304 | /* Possible flags for register IWN_FH_RX_CONFIG. */ |
| 305 | #define IWN_FH_RX_CONFIG_ENA (1U << 31) |
| 306 | #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) |
| 307 | #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) |
| 308 | #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) |
| 309 | #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) |
| 310 | #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) |
| 311 | #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) |
| 312 | |
| 313 | /* Possible flags for register IWN_FH_TX_CONFIG. */ |
| 314 | #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) |
| 315 | #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) |
| 316 | |
| 317 | /* Possible flags for register IWN_EEPROM. */ |
| 318 | #define IWN_EEPROM_READ_VALID (1 << 0) |
| 319 | #define IWN_EEPROM_CMD (1 << 1) |
| 320 | |
| 321 | /* Possible flags for register IWN_EEPROM_GP. */ |
| 322 | #define IWN_EEPROM_GP_IF_OWNER 0x00000180 |
| 323 | |
| 324 | /* Possible flags for register IWN_OTP_GP. */ |
| 325 | #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) |
| 326 | #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) |
| 327 | #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) |
| 328 | #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) |
| 329 | |
| 330 | /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ |
| 331 | #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 |
| 332 | #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 |
| 333 | #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) |
| 334 | #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) |
| 335 | #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 |
| 336 | #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 |
| 337 | #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) |
| 338 | |
| 339 | /* Possible flags for registers IWN_APMG_CLK_*. */ |
| 340 | #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) |
| 341 | #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) |
| 342 | |
| 343 | /* Possible flags for register IWN_APMG_PS. */ |
| 344 | #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) |
| 345 | #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) |
| 346 | #define IWN_APMG_PS_PWR_SRC_VMAIN 0 |
| 347 | #define IWN_APMG_PS_PWR_SRC_VAUX 2 |
| 348 | #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) |
| 349 | #define IWN_APMG_PS_RESET_REQ (1 << 26) |
| 350 | |
| 351 | /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ |
| 352 | #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) |
| 353 | #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ |
| 354 | IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) |
| 355 | #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ |
| 356 | IWN_APMG_DIGITAL_SVR_VOLTAGE(3) |
| 357 | |
| 358 | /* Possible flags for IWN_APMG_PCI_STT. */ |
| 359 | #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) |
| 360 | |
| 361 | /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ |
| 362 | #define IWN_FW_UPDATED (1U << 31) |
| 363 | |
| 364 | #define IWN_SCHED_WINSZ 64 |
| 365 | #define IWN_SCHED_LIMIT 64 |
| 366 | #define IWN4965_SCHED_COUNT 512 |
| 367 | #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) |
| 368 | #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) |
| 369 | #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) |
| 370 | |
| 371 | struct iwn_tx_desc { |
| 372 | uint8_t reserved1[3]; |
| 373 | uint8_t nsegs; |
| 374 | struct { |
| 375 | uint32_t addr; |
| 376 | uint16_t len; |
| 377 | } __packed segs[IWN_MAX_SCATTER]; |
| 378 | /* Pad to 128 bytes. */ |
| 379 | uint32_t reserved2; |
| 380 | } __packed; |
| 381 | |
| 382 | struct iwn_rx_status { |
| 383 | uint16_t closed_count; |
| 384 | uint16_t closed_rx_count; |
| 385 | uint16_t finished_count; |
| 386 | uint16_t finished_rx_count; |
| 387 | uint32_t reserved[2]; |
| 388 | } __packed; |
| 389 | |
| 390 | struct iwn_rx_desc { |
| 391 | uint32_t len; |
| 392 | uint8_t type; |
| 393 | #define IWN_UC_READY 1 |
| 394 | #define IWN_ADD_NODE_DONE 24 |
| 395 | #define IWN_TX_DONE 28 |
| 396 | #define IWN5000_CALIBRATION_RESULT 102 |
| 397 | #define IWN5000_CALIBRATION_DONE 103 |
| 398 | #define IWN_START_SCAN 130 |
| 399 | #define IWN_STOP_SCAN 132 |
| 400 | #define IWN_RX_STATISTICS 156 |
| 401 | #define IWN_BEACON_STATISTICS 157 |
| 402 | #define IWN_STATE_CHANGED 161 |
| 403 | #define IWN_BEACON_MISSED 162 |
| 404 | #define IWN_RX_PHY 192 |
| 405 | #define IWN_MPDU_RX_DONE 193 |
| 406 | #define IWN_RX_DONE 195 |
| 407 | #define IWN_RX_COMPRESSED_BA 197 |
| 408 | |
| 409 | uint8_t flags; |
| 410 | uint8_t idx; |
| 411 | uint8_t qid; |
| 412 | } __packed; |
| 413 | |
| 414 | /* Possible RX status flags. */ |
| 415 | #define IWN_RX_NO_CRC_ERR (1 << 0) |
| 416 | #define IWN_RX_NO_OVFL_ERR (1 << 1) |
| 417 | /* Shortcut for the above. */ |
| 418 | #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) |
| 419 | #define IWN_RX_MPDU_MIC_OK (1 << 6) |
| 420 | #define IWN_RX_CIPHER_MASK (7 << 8) |
| 421 | #define IWN_RX_CIPHER_CCMP (2 << 8) |
| 422 | #define IWN_RX_MPDU_DEC (1 << 11) |
| 423 | #define IWN_RX_DECRYPT_MASK (3 << 11) |
| 424 | #define IWN_RX_DECRYPT_OK (3 << 11) |
| 425 | |
| 426 | struct iwn_tx_cmd { |
| 427 | uint8_t code; |
| 428 | #define IWN_CMD_RXON 16 |
| 429 | #define IWN_CMD_RXON_ASSOC 17 |
| 430 | #define IWN_CMD_EDCA_PARAMS 19 |
| 431 | #define IWN_CMD_TIMING 20 |
| 432 | #define IWN_CMD_ADD_NODE 24 |
| 433 | #define IWN_CMD_TX_DATA 28 |
| 434 | #define IWN_CMD_SET_LED 72 |
| 435 | #define IWN_CMD_LINK_QUALITY 78 |
| 436 | #define IWN5000_CMD_WIMAX_COEX 90 |
| 437 | #define IWN5000_CMD_CALIB_CONFIG 101 |
| 438 | #define IWN_CMD_SET_POWER_MODE 119 |
| 439 | #define IWN_CMD_SCAN 128 |
| 440 | #define IWN_CMD_TXPOWER_DBM 149 |
| 441 | #define IWN_CMD_TXPOWER 151 |
| 442 | #define IWN5000_CMD_TX_ANT_CONFIG 152 |
| 443 | #define IWN_CMD_BT_COEX 155 |
| 444 | #define IWN_CMD_GET_STATISTICS 156 |
| 445 | #define IWN_CMD_SET_CRITICAL_TEMP 164 |
| 446 | #define IWN_CMD_SET_SENSITIVITY 168 |
| 447 | #define IWN_CMD_PHY_CALIB 176 |
| 448 | #define IWN_CMD_BT_COEX_PRIO_TABLE 204 |
| 449 | #define IWN_CMD_BT_COEX_PROT 205 |
| 450 | |
| 451 | uint8_t flags; |
| 452 | uint8_t idx; |
| 453 | uint8_t qid; |
| 454 | uint8_t data[136]; |
| 455 | } __packed; |
| 456 | |
| 457 | /* Antenna flags, used in various commands. */ |
| 458 | #define IWN_ANT_A (1 << 0) |
| 459 | #define IWN_ANT_B (1 << 1) |
| 460 | #define IWN_ANT_C (1 << 2) |
| 461 | /* Shortcuts. */ |
| 462 | #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) |
| 463 | #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) |
| 464 | #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) |
| 465 | |
| 466 | /* Structure for command IWN_CMD_RXON. */ |
| 467 | struct iwn_rxon { |
| 468 | uint8_t myaddr[IEEE80211_ADDR_LEN]; |
| 469 | uint16_t reserved1; |
| 470 | uint8_t bssid[IEEE80211_ADDR_LEN]; |
| 471 | uint16_t reserved2; |
| 472 | uint8_t wlap[IEEE80211_ADDR_LEN]; |
| 473 | uint16_t reserved3; |
| 474 | uint8_t mode; |
| 475 | #define IWN_MODE_HOSTAP 1 |
| 476 | #define IWN_MODE_STA 3 |
| 477 | #define IWN_MODE_IBSS 4 |
| 478 | #define IWN_MODE_MONITOR 6 |
| 479 | |
| 480 | uint8_t air; |
| 481 | uint16_t rxchain; |
| 482 | #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) |
| 483 | #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) |
| 484 | #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) |
| 485 | #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) |
| 486 | #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) |
| 487 | #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) |
| 488 | #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) |
| 489 | |
| 490 | uint8_t ofdm_mask; |
| 491 | uint8_t cck_mask; |
| 492 | uint16_t associd; |
| 493 | uint32_t flags; |
| 494 | #define IWN_RXON_24GHZ (1 << 0) |
| 495 | #define IWN_RXON_CCK (1 << 1) |
| 496 | #define IWN_RXON_AUTO (1 << 2) |
| 497 | #define IWN_RXON_SHSLOT (1 << 4) |
| 498 | #define IWN_RXON_SHPREAMBLE (1 << 5) |
| 499 | #define IWN_RXON_NODIVERSITY (1 << 7) |
| 500 | #define IWN_RXON_ANTENNA_A (1 << 8) |
| 501 | #define IWN_RXON_ANTENNA_B (1 << 9) |
| 502 | #define IWN_RXON_TSF (1 << 15) |
| 503 | #define IWN_RXON_CTS_TO_SELF (1 << 30) |
| 504 | |
| 505 | uint32_t filter; |
| 506 | #define IWN_FILTER_PROMISC (1 << 0) |
| 507 | #define IWN_FILTER_CTL (1 << 1) |
| 508 | #define IWN_FILTER_MULTICAST (1 << 2) |
| 509 | #define IWN_FILTER_NODECRYPT (1 << 3) |
| 510 | #define IWN_FILTER_BSS (1 << 5) |
| 511 | #define IWN_FILTER_BEACON (1 << 6) |
| 512 | |
| 513 | uint8_t chan; |
| 514 | uint8_t reserved4; |
| 515 | uint8_t ht_single_mask; |
| 516 | uint8_t ht_dual_mask; |
| 517 | /* The following fields are for >=5000 Series only. */ |
| 518 | uint8_t ht_triple_mask; |
| 519 | uint8_t reserved5; |
| 520 | uint16_t acquisition; |
| 521 | uint16_t reserved6; |
| 522 | } __packed; |
| 523 | |
| 524 | #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) |
| 525 | #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) |
| 526 | |
| 527 | /* Structure for command IWN_CMD_ASSOCIATE. */ |
| 528 | struct iwn_assoc { |
| 529 | uint32_t flags; |
| 530 | uint32_t filter; |
| 531 | uint8_t ofdm_mask; |
| 532 | uint8_t cck_mask; |
| 533 | uint16_t reserved; |
| 534 | } __packed; |
| 535 | |
| 536 | /* Structure for command IWN_CMD_EDCA_PARAMS. */ |
| 537 | struct iwn_edca_params { |
| 538 | uint32_t flags; |
| 539 | #define IWN_EDCA_UPDATE (1 << 0) |
| 540 | #define IWN_EDCA_TXOP (1 << 4) |
| 541 | |
| 542 | struct { |
| 543 | uint16_t cwmin; |
| 544 | uint16_t cwmax; |
| 545 | uint8_t aifsn; |
| 546 | uint8_t reserved; |
| 547 | uint16_t txoplimit; |
| 548 | } __packed ac[WME_NUM_AC]; |
| 549 | } __packed; |
| 550 | |
| 551 | /* Structure for command IWN_CMD_TIMING. */ |
| 552 | struct iwn_cmd_timing { |
| 553 | uint64_t tstamp; |
| 554 | uint16_t bintval; |
| 555 | uint16_t atim; |
| 556 | uint32_t binitval; |
| 557 | uint16_t lintval; |
| 558 | uint16_t reserved; |
| 559 | } __packed; |
| 560 | |
| 561 | /* Structure for command IWN_CMD_ADD_NODE. */ |
| 562 | struct iwn_node_info { |
| 563 | uint8_t control; |
| 564 | #define IWN_NODE_UPDATE (1 << 0) |
| 565 | |
| 566 | uint8_t reserved1[3]; |
| 567 | |
| 568 | uint8_t macaddr[IEEE80211_ADDR_LEN]; |
| 569 | uint16_t reserved2; |
| 570 | uint8_t id; |
| 571 | #define IWN_ID_BSS 0 |
| 572 | #define IWN5000_ID_BROADCAST 15 |
| 573 | #define IWN4965_ID_BROADCAST 31 |
| 574 | |
| 575 | uint8_t flags; |
| 576 | #define IWN_FLAG_SET_KEY (1 << 0) |
| 577 | #define IWN_FLAG_SET_DISABLE_TID (1 << 1) |
| 578 | #define IWN_FLAG_SET_TXRATE (1 << 2) |
| 579 | #define IWN_FLAG_SET_ADDBA (1 << 3) |
| 580 | #define IWN_FLAG_SET_DELBA (1 << 4) |
| 581 | |
| 582 | uint16_t reserved3; |
| 583 | uint16_t kflags; |
| 584 | #define IWN_KFLAG_CCMP (1 << 1) |
| 585 | #define IWN_KFLAG_MAP (1 << 3) |
| 586 | #define IWN_KFLAG_KID(kid) ((kid) << 8) |
| 587 | #define IWN_KFLAG_INVALID (1 << 11) |
| 588 | #define IWN_KFLAG_GROUP (1 << 14) |
| 589 | |
| 590 | uint8_t tsc2; /* TKIP TSC2 */ |
| 591 | uint8_t reserved4; |
| 592 | uint16_t ttak[5]; |
| 593 | uint8_t kid; |
| 594 | uint8_t reserved5; |
| 595 | uint8_t key[16]; |
| 596 | /* The following 3 fields are for 5000 Series only. */ |
| 597 | uint64_t tsc; |
| 598 | uint8_t rxmic[IEEE80211_TKIP_MICLEN]; |
| 599 | uint8_t txmic[IEEE80211_TKIP_MICLEN]; |
| 600 | |
| 601 | uint32_t htflags; |
| 602 | #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) |
| 603 | #define IWN_AMDPU_DENSITY(x) ((x) << 23) |
| 604 | |
| 605 | uint32_t mask; |
| 606 | uint16_t disable_tid; |
| 607 | uint16_t reserved6; |
| 608 | uint8_t addba_tid; |
| 609 | uint8_t delba_tid; |
| 610 | uint16_t addba_ssn; |
| 611 | uint32_t reserved7; |
| 612 | } __packed; |
| 613 | |
| 614 | struct iwn4965_node_info { |
| 615 | uint8_t control; |
| 616 | uint8_t reserved1[3]; |
| 617 | uint8_t macaddr[IEEE80211_ADDR_LEN]; |
| 618 | uint16_t reserved2; |
| 619 | uint8_t id; |
| 620 | uint8_t flags; |
| 621 | uint16_t reserved3; |
| 622 | uint16_t kflags; |
| 623 | uint8_t tsc2; /* TKIP TSC2 */ |
| 624 | uint8_t reserved4; |
| 625 | uint16_t ttak[5]; |
| 626 | uint8_t kid; |
| 627 | uint8_t reserved5; |
| 628 | uint8_t key[16]; |
| 629 | uint32_t htflags; |
| 630 | uint32_t mask; |
| 631 | uint16_t disable_tid; |
| 632 | uint16_t reserved6; |
| 633 | uint8_t addba_tid; |
| 634 | uint8_t delba_tid; |
| 635 | uint16_t addba_ssn; |
| 636 | uint32_t reserved7; |
| 637 | } __packed; |
| 638 | |
| 639 | #define IWN_RFLAG_CCK (1 << 1) |
| 640 | #define IWN_RFLAG_ANT(x) ((x) << 6) |
| 641 | |
| 642 | /* Structure for command IWN_CMD_TX_DATA. */ |
| 643 | struct iwn_cmd_data { |
| 644 | uint16_t len; |
| 645 | uint16_t lnext; |
| 646 | uint32_t flags; |
| 647 | #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ |
| 648 | #define IWN_TX_NEED_RTS (1 << 1) |
| 649 | #define IWN_TX_NEED_CTS (1 << 2) |
| 650 | #define IWN_TX_NEED_ACK (1 << 3) |
| 651 | #define IWN_TX_LINKQ (1 << 4) |
| 652 | #define IWN_TX_IMM_BA (1 << 6) |
| 653 | #define IWN_TX_FULL_TXOP (1 << 7) |
| 654 | #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ |
| 655 | #define IWN_TX_AUTO_SEQ (1 << 13) |
| 656 | #define IWN_TX_MORE_FRAG (1 << 14) |
| 657 | #define IWN_TX_INSERT_TSTAMP (1 << 16) |
| 658 | #define IWN_TX_NEED_PADDING (1 << 20) |
| 659 | |
| 660 | uint32_t scratch; |
| 661 | uint8_t plcp; |
| 662 | uint8_t rflags; |
| 663 | uint16_t xrflags; |
| 664 | |
| 665 | uint8_t id; |
| 666 | uint8_t security; |
| 667 | #define IWN_CIPHER_WEP40 1 |
| 668 | #define IWN_CIPHER_CCMP 2 |
| 669 | #define IWN_CIPHER_TKIP 3 |
| 670 | #define IWN_CIPHER_WEP104 9 |
| 671 | |
| 672 | uint8_t linkq; |
| 673 | uint8_t reserved2; |
| 674 | uint8_t key[16]; |
| 675 | uint16_t fnext; |
| 676 | uint16_t reserved3; |
| 677 | uint32_t lifetime; |
| 678 | #define IWN_LIFETIME_INFINITE 0xffffffff |
| 679 | |
| 680 | uint32_t loaddr; |
| 681 | uint8_t hiaddr; |
| 682 | uint8_t rts_ntries; |
| 683 | uint8_t data_ntries; |
| 684 | uint8_t tid; |
| 685 | uint16_t timeout; |
| 686 | uint16_t txop; |
| 687 | } __packed; |
| 688 | |
| 689 | /* Structure for command IWN_CMD_LINK_QUALITY. */ |
| 690 | #define IWN_MAX_TX_RETRIES 16 |
| 691 | struct iwn_cmd_link_quality { |
| 692 | uint8_t id; |
| 693 | uint8_t reserved1; |
| 694 | uint16_t ctl; |
| 695 | uint8_t flags; |
| 696 | uint8_t mimo; |
| 697 | uint8_t antmsk_1stream; |
| 698 | uint8_t antmsk_2stream; |
| 699 | uint8_t ridx[WME_NUM_AC]; |
| 700 | uint16_t ampdu_limit; |
| 701 | uint8_t ampdu_threshold; |
| 702 | uint8_t ampdu_max; |
| 703 | uint32_t reserved2; |
| 704 | struct { |
| 705 | uint8_t plcp; |
| 706 | uint8_t rflags; |
| 707 | uint16_t xrflags; |
| 708 | } __packed retry[IWN_MAX_TX_RETRIES]; |
| 709 | uint32_t reserved3; |
| 710 | } __packed; |
| 711 | |
| 712 | /* Structure for command IWN_CMD_SET_LED. */ |
| 713 | struct iwn_cmd_led { |
| 714 | uint32_t unit; /* multiplier (in usecs) */ |
| 715 | uint8_t which; |
| 716 | #define IWN_LED_ACTIVITY 1 |
| 717 | #define IWN_LED_LINK 2 |
| 718 | |
| 719 | uint8_t off; |
| 720 | uint8_t on; |
| 721 | uint8_t reserved; |
| 722 | } __packed; |
| 723 | |
| 724 | /* Structure for command IWN5000_CMD_WIMAX_COEX. */ |
| 725 | struct iwn5000_wimax_coex { |
| 726 | uint32_t flags; |
| 727 | #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) |
| 728 | #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) |
| 729 | #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) |
| 730 | #define IWN_WIMAX_COEX_ENABLE (1 << 7) |
| 731 | |
| 732 | struct iwn5000_wimax_event { |
| 733 | uint8_t request; |
| 734 | uint8_t window; |
| 735 | uint8_t reserved; |
| 736 | uint8_t flags; |
| 737 | } __packed events[16]; |
| 738 | } __packed; |
| 739 | |
| 740 | /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ |
| 741 | struct iwn5000_calib_elem { |
| 742 | uint32_t enable; |
| 743 | uint32_t start; |
| 744 | #define IWN5000_CALIB_DC (1 << 1) |
| 745 | uint32_t send; |
| 746 | uint32_t apply; |
| 747 | uint32_t reserved; |
| 748 | } __packed; |
| 749 | |
| 750 | struct iwn5000_calib_status { |
| 751 | struct iwn5000_calib_elem once; |
| 752 | struct iwn5000_calib_elem perd; |
| 753 | uint32_t flags; |
| 754 | } __packed; |
| 755 | |
| 756 | struct iwn5000_calib_config { |
| 757 | struct iwn5000_calib_status ucode; |
| 758 | struct iwn5000_calib_status driver; |
| 759 | uint32_t reserved; |
| 760 | } __packed; |
| 761 | |
| 762 | /* Structure for command IWN_CMD_SET_POWER_MODE. */ |
| 763 | struct iwn_pmgt_cmd { |
| 764 | uint16_t flags; |
| 765 | #define IWN_PS_ALLOW_SLEEP (1 << 0) |
| 766 | #define IWN_PS_NOTIFY (1 << 1) |
| 767 | #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) |
| 768 | #define IWN_PS_PCI_PMGT (1 << 3) |
| 769 | #define IWN_PS_FAST_PD (1 << 4) |
| 770 | |
| 771 | uint8_t keepalive; |
| 772 | uint8_t debug; |
| 773 | uint32_t rxtimeout; |
| 774 | uint32_t txtimeout; |
| 775 | uint32_t intval[5]; |
| 776 | uint32_t beacons; |
| 777 | } __packed; |
| 778 | |
| 779 | /* Structures for command IWN_CMD_SCAN. */ |
| 780 | struct iwn_scan_essid { |
| 781 | uint8_t id; |
| 782 | uint8_t len; |
| 783 | uint8_t data[IEEE80211_NWID_LEN]; |
| 784 | } __packed; |
| 785 | |
| 786 | struct iwn_scan_hdr { |
| 787 | uint16_t len; |
| 788 | uint8_t reserved1; |
| 789 | uint8_t nchan; |
| 790 | uint16_t quiet_time; |
| 791 | uint16_t quiet_threshold; |
| 792 | uint16_t crc_threshold; |
| 793 | uint16_t rxchain; |
| 794 | uint32_t max_svc; /* background scans */ |
| 795 | uint32_t pause_svc; /* background scans */ |
| 796 | uint32_t flags; |
| 797 | uint32_t filter; |
| 798 | |
| 799 | /* Followed by a struct iwn_cmd_data. */ |
| 800 | /* Followed by an array of 20 structs iwn_scan_essid. */ |
| 801 | /* Followed by probe request body. */ |
| 802 | /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ |
| 803 | } __packed; |
| 804 | |
| 805 | struct iwn_scan_chan { |
| 806 | uint32_t flags; |
| 807 | #define IWN_CHAN_ACTIVE (1 << 0) |
| 808 | #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) |
| 809 | |
| 810 | uint16_t chan; |
| 811 | uint8_t rf_gain; |
| 812 | uint8_t dsp_gain; |
| 813 | uint16_t active; /* msecs */ |
| 814 | uint16_t passive; /* msecs */ |
| 815 | } __packed; |
| 816 | |
| 817 | /* Maximum size of a scan command. */ |
| 818 | #define IWN_SCAN_MAXSZ (MCLBYTES - 4) |
| 819 | |
| 820 | /* |
| 821 | * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
| 822 | * sending probe req. This should be set long enough to hear probe responses |
| 823 | * from more than one AP. |
| 824 | */ |
| 825 | #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ |
| 826 | #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) |
| 827 | #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) |
| 828 | #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) |
| 829 | |
| 830 | /* |
| 831 | * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. |
| 832 | * Must be set longer than active dwell time. |
| 833 | * For the most reliable scan, set > AP beacon interval (typically 100msec). |
| 834 | */ |
| 835 | #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ |
| 836 | #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) |
| 837 | #define IWN_PASSIVE_DWELL_BASE (100) |
| 838 | #define IWN_CHANNEL_TUNE_TIME (5) |
| 839 | |
| 840 | /* |
| 841 | * If active scanning is requested but a certain channel is |
| 842 | * marked passive, we can do active scanning if we detect |
| 843 | * transmissions. |
| 844 | * |
| 845 | * There is an issue with some firmware versions that triggers |
| 846 | * a sysassert on a "good CRC threshold" of zero (== disabled), |
| 847 | * on a radar channel even though this means that we should NOT |
| 848 | * send probes. |
| 849 | * |
| 850 | * The "good CRC threshold" is the number of frames that we |
| 851 | * need to receive during our dwell time on a channel before |
| 852 | * sending out probes -- setting this to a huge value will |
| 853 | * mean we never reach it, but at the same time work around |
| 854 | * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER |
| 855 | * here instead of IWN_GOOD_CRC_TH_DISABLED. |
| 856 | * |
| 857 | * This was fixed in later versions along with some other |
| 858 | * scan changes, and the threshold behaves as a flag in those |
| 859 | * versions. |
| 860 | */ |
| 861 | #define IWN_GOOD_CRC_TH_DISABLED 0 |
| 862 | #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) |
| 863 | #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) |
| 864 | |
| 865 | /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ |
| 866 | #define IWN_RIDX_MAX 32 |
| 867 | struct iwn4965_cmd_txpower { |
| 868 | uint8_t band; |
| 869 | uint8_t reserved1; |
| 870 | uint8_t chan; |
| 871 | uint8_t reserved2; |
| 872 | struct { |
| 873 | uint8_t rf_gain[2]; |
| 874 | uint8_t dsp_gain[2]; |
| 875 | } __packed power[IWN_RIDX_MAX + 1]; |
| 876 | } __packed; |
| 877 | |
| 878 | /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ |
| 879 | struct iwn5000_cmd_txpower { |
| 880 | int8_t global_limit; /* in half-dBm */ |
| 881 | #define IWN5000_TXPOWER_AUTO 0x7f |
| 882 | #define IWN5000_TXPOWER_MAX_DBM 16 |
| 883 | |
| 884 | uint8_t flags; |
| 885 | #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) |
| 886 | |
| 887 | int8_t srv_limit; /* in half-dBm */ |
| 888 | uint8_t reserved; |
| 889 | } __packed; |
| 890 | |
| 891 | /* Structure for command IWN_CMD_BT_COEX. */ |
| 892 | struct iwn_bluetooth { |
| 893 | uint8_t flags; |
| 894 | #define IWN_BT_COEX_CHAN_ANN (1 << 0) |
| 895 | #define IWN_BT_COEX_BT_PRIO (1 << 1) |
| 896 | #define IWN_BT_COEX_2_WIRE (1 << 2) |
| 897 | #define IWN_BT_COEX_ENABLE (IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO) |
| 898 | uint8_t lead_time; |
| 899 | #define IWN_BT_LEAD_TIME_DEF 30 |
| 900 | uint8_t max_kill; |
| 901 | #define IWN_BT_MAX_KILL_DEF 5 |
| 902 | uint8_t bt3_timer_t7_value; |
| 903 | #define IWN_BT_BT3_T7_DEF 1 |
| 904 | uint32_t kill_ack_mask; |
| 905 | #define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000) |
| 906 | uint32_t kill_cts_mask; |
| 907 | #define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000) |
| 908 | } __packed; |
| 909 | |
| 910 | struct iwn_bt_basic { |
| 911 | struct iwn_bluetooth bt; |
| 912 | #define IWN_BT_BASIC_CHAN_INHIBITION 1 |
| 913 | #define IWN_BT_BASIC_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) |
| 914 | #define IWN_BT_BASIC_MODE_SHIFT 3 |
| 915 | #define IWN_BT_BASIC_MODE_DISABLED 0 |
| 916 | #define IWN_BT_BASIC_MODE_LEGACY_2W 1 |
| 917 | #define IWN_BT_BASIC_MODE_3W 2 |
| 918 | #define IWN_BT_BASIC_MODE_4W 3 |
| 919 | #define IWN_BT_UCODE_DEFAULT (1 << 6) |
| 920 | #define IWN_BT_SYNC_2_BT_DISABLE (1 << 7) |
| 921 | uint8_t bt3_prio_sample_time; |
| 922 | #define IWN_BT_BT3_PRIO_SAMPLE_DEF 2 |
| 923 | uint8_t bt3_timer_t2_value; |
| 924 | #define IWN_BT_BT3_T2_DEF 12 |
| 925 | uint16_t bt4_reaction_time; /* unused */ |
| 926 | uint32_t bt3_lookup_table[12]; |
| 927 | union { |
| 928 | struct { |
| 929 | uint8_t reduce_txpower; /* bit 0 */ |
| 930 | uint8_t reserved; |
| 931 | }; |
| 932 | uint16_t bt4_decision; |
| 933 | }; |
| 934 | uint16_t valid; |
| 935 | #define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0) |
| 936 | #define IWN_BT_VALID_BOOST htole16(1 << 1) |
| 937 | #define IWN_BT_VALID_MAX_KILL htole16(1 << 2) |
| 938 | #define IWN_BT_VALID_3W_TIMERS htole16(1 << 3) |
| 939 | #define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4) |
| 940 | #define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5) |
| 941 | #define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6) |
| 942 | #define IWN_BT_VALID_3W_LUT htole16(1 << 7) |
| 943 | #define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \ |
| 944 | IWN_BT_VALID_BOOST | \ |
| 945 | IWN_BT_VALID_MAX_KILL | \ |
| 946 | IWN_BT_VALID_3W_TIMERS | \ |
| 947 | IWN_BT_VALID_KILL_ACK_MASK | \ |
| 948 | IWN_BT_VALID_KILL_CTS_MASK | \ |
| 949 | IWN_BT_VALID_REDUCED_TX_PWR | \ |
| 950 | IWN_BT_VALID_3W_LUT) |
| 951 | } __packed; |
| 952 | |
| 953 | struct iwn_bt_adv1 { |
| 954 | struct iwn_bt_basic basic; |
| 955 | uint8_t prio_boost; |
| 956 | #define IWN_BT_PRIO_BOOST_DEF 0xf0 |
| 957 | /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ |
| 958 | uint8_t tx_prio_boost; |
| 959 | uint16_t rx_prio_boost; |
| 960 | } __packed; |
| 961 | |
| 962 | struct iwn_bt_adv2 { |
| 963 | struct iwn_bt_basic basic; |
| 964 | uint32_t prio_boost; |
| 965 | #define IWN_BT_PRIO_BOOST_DEF32 0xf0f0f0 |
| 966 | uint8_t reserved; |
| 967 | /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ |
| 968 | uint8_t tx_prio_boost; |
| 969 | uint16_t rx_prio_boost; |
| 970 | } __packed; |
| 971 | |
| 972 | /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ |
| 973 | struct iwn_btcoex_priotable { |
| 974 | uint8_t calib_init1; |
| 975 | uint8_t calib_init2; |
| 976 | uint8_t calib_periodic_low1; |
| 977 | uint8_t calib_periodic_low2; |
| 978 | uint8_t calib_periodic_high1; |
| 979 | uint8_t calib_periodic_high2; |
| 980 | uint8_t dtim; |
| 981 | uint8_t scan52; |
| 982 | uint8_t scan24; |
| 983 | uint8_t reserved[7]; |
| 984 | } __packed; |
| 985 | |
| 986 | /* Structure for command IWN_CMD_BT_COEX_PROT */ |
| 987 | struct iwn_btcoex_prot { |
| 988 | uint8_t open; |
| 989 | uint8_t type; |
| 990 | uint8_t reserved[2]; |
| 991 | } __packed; |
| 992 | |
| 993 | /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ |
| 994 | struct iwn_critical_temp { |
| 995 | uint32_t reserved; |
| 996 | uint32_t tempM; |
| 997 | uint32_t tempR; |
| 998 | /* degK <-> degC conversion macros. */ |
| 999 | #define IWN_CTOK(c) ((c) + 273) |
| 1000 | #define IWN_KTOC(k) ((k) - 273) |
| 1001 | #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) |
| 1002 | } __packed; |
| 1003 | |
| 1004 | /* Structures for command IWN_CMD_SET_SENSITIVITY. */ |
| 1005 | struct iwn_sensitivity_cmd { |
| 1006 | uint16_t which; |
| 1007 | #define IWN_SENSITIVITY_DEFAULTTBL 0 |
| 1008 | #define IWN_SENSITIVITY_WORKTBL 1 |
| 1009 | |
| 1010 | uint16_t energy_cck; |
| 1011 | uint16_t energy_ofdm; |
| 1012 | uint16_t corr_ofdm_x1; |
| 1013 | uint16_t corr_ofdm_mrc_x1; |
| 1014 | uint16_t corr_cck_mrc_x4; |
| 1015 | uint16_t corr_ofdm_x4; |
| 1016 | uint16_t corr_ofdm_mrc_x4; |
| 1017 | uint16_t corr_barker; |
| 1018 | uint16_t corr_barker_mrc; |
| 1019 | uint16_t corr_cck_x4; |
| 1020 | uint16_t energy_ofdm_th; |
| 1021 | } __packed; |
| 1022 | |
| 1023 | struct iwn_enhanced_sensitivity_cmd { |
| 1024 | uint16_t which; |
| 1025 | uint16_t energy_cck; |
| 1026 | uint16_t energy_ofdm; |
| 1027 | uint16_t corr_ofdm_x1; |
| 1028 | uint16_t corr_ofdm_mrc_x1; |
| 1029 | uint16_t corr_cck_mrc_x4; |
| 1030 | uint16_t corr_ofdm_x4; |
| 1031 | uint16_t corr_ofdm_mrc_x4; |
| 1032 | uint16_t corr_barker; |
| 1033 | uint16_t corr_barker_mrc; |
| 1034 | uint16_t corr_cck_x4; |
| 1035 | uint16_t energy_ofdm_th; |
| 1036 | /* "Enhanced" part. */ |
| 1037 | uint16_t ina_det_ofdm; |
| 1038 | uint16_t ina_det_cck; |
| 1039 | uint16_t corr_11_9_en; |
| 1040 | uint16_t ofdm_det_slope_mrc; |
| 1041 | uint16_t ofdm_det_icept_mrc; |
| 1042 | uint16_t ofdm_det_slope; |
| 1043 | uint16_t ofdm_det_icept; |
| 1044 | uint16_t cck_det_slope_mrc; |
| 1045 | uint16_t cck_det_icept_mrc; |
| 1046 | uint16_t cck_det_slope; |
| 1047 | uint16_t cck_det_icept; |
| 1048 | uint16_t reserved; |
| 1049 | } __packed; |
| 1050 | |
| 1051 | /* Structures for command IWN_CMD_PHY_CALIB. */ |
| 1052 | struct iwn_phy_calib { |
| 1053 | uint8_t code; |
| 1054 | #define IWN4965_PHY_CALIB_DIFF_GAIN 7 |
| 1055 | #define IWN5000_PHY_CALIB_DC 8 |
| 1056 | #define IWN5000_PHY_CALIB_LO 9 |
| 1057 | #define IWN5000_PHY_CALIB_TX_IQ 11 |
| 1058 | #define IWN5000_PHY_CALIB_CRYSTAL 15 |
| 1059 | #define IWN5000_PHY_CALIB_BASE_BAND 16 |
| 1060 | #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 |
| 1061 | #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 |
| 1062 | #define IWN5000_PHY_CALIB_NOISE_GAIN 19 |
| 1063 | |
| 1064 | #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 |
| 1065 | #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 |
| 1066 | |
| 1067 | #define IWN5000_PHY_CALIB_MAX 253 |
| 1068 | |
| 1069 | uint8_t group; |
| 1070 | uint8_t ngroups; |
| 1071 | uint8_t isvalid; |
| 1072 | } __packed; |
| 1073 | |
| 1074 | struct iwn5000_phy_calib_crystal { |
| 1075 | uint8_t code; |
| 1076 | uint8_t group; |
| 1077 | uint8_t ngroups; |
| 1078 | uint8_t isvalid; |
| 1079 | |
| 1080 | uint8_t cap_pin[2]; |
| 1081 | uint8_t reserved[2]; |
| 1082 | } __packed; |
| 1083 | |
| 1084 | struct iwn6000_phy_calib_temp_offset { |
| 1085 | uint8_t code; |
| 1086 | uint8_t group; |
| 1087 | uint8_t ngroups; |
| 1088 | uint8_t isvalid; |
| 1089 | int16_t offset; |
| 1090 | #define IWN_DEFAULT_TEMP_OFFSET 2700 |
| 1091 | |
| 1092 | uint16_t reserved; |
| 1093 | } __packed; |
| 1094 | |
| 1095 | struct iwn2000_phy_calib_temp_offset { |
| 1096 | uint8_t code; |
| 1097 | uint8_t group; |
| 1098 | uint8_t ngroups; |
| 1099 | uint8_t isvalid; |
| 1100 | int16_t offset_high; |
| 1101 | int16_t offset_low; |
| 1102 | int16_t burnt_voltage_ref; |
| 1103 | int16_t reserved; |
| 1104 | } __packed; |
| 1105 | |
| 1106 | struct iwn_phy_calib_gain { |
| 1107 | uint8_t code; |
| 1108 | uint8_t group; |
| 1109 | uint8_t ngroups; |
| 1110 | uint8_t isvalid; |
| 1111 | |
| 1112 | int8_t gain[3]; |
| 1113 | uint8_t reserved; |
| 1114 | } __packed; |
| 1115 | |
| 1116 | /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ |
| 1117 | struct iwn_spectrum_cmd { |
| 1118 | uint16_t len; |
| 1119 | uint8_t token; |
| 1120 | uint8_t id; |
| 1121 | uint8_t origin; |
| 1122 | uint8_t periodic; |
| 1123 | uint16_t timeout; |
| 1124 | uint32_t start; |
| 1125 | uint32_t reserved1; |
| 1126 | uint32_t flags; |
| 1127 | uint32_t filter; |
| 1128 | uint16_t nchan; |
| 1129 | uint16_t reserved2; |
| 1130 | struct { |
| 1131 | uint32_t duration; |
| 1132 | uint8_t chan; |
| 1133 | uint8_t type; |
| 1134 | #define IWN_MEASUREMENT_BASIC (1 << 0) |
| 1135 | #define IWN_MEASUREMENT_CCA (1 << 1) |
| 1136 | #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) |
| 1137 | #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) |
| 1138 | #define IWN_MEASUREMENT_FRAME (1 << 4) |
| 1139 | #define IWN_MEASUREMENT_IDLE (1 << 7) |
| 1140 | |
| 1141 | uint16_t reserved; |
| 1142 | } __packed chan[10]; |
| 1143 | } __packed; |
| 1144 | |
| 1145 | /* Structure for IWN_UC_READY notification. */ |
| 1146 | #define IWN_NATTEN_GROUPS 5 |
| 1147 | struct iwn_ucode_info { |
| 1148 | uint8_t minor; |
| 1149 | uint8_t major; |
| 1150 | uint16_t reserved1; |
| 1151 | uint8_t revision[8]; |
| 1152 | uint8_t type; |
| 1153 | uint8_t subtype; |
| 1154 | #define IWN_UCODE_RUNTIME 0 |
| 1155 | #define IWN_UCODE_INIT 9 |
| 1156 | |
| 1157 | uint16_t reserved2; |
| 1158 | uint32_t logptr; |
| 1159 | uint32_t errptr; |
| 1160 | uint32_t tstamp; |
| 1161 | uint32_t valid; |
| 1162 | |
| 1163 | /* The following fields are for UCODE_INIT only. */ |
| 1164 | int32_t volt; |
| 1165 | struct { |
| 1166 | int32_t chan20MHz; |
| 1167 | int32_t chan40MHz; |
| 1168 | } __packed temp[4]; |
| 1169 | int32_t atten[IWN_NATTEN_GROUPS][2]; |
| 1170 | } __packed; |
| 1171 | |
| 1172 | /* Structures for IWN_TX_DONE notification. */ |
| 1173 | struct iwn4965_tx_stat { |
| 1174 | uint8_t nframes; |
| 1175 | uint8_t btkillcnt; |
| 1176 | uint8_t rtsfailcnt; |
| 1177 | uint8_t ackfailcnt; |
| 1178 | uint8_t rate; |
| 1179 | uint8_t rflags; |
| 1180 | uint16_t xrflags; |
| 1181 | uint16_t duration; |
| 1182 | uint16_t reserved; |
| 1183 | uint32_t power[2]; |
| 1184 | uint32_t status; |
| 1185 | } __packed; |
| 1186 | |
| 1187 | struct iwn5000_tx_stat { |
| 1188 | uint8_t nframes; |
| 1189 | uint8_t btkillcnt; |
| 1190 | uint8_t rtsfailcnt; |
| 1191 | uint8_t ackfailcnt; |
| 1192 | uint8_t rate; |
| 1193 | uint8_t rflags; |
| 1194 | uint16_t xrflags; |
| 1195 | uint16_t duration; |
| 1196 | uint16_t reserved; |
| 1197 | uint32_t power[2]; |
| 1198 | uint32_t info; |
| 1199 | uint16_t seq; |
| 1200 | uint16_t len; |
| 1201 | uint8_t tlc; |
| 1202 | uint8_t ratid; |
| 1203 | uint8_t fc[2]; |
| 1204 | uint16_t status; |
| 1205 | uint16_t sequence; |
| 1206 | } __packed; |
| 1207 | |
| 1208 | /* Structure for IWN_BEACON_MISSED notification. */ |
| 1209 | struct iwn_beacon_missed { |
| 1210 | uint32_t consecutive; |
| 1211 | uint32_t total; |
| 1212 | uint32_t expected; |
| 1213 | uint32_t received; |
| 1214 | } __packed; |
| 1215 | |
| 1216 | /* Structure for IWN_MPDU_RX_DONE notification. */ |
| 1217 | struct iwn_rx_mpdu { |
| 1218 | uint16_t len; |
| 1219 | uint16_t reserved; |
| 1220 | } __packed; |
| 1221 | |
| 1222 | /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ |
| 1223 | struct iwn4965_rx_phystat { |
| 1224 | uint16_t antenna; |
| 1225 | uint16_t agc; |
| 1226 | uint8_t [6]; |
| 1227 | } __packed; |
| 1228 | |
| 1229 | struct iwn5000_rx_phystat { |
| 1230 | uint32_t reserved1; |
| 1231 | uint32_t agc; |
| 1232 | uint16_t [3]; |
| 1233 | } __packed; |
| 1234 | |
| 1235 | struct iwn_rx_stat { |
| 1236 | uint8_t phy_len; |
| 1237 | uint8_t cfg_phy_len; |
| 1238 | #define IWN_STAT_MAXLEN 20 |
| 1239 | |
| 1240 | uint8_t id; |
| 1241 | uint8_t reserved1; |
| 1242 | uint64_t tstamp; |
| 1243 | uint32_t beacon; |
| 1244 | uint16_t flags; |
| 1245 | #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) |
| 1246 | |
| 1247 | uint16_t chan; |
| 1248 | uint8_t phybuf[32]; |
| 1249 | uint8_t rate; |
| 1250 | uint8_t rflags; |
| 1251 | uint16_t xrflags; |
| 1252 | uint16_t len; |
| 1253 | uint16_t reserve3; |
| 1254 | } __packed; |
| 1255 | |
| 1256 | #define 44 |
| 1257 | |
| 1258 | /* Structure for IWN_RX_COMPRESSED_BA notification. */ |
| 1259 | struct iwn_compressed_ba { |
| 1260 | uint8_t macaddr[IEEE80211_ADDR_LEN]; |
| 1261 | uint16_t reserved; |
| 1262 | uint8_t id; |
| 1263 | uint8_t tid; |
| 1264 | uint16_t seq; |
| 1265 | uint64_t bitmap; |
| 1266 | uint16_t qid; |
| 1267 | uint16_t ssn; |
| 1268 | } __packed; |
| 1269 | |
| 1270 | /* Structure for IWN_START_SCAN notification. */ |
| 1271 | struct iwn_start_scan { |
| 1272 | uint64_t tstamp; |
| 1273 | uint32_t tbeacon; |
| 1274 | uint8_t chan; |
| 1275 | uint8_t band; |
| 1276 | uint16_t reserved; |
| 1277 | uint32_t status; |
| 1278 | } __packed; |
| 1279 | |
| 1280 | /* Structure for IWN_STOP_SCAN notification. */ |
| 1281 | struct iwn_stop_scan { |
| 1282 | uint8_t nchan; |
| 1283 | uint8_t status; |
| 1284 | uint8_t reserved; |
| 1285 | uint8_t chan; |
| 1286 | uint64_t tsf; |
| 1287 | } __packed; |
| 1288 | |
| 1289 | /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ |
| 1290 | struct iwn_spectrum_notif { |
| 1291 | uint8_t id; |
| 1292 | uint8_t token; |
| 1293 | uint8_t idx; |
| 1294 | uint8_t state; |
| 1295 | #define IWN_MEASUREMENT_START 0 |
| 1296 | #define IWN_MEASUREMENT_STOP 1 |
| 1297 | |
| 1298 | uint32_t start; |
| 1299 | uint8_t band; |
| 1300 | uint8_t chan; |
| 1301 | uint8_t type; |
| 1302 | uint8_t reserved1; |
| 1303 | uint32_t cca_ofdm; |
| 1304 | uint32_t cca_cck; |
| 1305 | uint32_t cca_time; |
| 1306 | uint8_t basic; |
| 1307 | uint8_t reserved2[3]; |
| 1308 | uint32_t ofdm[8]; |
| 1309 | uint32_t cck[8]; |
| 1310 | uint32_t stop; |
| 1311 | uint32_t status; |
| 1312 | #define IWN_MEASUREMENT_OK 0 |
| 1313 | #define IWN_MEASUREMENT_CONCURRENT 1 |
| 1314 | #define IWN_MEASUREMENT_CSA_CONFLICT 2 |
| 1315 | #define IWN_MEASUREMENT_TGH_CONFLICT 3 |
| 1316 | #define IWN_MEASUREMENT_STOPPED 6 |
| 1317 | #define IWN_MEASUREMENT_TIMEOUT 7 |
| 1318 | #define IWN_MEASUREMENT_FAILED 8 |
| 1319 | } __packed; |
| 1320 | |
| 1321 | /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ |
| 1322 | struct iwn_rx_phy_stats { |
| 1323 | uint32_t ina; |
| 1324 | uint32_t fina; |
| 1325 | uint32_t bad_plcp; |
| 1326 | uint32_t bad_crc32; |
| 1327 | uint32_t overrun; |
| 1328 | uint32_t eoverrun; |
| 1329 | uint32_t good_crc32; |
| 1330 | uint32_t fa; |
| 1331 | uint32_t bad_fina_sync; |
| 1332 | uint32_t sfd_timeout; |
| 1333 | uint32_t fina_timeout; |
| 1334 | uint32_t no_rts_ack; |
| 1335 | uint32_t rxe_limit; |
| 1336 | uint32_t ack; |
| 1337 | uint32_t cts; |
| 1338 | uint32_t ba_resp; |
| 1339 | uint32_t dsp_kill; |
| 1340 | uint32_t bad_mh; |
| 1341 | uint32_t ; |
| 1342 | uint32_t reserved; |
| 1343 | } __packed; |
| 1344 | |
| 1345 | struct iwn_rx_general_stats { |
| 1346 | uint32_t bad_cts; |
| 1347 | uint32_t bad_ack; |
| 1348 | uint32_t not_bss; |
| 1349 | uint32_t filtered; |
| 1350 | uint32_t bad_chan; |
| 1351 | uint32_t beacons; |
| 1352 | uint32_t missed_beacons; |
| 1353 | uint32_t adc_saturated; /* time in 0.8us */ |
| 1354 | uint32_t ina_searched; /* time in 0.8us */ |
| 1355 | uint32_t noise[3]; |
| 1356 | uint32_t flags; |
| 1357 | uint32_t load; |
| 1358 | uint32_t fa; |
| 1359 | uint32_t [3]; |
| 1360 | uint32_t energy[3]; |
| 1361 | } __packed; |
| 1362 | |
| 1363 | struct iwn_rx_ht_phy_stats { |
| 1364 | uint32_t bad_plcp; |
| 1365 | uint32_t overrun; |
| 1366 | uint32_t eoverrun; |
| 1367 | uint32_t good_crc32; |
| 1368 | uint32_t bad_crc32; |
| 1369 | uint32_t bad_mh; |
| 1370 | uint32_t good_ampdu_crc32; |
| 1371 | uint32_t ampdu; |
| 1372 | uint32_t fragment; |
| 1373 | uint32_t reserved; |
| 1374 | } __packed; |
| 1375 | |
| 1376 | struct iwn_rx_stats { |
| 1377 | struct iwn_rx_phy_stats ofdm; |
| 1378 | struct iwn_rx_phy_stats cck; |
| 1379 | struct iwn_rx_general_stats general; |
| 1380 | struct iwn_rx_ht_phy_stats ht; |
| 1381 | } __packed; |
| 1382 | |
| 1383 | struct iwn_tx_stats { |
| 1384 | uint32_t preamble; |
| 1385 | uint32_t rx_detected; |
| 1386 | uint32_t bt_defer; |
| 1387 | uint32_t bt_kill; |
| 1388 | uint32_t short_len; |
| 1389 | uint32_t cts_timeout; |
| 1390 | uint32_t ack_timeout; |
| 1391 | uint32_t exp_ack; |
| 1392 | uint32_t ack; |
| 1393 | uint32_t msdu; |
| 1394 | uint32_t busrt_err1; |
| 1395 | uint32_t burst_err2; |
| 1396 | uint32_t cts_collision; |
| 1397 | uint32_t ack_collision; |
| 1398 | uint32_t ba_timeout; |
| 1399 | uint32_t ba_resched; |
| 1400 | uint32_t query_ampdu; |
| 1401 | uint32_t query; |
| 1402 | uint32_t query_ampdu_frag; |
| 1403 | uint32_t query_mismatch; |
| 1404 | uint32_t not_ready; |
| 1405 | uint32_t underrun; |
| 1406 | uint32_t bt_ht_kill; |
| 1407 | uint32_t rx_ba_resp; |
| 1408 | uint32_t reserved[2]; |
| 1409 | } __packed; |
| 1410 | |
| 1411 | struct iwn_general_stats { |
| 1412 | uint32_t temp; |
| 1413 | uint32_t temp_m; |
| 1414 | uint32_t burst_check; |
| 1415 | uint32_t burst; |
| 1416 | uint32_t reserved1[4]; |
| 1417 | uint32_t sleep; |
| 1418 | uint32_t slot_out; |
| 1419 | uint32_t slot_idle; |
| 1420 | uint32_t ttl_tstamp; |
| 1421 | uint32_t tx_ant_a; |
| 1422 | uint32_t tx_ant_b; |
| 1423 | uint32_t exec; |
| 1424 | uint32_t probe; |
| 1425 | uint32_t reserved2[2]; |
| 1426 | uint32_t rx_enabled; |
| 1427 | uint32_t reserved3[3]; |
| 1428 | } __packed; |
| 1429 | |
| 1430 | struct iwn_stats { |
| 1431 | uint32_t flags; |
| 1432 | struct iwn_rx_stats rx; |
| 1433 | struct iwn_tx_stats tx; |
| 1434 | struct iwn_general_stats general; |
| 1435 | } __packed; |
| 1436 | |
| 1437 | |
| 1438 | /* Firmware error dump. */ |
| 1439 | struct iwn_fw_dump { |
| 1440 | uint32_t valid; |
| 1441 | uint32_t id; |
| 1442 | uint32_t pc; |
| 1443 | uint32_t branch_link[2]; |
| 1444 | uint32_t interrupt_link[2]; |
| 1445 | uint32_t error_data[2]; |
| 1446 | uint32_t src_line; |
| 1447 | uint32_t tsf; |
| 1448 | uint32_t time[2]; |
| 1449 | } __packed; |
| 1450 | |
| 1451 | /* TLV firmware header. */ |
| 1452 | struct iwn_fw_tlv_hdr { |
| 1453 | uint32_t zero; /* Always 0, to differentiate from legacy. */ |
| 1454 | uint32_t signature; |
| 1455 | #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ |
| 1456 | |
| 1457 | uint8_t descr[64]; |
| 1458 | uint32_t rev; |
| 1459 | #define IWN_FW_API(x) (((x) >> 8) & 0xff) |
| 1460 | |
| 1461 | uint32_t build; |
| 1462 | uint64_t altmask; |
| 1463 | } __packed; |
| 1464 | |
| 1465 | /* TLV header. */ |
| 1466 | struct iwn_fw_tlv { |
| 1467 | uint16_t type; |
| 1468 | #define IWN_FW_TLV_MAIN_TEXT 1 |
| 1469 | #define IWN_FW_TLV_MAIN_DATA 2 |
| 1470 | #define IWN_FW_TLV_INIT_TEXT 3 |
| 1471 | #define IWN_FW_TLV_INIT_DATA 4 |
| 1472 | #define IWN_FW_TLV_BOOT_TEXT 5 |
| 1473 | #define IWN_FW_TLV_PBREQ_MAXLEN 6 |
| 1474 | #define IWN_FW_TLV_ENH_SENS 14 |
| 1475 | #define IWN_FW_TLV_PHY_CALIB 15 |
| 1476 | #define IWN_FW_TLV_FLAGS 18 |
| 1477 | |
| 1478 | uint16_t alt; |
| 1479 | uint32_t len; |
| 1480 | } __packed; |
| 1481 | |
| 1482 | #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) |
| 1483 | #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) |
| 1484 | #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) |
| 1485 | #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) |
| 1486 | #define IWN_FW_BOOT_TEXT_MAXSZ 1024 |
| 1487 | #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) |
| 1488 | #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ |
| 1489 | |
| 1490 | /** |
| 1491 | * enum iwn_ucode_tlv_flag - ucode API flags |
| 1492 | * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously |
| 1493 | * was a separate TLV but moved here to save space. |
| 1494 | * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, |
| 1495 | * treats good CRC threshold as a boolean |
| 1496 | * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). |
| 1497 | * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. |
| 1498 | * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS |
| 1499 | * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD |
| 1500 | * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan |
| 1501 | * offload profile config command. |
| 1502 | * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api |
| 1503 | * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. |
| 1504 | * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six |
| 1505 | * (rather than two) IPv6 addresses |
| 1506 | * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API |
| 1507 | * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element |
| 1508 | * from the probe request template. |
| 1509 | * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping |
| 1510 | * connection when going back to D0 |
| 1511 | * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) |
| 1512 | * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) |
| 1513 | * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. |
| 1514 | * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API |
| 1515 | * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command |
| 1516 | * containing CAM (Continuous Active Mode) indication. |
| 1517 | */ |
| 1518 | enum iwn_ucode_tlv_flag { |
| 1519 | IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), |
| 1520 | IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), |
| 1521 | IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), |
| 1522 | IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), |
| 1523 | IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), |
| 1524 | IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), |
| 1525 | IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), |
| 1526 | IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), |
| 1527 | IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), |
| 1528 | IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), |
| 1529 | IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), |
| 1530 | IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), |
| 1531 | IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), |
| 1532 | IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), |
| 1533 | IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), |
| 1534 | IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), |
| 1535 | IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), |
| 1536 | IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), |
| 1537 | IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), |
| 1538 | }; |
| 1539 | |
| 1540 | /* |
| 1541 | * Offsets into EEPROM. |
| 1542 | */ |
| 1543 | #define IWN_EEPROM_MAC 0x015 |
| 1544 | #define IWN_EEPROM_SKU_CAP 0x045 |
| 1545 | #define IWN_EEPROM_RFCFG 0x048 |
| 1546 | #define IWN4965_EEPROM_DOMAIN 0x060 |
| 1547 | #define IWN4965_EEPROM_BAND1 0x063 |
| 1548 | #define IWN5000_EEPROM_REG 0x066 |
| 1549 | #define IWN5000_EEPROM_CAL 0x067 |
| 1550 | #define IWN4965_EEPROM_BAND2 0x072 |
| 1551 | #define IWN4965_EEPROM_BAND3 0x080 |
| 1552 | #define IWN4965_EEPROM_BAND4 0x08d |
| 1553 | #define IWN4965_EEPROM_BAND5 0x099 |
| 1554 | #define IWN4965_EEPROM_BAND6 0x0a0 |
| 1555 | #define IWN4965_EEPROM_BAND7 0x0a8 |
| 1556 | #define IWN4965_EEPROM_MAXPOW 0x0e8 |
| 1557 | #define IWN4965_EEPROM_VOLTAGE 0x0e9 |
| 1558 | #define IWN4965_EEPROM_BANDS 0x0ea |
| 1559 | /* Indirect offsets. */ |
| 1560 | #define IWN5000_EEPROM_DOMAIN 0x001 |
| 1561 | #define IWN5000_EEPROM_BAND1 0x004 |
| 1562 | #define IWN5000_EEPROM_BAND2 0x013 |
| 1563 | #define IWN5000_EEPROM_BAND3 0x021 |
| 1564 | #define IWN5000_EEPROM_BAND4 0x02e |
| 1565 | #define IWN5000_EEPROM_BAND5 0x03a |
| 1566 | #define IWN5000_EEPROM_BAND6 0x041 |
| 1567 | #define IWN5000_EEPROM_BAND7 0x049 |
| 1568 | #define IWN6000_EEPROM_ENHINFO 0x054 |
| 1569 | #define IWN5000_EEPROM_CRYSTAL 0x128 |
| 1570 | #define IWN5000_EEPROM_TEMP 0x12a |
| 1571 | #define IWN5000_EEPROM_VOLT 0x12b |
| 1572 | #define IWN2000_EEPROM_RAWTEMP 0x12b |
| 1573 | |
| 1574 | /* Possible flags for IWN_EEPROM_SKU_CAP. */ |
| 1575 | #define IWN_EEPROM_SKU_CAP_11N (1 << 6) |
| 1576 | #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) |
| 1577 | #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) |
| 1578 | |
| 1579 | /* Possible flags for IWN_EEPROM_RFCFG. */ |
| 1580 | #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) |
| 1581 | #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) |
| 1582 | #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) |
| 1583 | #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) |
| 1584 | #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) |
| 1585 | |
| 1586 | struct iwn_eeprom_chan { |
| 1587 | uint8_t flags; |
| 1588 | #define IWN_EEPROM_CHAN_VALID (1 << 0) |
| 1589 | #define IWN_EEPROM_CHAN_IBSS (1 << 1) |
| 1590 | #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) |
| 1591 | #define IWN_EEPROM_CHAN_RADAR (1 << 4) |
| 1592 | |
| 1593 | int8_t maxpwr; |
| 1594 | } __packed; |
| 1595 | |
| 1596 | struct iwn_eeprom_enhinfo { |
| 1597 | uint16_t chan; |
| 1598 | int8_t chain[3]; /* max power in half-dBm */ |
| 1599 | uint8_t reserved; |
| 1600 | int8_t mimo2; /* max power in half-dBm */ |
| 1601 | int8_t mimo3; /* max power in half-dBm */ |
| 1602 | } __packed; |
| 1603 | |
| 1604 | struct iwn5000_eeprom_calib_hdr { |
| 1605 | uint8_t version; |
| 1606 | uint8_t pa_type; |
| 1607 | uint16_t volt; |
| 1608 | } __packed; |
| 1609 | |
| 1610 | #define IWN_NSAMPLES 3 |
| 1611 | struct iwn4965_eeprom_chan_samples { |
| 1612 | uint8_t num; |
| 1613 | struct { |
| 1614 | uint8_t temp; |
| 1615 | uint8_t gain; |
| 1616 | uint8_t power; |
| 1617 | int8_t pa_det; |
| 1618 | } samples[2][IWN_NSAMPLES]; |
| 1619 | } __packed; |
| 1620 | |
| 1621 | #define IWN_NBANDS 8 |
| 1622 | struct iwn4965_eeprom_band { |
| 1623 | uint8_t lo; /* low channel number */ |
| 1624 | uint8_t hi; /* high channel number */ |
| 1625 | struct iwn4965_eeprom_chan_samples chans[2]; |
| 1626 | } __packed; |
| 1627 | |
| 1628 | /* |
| 1629 | * Offsets of channels descriptions in EEPROM. |
| 1630 | */ |
| 1631 | static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { |
| 1632 | IWN4965_EEPROM_BAND1, |
| 1633 | IWN4965_EEPROM_BAND2, |
| 1634 | IWN4965_EEPROM_BAND3, |
| 1635 | IWN4965_EEPROM_BAND4, |
| 1636 | IWN4965_EEPROM_BAND5, |
| 1637 | IWN4965_EEPROM_BAND6, |
| 1638 | IWN4965_EEPROM_BAND7 |
| 1639 | }; |
| 1640 | |
| 1641 | static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { |
| 1642 | IWN5000_EEPROM_BAND1, |
| 1643 | IWN5000_EEPROM_BAND2, |
| 1644 | IWN5000_EEPROM_BAND3, |
| 1645 | IWN5000_EEPROM_BAND4, |
| 1646 | IWN5000_EEPROM_BAND5, |
| 1647 | IWN5000_EEPROM_BAND6, |
| 1648 | IWN5000_EEPROM_BAND7 |
| 1649 | }; |
| 1650 | |
| 1651 | #define IWN_CHAN_BANDS_COUNT 7 |
| 1652 | #define IWN_MAX_CHAN_PER_BAND 14 |
| 1653 | static const struct iwn_chan_band { |
| 1654 | uint8_t nchan; |
| 1655 | uint8_t chan[IWN_MAX_CHAN_PER_BAND]; |
| 1656 | } iwn_bands[] = { |
| 1657 | /* 20MHz channels, 2GHz band. */ |
| 1658 | { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, |
| 1659 | /* 20MHz channels, 5GHz band. */ |
| 1660 | { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, |
| 1661 | { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, |
| 1662 | { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, |
| 1663 | { 6, { 145, 149, 153, 157, 161, 165 } }, |
| 1664 | /* 40MHz channels (primary channels), 2GHz band. */ |
| 1665 | { 7, { 1, 2, 3, 4, 5, 6, 7 } }, |
| 1666 | /* 40MHz channels (primary channels), 5GHz band. */ |
| 1667 | { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } |
| 1668 | }; |
| 1669 | |
| 1670 | #define IWN1000_OTP_NBLOCKS 3 |
| 1671 | #define IWN6000_OTP_NBLOCKS 4 |
| 1672 | #define IWN6050_OTP_NBLOCKS 7 |
| 1673 | |
| 1674 | /* HW rate indices. */ |
| 1675 | #define IWN_RIDX_CCK1 0 |
| 1676 | #define IWN_RIDX_OFDM6 4 |
| 1677 | |
| 1678 | static const struct iwn_rate { |
| 1679 | uint8_t rate; |
| 1680 | uint8_t plcp; |
| 1681 | uint8_t flags; |
| 1682 | } iwn_rates[IWN_RIDX_MAX + 1] = { |
| 1683 | { 2, 10, IWN_RFLAG_CCK }, |
| 1684 | { 4, 20, IWN_RFLAG_CCK }, |
| 1685 | { 11, 55, IWN_RFLAG_CCK }, |
| 1686 | { 22, 110, IWN_RFLAG_CCK }, |
| 1687 | { 12, 0xd, 0 }, |
| 1688 | { 18, 0xf, 0 }, |
| 1689 | { 24, 0x5, 0 }, |
| 1690 | { 36, 0x7, 0 }, |
| 1691 | { 48, 0x9, 0 }, |
| 1692 | { 72, 0xb, 0 }, |
| 1693 | { 96, 0x1, 0 }, |
| 1694 | { 108, 0x3, 0 }, |
| 1695 | { 120, 0x3, 0 } |
| 1696 | }; |
| 1697 | |
| 1698 | #define IWN4965_MAX_PWR_INDEX 107 |
| 1699 | |
| 1700 | /* |
| 1701 | * RF Tx gain values from highest to lowest power (values obtained from |
| 1702 | * the reference driver.) |
| 1703 | */ |
| 1704 | static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { |
| 1705 | 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, |
| 1706 | 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, |
| 1707 | 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, |
| 1708 | 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, |
| 1709 | 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, |
| 1710 | 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, |
| 1711 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 1712 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 1713 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 1714 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 1715 | }; |
| 1716 | |
| 1717 | static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { |
| 1718 | 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, |
| 1719 | 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, |
| 1720 | 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, |
| 1721 | 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, |
| 1722 | 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, |
| 1723 | 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, |
| 1724 | 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, |
| 1725 | 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, |
| 1726 | 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, |
| 1727 | 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 1728 | }; |
| 1729 | |
| 1730 | /* |
| 1731 | * DSP pre-DAC gain values from highest to lowest power (values obtained |
| 1732 | * from the reference driver.) |
| 1733 | */ |
| 1734 | static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { |
| 1735 | 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, |
| 1736 | 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, |
| 1737 | 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, |
| 1738 | 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, |
| 1739 | 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, |
| 1740 | 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, |
| 1741 | 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, |
| 1742 | 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, |
| 1743 | 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, |
| 1744 | 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b |
| 1745 | }; |
| 1746 | |
| 1747 | static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { |
| 1748 | 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, |
| 1749 | 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, |
| 1750 | 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, |
| 1751 | 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, |
| 1752 | 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, |
| 1753 | 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, |
| 1754 | 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, |
| 1755 | 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, |
| 1756 | 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, |
| 1757 | 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e |
| 1758 | }; |
| 1759 | |
| 1760 | /* |
| 1761 | * Power saving settings (values obtained from the reference driver.) |
| 1762 | */ |
| 1763 | #define IWN_NDTIMRANGES 3 |
| 1764 | #define IWN_NPOWERLEVELS 6 |
| 1765 | static const struct iwn_pmgt { |
| 1766 | uint32_t rxtimeout; |
| 1767 | uint32_t txtimeout; |
| 1768 | uint32_t intval[5]; |
| 1769 | int skip_dtim; |
| 1770 | } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { |
| 1771 | /* DTIM <= 2 */ |
| 1772 | { |
| 1773 | { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ |
| 1774 | { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ |
| 1775 | { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ |
| 1776 | { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ |
| 1777 | { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ |
| 1778 | { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ |
| 1779 | }, |
| 1780 | /* 3 <= DTIM <= 10 */ |
| 1781 | { |
| 1782 | { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ |
| 1783 | { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ |
| 1784 | { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ |
| 1785 | { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ |
| 1786 | { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ |
| 1787 | { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ |
| 1788 | }, |
| 1789 | /* DTIM >= 11 */ |
| 1790 | { |
| 1791 | { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ |
| 1792 | { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ |
| 1793 | { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ |
| 1794 | { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ |
| 1795 | { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ |
| 1796 | { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ |
| 1797 | } |
| 1798 | }; |
| 1799 | |
| 1800 | struct iwn_sensitivity_limits { |
| 1801 | uint32_t min_ofdm_x1; |
| 1802 | uint32_t max_ofdm_x1; |
| 1803 | uint32_t min_ofdm_mrc_x1; |
| 1804 | uint32_t max_ofdm_mrc_x1; |
| 1805 | uint32_t min_ofdm_x4; |
| 1806 | uint32_t max_ofdm_x4; |
| 1807 | uint32_t min_ofdm_mrc_x4; |
| 1808 | uint32_t max_ofdm_mrc_x4; |
| 1809 | uint32_t min_cck_x4; |
| 1810 | uint32_t max_cck_x4; |
| 1811 | uint32_t min_cck_mrc_x4; |
| 1812 | uint32_t max_cck_mrc_x4; |
| 1813 | uint32_t min_energy_cck; |
| 1814 | uint32_t energy_cck; |
| 1815 | uint32_t energy_ofdm; |
| 1816 | }; |
| 1817 | |
| 1818 | /* |
| 1819 | * RX sensitivity limits (values obtained from the reference driver.) |
| 1820 | */ |
| 1821 | static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { |
| 1822 | 105, 140, |
| 1823 | 220, 270, |
| 1824 | 85, 120, |
| 1825 | 170, 210, |
| 1826 | 125, 200, |
| 1827 | 200, 400, |
| 1828 | 97, |
| 1829 | 100, |
| 1830 | 100 |
| 1831 | }; |
| 1832 | |
| 1833 | static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { |
| 1834 | 120, 120, /* min = max for performance bug in DSP. */ |
| 1835 | 240, 240, /* min = max for performance bug in DSP. */ |
| 1836 | 90, 120, |
| 1837 | 170, 210, |
| 1838 | 125, 200, |
| 1839 | 170, 400, |
| 1840 | 95, |
| 1841 | 95, |
| 1842 | 95 |
| 1843 | }; |
| 1844 | |
| 1845 | static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { |
| 1846 | 105, 105, /* min = max for performance bug in DSP. */ |
| 1847 | 220, 220, /* min = max for performance bug in DSP. */ |
| 1848 | 90, 120, |
| 1849 | 170, 210, |
| 1850 | 125, 200, |
| 1851 | 170, 400, |
| 1852 | 95, |
| 1853 | 95, |
| 1854 | 95 |
| 1855 | }; |
| 1856 | |
| 1857 | static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { |
| 1858 | 120, 155, |
| 1859 | 240, 290, |
| 1860 | 90, 120, |
| 1861 | 170, 210, |
| 1862 | 125, 200, |
| 1863 | 170, 400, |
| 1864 | 95, |
| 1865 | 95, |
| 1866 | 95 |
| 1867 | }; |
| 1868 | |
| 1869 | static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { |
| 1870 | 105, 110, |
| 1871 | 192, 232, |
| 1872 | 80, 145, |
| 1873 | 128, 232, |
| 1874 | 125, 175, |
| 1875 | 160, 310, |
| 1876 | 97, |
| 1877 | 97, |
| 1878 | 100 |
| 1879 | }; |
| 1880 | |
| 1881 | static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { |
| 1882 | 105, 110, |
| 1883 | 192, 232, |
| 1884 | 80, 145, |
| 1885 | 128, 232, |
| 1886 | 125, 175, |
| 1887 | 160, 310, |
| 1888 | 97, |
| 1889 | 97, |
| 1890 | 100 |
| 1891 | }; |
| 1892 | |
| 1893 | /* Map TID to TX scheduler's FIFO. */ |
| 1894 | static const uint8_t iwn_tid2fifo[] = { |
| 1895 | 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 |
| 1896 | }; |
| 1897 | |
| 1898 | /* WiFi/WiMAX coexist event priority table for 6050. */ |
| 1899 | static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { |
| 1900 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1901 | { 0x04, 0x03, 0x00, 0x03 }, |
| 1902 | { 0x04, 0x03, 0x00, 0x03 }, |
| 1903 | { 0x04, 0x03, 0x00, 0x03 }, |
| 1904 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1905 | { 0x04, 0x03, 0x00, 0x07 }, |
| 1906 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1907 | { 0x04, 0x03, 0x00, 0x03 }, |
| 1908 | { 0x04, 0x03, 0x00, 0x03 }, |
| 1909 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1910 | { 0x06, 0x03, 0x00, 0x07 }, |
| 1911 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1912 | { 0x06, 0x06, 0x00, 0x03 }, |
| 1913 | { 0x04, 0x03, 0x00, 0x07 }, |
| 1914 | { 0x04, 0x03, 0x00, 0x00 }, |
| 1915 | { 0x04, 0x03, 0x00, 0x00 } |
| 1916 | }; |
| 1917 | |
| 1918 | /* Firmware errors. */ |
| 1919 | static const char * const iwn_fw_errmsg[] = { |
| 1920 | "OK" , |
| 1921 | "FAIL" , |
| 1922 | "BAD_PARAM" , |
| 1923 | "BAD_CHECKSUM" , |
| 1924 | "NMI_INTERRUPT_WDG" , |
| 1925 | "SYSASSERT" , |
| 1926 | "FATAL_ERROR" , |
| 1927 | "BAD_COMMAND" , |
| 1928 | "HW_ERROR_TUNE_LOCK" , |
| 1929 | "HW_ERROR_TEMPERATURE" , |
| 1930 | "ILLEGAL_CHAN_FREQ" , |
| 1931 | "VCC_NOT_STABLE" , |
| 1932 | "FH_ERROR" , |
| 1933 | "NMI_INTERRUPT_HOST" , |
| 1934 | "NMI_INTERRUPT_ACTION_PT" , |
| 1935 | "NMI_INTERRUPT_UNKNOWN" , |
| 1936 | "UCODE_VERSION_MISMATCH" , |
| 1937 | "HW_ERROR_ABS_LOCK" , |
| 1938 | "HW_ERROR_CAL_LOCK_FAIL" , |
| 1939 | "NMI_INTERRUPT_INST_ACTION_PT" , |
| 1940 | "NMI_INTERRUPT_DATA_ACTION_PT" , |
| 1941 | "NMI_TRM_HW_ER" , |
| 1942 | "NMI_INTERRUPT_TRM" , |
| 1943 | "NMI_INTERRUPT_BREAKPOINT" |
| 1944 | "DEBUG_0" , |
| 1945 | "DEBUG_1" , |
| 1946 | "DEBUG_2" , |
| 1947 | "DEBUG_3" , |
| 1948 | "ADVANCED_SYSASSERT" |
| 1949 | }; |
| 1950 | |
| 1951 | /* Find least significant bit that is set. */ |
| 1952 | #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) |
| 1953 | |
| 1954 | #define IWN_READ(sc, reg) \ |
| 1955 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
| 1956 | |
| 1957 | #define IWN_WRITE(sc, reg, val) \ |
| 1958 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 1959 | |
| 1960 | #define IWN_WRITE_1(sc, reg, val) \ |
| 1961 | bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 1962 | |
| 1963 | #define IWN_SETBITS(sc, reg, mask) \ |
| 1964 | IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) |
| 1965 | |
| 1966 | #define IWN_CLRBITS(sc, reg, mask) \ |
| 1967 | IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) |
| 1968 | |
| 1969 | #define IWN_BARRIER_WRITE(sc) \ |
| 1970 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ |
| 1971 | BUS_SPACE_BARRIER_WRITE) |
| 1972 | |
| 1973 | #define IWN_BARRIER_READ_WRITE(sc) \ |
| 1974 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ |
| 1975 | BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) |
| 1976 | |
| 1977 | |