| 1 | /* $NetBSD: intr.h,v 1.49 2016/07/07 06:55:39 msaitoh Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Charles M. Hannum, and by Jason R. Thorpe. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #ifndef _X86_INTR_H_ |
| 33 | #define _X86_INTR_H_ |
| 34 | |
| 35 | #define __HAVE_FAST_SOFTINTS |
| 36 | #define __HAVE_PREEMPTION |
| 37 | |
| 38 | #ifdef _KERNEL |
| 39 | #include <sys/types.h> |
| 40 | #else |
| 41 | #include <stdbool.h> |
| 42 | #endif |
| 43 | |
| 44 | #include <sys/evcnt.h> |
| 45 | #include <sys/queue.h> |
| 46 | #include <machine/intrdefs.h> |
| 47 | |
| 48 | #ifndef _LOCORE |
| 49 | #include <machine/pic.h> |
| 50 | |
| 51 | /* |
| 52 | * Struct describing an interrupt source for a CPU. struct cpu_info |
| 53 | * has an array of MAX_INTR_SOURCES of these. The index in the array |
| 54 | * is equal to the stub number of the stubcode as present in vector.s |
| 55 | * |
| 56 | * The primary CPU's array of interrupt sources has its first 16 |
| 57 | * entries reserved for legacy ISA irq handlers. This means that |
| 58 | * they have a 1:1 mapping for arrayindex:irq_num. This is not |
| 59 | * true for interrupts that come in through IO APICs, to find |
| 60 | * their source, go through ci->ci_isources[index].is_pic |
| 61 | * |
| 62 | * It's possible to always maintain a 1:1 mapping, but that means |
| 63 | * limiting the total number of interrupt sources to MAX_INTR_SOURCES |
| 64 | * (32), instead of 32 per CPU. It also would mean that having multiple |
| 65 | * IO APICs which deliver interrupts from an equal pin number would |
| 66 | * overlap if they were to be sent to the same CPU. |
| 67 | */ |
| 68 | |
| 69 | struct intrstub { |
| 70 | void *ist_entry; |
| 71 | void *ist_recurse; |
| 72 | void *ist_resume; |
| 73 | }; |
| 74 | |
| 75 | struct percpu_evcnt { |
| 76 | cpuid_t cpuid; |
| 77 | uint64_t count; |
| 78 | }; |
| 79 | |
| 80 | struct intrsource { |
| 81 | int is_maxlevel; /* max. IPL for this source */ |
| 82 | int is_pin; /* IRQ for legacy; pin for IO APIC, |
| 83 | -1 for MSI */ |
| 84 | struct intrhand *is_handlers; /* handler chain */ |
| 85 | struct pic *is_pic; /* originating PIC */ |
| 86 | void *is_recurse; /* entry for spllower */ |
| 87 | void *is_resume; /* entry for doreti */ |
| 88 | lwp_t *is_lwp; /* for soft interrupts */ |
| 89 | struct evcnt is_evcnt; /* interrupt counter per cpu */ |
| 90 | int is_flags; /* see below */ |
| 91 | int is_type; /* level, edge */ |
| 92 | int is_idtvec; |
| 93 | int is_minlevel; |
| 94 | char is_evname[32]; /* event counter name */ |
| 95 | char is_intrid[INTRIDBUF]; /* intrid created by create_intrid() */ |
| 96 | char is_xname[INTRDEVNAMEBUF]; /* device names */ |
| 97 | cpuid_t is_active_cpu; /* active cpuid */ |
| 98 | struct percpu_evcnt *is_saved_evcnt; /* interrupt count of deactivated cpus */ |
| 99 | SIMPLEQ_ENTRY(intrsource) is_list; /* link of intrsources */ |
| 100 | }; |
| 101 | |
| 102 | #define IS_LEGACY 0x0001 /* legacy ISA irq source */ |
| 103 | #define IS_IPI 0x0002 |
| 104 | #define IS_LOG 0x0004 |
| 105 | |
| 106 | /* |
| 107 | * Interrupt handler chains. *_intr_establish() insert a handler into |
| 108 | * the list. The handler is called with its (single) argument. |
| 109 | */ |
| 110 | |
| 111 | struct intrhand { |
| 112 | int (*ih_fun)(void *); |
| 113 | void *ih_arg; |
| 114 | int ih_level; |
| 115 | int (*ih_realfun)(void *); |
| 116 | void *ih_realarg; |
| 117 | struct intrhand *ih_next; |
| 118 | struct intrhand **ih_prevp; |
| 119 | int ih_pin; |
| 120 | int ih_slot; |
| 121 | struct cpu_info *ih_cpu; |
| 122 | }; |
| 123 | |
| 124 | #define IMASK(ci,level) (ci)->ci_imask[(level)] |
| 125 | #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)] |
| 126 | |
| 127 | #ifdef _KERNEL |
| 128 | |
| 129 | void Xspllower(int); |
| 130 | void spllower(int); |
| 131 | int splraise(int); |
| 132 | void softintr(int); |
| 133 | |
| 134 | /* |
| 135 | * Convert spl level to local APIC level |
| 136 | */ |
| 137 | |
| 138 | #define APIC_LEVEL(l) ((l) << 4) |
| 139 | |
| 140 | /* |
| 141 | * Miscellaneous |
| 142 | */ |
| 143 | |
| 144 | #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x)) |
| 145 | #define spl0() spllower(IPL_NONE) |
| 146 | #define splx(x) spllower(x) |
| 147 | |
| 148 | typedef uint8_t ipl_t; |
| 149 | typedef struct { |
| 150 | ipl_t _ipl; |
| 151 | } ipl_cookie_t; |
| 152 | |
| 153 | static inline ipl_cookie_t |
| 154 | makeiplcookie(ipl_t ipl) |
| 155 | { |
| 156 | |
| 157 | return (ipl_cookie_t){._ipl = ipl}; |
| 158 | } |
| 159 | |
| 160 | static inline int |
| 161 | splraiseipl(ipl_cookie_t icookie) |
| 162 | { |
| 163 | |
| 164 | return splraise(icookie._ipl); |
| 165 | } |
| 166 | |
| 167 | #include <sys/spl.h> |
| 168 | |
| 169 | /* |
| 170 | * Stub declarations. |
| 171 | */ |
| 172 | |
| 173 | void Xsoftintr(void); |
| 174 | void Xpreemptrecurse(void); |
| 175 | void Xpreemptresume(void); |
| 176 | |
| 177 | extern struct intrstub i8259_stubs[]; |
| 178 | extern struct intrstub ioapic_edge_stubs[]; |
| 179 | extern struct intrstub ioapic_level_stubs[]; |
| 180 | |
| 181 | struct cpu_info; |
| 182 | |
| 183 | struct pcibus_attach_args; |
| 184 | |
| 185 | typedef uint64_t intr_handle_t; |
| 186 | |
| 187 | void intr_default_setup(void); |
| 188 | void x86_nmi(void); |
| 189 | void *intr_establish_xname(int, struct pic *, int, int, int, int (*)(void *), |
| 190 | void *, bool, const char *); |
| 191 | void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool); |
| 192 | void intr_disestablish(struct intrhand *); |
| 193 | void intr_add_pcibus(struct pcibus_attach_args *); |
| 194 | const char *intr_string(intr_handle_t, char *, size_t); |
| 195 | void cpu_intr_init(struct cpu_info *); |
| 196 | int intr_find_mpmapping(int, int, intr_handle_t *); |
| 197 | struct pic *intr_findpic(int); |
| 198 | void intr_printconfig(void); |
| 199 | |
| 200 | struct intrsource *intr_allocate_io_intrsource(const char *); |
| 201 | void intr_free_io_intrsource(const char *); |
| 202 | |
| 203 | int x86_send_ipi(struct cpu_info *, int); |
| 204 | void x86_broadcast_ipi(int); |
| 205 | void x86_ipi_handler(void); |
| 206 | |
| 207 | extern void (* const ipifunc[X86_NIPI])(struct cpu_info *); |
| 208 | |
| 209 | #endif /* _KERNEL */ |
| 210 | |
| 211 | #endif /* !_LOCORE */ |
| 212 | |
| 213 | #endif /* !_X86_INTR_H_ */ |
| 214 | |