| 1 | /* $NetBSD: trm.c,v 1.37 2016/07/07 06:55:41 msaitoh Exp $ */ |
| 2 | /*- |
| 3 | * Copyright (c) 2002 Izumi Tsutsui. All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 15 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 16 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 17 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 20 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 21 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 24 | */ |
| 25 | |
| 26 | /* |
| 27 | * Device Driver for Tekram DC395U/UW/F, DC315/U |
| 28 | * PCI SCSI Bus Master Host Adapter |
| 29 | * (SCSI chip set used Tekram ASIC TRM-S1040) |
| 30 | * |
| 31 | * Copyright (c) 2001 Rui-Xiang Guo |
| 32 | * All rights reserved. |
| 33 | * |
| 34 | * Redistribution and use in source and binary forms, with or without |
| 35 | * modification, are permitted provided that the following conditions |
| 36 | * are met: |
| 37 | * 1. Redistributions of source code must retain the above copyright |
| 38 | * notice, this list of conditions and the following disclaimer. |
| 39 | * 2. Redistributions in binary form must reproduce the above copyright |
| 40 | * notice, this list of conditions and the following disclaimer in the |
| 41 | * documentation and/or other materials provided with the distribution. |
| 42 | * 3. The name of the author may not be used to endorse or promote products |
| 43 | * derived from this software without specific prior written permission. |
| 44 | * |
| 45 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 46 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 47 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 48 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 49 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 50 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 51 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 52 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 53 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 54 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 55 | */ |
| 56 | /* |
| 57 | * Ported from |
| 58 | * dc395x_trm.c |
| 59 | * |
| 60 | * Written for NetBSD 1.4.x by |
| 61 | * Erich Chen (erich@tekram.com.tw) |
| 62 | * |
| 63 | * Provided by |
| 64 | * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. |
| 65 | */ |
| 66 | |
| 67 | #include <sys/cdefs.h> |
| 68 | __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.37 2016/07/07 06:55:41 msaitoh Exp $" ); |
| 69 | |
| 70 | /* #define TRM_DEBUG */ |
| 71 | #ifdef TRM_DEBUG |
| 72 | int trm_debug = 1; |
| 73 | #define DPRINTF(arg) if (trm_debug > 0) printf arg; |
| 74 | #else |
| 75 | #define DPRINTF(arg) |
| 76 | #endif |
| 77 | |
| 78 | #include <sys/param.h> |
| 79 | #include <sys/systm.h> |
| 80 | #include <sys/malloc.h> |
| 81 | #include <sys/buf.h> |
| 82 | #include <sys/kernel.h> |
| 83 | #include <sys/device.h> |
| 84 | #include <sys/queue.h> |
| 85 | |
| 86 | #include <sys/bus.h> |
| 87 | #include <sys/intr.h> |
| 88 | |
| 89 | #include <dev/scsipi/scsi_spc.h> |
| 90 | #include <dev/scsipi/scsi_all.h> |
| 91 | #include <dev/scsipi/scsi_message.h> |
| 92 | #include <dev/scsipi/scsipi_all.h> |
| 93 | #include <dev/scsipi/scsiconf.h> |
| 94 | |
| 95 | #include <dev/pci/pcidevs.h> |
| 96 | #include <dev/pci/pcireg.h> |
| 97 | #include <dev/pci/pcivar.h> |
| 98 | #include <dev/pci/trmreg.h> |
| 99 | |
| 100 | /* |
| 101 | * feature of chip set MAX value |
| 102 | */ |
| 103 | #define TRM_MAX_TARGETS 16 |
| 104 | #define TRM_MAX_LUNS 8 |
| 105 | #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) |
| 106 | #define TRM_MAX_SRB 32 /* XXX */ |
| 107 | #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ |
| 108 | #define TRM_MAX_OFFSET 15 |
| 109 | #define TRM_MAX_PERIOD 125 |
| 110 | |
| 111 | /* |
| 112 | * Segment Entry |
| 113 | */ |
| 114 | struct trm_sg_entry { |
| 115 | uint32_t address; |
| 116 | uint32_t length; |
| 117 | }; |
| 118 | |
| 119 | #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) |
| 120 | |
| 121 | /* |
| 122 | ********************************************************************** |
| 123 | * The SEEPROM structure for TRM_S1040 |
| 124 | ********************************************************************** |
| 125 | */ |
| 126 | struct nvram_target { |
| 127 | uint8_t config0; /* Target configuration byte 0 */ |
| 128 | #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ |
| 129 | #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ |
| 130 | #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ |
| 131 | #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ |
| 132 | #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ |
| 133 | #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ |
| 134 | uint8_t period; /* Target period */ |
| 135 | uint8_t config2; /* Target configuration byte 2 */ |
| 136 | uint8_t config3; /* Target configuration byte 3 */ |
| 137 | }; |
| 138 | |
| 139 | struct trm_nvram { |
| 140 | uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ |
| 141 | uint8_t subsys_id[2]; /* 2,3 Sub System ID */ |
| 142 | uint8_t subclass; /* 4 Sub Class */ |
| 143 | uint8_t vendor_id[2]; /* 5,6 Vendor ID */ |
| 144 | uint8_t device_id[2]; /* 7,8 Device ID */ |
| 145 | uint8_t reserved0; /* 9 Reserved */ |
| 146 | struct nvram_target target[TRM_MAX_TARGETS]; |
| 147 | /* 10,11,12,13 |
| 148 | * 14,15,16,17 |
| 149 | * .... |
| 150 | * 70,71,72,73 */ |
| 151 | uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ |
| 152 | uint8_t channel_cfg; /* 75 Channel configuration */ |
| 153 | #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ |
| 154 | #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ |
| 155 | #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ |
| 156 | #define NAC_GREATER_1G 0x02 /* > 1G support enable */ |
| 157 | #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ |
| 158 | uint8_t delay_time; /* 76 Power on delay time */ |
| 159 | uint8_t max_tag; /* 77 Maximum tags */ |
| 160 | uint8_t reserved1; /* 78 */ |
| 161 | uint8_t boot_target; /* 79 */ |
| 162 | uint8_t boot_lun; /* 80 */ |
| 163 | uint8_t reserved2; /* 81 */ |
| 164 | uint8_t reserved3[44]; /* 82,..125 */ |
| 165 | uint8_t checksum0; /* 126 */ |
| 166 | uint8_t checksum1; /* 127 */ |
| 167 | #define TRM_NVRAM_CKSUM 0x1234 |
| 168 | }; |
| 169 | |
| 170 | /* Nvram Initiater bits definition */ |
| 171 | #define MORE2_DRV 0x00000001 |
| 172 | #define GREATER_1G 0x00000002 |
| 173 | #define RST_SCSI_BUS 0x00000004 |
| 174 | #define ACTIVE_NEGATION 0x00000008 |
| 175 | #define NO_SEEK 0x00000010 |
| 176 | #define LUN_CHECK 0x00000020 |
| 177 | |
| 178 | #define trm_eeprom_wait() DELAY(30) |
| 179 | |
| 180 | /* |
| 181 | *----------------------------------------------------------------------- |
| 182 | * SCSI Request Block |
| 183 | *----------------------------------------------------------------------- |
| 184 | */ |
| 185 | struct trm_srb { |
| 186 | TAILQ_ENTRY(trm_srb) next; |
| 187 | |
| 188 | struct trm_sg_entry *sgentry; |
| 189 | struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ |
| 190 | bus_dmamap_t dmap; |
| 191 | bus_size_t sgoffset; /* Xfer buf offset */ |
| 192 | |
| 193 | uint32_t buflen; /* Total xfer length */ |
| 194 | uint32_t sgaddr; /* SGList physical starting address */ |
| 195 | |
| 196 | int sgcnt; |
| 197 | int sgindex; |
| 198 | |
| 199 | int hastat; /* Host Adapter Status */ |
| 200 | #define H_STATUS_GOOD 0x00 |
| 201 | #define H_SEL_TIMEOUT 0x11 |
| 202 | #define H_OVER_UNDER_RUN 0x12 |
| 203 | #define H_UNEXP_BUS_FREE 0x13 |
| 204 | #define H_TARGET_PHASE_F 0x14 |
| 205 | #define H_INVALID_CCB_OP 0x16 |
| 206 | #define H_LINK_CCB_BAD 0x17 |
| 207 | #define H_BAD_TARGET_DIR 0x18 |
| 208 | #define H_DUPLICATE_CCB 0x19 |
| 209 | #define H_BAD_CCB_OR_SG 0x1A |
| 210 | #define H_ABORT 0xFF |
| 211 | int tastat; /* Target SCSI Status Byte */ |
| 212 | int flag; /* SRBFlag */ |
| 213 | #define AUTO_REQSENSE 0x0001 |
| 214 | #define PARITY_ERROR 0x0002 |
| 215 | #define SRB_TIMEOUT 0x0004 |
| 216 | |
| 217 | int cmdlen; /* SCSI command length */ |
| 218 | uint8_t cmd[12]; /* SCSI command */ |
| 219 | |
| 220 | uint8_t tag[2]; |
| 221 | }; |
| 222 | |
| 223 | /* |
| 224 | * some info about each target and lun on the SCSI bus |
| 225 | */ |
| 226 | struct trm_linfo { |
| 227 | int used; /* number of slots in use */ |
| 228 | int avail; /* where to start scanning */ |
| 229 | int busy; /* lun in use */ |
| 230 | struct trm_srb *untagged; |
| 231 | struct trm_srb *queued[TRM_MAX_TAG]; |
| 232 | }; |
| 233 | |
| 234 | struct trm_tinfo { |
| 235 | u_int flag; /* Sync mode ? (1 sync):(0 async) */ |
| 236 | #define SYNC_NEGO_ENABLE 0x0001 |
| 237 | #define SYNC_NEGO_DOING 0x0002 |
| 238 | #define SYNC_NEGO_DONE 0x0004 |
| 239 | #define WIDE_NEGO_ENABLE 0x0008 |
| 240 | #define WIDE_NEGO_DOING 0x0010 |
| 241 | #define WIDE_NEGO_DONE 0x0020 |
| 242 | #define USE_TAG_QUEUING 0x0040 |
| 243 | #define NO_RESELECT 0x0080 |
| 244 | struct trm_linfo *linfo[TRM_MAX_LUNS]; |
| 245 | |
| 246 | uint8_t config0; /* Target Config */ |
| 247 | uint8_t period; /* Max Period for nego. */ |
| 248 | uint8_t synctl; /* Sync control for reg. */ |
| 249 | uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ |
| 250 | }; |
| 251 | |
| 252 | /* |
| 253 | *----------------------------------------------------------------------- |
| 254 | * Adapter Control Block |
| 255 | *----------------------------------------------------------------------- |
| 256 | */ |
| 257 | struct trm_softc { |
| 258 | device_t sc_dev; |
| 259 | |
| 260 | bus_space_tag_t sc_iot; |
| 261 | bus_space_handle_t sc_ioh; |
| 262 | bus_dma_tag_t sc_dmat; |
| 263 | bus_dmamap_t sc_dmamap; /* Map the control structures */ |
| 264 | |
| 265 | struct trm_srb *sc_actsrb; |
| 266 | struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; |
| 267 | |
| 268 | TAILQ_HEAD(, trm_srb) sc_freesrb, |
| 269 | sc_readysrb; |
| 270 | struct trm_srb *sc_srb; /* SRB array */ |
| 271 | |
| 272 | struct trm_sg_entry *sc_sglist; |
| 273 | |
| 274 | int sc_maxid; |
| 275 | /* |
| 276 | * Link to the generic SCSI driver |
| 277 | */ |
| 278 | struct scsipi_channel sc_channel; |
| 279 | struct scsipi_adapter sc_adapter; |
| 280 | |
| 281 | int sc_id; /* Adapter SCSI Target ID */ |
| 282 | |
| 283 | int sc_state; /* SRB State */ |
| 284 | #define TRM_IDLE 0 |
| 285 | #define TRM_WAIT 1 |
| 286 | #define TRM_READY 2 |
| 287 | #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ |
| 288 | #define TRM_MSGIN 4 |
| 289 | #define TRM_EXTEND_MSGIN 5 |
| 290 | #define TRM_COMMAND 6 |
| 291 | #define TRM_START 7 /* arbitration+msg_out+command_out */ |
| 292 | #define TRM_DISCONNECTED 8 |
| 293 | #define TRM_DATA_XFER 9 |
| 294 | #define TRM_XFERPAD 10 |
| 295 | #define TRM_STATUS 11 |
| 296 | #define TRM_COMPLETED 12 |
| 297 | #define TRM_ABORT_SENT 13 |
| 298 | #define TRM_UNEXPECT_RESEL 14 |
| 299 | |
| 300 | int sc_phase; /* SCSI phase */ |
| 301 | int sc_config; |
| 302 | #define HCC_WIDE_CARD 0x01 |
| 303 | #define HCC_SCSI_RESET 0x02 |
| 304 | #define HCC_PARITY 0x04 |
| 305 | #define HCC_AUTOTERM 0x08 |
| 306 | #define HCC_LOW8TERM 0x10 |
| 307 | #define HCC_UP8TERM 0x20 |
| 308 | |
| 309 | int sc_flag; |
| 310 | #define RESET_DEV 0x01 |
| 311 | #define RESET_DETECT 0x02 |
| 312 | #define RESET_DONE 0x04 |
| 313 | #define WAIT_TAGMSG 0x08 /* XXX */ |
| 314 | |
| 315 | int sc_msgcnt; |
| 316 | |
| 317 | int resel_target; /* XXX */ |
| 318 | int resel_lun; /* XXX */ |
| 319 | |
| 320 | uint8_t *sc_msg; |
| 321 | uint8_t sc_msgbuf[6]; |
| 322 | }; |
| 323 | |
| 324 | /* |
| 325 | * SCSI Status codes not defined in scsi_all.h |
| 326 | */ |
| 327 | #define SCSI_COND_MET 0x04 /* Condition Met */ |
| 328 | #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ |
| 329 | #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ |
| 330 | #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ |
| 331 | #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ |
| 332 | |
| 333 | static int trm_match(device_t, cfdata_t, void *); |
| 334 | static void trm_attach(device_t, device_t, void *); |
| 335 | |
| 336 | static int trm_init(struct trm_softc *); |
| 337 | |
| 338 | static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, |
| 339 | void *); |
| 340 | static void trm_update_xfer_mode(struct trm_softc *, int); |
| 341 | static void trm_sched(struct trm_softc *); |
| 342 | static int trm_select(struct trm_softc *, struct trm_srb *); |
| 343 | static void trm_reset(struct trm_softc *); |
| 344 | static void trm_timeout(void *); |
| 345 | static int trm_intr(void *); |
| 346 | |
| 347 | static void trm_dataout_phase0(struct trm_softc *, int); |
| 348 | static void trm_datain_phase0(struct trm_softc *, int); |
| 349 | static void trm_status_phase0(struct trm_softc *); |
| 350 | static void trm_msgin_phase0(struct trm_softc *); |
| 351 | static void trm_command_phase1(struct trm_softc *); |
| 352 | static void trm_status_phase1(struct trm_softc *); |
| 353 | static void trm_msgout_phase1(struct trm_softc *); |
| 354 | static void trm_msgin_phase1(struct trm_softc *); |
| 355 | |
| 356 | static void trm_dataio_xfer(struct trm_softc *, int); |
| 357 | static void trm_disconnect(struct trm_softc *); |
| 358 | static void trm_reselect(struct trm_softc *); |
| 359 | static void trm_done(struct trm_softc *, struct trm_srb *); |
| 360 | static int trm_request_sense(struct trm_softc *, struct trm_srb *); |
| 361 | static void trm_dequeue(struct trm_softc *, struct trm_srb *); |
| 362 | |
| 363 | static void trm_scsi_reset_detect(struct trm_softc *); |
| 364 | static void trm_reset_scsi_bus(struct trm_softc *); |
| 365 | |
| 366 | static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); |
| 367 | static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); |
| 368 | static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); |
| 369 | static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); |
| 370 | static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); |
| 371 | static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); |
| 372 | |
| 373 | CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc), |
| 374 | trm_match, trm_attach, NULL, NULL); |
| 375 | |
| 376 | /* real period: */ |
| 377 | static const uint8_t trm_clock_period[] = { |
| 378 | 12, /* 48 ns 20.0 MB/sec */ |
| 379 | 18, /* 72 ns 13.3 MB/sec */ |
| 380 | 25, /* 100 ns 10.0 MB/sec */ |
| 381 | 31, /* 124 ns 8.0 MB/sec */ |
| 382 | 37, /* 148 ns 6.6 MB/sec */ |
| 383 | 43, /* 172 ns 5.7 MB/sec */ |
| 384 | 50, /* 200 ns 5.0 MB/sec */ |
| 385 | 62 /* 248 ns 4.0 MB/sec */ |
| 386 | }; |
| 387 | #define NPERIOD __arraycount(trm_clock_period) |
| 388 | |
| 389 | static int |
| 390 | trm_match(device_t parent, cfdata_t cf, void *aux) |
| 391 | { |
| 392 | struct pci_attach_args *pa = aux; |
| 393 | |
| 394 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) |
| 395 | switch (PCI_PRODUCT(pa->pa_id)) { |
| 396 | case PCI_PRODUCT_TEKRAM2_DC315: |
| 397 | return 1; |
| 398 | } |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | /* |
| 403 | * attach and init a host adapter |
| 404 | */ |
| 405 | static void |
| 406 | trm_attach(device_t parent, device_t self, void *aux) |
| 407 | { |
| 408 | struct trm_softc *sc = device_private(self); |
| 409 | struct pci_attach_args *const pa = aux; |
| 410 | bus_space_tag_t iot; |
| 411 | bus_space_handle_t ioh; |
| 412 | pci_intr_handle_t ih; |
| 413 | pcireg_t command; |
| 414 | const char *intrstr; |
| 415 | int fl = 0; |
| 416 | char intrbuf[PCI_INTRSTR_LEN]; |
| 417 | |
| 418 | sc->sc_dev = self; |
| 419 | |
| 420 | /* |
| 421 | * Some cards do not allow memory mapped accesses |
| 422 | * pa_pc: chipset tag |
| 423 | * pa_tag: pci tag |
| 424 | */ |
| 425 | command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
| 426 | if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != |
| 427 | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { |
| 428 | command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; |
| 429 | pci_conf_write(pa->pa_pc, pa->pa_tag, |
| 430 | PCI_COMMAND_STATUS_REG, command); |
| 431 | } |
| 432 | /* |
| 433 | * mask for get correct base address of pci IO port |
| 434 | */ |
| 435 | if (command & PCI_COMMAND_MEM_ENABLE) { |
| 436 | fl = pci_mapreg_map(pa, TRM_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, &iot, |
| 437 | &ioh, NULL, NULL); |
| 438 | } |
| 439 | if (fl != 0) { |
| 440 | aprint_verbose_dev(self, "couldn't map MMIO registers, tryion PIO\n" ); |
| 441 | if ((fl = pci_mapreg_map(pa, TRM_BAR_PIO, PCI_MAPREG_TYPE_IO, |
| 442 | 0, &iot, &ioh, NULL, NULL)) != 0) { |
| 443 | aprint_error(": unable to map registers (%d)\n" , fl); |
| 444 | return; |
| 445 | } |
| 446 | } |
| 447 | /* |
| 448 | * test checksum of eeprom.. & initialize softc... |
| 449 | */ |
| 450 | sc->sc_iot = iot; |
| 451 | sc->sc_ioh = ioh; |
| 452 | sc->sc_dmat = pa->pa_dmat; |
| 453 | |
| 454 | if (trm_init(sc) != 0) { |
| 455 | /* |
| 456 | * Error during initialization! |
| 457 | */ |
| 458 | return; |
| 459 | } |
| 460 | /* |
| 461 | * Now try to attach all the sub-devices |
| 462 | */ |
| 463 | if ((sc->sc_config & HCC_WIDE_CARD) != 0) |
| 464 | aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 " |
| 465 | "Ultra Wide SCSI Adapter\n" ); |
| 466 | else |
| 467 | aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " |
| 468 | "Ultra SCSI Adapter\n" ); |
| 469 | |
| 470 | /* |
| 471 | * Now tell the generic SCSI layer about our bus. |
| 472 | * map and establish interrupt |
| 473 | */ |
| 474 | if (pci_intr_map(pa, &ih)) { |
| 475 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
| 476 | return; |
| 477 | } |
| 478 | intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); |
| 479 | |
| 480 | if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { |
| 481 | aprint_error_dev(self, "couldn't establish interrupt" ); |
| 482 | if (intrstr != NULL) |
| 483 | aprint_error(" at %s" , intrstr); |
| 484 | aprint_error("\n" ); |
| 485 | return; |
| 486 | } |
| 487 | if (intrstr != NULL) |
| 488 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
| 489 | |
| 490 | sc->sc_adapter.adapt_dev = self; |
| 491 | sc->sc_adapter.adapt_nchannels = 1; |
| 492 | sc->sc_adapter.adapt_openings = TRM_MAX_SRB; |
| 493 | sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; |
| 494 | sc->sc_adapter.adapt_request = trm_scsipi_request; |
| 495 | sc->sc_adapter.adapt_minphys = minphys; |
| 496 | |
| 497 | sc->sc_channel.chan_adapter = &sc->sc_adapter; |
| 498 | sc->sc_channel.chan_bustype = &scsi_bustype; |
| 499 | sc->sc_channel.chan_channel = 0; |
| 500 | sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; |
| 501 | sc->sc_channel.chan_nluns = 8; |
| 502 | sc->sc_channel.chan_id = sc->sc_id; |
| 503 | |
| 504 | config_found(self, &sc->sc_channel, scsiprint); |
| 505 | } |
| 506 | |
| 507 | /* |
| 508 | * initialize the internal structures for a given SCSI host |
| 509 | */ |
| 510 | static int |
| 511 | trm_init(struct trm_softc *sc) |
| 512 | { |
| 513 | bus_space_tag_t iot = sc->sc_iot; |
| 514 | bus_space_handle_t ioh = sc->sc_ioh; |
| 515 | bus_dma_segment_t seg; |
| 516 | struct trm_nvram eeprom; |
| 517 | struct trm_srb *srb; |
| 518 | struct trm_tinfo *ti; |
| 519 | struct nvram_target *tconf; |
| 520 | int error, rseg, all_sgsize; |
| 521 | int i, target; |
| 522 | uint8_t bval; |
| 523 | |
| 524 | DPRINTF(("\n" )); |
| 525 | |
| 526 | /* |
| 527 | * allocate the space for all SCSI control blocks (SRB) for DMA memory |
| 528 | */ |
| 529 | all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; |
| 530 | if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, |
| 531 | 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { |
| 532 | aprint_error(": unable to allocate SCSI REQUEST BLOCKS, " |
| 533 | "error = %d\n" , error); |
| 534 | return 1; |
| 535 | } |
| 536 | if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, |
| 537 | all_sgsize, (void **) &sc->sc_sglist, |
| 538 | BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { |
| 539 | aprint_error(": unable to map SCSI REQUEST BLOCKS, " |
| 540 | "error = %d\n" , error); |
| 541 | return 1; |
| 542 | } |
| 543 | if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, |
| 544 | all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { |
| 545 | aprint_error(": unable to create SRB DMA maps, " |
| 546 | "error = %d\n" , error); |
| 547 | return 1; |
| 548 | } |
| 549 | if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, |
| 550 | sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { |
| 551 | aprint_error(": unable to load SRB DMA maps, " |
| 552 | "error = %d\n" , error); |
| 553 | return 1; |
| 554 | } |
| 555 | DPRINTF(("all_sgsize=%x\n" , all_sgsize)); |
| 556 | memset(sc->sc_sglist, 0, all_sgsize); |
| 557 | |
| 558 | /* |
| 559 | * EEPROM CHECKSUM |
| 560 | */ |
| 561 | trm_check_eeprom(sc, &eeprom); |
| 562 | |
| 563 | sc->sc_maxid = 7; |
| 564 | sc->sc_config = HCC_AUTOTERM | HCC_PARITY; |
| 565 | if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { |
| 566 | sc->sc_config |= HCC_WIDE_CARD; |
| 567 | sc->sc_maxid = 15; |
| 568 | } |
| 569 | if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) |
| 570 | sc->sc_config |= HCC_SCSI_RESET; |
| 571 | |
| 572 | sc->sc_actsrb = NULL; |
| 573 | sc->sc_id = eeprom.scsi_id; |
| 574 | sc->sc_flag = 0; |
| 575 | |
| 576 | /* |
| 577 | * initialize and link all device's SRB queues of this adapter |
| 578 | */ |
| 579 | TAILQ_INIT(&sc->sc_freesrb); |
| 580 | TAILQ_INIT(&sc->sc_readysrb); |
| 581 | |
| 582 | sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, |
| 583 | M_DEVBUF, M_NOWAIT|M_ZERO); |
| 584 | DPRINTF(("all SRB size=%zx\n" , sizeof(struct trm_srb) * TRM_MAX_SRB)); |
| 585 | if (sc->sc_srb == NULL) { |
| 586 | aprint_error(": can not allocate SRB\n" ); |
| 587 | return 1; |
| 588 | } |
| 589 | |
| 590 | for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { |
| 591 | srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; |
| 592 | srb->sgoffset = TRM_SG_SIZE * i; |
| 593 | srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; |
| 594 | /* |
| 595 | * map all SRB space to SRB_array |
| 596 | */ |
| 597 | if (bus_dmamap_create(sc->sc_dmat, |
| 598 | MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, |
| 599 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { |
| 600 | aprint_error(": unable to create DMA transfer map.\n" ); |
| 601 | free(sc->sc_srb, M_DEVBUF); |
| 602 | return 1; |
| 603 | } |
| 604 | TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); |
| 605 | srb++; |
| 606 | } |
| 607 | |
| 608 | /* |
| 609 | * initialize all target info structures |
| 610 | */ |
| 611 | for (target = 0; target < TRM_MAX_TARGETS; target++) { |
| 612 | ti = &sc->sc_tinfo[target]; |
| 613 | ti->synctl = 0; |
| 614 | ti->offset = 0; |
| 615 | tconf = &eeprom.target[target]; |
| 616 | ti->config0 = tconf->config0; |
| 617 | ti->period = trm_clock_period[tconf->period & 0x07]; |
| 618 | ti->flag = 0; |
| 619 | if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { |
| 620 | #ifdef notyet |
| 621 | if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) |
| 622 | ti->flag |= USE_TAG_QUEUING; |
| 623 | #endif |
| 624 | } else |
| 625 | ti->flag |= NO_RESELECT; |
| 626 | |
| 627 | DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x" , |
| 628 | target, ti->config0, ti->period)); |
| 629 | DPRINTF((", flag = 0x%02x\n" , ti->flag)); |
| 630 | } |
| 631 | |
| 632 | /* program configuration 0 */ |
| 633 | bval = PHASELATCH | INITIATOR | BLOCKRST; |
| 634 | if ((sc->sc_config & HCC_PARITY) != 0) |
| 635 | bval |= PARITYCHECK; |
| 636 | bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); |
| 637 | |
| 638 | /* program configuration 1 */ |
| 639 | bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, |
| 640 | ACTIVE_NEG | ACTIVE_NEGPLUS); |
| 641 | |
| 642 | /* 250ms selection timeout */ |
| 643 | bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); |
| 644 | |
| 645 | /* Mask all interrupts */ |
| 646 | bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); |
| 647 | bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); |
| 648 | |
| 649 | /* Reset SCSI module */ |
| 650 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); |
| 651 | |
| 652 | /* program Host ID */ |
| 653 | bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); |
| 654 | |
| 655 | /* set asynchronous transfer */ |
| 656 | bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); |
| 657 | |
| 658 | /* Turn LED control off */ |
| 659 | bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, |
| 660 | bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); |
| 661 | |
| 662 | /* DMA config */ |
| 663 | bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, |
| 664 | bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); |
| 665 | |
| 666 | /* Clear pending interrupt status */ |
| 667 | (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); |
| 668 | |
| 669 | /* Enable SCSI interrupt */ |
| 670 | bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, |
| 671 | EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | |
| 672 | EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); |
| 673 | bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); |
| 674 | |
| 675 | trm_reset(sc); |
| 676 | |
| 677 | return 0; |
| 678 | } |
| 679 | |
| 680 | /* |
| 681 | * enqueues a SCSI command |
| 682 | * called by the higher level SCSI driver |
| 683 | */ |
| 684 | static void |
| 685 | trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, |
| 686 | void *arg) |
| 687 | { |
| 688 | bus_space_tag_t iot; |
| 689 | bus_space_handle_t ioh; |
| 690 | struct trm_softc *sc; |
| 691 | struct trm_srb *srb; |
| 692 | struct scsipi_xfer *xs; |
| 693 | int error, i, s; |
| 694 | |
| 695 | sc = device_private(chan->chan_adapter->adapt_dev); |
| 696 | iot = sc->sc_iot; |
| 697 | ioh = sc->sc_ioh; |
| 698 | |
| 699 | switch (req) { |
| 700 | case ADAPTER_REQ_RUN_XFER: |
| 701 | xs = arg; |
| 702 | DPRINTF(("trm_scsipi_request.....\n" )); |
| 703 | DPRINTF(("target= %d lun= %d\n" , xs->xs_periph->periph_target, |
| 704 | xs->xs_periph->periph_lun)); |
| 705 | if (xs->xs_control & XS_CTL_RESET) { |
| 706 | trm_reset(sc); |
| 707 | xs->error = XS_RESET; |
| 708 | return; |
| 709 | } |
| 710 | if (xs->xs_status & XS_STS_DONE) { |
| 711 | printf("%s: Is it done?\n" , device_xname(sc->sc_dev)); |
| 712 | xs->xs_status &= ~XS_STS_DONE; |
| 713 | } |
| 714 | |
| 715 | s = splbio(); |
| 716 | |
| 717 | /* Get SRB */ |
| 718 | srb = TAILQ_FIRST(&sc->sc_freesrb); |
| 719 | if (srb != NULL) { |
| 720 | TAILQ_REMOVE(&sc->sc_freesrb, srb, next); |
| 721 | } else { |
| 722 | xs->error = XS_RESOURCE_SHORTAGE; |
| 723 | scsipi_done(xs); |
| 724 | splx(s); |
| 725 | return; |
| 726 | } |
| 727 | |
| 728 | srb->xs = xs; |
| 729 | srb->cmdlen = xs->cmdlen; |
| 730 | memcpy(srb->cmd, xs->cmd, xs->cmdlen); |
| 731 | |
| 732 | if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { |
| 733 | if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, |
| 734 | xs->data, xs->datalen, NULL, |
| 735 | ((xs->xs_control & XS_CTL_NOSLEEP) ? |
| 736 | BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | |
| 737 | BUS_DMA_STREAMING | |
| 738 | ((xs->xs_control & XS_CTL_DATA_IN) ? |
| 739 | BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { |
| 740 | printf("%s: DMA transfer map unable to load, " |
| 741 | "error = %d\n" , device_xname(sc->sc_dev), |
| 742 | error); |
| 743 | xs->error = XS_DRIVER_STUFFUP; |
| 744 | /* |
| 745 | * free SRB |
| 746 | */ |
| 747 | TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); |
| 748 | splx(s); |
| 749 | return; |
| 750 | } |
| 751 | bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, |
| 752 | srb->dmap->dm_mapsize, |
| 753 | (xs->xs_control & XS_CTL_DATA_IN) ? |
| 754 | BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); |
| 755 | |
| 756 | /* Set up the scatter gather list */ |
| 757 | for (i = 0; i < srb->dmap->dm_nsegs; i++) { |
| 758 | srb->sgentry[i].address = |
| 759 | htole32(srb->dmap->dm_segs[i].ds_addr); |
| 760 | srb->sgentry[i].length = |
| 761 | htole32(srb->dmap->dm_segs[i].ds_len); |
| 762 | } |
| 763 | srb->buflen = xs->datalen; |
| 764 | srb->sgcnt = srb->dmap->dm_nsegs; |
| 765 | } else { |
| 766 | srb->sgentry[0].address = 0; |
| 767 | srb->sgentry[0].length = 0; |
| 768 | srb->buflen = 0; |
| 769 | srb->sgcnt = 0; |
| 770 | } |
| 771 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, |
| 772 | srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); |
| 773 | |
| 774 | sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ |
| 775 | |
| 776 | srb->sgindex = 0; |
| 777 | srb->hastat = 0; |
| 778 | srb->tastat = 0; |
| 779 | srb->flag = 0; |
| 780 | |
| 781 | TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); |
| 782 | if (sc->sc_actsrb == NULL) |
| 783 | trm_sched(sc); |
| 784 | splx(s); |
| 785 | |
| 786 | if ((xs->xs_control & XS_CTL_POLL) != 0) { |
| 787 | int timeout = xs->timeout; |
| 788 | |
| 789 | s = splbio(); |
| 790 | do { |
| 791 | while (--timeout) { |
| 792 | DELAY(1000); |
| 793 | if (bus_space_read_2(iot, ioh, |
| 794 | TRM_SCSI_STATUS) & SCSIINTERRUPT) |
| 795 | break; |
| 796 | } |
| 797 | if (timeout == 0) { |
| 798 | trm_timeout(srb); |
| 799 | break; |
| 800 | } else |
| 801 | trm_intr(sc); |
| 802 | } while ((xs->xs_status & XS_STS_DONE) == 0); |
| 803 | splx(s); |
| 804 | } |
| 805 | return; |
| 806 | |
| 807 | case ADAPTER_REQ_GROW_RESOURCES: |
| 808 | /* XXX Not supported. */ |
| 809 | return; |
| 810 | |
| 811 | case ADAPTER_REQ_SET_XFER_MODE: |
| 812 | { |
| 813 | struct trm_tinfo *ti; |
| 814 | struct scsipi_xfer_mode *xm; |
| 815 | |
| 816 | xm = arg; |
| 817 | ti = &sc->sc_tinfo[xm->xm_target]; |
| 818 | ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); |
| 819 | |
| 820 | #ifdef notyet |
| 821 | if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) |
| 822 | ti->flag |= USE_TAG_QUEUING; |
| 823 | else |
| 824 | #endif |
| 825 | ti->flag &= ~USE_TAG_QUEUING; |
| 826 | |
| 827 | if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && |
| 828 | (sc->sc_config & HCC_WIDE_CARD) != 0 && |
| 829 | (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { |
| 830 | ti->flag |= WIDE_NEGO_ENABLE; |
| 831 | ti->flag &= ~WIDE_NEGO_DONE; |
| 832 | } |
| 833 | |
| 834 | if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && |
| 835 | (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { |
| 836 | ti->flag |= SYNC_NEGO_ENABLE; |
| 837 | ti->flag &= ~SYNC_NEGO_DONE; |
| 838 | ti->period = trm_clock_period[0]; |
| 839 | } |
| 840 | |
| 841 | /* |
| 842 | * If we're not going to negotiate, send the |
| 843 | * notification now, since it won't happen later. |
| 844 | */ |
| 845 | if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == |
| 846 | (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) |
| 847 | trm_update_xfer_mode(sc, xm->xm_target); |
| 848 | |
| 849 | return; |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | |
| 854 | static void |
| 855 | trm_update_xfer_mode(struct trm_softc *sc, int target) |
| 856 | { |
| 857 | struct scsipi_xfer_mode xm; |
| 858 | struct trm_tinfo *ti; |
| 859 | |
| 860 | ti = &sc->sc_tinfo[target]; |
| 861 | xm.xm_target = target; |
| 862 | xm.xm_mode = 0; |
| 863 | xm.xm_period = 0; |
| 864 | xm.xm_offset = 0; |
| 865 | |
| 866 | if ((ti->synctl & WIDE_SYNC) != 0) |
| 867 | xm.xm_mode |= PERIPH_CAP_WIDE16; |
| 868 | |
| 869 | if (ti->period > 0) { |
| 870 | xm.xm_mode |= PERIPH_CAP_SYNC; |
| 871 | xm.xm_period = ti->period; |
| 872 | xm.xm_offset = ti->offset; |
| 873 | } |
| 874 | |
| 875 | #ifdef notyet |
| 876 | if ((ti->flag & USE_TAG_QUEUING) != 0) |
| 877 | xm.xm_mode |= PERIPH_CAP_TQING; |
| 878 | #endif |
| 879 | |
| 880 | scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); |
| 881 | } |
| 882 | |
| 883 | static void |
| 884 | trm_sched(struct trm_softc *sc) |
| 885 | { |
| 886 | struct trm_srb *srb; |
| 887 | struct scsipi_periph *periph; |
| 888 | struct trm_tinfo *ti; |
| 889 | struct trm_linfo *li; |
| 890 | int s, lun, tag; |
| 891 | |
| 892 | DPRINTF(("trm_sched...\n" )); |
| 893 | |
| 894 | TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { |
| 895 | periph = srb->xs->xs_periph; |
| 896 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 897 | lun = periph->periph_lun; |
| 898 | |
| 899 | /* select type of tag for this command */ |
| 900 | if ((ti->flag & NO_RESELECT) != 0 || |
| 901 | (ti->flag & USE_TAG_QUEUING) == 0 || |
| 902 | (srb->flag & AUTO_REQSENSE) != 0 || |
| 903 | (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) |
| 904 | tag = 0; |
| 905 | else |
| 906 | tag = srb->xs->xs_tag_type; |
| 907 | #if 0 |
| 908 | /* XXX use tags for polled commands? */ |
| 909 | if (srb->xs->xs_control & XS_CTL_POLL) |
| 910 | tag = 0; |
| 911 | #endif |
| 912 | |
| 913 | s = splbio(); |
| 914 | li = ti->linfo[lun]; |
| 915 | if (li == NULL) { |
| 916 | /* initialize lun info */ |
| 917 | if ((li = malloc(sizeof(*li), M_DEVBUF, |
| 918 | M_NOWAIT|M_ZERO)) == NULL) { |
| 919 | splx(s); |
| 920 | continue; |
| 921 | } |
| 922 | ti->linfo[lun] = li; |
| 923 | } |
| 924 | |
| 925 | if (tag == 0) { |
| 926 | /* try to issue this srb as an un-tagged command */ |
| 927 | if (li->untagged == NULL) |
| 928 | li->untagged = srb; |
| 929 | } |
| 930 | if (li->untagged != NULL) { |
| 931 | tag = 0; |
| 932 | if (li->busy != 1 && li->used == 0) { |
| 933 | /* we need to issue the untagged command now */ |
| 934 | srb = li->untagged; |
| 935 | periph = srb->xs->xs_periph; |
| 936 | } else { |
| 937 | /* not ready yet */ |
| 938 | splx(s); |
| 939 | continue; |
| 940 | } |
| 941 | } |
| 942 | srb->tag[0] = tag; |
| 943 | if (tag != 0) { |
| 944 | li->queued[srb->xs->xs_tag_id] = srb; |
| 945 | srb->tag[1] = srb->xs->xs_tag_id; |
| 946 | li->used++; |
| 947 | } |
| 948 | |
| 949 | if (li->untagged != NULL && li->busy != 1) { |
| 950 | li->busy = 1; |
| 951 | TAILQ_REMOVE(&sc->sc_readysrb, srb, next); |
| 952 | sc->sc_actsrb = srb; |
| 953 | trm_select(sc, srb); |
| 954 | splx(s); |
| 955 | break; |
| 956 | } |
| 957 | if (li->untagged == NULL && tag != 0) { |
| 958 | TAILQ_REMOVE(&sc->sc_readysrb, srb, next); |
| 959 | sc->sc_actsrb = srb; |
| 960 | trm_select(sc, srb); |
| 961 | splx(s); |
| 962 | break; |
| 963 | } else |
| 964 | splx(s); |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | static int |
| 969 | trm_select(struct trm_softc *sc, struct trm_srb *srb) |
| 970 | { |
| 971 | bus_space_tag_t iot = sc->sc_iot; |
| 972 | bus_space_handle_t ioh = sc->sc_ioh; |
| 973 | struct scsipi_periph *periph = srb->xs->xs_periph; |
| 974 | int target = periph->periph_target; |
| 975 | int lun = periph->periph_lun; |
| 976 | struct trm_tinfo *ti = &sc->sc_tinfo[target]; |
| 977 | uint8_t scsicmd; |
| 978 | |
| 979 | DPRINTF(("trm_select.....\n" )); |
| 980 | |
| 981 | if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { |
| 982 | callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), |
| 983 | trm_timeout, srb); |
| 984 | } |
| 985 | |
| 986 | bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); |
| 987 | bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); |
| 988 | bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); |
| 989 | bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); |
| 990 | /* Flush FIFO */ |
| 991 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 992 | DELAY(10); |
| 993 | |
| 994 | sc->sc_phase = PH_BUS_FREE; /* initial phase */ |
| 995 | |
| 996 | DPRINTF(("cmd = 0x%02x\n" , srb->cmd[0])); |
| 997 | |
| 998 | if (((ti->flag & WIDE_NEGO_ENABLE) && |
| 999 | (ti->flag & WIDE_NEGO_DONE) == 0) || |
| 1000 | ((ti->flag & SYNC_NEGO_ENABLE) && |
| 1001 | (ti->flag & SYNC_NEGO_DONE) == 0)) { |
| 1002 | sc->sc_state = TRM_MSGOUT; |
| 1003 | bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, |
| 1004 | MSG_IDENTIFY(lun, 0)); |
| 1005 | bus_space_write_multi_1(iot, ioh, |
| 1006 | TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); |
| 1007 | /* it's important for atn stop */ |
| 1008 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 1009 | DO_DATALATCH | DO_HWRESELECT); |
| 1010 | /* SCSI command */ |
| 1011 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); |
| 1012 | DPRINTF(("select with SEL_ATNSTOP\n" )); |
| 1013 | return 0; |
| 1014 | } |
| 1015 | |
| 1016 | if (srb->tag[0] != 0) { |
| 1017 | /* Send identify message */ |
| 1018 | bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, |
| 1019 | MSG_IDENTIFY(lun, 1)); |
| 1020 | /* Send Tag id */ |
| 1021 | bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); |
| 1022 | bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); |
| 1023 | scsicmd = SCMD_SEL_ATN3; |
| 1024 | DPRINTF(("select with SEL_ATN3\n" )); |
| 1025 | } else { |
| 1026 | /* Send identify message */ |
| 1027 | bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, |
| 1028 | MSG_IDENTIFY(lun, |
| 1029 | (ti->flag & NO_RESELECT) == 0 && |
| 1030 | (srb->flag & AUTO_REQSENSE) == 0 && |
| 1031 | (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); |
| 1032 | scsicmd = SCMD_SEL_ATN; |
| 1033 | DPRINTF(("select with SEL_ATN\n" )); |
| 1034 | } |
| 1035 | sc->sc_state = TRM_START; |
| 1036 | |
| 1037 | /* |
| 1038 | * Send CDB ..command block... |
| 1039 | */ |
| 1040 | bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); |
| 1041 | |
| 1042 | /* |
| 1043 | * If trm_select returns 0: current interrupt status |
| 1044 | * is interrupt enable. It's said that SCSI processor is |
| 1045 | * unoccupied. |
| 1046 | */ |
| 1047 | sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ |
| 1048 | /* SCSI command */ |
| 1049 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); |
| 1050 | return 0; |
| 1051 | } |
| 1052 | |
| 1053 | /* |
| 1054 | * perform a hard reset on the SCSI bus (and TRM_S1040 chip). |
| 1055 | */ |
| 1056 | static void |
| 1057 | trm_reset(struct trm_softc *sc) |
| 1058 | { |
| 1059 | bus_space_tag_t iot = sc->sc_iot; |
| 1060 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1061 | int s; |
| 1062 | |
| 1063 | DPRINTF(("trm_reset.........\n" )); |
| 1064 | |
| 1065 | s = splbio(); |
| 1066 | |
| 1067 | /* disable SCSI and DMA interrupt */ |
| 1068 | bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); |
| 1069 | bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); |
| 1070 | |
| 1071 | trm_reset_scsi_bus(sc); |
| 1072 | DELAY(100000); |
| 1073 | |
| 1074 | /* Enable SCSI interrupt */ |
| 1075 | bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, |
| 1076 | EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | |
| 1077 | EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); |
| 1078 | |
| 1079 | /* Enable DMA interrupt */ |
| 1080 | bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); |
| 1081 | |
| 1082 | /* Clear DMA FIFO */ |
| 1083 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); |
| 1084 | |
| 1085 | /* Clear SCSI FIFO */ |
| 1086 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1087 | |
| 1088 | sc->sc_actsrb = NULL; |
| 1089 | sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ |
| 1090 | |
| 1091 | splx(s); |
| 1092 | } |
| 1093 | |
| 1094 | static void |
| 1095 | trm_timeout(void *arg) |
| 1096 | { |
| 1097 | struct trm_srb *srb = (struct trm_srb *)arg; |
| 1098 | struct scsipi_xfer *xs; |
| 1099 | struct scsipi_periph *periph; |
| 1100 | struct trm_softc *sc; |
| 1101 | int s; |
| 1102 | |
| 1103 | if (srb == NULL) { |
| 1104 | printf("trm_timeout called with srb == NULL\n" ); |
| 1105 | return; |
| 1106 | } |
| 1107 | |
| 1108 | xs = srb->xs; |
| 1109 | if (xs == NULL) { |
| 1110 | printf("trm_timeout called with xs == NULL\n" ); |
| 1111 | return; |
| 1112 | } |
| 1113 | |
| 1114 | periph = xs->xs_periph; |
| 1115 | scsipi_printaddr(xs->xs_periph); |
| 1116 | printf("SCSI OpCode 0x%02x timed out\n" , xs->cmd->opcode); |
| 1117 | |
| 1118 | sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); |
| 1119 | |
| 1120 | trm_reset_scsi_bus(sc); |
| 1121 | s = splbio(); |
| 1122 | srb->flag |= SRB_TIMEOUT; |
| 1123 | trm_done(sc, srb); |
| 1124 | /* XXX needs more.. */ |
| 1125 | splx(s); |
| 1126 | } |
| 1127 | |
| 1128 | /* |
| 1129 | * Catch an interrupt from the adapter |
| 1130 | * Process pending device interrupts. |
| 1131 | */ |
| 1132 | static int |
| 1133 | trm_intr(void *arg) |
| 1134 | { |
| 1135 | bus_space_tag_t iot; |
| 1136 | bus_space_handle_t ioh; |
| 1137 | struct trm_softc *sc; |
| 1138 | int intstat, stat; |
| 1139 | |
| 1140 | DPRINTF(("trm_intr......\n" )); |
| 1141 | sc = arg; |
| 1142 | if (sc == NULL) |
| 1143 | return 0; |
| 1144 | |
| 1145 | iot = sc->sc_iot; |
| 1146 | ioh = sc->sc_ioh; |
| 1147 | |
| 1148 | stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); |
| 1149 | if ((stat & SCSIINTERRUPT) == 0) |
| 1150 | return 0; |
| 1151 | |
| 1152 | DPRINTF(("stat = %04x, " , stat)); |
| 1153 | intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); |
| 1154 | |
| 1155 | DPRINTF(("intstat=%02x, " , intstat)); |
| 1156 | if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { |
| 1157 | DPRINTF(("\n" )); |
| 1158 | trm_disconnect(sc); |
| 1159 | return 1; |
| 1160 | } |
| 1161 | if (intstat & INT_RESELECTED) { |
| 1162 | DPRINTF(("\n" )); |
| 1163 | trm_reselect(sc); |
| 1164 | return 1; |
| 1165 | } |
| 1166 | if (intstat & INT_SCSIRESET) { |
| 1167 | DPRINTF(("\n" )); |
| 1168 | trm_scsi_reset_detect(sc); |
| 1169 | return 1; |
| 1170 | } |
| 1171 | if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { |
| 1172 | DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n" , |
| 1173 | sc->sc_phase, sc->sc_state)); |
| 1174 | /* |
| 1175 | * software sequential machine |
| 1176 | */ |
| 1177 | |
| 1178 | /* |
| 1179 | * call phase0 functions... "phase entry" handle |
| 1180 | * every phase before start transfer |
| 1181 | */ |
| 1182 | switch (sc->sc_phase) { |
| 1183 | case PH_DATA_OUT: |
| 1184 | trm_dataout_phase0(sc, stat); |
| 1185 | break; |
| 1186 | case PH_DATA_IN: |
| 1187 | trm_datain_phase0(sc, stat); |
| 1188 | break; |
| 1189 | case PH_COMMAND: |
| 1190 | break; |
| 1191 | case PH_STATUS: |
| 1192 | trm_status_phase0(sc); |
| 1193 | stat = PH_BUS_FREE; |
| 1194 | break; |
| 1195 | case PH_MSG_OUT: |
| 1196 | if (sc->sc_state == TRM_UNEXPECT_RESEL || |
| 1197 | sc->sc_state == TRM_ABORT_SENT) |
| 1198 | stat = PH_BUS_FREE; |
| 1199 | break; |
| 1200 | case PH_MSG_IN: |
| 1201 | trm_msgin_phase0(sc); |
| 1202 | stat = PH_BUS_FREE; |
| 1203 | break; |
| 1204 | case PH_BUS_FREE: |
| 1205 | break; |
| 1206 | default: |
| 1207 | printf("%s: unexpected phase in trm_intr() phase0\n" , |
| 1208 | device_xname(sc->sc_dev)); |
| 1209 | break; |
| 1210 | } |
| 1211 | |
| 1212 | sc->sc_phase = stat & PHASEMASK; |
| 1213 | |
| 1214 | switch (sc->sc_phase) { |
| 1215 | case PH_DATA_OUT: |
| 1216 | trm_dataio_xfer(sc, XFERDATAOUT); |
| 1217 | break; |
| 1218 | case PH_DATA_IN: |
| 1219 | trm_dataio_xfer(sc, XFERDATAIN); |
| 1220 | break; |
| 1221 | case PH_COMMAND: |
| 1222 | trm_command_phase1(sc); |
| 1223 | break; |
| 1224 | case PH_STATUS: |
| 1225 | trm_status_phase1(sc); |
| 1226 | break; |
| 1227 | case PH_MSG_OUT: |
| 1228 | trm_msgout_phase1(sc); |
| 1229 | break; |
| 1230 | case PH_MSG_IN: |
| 1231 | trm_msgin_phase1(sc); |
| 1232 | break; |
| 1233 | case PH_BUS_FREE: |
| 1234 | break; |
| 1235 | default: |
| 1236 | printf("%s: unexpected phase in trm_intr() phase1\n" , |
| 1237 | device_xname(sc->sc_dev)); |
| 1238 | break; |
| 1239 | } |
| 1240 | |
| 1241 | return 1; |
| 1242 | } |
| 1243 | return 0; |
| 1244 | } |
| 1245 | |
| 1246 | static void |
| 1247 | trm_msgout_phase1(struct trm_softc *sc) |
| 1248 | { |
| 1249 | bus_space_tag_t iot = sc->sc_iot; |
| 1250 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1251 | struct trm_srb *srb; |
| 1252 | struct scsipi_periph *periph; |
| 1253 | struct trm_tinfo *ti; |
| 1254 | |
| 1255 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1256 | |
| 1257 | srb = sc->sc_actsrb; |
| 1258 | |
| 1259 | /* message out phase */ |
| 1260 | if (srb != NULL) { |
| 1261 | periph = srb->xs->xs_periph; |
| 1262 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 1263 | |
| 1264 | if ((ti->flag & WIDE_NEGO_DOING) == 0 && |
| 1265 | (ti->flag & WIDE_NEGO_ENABLE)) { |
| 1266 | /* send WDTR */ |
| 1267 | ti->flag &= ~SYNC_NEGO_DONE; |
| 1268 | |
| 1269 | sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); |
| 1270 | sc->sc_msgbuf[1] = MSG_EXTENDED; |
| 1271 | sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; |
| 1272 | sc->sc_msgbuf[3] = MSG_EXT_WDTR; |
| 1273 | sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; |
| 1274 | sc->sc_msgcnt = 5; |
| 1275 | |
| 1276 | ti->flag |= WIDE_NEGO_DOING; |
| 1277 | } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && |
| 1278 | (ti->flag & SYNC_NEGO_ENABLE)) { |
| 1279 | /* send SDTR */ |
| 1280 | int cnt = 0; |
| 1281 | |
| 1282 | if ((ti->flag & WIDE_NEGO_DONE) == 0) |
| 1283 | sc->sc_msgbuf[cnt++] = |
| 1284 | MSG_IDENTIFY(periph->periph_lun, 0); |
| 1285 | |
| 1286 | sc->sc_msgbuf[cnt++] = MSG_EXTENDED; |
| 1287 | sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; |
| 1288 | sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; |
| 1289 | sc->sc_msgbuf[cnt++] = ti->period; |
| 1290 | sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; |
| 1291 | sc->sc_msgcnt = cnt; |
| 1292 | ti->flag |= SYNC_NEGO_DOING; |
| 1293 | } |
| 1294 | } |
| 1295 | if (sc->sc_msgcnt == 0) { |
| 1296 | sc->sc_msgbuf[0] = MSG_ABORT; |
| 1297 | sc->sc_msgcnt = 1; |
| 1298 | sc->sc_state = TRM_ABORT_SENT; |
| 1299 | } |
| 1300 | |
| 1301 | DPRINTF(("msgout: cnt = %d, " , sc->sc_msgcnt)); |
| 1302 | DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n" , |
| 1303 | sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], |
| 1304 | sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); |
| 1305 | |
| 1306 | bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, |
| 1307 | sc->sc_msgbuf, sc->sc_msgcnt); |
| 1308 | sc->sc_msgcnt = 0; |
| 1309 | memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); |
| 1310 | |
| 1311 | /* it's important for atn stop */ |
| 1312 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1313 | |
| 1314 | /* |
| 1315 | * SCSI command |
| 1316 | */ |
| 1317 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); |
| 1318 | } |
| 1319 | |
| 1320 | static void |
| 1321 | trm_command_phase1(struct trm_softc *sc) |
| 1322 | { |
| 1323 | bus_space_tag_t iot = sc->sc_iot; |
| 1324 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1325 | struct trm_srb *srb; |
| 1326 | |
| 1327 | srb = sc->sc_actsrb; |
| 1328 | if (srb == NULL) { |
| 1329 | DPRINTF(("trm_command_phase1: no active srb\n" )); |
| 1330 | return; |
| 1331 | } |
| 1332 | |
| 1333 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); |
| 1334 | bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); |
| 1335 | |
| 1336 | sc->sc_state = TRM_COMMAND; |
| 1337 | /* it's important for atn stop */ |
| 1338 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1339 | |
| 1340 | /* |
| 1341 | * SCSI command |
| 1342 | */ |
| 1343 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); |
| 1344 | } |
| 1345 | |
| 1346 | static void |
| 1347 | trm_dataout_phase0(struct trm_softc *sc, int stat) |
| 1348 | { |
| 1349 | bus_space_tag_t iot = sc->sc_iot; |
| 1350 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1351 | struct trm_srb *srb; |
| 1352 | struct scsipi_periph *periph; |
| 1353 | struct trm_tinfo *ti; |
| 1354 | struct trm_sg_entry *sg; |
| 1355 | int sgindex; |
| 1356 | uint32_t xferlen, leftcnt = 0; |
| 1357 | |
| 1358 | if (sc->sc_state == TRM_XFERPAD) |
| 1359 | return; |
| 1360 | |
| 1361 | srb = sc->sc_actsrb; |
| 1362 | if (srb == NULL) { |
| 1363 | DPRINTF(("trm_dataout_phase0: no active srb\n" )); |
| 1364 | return; |
| 1365 | } |
| 1366 | periph = srb->xs->xs_periph; |
| 1367 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 1368 | |
| 1369 | if ((stat & PARITYERROR) != 0) |
| 1370 | srb->flag |= PARITY_ERROR; |
| 1371 | |
| 1372 | if ((stat & SCSIXFERDONE) == 0) { |
| 1373 | /* |
| 1374 | * when data transfer from DMA FIFO to SCSI FIFO |
| 1375 | * if there was some data left in SCSI FIFO |
| 1376 | */ |
| 1377 | leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & |
| 1378 | SCSI_FIFOCNT_MASK; |
| 1379 | if (ti->synctl & WIDE_SYNC) |
| 1380 | /* |
| 1381 | * if WIDE scsi SCSI FIFOCNT unit is word |
| 1382 | * so need to * 2 |
| 1383 | */ |
| 1384 | leftcnt <<= 1; |
| 1385 | } |
| 1386 | /* |
| 1387 | * calculate all the residue data that was not yet transferred |
| 1388 | * SCSI transfer counter + left in SCSI FIFO data |
| 1389 | * |
| 1390 | * .....TRM_SCSI_XCNT (24bits) |
| 1391 | * The counter always decrements by one for every SCSI |
| 1392 | * byte transfer. |
| 1393 | * .....TRM_SCSI_FIFOCNT ( 5bits) |
| 1394 | * The counter is SCSI FIFO offset counter |
| 1395 | */ |
| 1396 | leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); |
| 1397 | if (leftcnt == 1) { |
| 1398 | leftcnt = 0; |
| 1399 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1400 | } |
| 1401 | if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { |
| 1402 | while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & |
| 1403 | DMAXFERCOMP) == 0) |
| 1404 | ; /* XXX needs timeout */ |
| 1405 | |
| 1406 | srb->buflen = 0; |
| 1407 | } else { |
| 1408 | /* Update SG list */ |
| 1409 | |
| 1410 | /* |
| 1411 | * if transfer not yet complete |
| 1412 | * there were some data residue in SCSI FIFO or |
| 1413 | * SCSI transfer counter not empty |
| 1414 | */ |
| 1415 | if (srb->buflen != leftcnt) { |
| 1416 | /* data that had transferred length */ |
| 1417 | xferlen = srb->buflen - leftcnt; |
| 1418 | |
| 1419 | /* next time to be transferred length */ |
| 1420 | srb->buflen = leftcnt; |
| 1421 | |
| 1422 | /* |
| 1423 | * parsing from last time disconnect sgindex |
| 1424 | */ |
| 1425 | sg = srb->sgentry + srb->sgindex; |
| 1426 | for (sgindex = srb->sgindex; |
| 1427 | sgindex < srb->sgcnt; |
| 1428 | sgindex++, sg++) { |
| 1429 | /* |
| 1430 | * find last time which SG transfer |
| 1431 | * be disconnect |
| 1432 | */ |
| 1433 | if (xferlen >= le32toh(sg->length)) |
| 1434 | xferlen -= le32toh(sg->length); |
| 1435 | else { |
| 1436 | /* |
| 1437 | * update last time |
| 1438 | * disconnected SG list |
| 1439 | */ |
| 1440 | /* residue data length */ |
| 1441 | sg->length = |
| 1442 | htole32(le32toh(sg->length) |
| 1443 | - xferlen); |
| 1444 | /* residue data pointer */ |
| 1445 | sg->address = |
| 1446 | htole32(le32toh(sg->address) |
| 1447 | + xferlen); |
| 1448 | srb->sgindex = sgindex; |
| 1449 | break; |
| 1450 | } |
| 1451 | } |
| 1452 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, |
| 1453 | srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); |
| 1454 | } |
| 1455 | } |
| 1456 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); |
| 1457 | } |
| 1458 | |
| 1459 | static void |
| 1460 | trm_datain_phase0(struct trm_softc *sc, int stat) |
| 1461 | { |
| 1462 | bus_space_tag_t iot = sc->sc_iot; |
| 1463 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1464 | struct trm_srb *srb; |
| 1465 | struct trm_sg_entry *sg; |
| 1466 | int sgindex; |
| 1467 | uint32_t xferlen, leftcnt = 0; |
| 1468 | |
| 1469 | if (sc->sc_state == TRM_XFERPAD) |
| 1470 | return; |
| 1471 | |
| 1472 | srb = sc->sc_actsrb; |
| 1473 | if (srb == NULL) { |
| 1474 | DPRINTF(("trm_datain_phase0: no active srb\n" )); |
| 1475 | return; |
| 1476 | } |
| 1477 | |
| 1478 | if (stat & PARITYERROR) |
| 1479 | srb->flag |= PARITY_ERROR; |
| 1480 | |
| 1481 | leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); |
| 1482 | if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { |
| 1483 | while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & |
| 1484 | DMAXFERCOMP) == 0) |
| 1485 | ; /* XXX needs timeout */ |
| 1486 | |
| 1487 | srb->buflen = 0; |
| 1488 | } else { /* phase changed */ |
| 1489 | /* |
| 1490 | * parsing the case: |
| 1491 | * when a transfer not yet complete |
| 1492 | * but be disconnected by upper layer |
| 1493 | * if transfer not yet complete |
| 1494 | * there were some data residue in SCSI FIFO or |
| 1495 | * SCSI transfer counter not empty |
| 1496 | */ |
| 1497 | if (srb->buflen != leftcnt) { |
| 1498 | /* |
| 1499 | * data that had transferred length |
| 1500 | */ |
| 1501 | xferlen = srb->buflen - leftcnt; |
| 1502 | |
| 1503 | /* |
| 1504 | * next time to be transferred length |
| 1505 | */ |
| 1506 | srb->buflen = leftcnt; |
| 1507 | |
| 1508 | /* |
| 1509 | * parsing from last time disconnect sgindex |
| 1510 | */ |
| 1511 | sg = srb->sgentry + srb->sgindex; |
| 1512 | for (sgindex = srb->sgindex; |
| 1513 | sgindex < srb->sgcnt; |
| 1514 | sgindex++, sg++) { |
| 1515 | /* |
| 1516 | * find last time which SG transfer |
| 1517 | * be disconnect |
| 1518 | */ |
| 1519 | if (xferlen >= le32toh(sg->length)) |
| 1520 | xferlen -= le32toh(sg->length); |
| 1521 | else { |
| 1522 | /* |
| 1523 | * update last time |
| 1524 | * disconnected SG list |
| 1525 | */ |
| 1526 | /* residue data length */ |
| 1527 | sg->length = |
| 1528 | htole32(le32toh(sg->length) |
| 1529 | - xferlen); |
| 1530 | /* residue data pointer */ |
| 1531 | sg->address = |
| 1532 | htole32(le32toh(sg->address) |
| 1533 | + xferlen); |
| 1534 | srb->sgindex = sgindex; |
| 1535 | break; |
| 1536 | } |
| 1537 | } |
| 1538 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, |
| 1539 | srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); |
| 1540 | } |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | static void |
| 1545 | trm_dataio_xfer(struct trm_softc *sc, int iodir) |
| 1546 | { |
| 1547 | bus_space_tag_t iot = sc->sc_iot; |
| 1548 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1549 | struct trm_srb *srb; |
| 1550 | struct scsipi_periph *periph; |
| 1551 | struct trm_tinfo *ti; |
| 1552 | |
| 1553 | srb = sc->sc_actsrb; |
| 1554 | if (srb == NULL) { |
| 1555 | DPRINTF(("trm_dataio_xfer: no active srb\n" )); |
| 1556 | return; |
| 1557 | } |
| 1558 | periph = srb->xs->xs_periph; |
| 1559 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 1560 | |
| 1561 | if (srb->sgindex < srb->sgcnt) { |
| 1562 | if (srb->buflen > 0) { |
| 1563 | /* |
| 1564 | * load what physical address of Scatter/Gather |
| 1565 | * list table want to be transfer |
| 1566 | */ |
| 1567 | sc->sc_state = TRM_DATA_XFER; |
| 1568 | bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); |
| 1569 | bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, |
| 1570 | srb->sgaddr + |
| 1571 | srb->sgindex * sizeof(struct trm_sg_entry)); |
| 1572 | /* |
| 1573 | * load how many bytes in the Scatter/Gather list table |
| 1574 | */ |
| 1575 | bus_space_write_4(iot, ioh, TRM_DMA_XCNT, |
| 1576 | (srb->sgcnt - srb->sgindex) |
| 1577 | * sizeof(struct trm_sg_entry)); |
| 1578 | /* |
| 1579 | * load total xfer length (24bits) max value 16Mbyte |
| 1580 | */ |
| 1581 | bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); |
| 1582 | /* Start DMA transfer */ |
| 1583 | bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, |
| 1584 | iodir | SGXFER); |
| 1585 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, |
| 1586 | STARTDMAXFER); |
| 1587 | |
| 1588 | /* Start SCSI transfer */ |
| 1589 | /* it's important for atn stop */ |
| 1590 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 1591 | DO_DATALATCH); |
| 1592 | |
| 1593 | /* |
| 1594 | * SCSI command |
| 1595 | */ |
| 1596 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, |
| 1597 | (iodir == XFERDATAOUT) ? |
| 1598 | SCMD_DMA_OUT : SCMD_DMA_IN); |
| 1599 | } else { /* xfer pad */ |
| 1600 | if (srb->sgcnt) { |
| 1601 | srb->hastat = H_OVER_UNDER_RUN; |
| 1602 | } |
| 1603 | bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, |
| 1604 | (ti->synctl & WIDE_SYNC) ? 2 : 1); |
| 1605 | |
| 1606 | if (iodir == XFERDATAOUT) |
| 1607 | bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); |
| 1608 | else |
| 1609 | (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); |
| 1610 | |
| 1611 | sc->sc_state = TRM_XFERPAD; |
| 1612 | /* it's important for atn stop */ |
| 1613 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 1614 | DO_DATALATCH); |
| 1615 | |
| 1616 | /* |
| 1617 | * SCSI command |
| 1618 | */ |
| 1619 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, |
| 1620 | (iodir == XFERDATAOUT) ? |
| 1621 | SCMD_FIFO_OUT : SCMD_FIFO_IN); |
| 1622 | } |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | static void |
| 1627 | trm_status_phase0(struct trm_softc *sc) |
| 1628 | { |
| 1629 | bus_space_tag_t iot = sc->sc_iot; |
| 1630 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1631 | struct trm_srb *srb; |
| 1632 | |
| 1633 | srb = sc->sc_actsrb; |
| 1634 | if (srb == NULL) { |
| 1635 | DPRINTF(("trm_status_phase0: no active srb\n" )); |
| 1636 | return; |
| 1637 | } |
| 1638 | srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); |
| 1639 | sc->sc_state = TRM_COMPLETED; |
| 1640 | /* it's important for atn stop */ |
| 1641 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1642 | |
| 1643 | /* |
| 1644 | * SCSI command |
| 1645 | */ |
| 1646 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); |
| 1647 | } |
| 1648 | |
| 1649 | static void |
| 1650 | trm_status_phase1(struct trm_softc *sc) |
| 1651 | { |
| 1652 | bus_space_tag_t iot = sc->sc_iot; |
| 1653 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1654 | |
| 1655 | if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { |
| 1656 | if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) |
| 1657 | & SCSI_FIFO_EMPTY) == 0) |
| 1658 | bus_space_write_2(iot, ioh, |
| 1659 | TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1660 | if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) |
| 1661 | & DMA_FIFO_EMPTY) == 0) |
| 1662 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); |
| 1663 | } else { |
| 1664 | if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) |
| 1665 | & DMA_FIFO_EMPTY) == 0) |
| 1666 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); |
| 1667 | if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) |
| 1668 | & SCSI_FIFO_EMPTY) == 0) |
| 1669 | bus_space_write_2(iot, ioh, |
| 1670 | TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1671 | } |
| 1672 | sc->sc_state = TRM_STATUS; |
| 1673 | /* it's important for atn stop */ |
| 1674 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1675 | |
| 1676 | /* |
| 1677 | * SCSI command |
| 1678 | */ |
| 1679 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); |
| 1680 | } |
| 1681 | |
| 1682 | static void |
| 1683 | trm_msgin_phase0(struct trm_softc *sc) |
| 1684 | { |
| 1685 | bus_space_tag_t iot = sc->sc_iot; |
| 1686 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1687 | struct trm_srb *srb; |
| 1688 | struct scsipi_periph *periph; |
| 1689 | struct trm_tinfo *ti; |
| 1690 | int index; |
| 1691 | uint8_t msgin_code; |
| 1692 | |
| 1693 | msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); |
| 1694 | if (sc->sc_state != TRM_EXTEND_MSGIN) { |
| 1695 | DPRINTF(("msgin: code = %02x\n" , msgin_code)); |
| 1696 | switch (msgin_code) { |
| 1697 | case MSG_DISCONNECT: |
| 1698 | sc->sc_state = TRM_DISCONNECTED; |
| 1699 | break; |
| 1700 | |
| 1701 | case MSG_SAVEDATAPOINTER: |
| 1702 | break; |
| 1703 | |
| 1704 | case MSG_EXTENDED: |
| 1705 | case MSG_SIMPLE_Q_TAG: |
| 1706 | case MSG_HEAD_OF_Q_TAG: |
| 1707 | case MSG_ORDERED_Q_TAG: |
| 1708 | sc->sc_state = TRM_EXTEND_MSGIN; |
| 1709 | /* extended message (01h) */ |
| 1710 | sc->sc_msgbuf[0] = msgin_code; |
| 1711 | |
| 1712 | sc->sc_msgcnt = 1; |
| 1713 | /* extended message length (n) */ |
| 1714 | sc->sc_msg = &sc->sc_msgbuf[1]; |
| 1715 | |
| 1716 | break; |
| 1717 | case MSG_MESSAGE_REJECT: |
| 1718 | /* Reject message */ |
| 1719 | srb = sc->sc_actsrb; |
| 1720 | if (srb == NULL) { |
| 1721 | DPRINTF(("trm_msgin_phase0: " |
| 1722 | " message reject without actsrb\n" )); |
| 1723 | break; |
| 1724 | } |
| 1725 | periph = srb->xs->xs_periph; |
| 1726 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 1727 | |
| 1728 | if (ti->flag & WIDE_NEGO_ENABLE) { |
| 1729 | /* do wide nego reject */ |
| 1730 | ti->flag |= WIDE_NEGO_DONE; |
| 1731 | ti->flag &= |
| 1732 | ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); |
| 1733 | if ((ti->flag & SYNC_NEGO_ENABLE) && |
| 1734 | (ti->flag & SYNC_NEGO_DONE) == 0) { |
| 1735 | /* Set ATN, in case ATN was clear */ |
| 1736 | sc->sc_state = TRM_MSGOUT; |
| 1737 | bus_space_write_2(iot, ioh, |
| 1738 | TRM_SCSI_CONTROL, DO_SETATN); |
| 1739 | } else |
| 1740 | /* Clear ATN */ |
| 1741 | bus_space_write_2(iot, ioh, |
| 1742 | TRM_SCSI_CONTROL, DO_CLRATN); |
| 1743 | } else if (ti->flag & SYNC_NEGO_ENABLE) { |
| 1744 | /* do sync nego reject */ |
| 1745 | bus_space_write_2(iot, ioh, |
| 1746 | TRM_SCSI_CONTROL, DO_CLRATN); |
| 1747 | if (ti->flag & SYNC_NEGO_DOING) { |
| 1748 | ti->flag &=~(SYNC_NEGO_ENABLE | |
| 1749 | SYNC_NEGO_DONE); |
| 1750 | ti->synctl = 0; |
| 1751 | ti->offset = 0; |
| 1752 | bus_space_write_1(iot, ioh, |
| 1753 | TRM_SCSI_SYNC, ti->synctl); |
| 1754 | bus_space_write_1(iot, ioh, |
| 1755 | TRM_SCSI_OFFSET, ti->offset); |
| 1756 | } |
| 1757 | } |
| 1758 | break; |
| 1759 | |
| 1760 | case MSG_IGN_WIDE_RESIDUE: |
| 1761 | bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); |
| 1762 | (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); |
| 1763 | break; |
| 1764 | |
| 1765 | default: |
| 1766 | /* |
| 1767 | * Restore data pointer message |
| 1768 | * Save data pointer message |
| 1769 | * Completion message |
| 1770 | * NOP message |
| 1771 | */ |
| 1772 | break; |
| 1773 | } |
| 1774 | } else { |
| 1775 | /* |
| 1776 | * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN |
| 1777 | * Parsing incoming extented messages |
| 1778 | */ |
| 1779 | *sc->sc_msg++ = msgin_code; |
| 1780 | sc->sc_msgcnt++; |
| 1781 | |
| 1782 | DPRINTF(("extended_msgin: cnt = %d, " , sc->sc_msgcnt)); |
| 1783 | DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n" , |
| 1784 | sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], |
| 1785 | sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); |
| 1786 | |
| 1787 | switch (sc->sc_msgbuf[0]) { |
| 1788 | case MSG_SIMPLE_Q_TAG: |
| 1789 | case MSG_HEAD_OF_Q_TAG: |
| 1790 | case MSG_ORDERED_Q_TAG: |
| 1791 | /* |
| 1792 | * is QUEUE tag message : |
| 1793 | * |
| 1794 | * byte 0: |
| 1795 | * HEAD QUEUE TAG (20h) |
| 1796 | * ORDERED QUEUE TAG (21h) |
| 1797 | * SIMPLE QUEUE TAG (22h) |
| 1798 | * byte 1: |
| 1799 | * Queue tag (00h - FFh) |
| 1800 | */ |
| 1801 | if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { |
| 1802 | /* XXX XXX XXX */ |
| 1803 | struct trm_linfo *li; |
| 1804 | int tagid; |
| 1805 | |
| 1806 | sc->sc_flag &= ~WAIT_TAGMSG; |
| 1807 | tagid = sc->sc_msgbuf[1]; |
| 1808 | ti = &sc->sc_tinfo[sc->resel_target]; |
| 1809 | li = ti->linfo[sc->resel_lun]; |
| 1810 | srb = li->queued[tagid]; |
| 1811 | if (srb != NULL) { |
| 1812 | sc->sc_actsrb = srb; |
| 1813 | sc->sc_state = TRM_DATA_XFER; |
| 1814 | break; |
| 1815 | } else { |
| 1816 | printf("%s: invalid tag id\n" , |
| 1817 | device_xname(sc->sc_dev)); |
| 1818 | } |
| 1819 | |
| 1820 | sc->sc_state = TRM_UNEXPECT_RESEL; |
| 1821 | sc->sc_msgbuf[0] = MSG_ABORT_TAG; |
| 1822 | sc->sc_msgcnt = 1; |
| 1823 | bus_space_write_2(iot, ioh, |
| 1824 | TRM_SCSI_CONTROL, DO_SETATN); |
| 1825 | } else |
| 1826 | sc->sc_state = TRM_IDLE; |
| 1827 | break; |
| 1828 | |
| 1829 | case MSG_EXTENDED: |
| 1830 | srb = sc->sc_actsrb; |
| 1831 | if (srb == NULL) { |
| 1832 | DPRINTF(("trm_msgin_phase0: " |
| 1833 | "extended message without actsrb\n" )); |
| 1834 | break; |
| 1835 | } |
| 1836 | periph = srb->xs->xs_periph; |
| 1837 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 1838 | |
| 1839 | if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && |
| 1840 | sc->sc_msgcnt == 4) { |
| 1841 | /* |
| 1842 | * is Wide data xfer Extended message : |
| 1843 | * ====================================== |
| 1844 | * WIDE DATA TRANSFER REQUEST |
| 1845 | * ====================================== |
| 1846 | * byte 0 : Extended message (01h) |
| 1847 | * byte 1 : Extended message length (02h) |
| 1848 | * byte 2 : WIDE DATA TRANSFER code (03h) |
| 1849 | * byte 3 : Transfer width exponent |
| 1850 | */ |
| 1851 | if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { |
| 1852 | /* Length is wrong, reject it */ |
| 1853 | ti->flag &= ~(WIDE_NEGO_ENABLE | |
| 1854 | WIDE_NEGO_DONE); |
| 1855 | sc->sc_state = TRM_MSGOUT; |
| 1856 | sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; |
| 1857 | sc->sc_msgcnt = 1; |
| 1858 | bus_space_write_2(iot, ioh, |
| 1859 | TRM_SCSI_CONTROL, DO_SETATN); |
| 1860 | break; |
| 1861 | } |
| 1862 | |
| 1863 | if ((ti->flag & WIDE_NEGO_ENABLE) == 0) |
| 1864 | sc->sc_msgbuf[3] = |
| 1865 | MSG_EXT_WDTR_BUS_8_BIT; |
| 1866 | |
| 1867 | if (sc->sc_msgbuf[3] > |
| 1868 | MSG_EXT_WDTR_BUS_32_BIT) { |
| 1869 | /* reject_msg: */ |
| 1870 | ti->flag &= ~(WIDE_NEGO_ENABLE | |
| 1871 | WIDE_NEGO_DONE); |
| 1872 | sc->sc_state = TRM_MSGOUT; |
| 1873 | sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; |
| 1874 | sc->sc_msgcnt = 1; |
| 1875 | bus_space_write_2(iot, ioh, |
| 1876 | TRM_SCSI_CONTROL, DO_SETATN); |
| 1877 | break; |
| 1878 | } |
| 1879 | if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) |
| 1880 | /* do 16 bits */ |
| 1881 | sc->sc_msgbuf[3] = |
| 1882 | MSG_EXT_WDTR_BUS_16_BIT; |
| 1883 | if ((ti->flag & WIDE_NEGO_DONE) == 0) { |
| 1884 | ti->flag |= WIDE_NEGO_DONE; |
| 1885 | ti->flag &= ~(SYNC_NEGO_DONE | |
| 1886 | WIDE_NEGO_ENABLE); |
| 1887 | if (sc->sc_msgbuf[3] != |
| 1888 | MSG_EXT_WDTR_BUS_8_BIT) |
| 1889 | /* is Wide data xfer */ |
| 1890 | ti->synctl |= WIDE_SYNC; |
| 1891 | trm_update_xfer_mode(sc, |
| 1892 | periph->periph_target); |
| 1893 | } |
| 1894 | |
| 1895 | sc->sc_state = TRM_MSGOUT; |
| 1896 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 1897 | DO_SETATN); |
| 1898 | break; |
| 1899 | |
| 1900 | } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && |
| 1901 | sc->sc_msgcnt == 5) { |
| 1902 | /* |
| 1903 | * is 8bit transfer Extended message : |
| 1904 | * ================================= |
| 1905 | * SYNCHRONOUS DATA TRANSFER REQUEST |
| 1906 | * ================================= |
| 1907 | * byte 0 : Extended message (01h) |
| 1908 | * byte 1 : Extended message length (03) |
| 1909 | * byte 2 : SYNC DATA TRANSFER code (01h) |
| 1910 | * byte 3 : Transfer period factor |
| 1911 | * byte 4 : REQ/ACK offset |
| 1912 | */ |
| 1913 | if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { |
| 1914 | /* reject_msg */ |
| 1915 | sc->sc_state = TRM_MSGOUT; |
| 1916 | sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; |
| 1917 | sc->sc_msgcnt = 1; |
| 1918 | bus_space_write_2(iot, ioh, |
| 1919 | TRM_SCSI_CONTROL, DO_SETATN); |
| 1920 | break; |
| 1921 | } |
| 1922 | |
| 1923 | if ((ti->flag & SYNC_NEGO_DONE) == 0) { |
| 1924 | ti->flag &= |
| 1925 | ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); |
| 1926 | ti->flag |= SYNC_NEGO_DONE; |
| 1927 | if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) |
| 1928 | sc->sc_msgbuf[3] = 0; |
| 1929 | if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) |
| 1930 | sc->sc_msgbuf[4] = |
| 1931 | TRM_MAX_OFFSET; |
| 1932 | |
| 1933 | if (sc->sc_msgbuf[3] == 0 || |
| 1934 | sc->sc_msgbuf[4] == 0) { |
| 1935 | /* set async */ |
| 1936 | ti->synctl = 0; |
| 1937 | ti->offset = 0; |
| 1938 | } else { |
| 1939 | /* set sync */ |
| 1940 | /* Transfer period factor */ |
| 1941 | ti->period = sc->sc_msgbuf[3]; |
| 1942 | /* REQ/ACK offset */ |
| 1943 | ti->offset = sc->sc_msgbuf[4]; |
| 1944 | for (index = 0; |
| 1945 | index < NPERIOD; |
| 1946 | index++) |
| 1947 | if (ti->period <= |
| 1948 | trm_clock_period[ |
| 1949 | index]) |
| 1950 | break; |
| 1951 | |
| 1952 | ti->synctl |= ALT_SYNC | index; |
| 1953 | } |
| 1954 | /* |
| 1955 | * program SCSI control register |
| 1956 | */ |
| 1957 | bus_space_write_1(iot, ioh, |
| 1958 | TRM_SCSI_SYNC, ti->synctl); |
| 1959 | bus_space_write_1(iot, ioh, |
| 1960 | TRM_SCSI_OFFSET, ti->offset); |
| 1961 | trm_update_xfer_mode(sc, |
| 1962 | periph->periph_target); |
| 1963 | } |
| 1964 | sc->sc_state = TRM_IDLE; |
| 1965 | } |
| 1966 | break; |
| 1967 | default: |
| 1968 | break; |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | /* it's important for atn stop */ |
| 1973 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1974 | |
| 1975 | /* |
| 1976 | * SCSI command |
| 1977 | */ |
| 1978 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); |
| 1979 | } |
| 1980 | |
| 1981 | static void |
| 1982 | trm_msgin_phase1(struct trm_softc *sc) |
| 1983 | { |
| 1984 | bus_space_tag_t iot = sc->sc_iot; |
| 1985 | bus_space_handle_t ioh = sc->sc_ioh; |
| 1986 | |
| 1987 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 1988 | bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); |
| 1989 | if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { |
| 1990 | sc->sc_state = TRM_MSGIN; |
| 1991 | } |
| 1992 | |
| 1993 | /* it's important for atn stop */ |
| 1994 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 1995 | |
| 1996 | /* |
| 1997 | * SCSI command |
| 1998 | */ |
| 1999 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); |
| 2000 | } |
| 2001 | |
| 2002 | static void |
| 2003 | trm_disconnect(struct trm_softc *sc) |
| 2004 | { |
| 2005 | bus_space_tag_t iot = sc->sc_iot; |
| 2006 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2007 | struct trm_srb *srb; |
| 2008 | int s; |
| 2009 | |
| 2010 | s = splbio(); |
| 2011 | |
| 2012 | srb = sc->sc_actsrb; |
| 2013 | DPRINTF(("trm_disconnect...............\n" )); |
| 2014 | |
| 2015 | if (srb == NULL) { |
| 2016 | DPRINTF(("trm_disconnect: no active srb\n" )); |
| 2017 | DELAY(1000); /* 1 msec */ |
| 2018 | |
| 2019 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 2020 | DO_CLRFIFO | DO_HWRESELECT); |
| 2021 | return; |
| 2022 | } |
| 2023 | sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ |
| 2024 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, |
| 2025 | DO_CLRFIFO | DO_HWRESELECT); |
| 2026 | DELAY(100); |
| 2027 | |
| 2028 | switch (sc->sc_state) { |
| 2029 | case TRM_UNEXPECT_RESEL: |
| 2030 | sc->sc_state = TRM_IDLE; |
| 2031 | break; |
| 2032 | |
| 2033 | case TRM_ABORT_SENT: |
| 2034 | goto finish; |
| 2035 | |
| 2036 | case TRM_START: |
| 2037 | case TRM_MSGOUT: |
| 2038 | { |
| 2039 | /* Selection time out - discard all LUNs if empty */ |
| 2040 | struct scsipi_periph *periph; |
| 2041 | struct trm_tinfo *ti; |
| 2042 | struct trm_linfo *li; |
| 2043 | int lun; |
| 2044 | |
| 2045 | DPRINTF(("selection timeout\n" )); |
| 2046 | |
| 2047 | srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ |
| 2048 | |
| 2049 | periph = srb->xs->xs_periph; |
| 2050 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 2051 | for (lun = 0; lun < TRM_MAX_LUNS; lun++) { |
| 2052 | li = ti->linfo[lun]; |
| 2053 | if (li != NULL && |
| 2054 | li->untagged == NULL && li->used == 0) { |
| 2055 | ti->linfo[lun] = NULL; |
| 2056 | free(li, M_DEVBUF); |
| 2057 | } |
| 2058 | } |
| 2059 | } |
| 2060 | goto finish; |
| 2061 | |
| 2062 | case TRM_DISCONNECTED: |
| 2063 | sc->sc_actsrb = NULL; |
| 2064 | sc->sc_state = TRM_IDLE; |
| 2065 | goto sched; |
| 2066 | |
| 2067 | case TRM_COMPLETED: |
| 2068 | goto finish; |
| 2069 | } |
| 2070 | |
| 2071 | out: |
| 2072 | splx(s); |
| 2073 | return; |
| 2074 | |
| 2075 | finish: |
| 2076 | sc->sc_state = TRM_IDLE; |
| 2077 | trm_done(sc, srb); |
| 2078 | goto out; |
| 2079 | |
| 2080 | sched: |
| 2081 | trm_sched(sc); |
| 2082 | goto out; |
| 2083 | } |
| 2084 | |
| 2085 | static void |
| 2086 | trm_reselect(struct trm_softc *sc) |
| 2087 | { |
| 2088 | bus_space_tag_t iot = sc->sc_iot; |
| 2089 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2090 | struct trm_tinfo *ti; |
| 2091 | struct trm_linfo *li; |
| 2092 | int target, lun; |
| 2093 | |
| 2094 | DPRINTF(("trm_reselect.................\n" )); |
| 2095 | |
| 2096 | if (sc->sc_actsrb != NULL) { |
| 2097 | /* arbitration lost but reselection win */ |
| 2098 | sc->sc_state = TRM_READY; |
| 2099 | target = sc->sc_actsrb->xs->xs_periph->periph_target; |
| 2100 | ti = &sc->sc_tinfo[target]; |
| 2101 | } else { |
| 2102 | /* Read Reselected Target Id and LUN */ |
| 2103 | target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); |
| 2104 | lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; |
| 2105 | ti = &sc->sc_tinfo[target]; |
| 2106 | li = ti->linfo[lun]; |
| 2107 | DPRINTF(("target = %d, lun = %d\n" , target, lun)); |
| 2108 | |
| 2109 | /* |
| 2110 | * Check to see if we are running an un-tagged command. |
| 2111 | * Otherwise ack the IDENTIFY and wait for a tag message. |
| 2112 | */ |
| 2113 | if (li != NULL) { |
| 2114 | if (li->untagged != NULL && li->busy) { |
| 2115 | sc->sc_actsrb = li->untagged; |
| 2116 | sc->sc_state = TRM_DATA_XFER; |
| 2117 | } else { |
| 2118 | sc->resel_target = target; |
| 2119 | sc->resel_lun = lun; |
| 2120 | /* XXX XXX XXX */ |
| 2121 | sc->sc_flag |= WAIT_TAGMSG; |
| 2122 | } |
| 2123 | } |
| 2124 | |
| 2125 | if ((ti->flag & USE_TAG_QUEUING) == 0 && |
| 2126 | sc->sc_actsrb == NULL) { |
| 2127 | printf("%s: reselect from target %d lun %d " |
| 2128 | "without nexus; sending abort\n" , |
| 2129 | device_xname(sc->sc_dev), target, lun); |
| 2130 | sc->sc_state = TRM_UNEXPECT_RESEL; |
| 2131 | sc->sc_msgbuf[0] = MSG_ABORT_TAG; |
| 2132 | sc->sc_msgcnt = 1; |
| 2133 | bus_space_write_2(iot, ioh, |
| 2134 | TRM_SCSI_CONTROL, DO_SETATN); |
| 2135 | } |
| 2136 | } |
| 2137 | sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ |
| 2138 | /* |
| 2139 | * Program HA ID, target ID, period and offset |
| 2140 | */ |
| 2141 | /* target ID */ |
| 2142 | bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); |
| 2143 | |
| 2144 | /* host ID */ |
| 2145 | bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); |
| 2146 | |
| 2147 | /* period */ |
| 2148 | bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); |
| 2149 | |
| 2150 | /* offset */ |
| 2151 | bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); |
| 2152 | |
| 2153 | /* it's important for atn stop */ |
| 2154 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); |
| 2155 | /* |
| 2156 | * SCSI command |
| 2157 | */ |
| 2158 | /* to rls the /ACK signal */ |
| 2159 | bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); |
| 2160 | } |
| 2161 | |
| 2162 | /* |
| 2163 | * Complete execution of a SCSI command |
| 2164 | * Signal completion to the generic SCSI driver |
| 2165 | */ |
| 2166 | static void |
| 2167 | trm_done(struct trm_softc *sc, struct trm_srb *srb) |
| 2168 | { |
| 2169 | struct scsipi_xfer *xs = srb->xs; |
| 2170 | |
| 2171 | DPRINTF(("trm_done..................\n" )); |
| 2172 | |
| 2173 | if (xs == NULL) |
| 2174 | return; |
| 2175 | |
| 2176 | if ((xs->xs_control & XS_CTL_POLL) == 0) |
| 2177 | callout_stop(&xs->xs_callout); |
| 2178 | |
| 2179 | if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || |
| 2180 | srb->flag & AUTO_REQSENSE) { |
| 2181 | bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, |
| 2182 | srb->dmap->dm_mapsize, |
| 2183 | ((xs->xs_control & XS_CTL_DATA_IN) || |
| 2184 | (srb->flag & AUTO_REQSENSE)) ? |
| 2185 | BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); |
| 2186 | bus_dmamap_unload(sc->sc_dmat, srb->dmap); |
| 2187 | } |
| 2188 | |
| 2189 | /* |
| 2190 | * target status |
| 2191 | */ |
| 2192 | xs->status = srb->tastat; |
| 2193 | |
| 2194 | DPRINTF(("xs->status = 0x%02x\n" , xs->status)); |
| 2195 | |
| 2196 | switch (xs->status) { |
| 2197 | case SCSI_OK: |
| 2198 | /* |
| 2199 | * process initiator status...... |
| 2200 | * Adapter (initiator) status |
| 2201 | */ |
| 2202 | if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { |
| 2203 | printf("%s: over/under run error\n" , |
| 2204 | device_xname(sc->sc_dev)); |
| 2205 | srb->tastat = 0; |
| 2206 | /* Illegal length (over/under run) */ |
| 2207 | xs->error = XS_DRIVER_STUFFUP; |
| 2208 | } else if ((srb->flag & PARITY_ERROR) != 0) { |
| 2209 | printf("%s: parity error\n" , device_xname(sc->sc_dev)); |
| 2210 | /* Driver failed to perform operation */ |
| 2211 | xs->error = XS_DRIVER_STUFFUP; /* XXX */ |
| 2212 | } else if ((srb->flag & SRB_TIMEOUT) != 0) { |
| 2213 | xs->resid = srb->buflen; |
| 2214 | xs->error = XS_TIMEOUT; |
| 2215 | } else { |
| 2216 | /* No error */ |
| 2217 | xs->resid = srb->buflen; |
| 2218 | srb->hastat = 0; |
| 2219 | if (srb->flag & AUTO_REQSENSE) { |
| 2220 | /* there is no error, (sense is invalid) */ |
| 2221 | xs->error = XS_SENSE; |
| 2222 | } else { |
| 2223 | srb->tastat = 0; |
| 2224 | xs->error = XS_NOERROR; |
| 2225 | } |
| 2226 | } |
| 2227 | break; |
| 2228 | |
| 2229 | case SCSI_CHECK: |
| 2230 | if ((srb->flag & AUTO_REQSENSE) != 0 || |
| 2231 | trm_request_sense(sc, srb) != 0) { |
| 2232 | printf("%s: request sense failed\n" , |
| 2233 | device_xname(sc->sc_dev)); |
| 2234 | xs->error = XS_DRIVER_STUFFUP; |
| 2235 | break; |
| 2236 | } |
| 2237 | xs->error = XS_SENSE; |
| 2238 | return; |
| 2239 | |
| 2240 | case SCSI_SEL_TIMEOUT: |
| 2241 | srb->hastat = H_SEL_TIMEOUT; |
| 2242 | srb->tastat = 0; |
| 2243 | xs->error = XS_SELTIMEOUT; |
| 2244 | break; |
| 2245 | |
| 2246 | case SCSI_QUEUE_FULL: |
| 2247 | case SCSI_BUSY: |
| 2248 | xs->error = XS_BUSY; |
| 2249 | break; |
| 2250 | |
| 2251 | case SCSI_RESV_CONFLICT: |
| 2252 | DPRINTF(("%s: target reserved at " , device_xname(sc->sc_dev))); |
| 2253 | DPRINTF(("%s %d\n" , __FILE__, __LINE__)); |
| 2254 | xs->error = XS_BUSY; |
| 2255 | break; |
| 2256 | |
| 2257 | default: |
| 2258 | srb->hastat = 0; |
| 2259 | printf("%s: trm_done(): unknown status = %02x\n" , |
| 2260 | device_xname(sc->sc_dev), xs->status); |
| 2261 | xs->error = XS_DRIVER_STUFFUP; |
| 2262 | break; |
| 2263 | } |
| 2264 | |
| 2265 | trm_dequeue(sc, srb); |
| 2266 | if (srb == sc->sc_actsrb) { |
| 2267 | sc->sc_actsrb = NULL; |
| 2268 | trm_sched(sc); |
| 2269 | } |
| 2270 | |
| 2271 | TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); |
| 2272 | |
| 2273 | /* Notify cmd done */ |
| 2274 | scsipi_done(xs); |
| 2275 | } |
| 2276 | |
| 2277 | static int |
| 2278 | trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) |
| 2279 | { |
| 2280 | struct scsipi_xfer *xs; |
| 2281 | struct scsipi_periph *periph; |
| 2282 | struct trm_tinfo *ti; |
| 2283 | struct trm_linfo *li; |
| 2284 | struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; |
| 2285 | int error; |
| 2286 | |
| 2287 | DPRINTF(("trm_request_sense...\n" )); |
| 2288 | |
| 2289 | xs = srb->xs; |
| 2290 | periph = xs->xs_periph; |
| 2291 | |
| 2292 | srb->flag |= AUTO_REQSENSE; |
| 2293 | |
| 2294 | /* Status of initiator/target */ |
| 2295 | srb->hastat = 0; |
| 2296 | srb->tastat = 0; |
| 2297 | |
| 2298 | memset(ss, 0, sizeof(*ss)); |
| 2299 | ss->opcode = SCSI_REQUEST_SENSE; |
| 2300 | ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; |
| 2301 | ss->length = sizeof(struct scsi_sense_data); |
| 2302 | |
| 2303 | srb->buflen = sizeof(struct scsi_sense_data); |
| 2304 | srb->sgcnt = 1; |
| 2305 | srb->sgindex = 0; |
| 2306 | srb->cmdlen = sizeof(struct scsi_request_sense); |
| 2307 | |
| 2308 | if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, |
| 2309 | &xs->sense.scsi_sense, srb->buflen, NULL, |
| 2310 | BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { |
| 2311 | return error; |
| 2312 | } |
| 2313 | bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, |
| 2314 | srb->buflen, BUS_DMASYNC_PREREAD); |
| 2315 | |
| 2316 | srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); |
| 2317 | srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); |
| 2318 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, |
| 2319 | TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); |
| 2320 | |
| 2321 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 2322 | li = ti->linfo[periph->periph_lun]; |
| 2323 | if (li->busy > 0) |
| 2324 | li->busy = 0; |
| 2325 | trm_dequeue(sc, srb); |
| 2326 | li->untagged = srb; /* must be executed first to fix C/A */ |
| 2327 | li->busy = 2; |
| 2328 | |
| 2329 | if (srb == sc->sc_actsrb) |
| 2330 | trm_select(sc, srb); |
| 2331 | else { |
| 2332 | TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); |
| 2333 | if (sc->sc_actsrb == NULL) |
| 2334 | trm_sched(sc); |
| 2335 | } |
| 2336 | return 0; |
| 2337 | } |
| 2338 | |
| 2339 | static void |
| 2340 | trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) |
| 2341 | { |
| 2342 | struct scsipi_periph *periph; |
| 2343 | struct trm_tinfo *ti; |
| 2344 | struct trm_linfo *li; |
| 2345 | |
| 2346 | periph = srb->xs->xs_periph; |
| 2347 | ti = &sc->sc_tinfo[periph->periph_target]; |
| 2348 | li = ti->linfo[periph->periph_lun]; |
| 2349 | |
| 2350 | if (li->untagged == srb) { |
| 2351 | li->busy = 0; |
| 2352 | li->untagged = NULL; |
| 2353 | } |
| 2354 | if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { |
| 2355 | li->queued[srb->tag[1]] = NULL; |
| 2356 | li->used--; |
| 2357 | } |
| 2358 | } |
| 2359 | |
| 2360 | static void |
| 2361 | trm_reset_scsi_bus(struct trm_softc *sc) |
| 2362 | { |
| 2363 | bus_space_tag_t iot = sc->sc_iot; |
| 2364 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2365 | int timeout, s; |
| 2366 | |
| 2367 | DPRINTF(("trm_reset_scsi_bus.........\n" )); |
| 2368 | |
| 2369 | s = splbio(); |
| 2370 | |
| 2371 | sc->sc_flag |= RESET_DEV; |
| 2372 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); |
| 2373 | for (timeout = 20000; timeout >= 0; timeout--) { |
| 2374 | DELAY(1); |
| 2375 | if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & |
| 2376 | INT_SCSIRESET) == 0) |
| 2377 | break; |
| 2378 | } |
| 2379 | if (timeout == 0) |
| 2380 | printf(": scsibus reset timeout\n" ); |
| 2381 | |
| 2382 | splx(s); |
| 2383 | } |
| 2384 | |
| 2385 | static void |
| 2386 | trm_scsi_reset_detect(struct trm_softc *sc) |
| 2387 | { |
| 2388 | bus_space_tag_t iot = sc->sc_iot; |
| 2389 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2390 | int s; |
| 2391 | |
| 2392 | DPRINTF(("trm_scsi_reset_detect...............\n" )); |
| 2393 | DELAY(1000000); /* delay 1 sec */ |
| 2394 | |
| 2395 | s = splbio(); |
| 2396 | |
| 2397 | bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); |
| 2398 | bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); |
| 2399 | |
| 2400 | if (sc->sc_flag & RESET_DEV) { |
| 2401 | sc->sc_flag |= RESET_DONE; |
| 2402 | } else { |
| 2403 | sc->sc_flag |= RESET_DETECT; |
| 2404 | sc->sc_actsrb = NULL; |
| 2405 | sc->sc_flag = 0; |
| 2406 | trm_sched(sc); |
| 2407 | } |
| 2408 | splx(s); |
| 2409 | } |
| 2410 | |
| 2411 | /* |
| 2412 | * read seeprom 128 bytes to struct eeprom and check checksum. |
| 2413 | * If it is wrong, update with default value. |
| 2414 | */ |
| 2415 | static void |
| 2416 | trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) |
| 2417 | { |
| 2418 | struct nvram_target *target; |
| 2419 | uint16_t *ep; |
| 2420 | uint16_t chksum; |
| 2421 | int i; |
| 2422 | |
| 2423 | DPRINTF(("trm_check_eeprom......\n" )); |
| 2424 | trm_eeprom_read_all(sc, eeprom); |
| 2425 | ep = (uint16_t *)eeprom; |
| 2426 | chksum = 0; |
| 2427 | for (i = 0; i < 64; i++) |
| 2428 | chksum += le16toh(*ep++); |
| 2429 | |
| 2430 | if (chksum != TRM_NVRAM_CKSUM) { |
| 2431 | DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n" )); |
| 2432 | /* |
| 2433 | * Checksum error, load default |
| 2434 | */ |
| 2435 | eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; |
| 2436 | eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; |
| 2437 | eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; |
| 2438 | eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; |
| 2439 | eeprom->subclass = 0x00; |
| 2440 | eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; |
| 2441 | eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; |
| 2442 | eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; |
| 2443 | eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; |
| 2444 | eeprom->reserved0 = 0x00; |
| 2445 | |
| 2446 | for (i = 0, target = eeprom->target; |
| 2447 | i < TRM_MAX_TARGETS; |
| 2448 | i++, target++) { |
| 2449 | target->config0 = 0x77; |
| 2450 | target->period = 0x00; |
| 2451 | target->config2 = 0x00; |
| 2452 | target->config3 = 0x00; |
| 2453 | } |
| 2454 | |
| 2455 | eeprom->scsi_id = 7; |
| 2456 | eeprom->channel_cfg = 0x0F; |
| 2457 | eeprom->delay_time = 0; |
| 2458 | eeprom->max_tag = 4; |
| 2459 | eeprom->reserved1 = 0x15; |
| 2460 | eeprom->boot_target = 0; |
| 2461 | eeprom->boot_lun = 0; |
| 2462 | eeprom->reserved2 = 0; |
| 2463 | memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); |
| 2464 | |
| 2465 | chksum = 0; |
| 2466 | ep = (uint16_t *)eeprom; |
| 2467 | for (i = 0; i < 63; i++) |
| 2468 | chksum += le16toh(*ep++); |
| 2469 | |
| 2470 | chksum = TRM_NVRAM_CKSUM - chksum; |
| 2471 | eeprom->checksum0 = chksum & 0xFF; |
| 2472 | eeprom->checksum1 = chksum >> 8; |
| 2473 | |
| 2474 | trm_eeprom_write_all(sc, eeprom); |
| 2475 | } |
| 2476 | } |
| 2477 | |
| 2478 | /* |
| 2479 | * write struct eeprom 128 bytes to seeprom |
| 2480 | */ |
| 2481 | static void |
| 2482 | trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) |
| 2483 | { |
| 2484 | bus_space_tag_t iot = sc->sc_iot; |
| 2485 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2486 | uint8_t *sbuf = (uint8_t *)eeprom; |
| 2487 | uint8_t addr; |
| 2488 | |
| 2489 | /* Enable SEEPROM */ |
| 2490 | bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, |
| 2491 | bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); |
| 2492 | |
| 2493 | /* |
| 2494 | * Write enable |
| 2495 | */ |
| 2496 | trm_eeprom_write_cmd(sc, 0x04, 0xFF); |
| 2497 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); |
| 2498 | trm_eeprom_wait(); |
| 2499 | |
| 2500 | for (addr = 0; addr < 128; addr++, sbuf++) |
| 2501 | trm_eeprom_set_data(sc, addr, *sbuf); |
| 2502 | |
| 2503 | /* |
| 2504 | * Write disable |
| 2505 | */ |
| 2506 | trm_eeprom_write_cmd(sc, 0x04, 0x00); |
| 2507 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); |
| 2508 | trm_eeprom_wait(); |
| 2509 | |
| 2510 | /* Disable SEEPROM */ |
| 2511 | bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, |
| 2512 | bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); |
| 2513 | } |
| 2514 | |
| 2515 | /* |
| 2516 | * write one byte to seeprom |
| 2517 | */ |
| 2518 | static void |
| 2519 | trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) |
| 2520 | { |
| 2521 | bus_space_tag_t iot = sc->sc_iot; |
| 2522 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2523 | int i; |
| 2524 | uint8_t send; |
| 2525 | |
| 2526 | /* |
| 2527 | * Send write command & address |
| 2528 | */ |
| 2529 | trm_eeprom_write_cmd(sc, 0x05, addr); |
| 2530 | /* |
| 2531 | * Write data |
| 2532 | */ |
| 2533 | for (i = 0; i < 8; i++, data <<= 1) { |
| 2534 | send = NVR_SELECT; |
| 2535 | if (data & 0x80) /* Start from bit 7 */ |
| 2536 | send |= NVR_BITOUT; |
| 2537 | |
| 2538 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); |
| 2539 | trm_eeprom_wait(); |
| 2540 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); |
| 2541 | trm_eeprom_wait(); |
| 2542 | } |
| 2543 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); |
| 2544 | trm_eeprom_wait(); |
| 2545 | /* |
| 2546 | * Disable chip select |
| 2547 | */ |
| 2548 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); |
| 2549 | trm_eeprom_wait(); |
| 2550 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); |
| 2551 | trm_eeprom_wait(); |
| 2552 | /* |
| 2553 | * Wait for write ready |
| 2554 | */ |
| 2555 | for (;;) { |
| 2556 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, |
| 2557 | NVR_SELECT | NVR_CLOCK); |
| 2558 | trm_eeprom_wait(); |
| 2559 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); |
| 2560 | trm_eeprom_wait(); |
| 2561 | if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) |
| 2562 | break; |
| 2563 | } |
| 2564 | /* |
| 2565 | * Disable chip select |
| 2566 | */ |
| 2567 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); |
| 2568 | } |
| 2569 | |
| 2570 | /* |
| 2571 | * read seeprom 128 bytes to struct eeprom |
| 2572 | */ |
| 2573 | static void |
| 2574 | trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) |
| 2575 | { |
| 2576 | bus_space_tag_t iot = sc->sc_iot; |
| 2577 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2578 | uint8_t *sbuf = (uint8_t *)eeprom; |
| 2579 | uint8_t addr; |
| 2580 | |
| 2581 | /* |
| 2582 | * Enable SEEPROM |
| 2583 | */ |
| 2584 | bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, |
| 2585 | bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); |
| 2586 | |
| 2587 | for (addr = 0; addr < 128; addr++) |
| 2588 | *sbuf++ = trm_eeprom_get_data(sc, addr); |
| 2589 | |
| 2590 | /* |
| 2591 | * Disable SEEPROM |
| 2592 | */ |
| 2593 | bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, |
| 2594 | bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); |
| 2595 | } |
| 2596 | |
| 2597 | /* |
| 2598 | * read one byte from seeprom |
| 2599 | */ |
| 2600 | static uint8_t |
| 2601 | trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) |
| 2602 | { |
| 2603 | bus_space_tag_t iot = sc->sc_iot; |
| 2604 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2605 | int i; |
| 2606 | uint8_t read, data = 0; |
| 2607 | |
| 2608 | /* |
| 2609 | * Send read command & address |
| 2610 | */ |
| 2611 | trm_eeprom_write_cmd(sc, 0x06, addr); |
| 2612 | |
| 2613 | for (i = 0; i < 8; i++) { /* Read data */ |
| 2614 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, |
| 2615 | NVR_SELECT | NVR_CLOCK); |
| 2616 | trm_eeprom_wait(); |
| 2617 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); |
| 2618 | /* |
| 2619 | * Get data bit while falling edge |
| 2620 | */ |
| 2621 | read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); |
| 2622 | data <<= 1; |
| 2623 | if (read & NVR_BITIN) |
| 2624 | data |= 1; |
| 2625 | |
| 2626 | trm_eeprom_wait(); |
| 2627 | } |
| 2628 | /* |
| 2629 | * Disable chip select |
| 2630 | */ |
| 2631 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); |
| 2632 | return data; |
| 2633 | } |
| 2634 | |
| 2635 | /* |
| 2636 | * write SB and Op Code into seeprom |
| 2637 | */ |
| 2638 | static void |
| 2639 | trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) |
| 2640 | { |
| 2641 | bus_space_tag_t iot = sc->sc_iot; |
| 2642 | bus_space_handle_t ioh = sc->sc_ioh; |
| 2643 | int i; |
| 2644 | uint8_t send; |
| 2645 | |
| 2646 | /* Program SB+OP code */ |
| 2647 | for (i = 0; i < 3; i++, cmd <<= 1) { |
| 2648 | send = NVR_SELECT; |
| 2649 | if (cmd & 0x04) /* Start from bit 2 */ |
| 2650 | send |= NVR_BITOUT; |
| 2651 | |
| 2652 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); |
| 2653 | trm_eeprom_wait(); |
| 2654 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); |
| 2655 | trm_eeprom_wait(); |
| 2656 | } |
| 2657 | |
| 2658 | /* Program address */ |
| 2659 | for (i = 0; i < 7; i++, addr <<= 1) { |
| 2660 | send = NVR_SELECT; |
| 2661 | if (addr & 0x40) /* Start from bit 6 */ |
| 2662 | send |= NVR_BITOUT; |
| 2663 | |
| 2664 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); |
| 2665 | trm_eeprom_wait(); |
| 2666 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); |
| 2667 | trm_eeprom_wait(); |
| 2668 | } |
| 2669 | bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); |
| 2670 | trm_eeprom_wait(); |
| 2671 | } |
| 2672 | |