| 1 | /* $NetBSD: rt2560reg.h,v 1.1 2006/06/04 20:38:06 rpaulo Exp $ */ |
| 2 | /* $OpenBSD: rt2560reg.h,v 1.3 2006/01/14 12:43:27 damien Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2005, 2006 |
| 6 | * Damien Bergamini <damien.bergamini@free.fr> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #define RT2560_TX_RING_COUNT 48 |
| 22 | #define RT2560_ATIM_RING_COUNT 4 |
| 23 | #define RT2560_PRIO_RING_COUNT 16 |
| 24 | #define RT2560_BEACON_RING_COUNT 1 |
| 25 | #define RT2560_RX_RING_COUNT 32 |
| 26 | |
| 27 | #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc)) |
| 28 | #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc)) |
| 29 | |
| 30 | #define RT2560_MAX_SCATTER 1 |
| 31 | |
| 32 | /* |
| 33 | * Control and status registers. |
| 34 | */ |
| 35 | #define RT2560_CSR0 0x0000 /* ASIC version number */ |
| 36 | #define RT2560_CSR1 0x0004 /* System control */ |
| 37 | #define RT2560_CSR3 0x000c /* STA MAC address 0 */ |
| 38 | #define RT2560_CSR4 0x0010 /* STA MAC address 1 */ |
| 39 | #define RT2560_CSR5 0x0014 /* BSSID 0 */ |
| 40 | #define RT2560_CSR6 0x0018 /* BSSID 1 */ |
| 41 | #define RT2560_CSR7 0x001c /* Interrupt source */ |
| 42 | #define RT2560_CSR8 0x0020 /* Interrupt mask */ |
| 43 | #define RT2560_CSR9 0x0024 /* Maximum frame length */ |
| 44 | #define RT2560_SECCSR0 0x0028 /* WEP control */ |
| 45 | #define RT2560_CSR11 0x002c /* Back-off control */ |
| 46 | #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */ |
| 47 | #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */ |
| 48 | #define RT2560_CSR14 0x0038 /* Synchronization control */ |
| 49 | #define RT2560_CSR15 0x003c /* Synchronization status */ |
| 50 | #define RT2560_CSR16 0x0040 /* TSF timer 0 */ |
| 51 | #define RT2560_CSR17 0x0044 /* TSF timer 1 */ |
| 52 | #define RT2560_CSR18 0x0048 /* IFS timer 0 */ |
| 53 | #define RT2560_CSR19 0x004c /* IFS timer 1 */ |
| 54 | #define RT2560_CSR20 0x0050 /* WAKEUP timer */ |
| 55 | #define RT2560_CSR21 0x0054 /* EEPROM control */ |
| 56 | #define RT2560_CSR22 0x0058 /* CFP control */ |
| 57 | #define RT2560_TXCSR0 0x0060 /* TX control */ |
| 58 | #define RT2560_TXCSR1 0x0064 /* TX configuration */ |
| 59 | #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */ |
| 60 | #define RT2560_TXCSR3 0x006c /* TX ring base address */ |
| 61 | #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */ |
| 62 | #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */ |
| 63 | #define RT2560_TXCSR6 0x0078 /* Beacon base address */ |
| 64 | #define RT2560_TXCSR7 0x007c /* AutoResponder control */ |
| 65 | #define RT2560_RXCSR0 0x0080 /* RX control */ |
| 66 | #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */ |
| 67 | #define RT2560_RXCSR2 0x0088 /* RX ring base address */ |
| 68 | #define RT2560_PCICSR 0x008c /* PCI control */ |
| 69 | #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */ |
| 70 | #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */ |
| 71 | #define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */ |
| 72 | #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */ |
| 73 | #define RT2560_CNT0 0x00a0 /* FCS error counter */ |
| 74 | #define RT2560_CNT1 0x00ac /* PLCP error counter */ |
| 75 | #define RT2560_CNT2 0x00b0 /* Long error counter */ |
| 76 | #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */ |
| 77 | #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */ |
| 78 | #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */ |
| 79 | #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */ |
| 80 | #define RT2560_PSCSR0 0x00c8 /* Power state transition time */ |
| 81 | #define RT2560_PSCSR1 0x00cc /* Power state transition time */ |
| 82 | #define RT2560_PSCSR2 0x00d0 /* Power state transition time */ |
| 83 | #define RT2560_PSCSR3 0x00d4 /* Power state transition time */ |
| 84 | #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */ |
| 85 | #define RT2560_TIMECSR 0x00dc /* Timer control */ |
| 86 | #define RT2560_MACCSR0 0x00e0 /* MAC configuration */ |
| 87 | #define RT2560_MACCSR1 0x00e4 /* MAC configuration */ |
| 88 | #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */ |
| 89 | #define RT2560_BCNCSR 0x00ec /* Beacon interval control */ |
| 90 | #define RT2560_BBPCSR 0x00f0 /* BBP serial control */ |
| 91 | #define RT2560_RFCSR 0x00f4 /* RF serial control */ |
| 92 | #define RT2560_LEDCSR 0x00f8 /* LED control */ |
| 93 | #define RT2560_SECCSR3 0x00fc /* XXX not documented */ |
| 94 | #define RT2560_DMACSR0 0x0100 /* Current RX ring address */ |
| 95 | #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */ |
| 96 | #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */ |
| 97 | #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */ |
| 98 | #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */ |
| 99 | #define RT2560_GPIOCSR 0x0120 /* */ |
| 100 | #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */ |
| 101 | #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */ |
| 102 | #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */ |
| 103 | #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */ |
| 104 | #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */ |
| 105 | #define RT2560_TESTCSR 0x0138 /* Test Mode Select */ |
| 106 | #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */ |
| 107 | #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */ |
| 108 | #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */ |
| 109 | #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */ |
| 110 | #define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */ |
| 111 | #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */ |
| 112 | #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */ |
| 113 | #define RT2560_SECCSR1 0x0158 /* WEP control */ |
| 114 | #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */ |
| 115 | |
| 116 | |
| 117 | /* possible flags for register RXCSR0 */ |
| 118 | #define RT2560_DISABLE_RX (1 << 0) |
| 119 | #define RT2560_DROP_CRC_ERROR (1 << 1) |
| 120 | #define RT2560_DROP_PHY_ERROR (1 << 2) |
| 121 | #define RT2560_DROP_CTL (1 << 3) |
| 122 | #define RT2560_DROP_NOT_TO_ME (1 << 4) |
| 123 | #define RT2560_DROP_TODS (1 << 5) |
| 124 | #define RT2560_DROP_VERSION_ERROR (1 << 6) |
| 125 | |
| 126 | /* possible flags for register CSR1 */ |
| 127 | #define RT2560_RESET_ASIC (1 << 0) |
| 128 | #define RT2560_RESET_BBP (1 << 1) |
| 129 | #define RT2560_HOST_READY (1 << 2) |
| 130 | |
| 131 | /* possible flags for register CSR14 */ |
| 132 | #define RT2560_ENABLE_TSF (1 << 0) |
| 133 | #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) |
| 134 | #define RT2560_ENABLE_TBCN (1 << 3) |
| 135 | #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6) |
| 136 | |
| 137 | /* possible flags for register CSR21 */ |
| 138 | #define RT2560_C (1 << 1) |
| 139 | #define RT2560_S (1 << 2) |
| 140 | #define RT2560_D (1 << 3) |
| 141 | #define RT2560_Q (1 << 4) |
| 142 | #define RT2560_93C46 (1 << 5) |
| 143 | |
| 144 | #define RT2560_SHIFT_D 3 |
| 145 | #define RT2560_SHIFT_Q 4 |
| 146 | |
| 147 | /* possible flags for register TXCSR0 */ |
| 148 | #define RT2560_KICK_TX (1 << 0) |
| 149 | #define RT2560_KICK_ATIM (1 << 1) |
| 150 | #define RT2560_KICK_PRIO (1 << 2) |
| 151 | #define RT2560_ABORT_TX (1 << 3) |
| 152 | |
| 153 | /* possible flags for register SECCSR0 */ |
| 154 | #define RT2560_KICK_DECRYPT (1 << 0) |
| 155 | |
| 156 | /* possible flags for register SECCSR1 */ |
| 157 | #define RT2560_KICK_ENCRYPT (1 << 0) |
| 158 | |
| 159 | /* possible flags for register CSR7 */ |
| 160 | #define RT2560_BEACON_EXPIRE 0x00000001 |
| 161 | #define RT2560_WAKEUP_EXPIRE 0x00000002 |
| 162 | #define RT2560_ATIM_EXPIRE 0x00000004 |
| 163 | #define RT2560_TX_DONE 0x00000008 |
| 164 | #define RT2560_ATIM_DONE 0x00000010 |
| 165 | #define RT2560_PRIO_DONE 0x00000020 |
| 166 | #define RT2560_RX_DONE 0x00000040 |
| 167 | #define RT2560_DECRYPTION_DONE 0x00000080 |
| 168 | #define RT2560_ENCRYPTION_DONE 0x00000100 |
| 169 | |
| 170 | #define RT2560_INTR_MASK \ |
| 171 | (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \ |
| 172 | RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \ |
| 173 | RT2560_ENCRYPTION_DONE)) |
| 174 | |
| 175 | /* Tx descriptor */ |
| 176 | struct rt2560_tx_desc { |
| 177 | uint32_t flags; |
| 178 | #define RT2560_TX_BUSY (1 << 0) |
| 179 | #define RT2560_TX_VALID (1 << 1) |
| 180 | |
| 181 | #define RT2560_TX_RESULT_MASK 0x0000001c |
| 182 | #define RT2560_TX_SUCCESS (0 << 2) |
| 183 | #define RT2560_TX_SUCCESS_RETRY (1 << 2) |
| 184 | #define RT2560_TX_FAIL_RETRY (2 << 2) |
| 185 | #define RT2560_TX_FAIL_INVALID (3 << 2) |
| 186 | #define RT2560_TX_FAIL_OTHER (4 << 2) |
| 187 | |
| 188 | #define RT2560_TX_MORE_FRAG (1 << 8) |
| 189 | #define RT2560_TX_ACK (1 << 9) |
| 190 | #define RT2560_TX_TIMESTAMP (1 << 10) |
| 191 | #define RT2560_TX_OFDM (1 << 11) |
| 192 | #define RT2560_TX_CIPHER_BUSY (1 << 12) |
| 193 | |
| 194 | #define RT2560_TX_IFS_MASK 0x00006000 |
| 195 | #define RT2560_TX_IFS_BACKOFF (0 << 13) |
| 196 | #define RT2560_TX_IFS_SIFS (1 << 13) |
| 197 | #define RT2560_TX_IFS_NEWBACKOFF (2 << 13) |
| 198 | #define RT2560_TX_IFS_NONE (3 << 13) |
| 199 | |
| 200 | #define RT2560_TX_LONG_RETRY (1 << 15) |
| 201 | |
| 202 | #define RT2560_TX_CIPHER_MASK 0xe0000000 |
| 203 | #define RT2560_TX_CIPHER_NONE (0 << 29) |
| 204 | #define RT2560_TX_CIPHER_WEP40 (1 << 29) |
| 205 | #define RT2560_TX_CIPHER_WEP104 (2 << 29) |
| 206 | #define RT2560_TX_CIPHER_TKIP (3 << 29) |
| 207 | #define RT2560_TX_CIPHER_AES (4 << 29) |
| 208 | |
| 209 | uint32_t physaddr; |
| 210 | uint16_t wme; |
| 211 | #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12) |
| 212 | #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8) |
| 213 | #define RT2560_AIFSN(x) (((x) & 0x3) << 6) |
| 214 | #define RT2560_IVOFFSET(x) (((x) & 0x3f)) |
| 215 | |
| 216 | uint16_t reserved1; |
| 217 | uint8_t plcp_signal; |
| 218 | uint8_t plcp_service; |
| 219 | #define RT2560_PLCP_LENGEXT 0x80 |
| 220 | |
| 221 | uint8_t plcp_length_lo; |
| 222 | uint8_t plcp_length_hi; |
| 223 | uint32_t iv; |
| 224 | uint32_t eiv; |
| 225 | uint8_t key[IEEE80211_KEYBUF_SIZE]; |
| 226 | uint32_t reserved2[2]; |
| 227 | } __packed; |
| 228 | |
| 229 | /* Rx descriptor */ |
| 230 | struct rt2560_rx_desc { |
| 231 | uint32_t flags; |
| 232 | #define RT2560_RX_BUSY (1 << 0) |
| 233 | #define RT2560_RX_CRC_ERROR (1 << 5) |
| 234 | #define RT2560_RX_OFDM (1 << 6) |
| 235 | #define RT2560_RX_PHY_ERROR (1 << 7) |
| 236 | #define RT2560_RX_CIPHER_BUSY (1 << 8) |
| 237 | #define RT2560_RX_ICV_ERROR (1 << 9) |
| 238 | |
| 239 | #define RT2560_RX_CIPHER_MASK 0xe0000000 |
| 240 | #define RT2560_RX_CIPHER_NONE (0 << 29) |
| 241 | #define RT2560_RX_CIPHER_WEP40 (1 << 29) |
| 242 | #define RT2560_RX_CIPHER_WEP104 (2 << 29) |
| 243 | #define RT2560_RX_CIPHER_TKIP (3 << 29) |
| 244 | #define RT2560_RX_CIPHER_AES (4 << 29) |
| 245 | |
| 246 | uint32_t physaddr; |
| 247 | uint8_t rate; |
| 248 | uint8_t ; |
| 249 | uint8_t ta[IEEE80211_ADDR_LEN]; |
| 250 | uint32_t iv; |
| 251 | uint32_t eiv; |
| 252 | uint8_t key[IEEE80211_KEYBUF_SIZE]; |
| 253 | uint32_t reserved[2]; |
| 254 | } __packed; |
| 255 | |
| 256 | #define RT2560_RF1 0 |
| 257 | #define RT2560_RF2 2 |
| 258 | #define RT2560_RF3 1 |
| 259 | #define RT2560_RF4 3 |
| 260 | |
| 261 | #define RT2560_RF1_AUTOTUNE 0x08000 |
| 262 | #define RT2560_RF3_AUTOTUNE 0x00040 |
| 263 | |
| 264 | #define RT2560_BBP_BUSY (1 << 15) |
| 265 | #define RT2560_BBP_WRITE (1 << 16) |
| 266 | #define RT2560_RF_20BIT (20 << 24) |
| 267 | #define RT2560_RF_BUSY (1 << 31) |
| 268 | |
| 269 | #define RT2560_RF_2522 0x00 |
| 270 | #define RT2560_RF_2523 0x01 |
| 271 | #define RT2560_RF_2524 0x02 |
| 272 | #define RT2560_RF_2525 0x03 |
| 273 | #define RT2560_RF_2525E 0x04 |
| 274 | #define RT2560_RF_2526 0x05 |
| 275 | /* dual-band RF */ |
| 276 | #define RT2560_RF_5222 0x10 |
| 277 | |
| 278 | #define RT2560_BBP_VERSION 0 |
| 279 | #define RT2560_BBP_TX 2 |
| 280 | #define RT2560_BBP_RX 14 |
| 281 | |
| 282 | #define RT2560_BBP_ANTA 0x00 |
| 283 | #define RT2560_BBP_DIVERSITY 0x01 |
| 284 | #define RT2560_BBP_ANTB 0x02 |
| 285 | #define RT2560_BBP_ANTMASK 0x03 |
| 286 | #define RT2560_BBP_FLIPIQ 0x04 |
| 287 | |
| 288 | #define RT2560_LED_MODE_DEFAULT 0 |
| 289 | #define RT2560_LED_MODE_TXRX_ACTIVITY 1 |
| 290 | #define RT2560_LED_MODE_SINGLE 2 |
| 291 | #define RT2560_LED_MODE_ASUS 3 |
| 292 | |
| 293 | #define RT2560_JAPAN_FILTER 0x8 |
| 294 | |
| 295 | #define RT2560_EEPROM_CONFIG0 16 |
| 296 | #define RT2560_EEPROM_BBP_BASE 19 |
| 297 | #define RT2560_EEPROM_TXPOWER 35 |
| 298 | |
| 299 | #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ |
| 300 | |
| 301 | /* |
| 302 | * control and status registers access macros |
| 303 | */ |
| 304 | #define RAL_READ(sc, reg) \ |
| 305 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
| 306 | |
| 307 | #define RAL_WRITE(sc, reg, val) \ |
| 308 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 309 | |
| 310 | /* |
| 311 | * EEPROM access macro |
| 312 | */ |
| 313 | #define RT2560_EEPROM_CTL(sc, val) do { \ |
| 314 | RAL_WRITE((sc), RT2560_CSR21, (val)); \ |
| 315 | DELAY(RT2560_EEPROM_DELAY); \ |
| 316 | } while (/* CONSTCOND */0) |
| 317 | |