| 1 | /* $NetBSD: ihphyreg.h,v 1.1 2010/11/27 20:15:27 christos Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2010 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 26 | * POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _DEV_MII_IHPHYREG_H_ |
| 30 | #define _DEV_MII_IHPHYREG_H_ |
| 31 | |
| 32 | #include <dev/mii/inbmphyreg.h> |
| 33 | |
| 34 | /* |
| 35 | * Intel 82577LM registers. |
| 36 | */ |
| 37 | |
| 38 | /* PHY Control Register 2 */ |
| 39 | #define IHPHY_MII_ECR2 BME1000_REG(0, 18) |
| 40 | |
| 41 | /* Loopback Control Register */ |
| 42 | #define IHPHY_MII_LCR BME1000_REG(0, 19) |
| 43 | |
| 44 | /* RX Error Counter Register */ |
| 45 | #define IHPHY_MII_RXERR BME1000_REG(0, 20) |
| 46 | |
| 47 | /* Management Interface Register */ |
| 48 | #define IHPHY_MII_MIR BME1000_REG(0, 21) |
| 49 | |
| 50 | /* PHY Configuration Register */ |
| 51 | #define IHPHY_MII_CFG BME1000_REG(0, 22) |
| 52 | #define IHPHY_CFG_TX_CRS 0x8000 /* CRS transmit enable */ |
| 53 | #define IHPHY_CFG_FIFO_DEPTH 0x3000 /* Transmit FIFO depth*/ |
| 54 | #define IHPHY_CFG_DOWN_SHIFT 0x0C00 /* Automatic speed downshift mode */ |
| 55 | #define IHPHY_CFG_ALT_PAGE 0x0080 /* Alternate next page */ |
| 56 | #define IHPHY_CFG_GRP_MDIO 0x0040 /* Group MDIO mode enable */ |
| 57 | #define IHPHY_CFG_TX_CLOCK 0x0020 /* Transmit clock enable */ |
| 58 | |
| 59 | /* PHY Control Register */ |
| 60 | #define IHPHY_MII_ECR BME1000_REG(0, 23) |
| 61 | #define IHPHY_ECR_LNK_EN 0x2000 /* Link enable */ |
| 62 | #define IHPHY_ECR_DOWN_SHIFT 0x1C00 /* Automatic speed downshift attempts */ |
| 63 | #define IHPHY_ECR_LNK_PARTNER 0x0080 /* Link Partner Detected */ |
| 64 | #define IHPHY_ECR_JABBER 0x0040 /* Jabber (10BASE-T) */ |
| 65 | #define IHPHY_ECR_SQE 0x0020 /* Heartbeat (10BASE-T) */ |
| 66 | #define IHPHY_ECR_TP_LOOPBACK 0x0010 /* TP loopback (10BASE-T) */ |
| 67 | #define IHPHY_ECR_PRE_LENGTH 0x000C /* Preamble length (10BASE-T) */ |
| 68 | |
| 69 | /* Interrupt Mask Register */ |
| 70 | #define IHPHY_MII_IMR BME1000_REG(0, 24) |
| 71 | |
| 72 | /* Interrupt Status Register */ |
| 73 | #define IHPHY_MII_ISR BME1000_REG(0, 25) |
| 74 | |
| 75 | /* PHY Status Register */ |
| 76 | #define IHPHY_MII_ESR BME1000_REG(0, 26) |
| 77 | #define IHPHY_ESR_STANDBY 0x8000 /* PHY in standby */ |
| 78 | #define IHPHY_ESR_ANEG_FAULT 0x6000 /* Autonegotation fault status */ |
| 79 | #define IHPHY_ESR_ANEG_STAT 0x1000 /* Autonegotiation status */ |
| 80 | #define IHPHY_ESR_PAIR_SWAP 0x0800 /* Pair swap on pairs A and B */ |
| 81 | #define IHPHY_ESR_POLARITY 0x0400 /* Polarity status */ |
| 82 | #define IHPHY_ESR_SPEED 0x0300 /* Speed status */ |
| 83 | #define IHPHY_ESR_DUPLEX 0x0080 /* Duplex status */ |
| 84 | #define IHPHY_ESR_LINK 0x0040 /* Link status */ |
| 85 | #define IHPHY_ESR_TRANSMIT 0x0020 /* Transmit status */ |
| 86 | #define IHPHY_ESR_RECEIVE 0x0010 /* Receive status */ |
| 87 | #define IHPHY_ESR_COLLISION 0x0008 /* Collision status */ |
| 88 | #define IHPHY_ESR_ANEG_BOTH 0x0004 /* Autonegotiation enabled for both */ |
| 89 | #define IHPHY_ESR_PAUSE 0x0002 /* Link partner has PAUSE */ |
| 90 | #define IHPHY_ESR_ASYM_PAUSE 0x0001 /* Link partner has asymmetric PAUSE */ |
| 91 | |
| 92 | #define IHPHY_SPEED_10 0x0000 |
| 93 | #define IHPHY_SPEED_100 0x0100 |
| 94 | #define IHPHY_SPEED_1000 0x0200 |
| 95 | |
| 96 | /* LED Control Register 1 */ |
| 97 | #define IHPHY_MII_LED1 BME1000_REG(0, 27) |
| 98 | |
| 99 | /* LED Control Register 2 */ |
| 100 | #define IHPHY_MII_LED2 BME1000_REG(0, 28) |
| 101 | |
| 102 | /* LED Control Register 3 */ |
| 103 | #define IHPHY_MII_LED3 BME1000_REG(0, 29) |
| 104 | |
| 105 | /* Diagnostics Control Register */ |
| 106 | #define IHPHY_MII_DCR BME1000_REG(0, 30) |
| 107 | |
| 108 | /* Diagnostics Status Register */ |
| 109 | #define IHPHY_MII_DSR BME1000_REG(0, 31) |
| 110 | |
| 111 | #endif /* _DEV_IHPHY_MIIREG_H_ */ |
| 112 | |