| 1 | /* $NetBSD: nouveau_subdev_pwr_base.c,v 1.4 2015/02/25 22:12:00 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2013 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_pwr_base.c,v 1.4 2015/02/25 22:12:00 riastradh Exp $" ); |
| 29 | |
| 30 | #include <subdev/pwr.h> |
| 31 | #include <subdev/timer.h> |
| 32 | |
| 33 | static int |
| 34 | nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], |
| 35 | u32 process, u32 message, u32 data0, u32 data1) |
| 36 | { |
| 37 | struct nouveau_subdev *subdev = nv_subdev(ppwr); |
| 38 | u32 addr; |
| 39 | |
| 40 | /* wait for a free slot in the fifo */ |
| 41 | addr = nv_rd32(ppwr, 0x10a4a0); |
| 42 | if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8)) |
| 43 | return -EBUSY; |
| 44 | |
| 45 | /* we currently only support a single process at a time waiting |
| 46 | * on a synchronous reply, take the PPWR mutex and tell the |
| 47 | * receive handler what we're waiting for |
| 48 | */ |
| 49 | if (reply) { |
| 50 | mutex_lock(&subdev->mutex); |
| 51 | ppwr->recv.message = message; |
| 52 | ppwr->recv.process = process; |
| 53 | } |
| 54 | |
| 55 | /* acquire data segment access */ |
| 56 | do { |
| 57 | nv_wr32(ppwr, 0x10a580, 0x00000001); |
| 58 | } while (nv_rd32(ppwr, 0x10a580) != 0x00000001); |
| 59 | |
| 60 | /* write the packet */ |
| 61 | nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + |
| 62 | ppwr->send.base)); |
| 63 | nv_wr32(ppwr, 0x10a1c4, process); |
| 64 | nv_wr32(ppwr, 0x10a1c4, message); |
| 65 | nv_wr32(ppwr, 0x10a1c4, data0); |
| 66 | nv_wr32(ppwr, 0x10a1c4, data1); |
| 67 | nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f); |
| 68 | |
| 69 | /* release data segment access */ |
| 70 | nv_wr32(ppwr, 0x10a580, 0x00000000); |
| 71 | |
| 72 | /* wait for reply, if requested */ |
| 73 | if (reply) { |
| 74 | #ifdef __NetBSD__ |
| 75 | int ret; |
| 76 | |
| 77 | DRM_WAIT_NOINTR_UNTIL(ret, &ppwr->recv.wait, &subdev->mutex, |
| 78 | (ppwr->recv.process == 0)); |
| 79 | KASSERT(ret == 0); |
| 80 | #else |
| 81 | wait_event(ppwr->recv.wait, (ppwr->recv.process == 0)); |
| 82 | #endif |
| 83 | reply[0] = ppwr->recv.data[0]; |
| 84 | reply[1] = ppwr->recv.data[1]; |
| 85 | mutex_unlock(&subdev->mutex); |
| 86 | } |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static void |
| 92 | nouveau_pwr_recv(struct work_struct *work) |
| 93 | { |
| 94 | struct nouveau_pwr *ppwr = |
| 95 | container_of(work, struct nouveau_pwr, recv.work); |
| 96 | struct nouveau_subdev *subdev = nv_subdev(ppwr); |
| 97 | u32 process, message, data0, data1; |
| 98 | |
| 99 | /* nothing to do if GET == PUT */ |
| 100 | u32 addr = nv_rd32(ppwr, 0x10a4cc); |
| 101 | if (addr == nv_rd32(ppwr, 0x10a4c8)) |
| 102 | return; |
| 103 | |
| 104 | /* acquire data segment access */ |
| 105 | do { |
| 106 | nv_wr32(ppwr, 0x10a580, 0x00000002); |
| 107 | } while (nv_rd32(ppwr, 0x10a580) != 0x00000002); |
| 108 | |
| 109 | /* read the packet */ |
| 110 | nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + |
| 111 | ppwr->recv.base)); |
| 112 | process = nv_rd32(ppwr, 0x10a1c4); |
| 113 | message = nv_rd32(ppwr, 0x10a1c4); |
| 114 | data0 = nv_rd32(ppwr, 0x10a1c4); |
| 115 | data1 = nv_rd32(ppwr, 0x10a1c4); |
| 116 | nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f); |
| 117 | |
| 118 | /* release data segment access */ |
| 119 | nv_wr32(ppwr, 0x10a580, 0x00000000); |
| 120 | |
| 121 | /* wake process if it's waiting on a synchronous reply */ |
| 122 | if (ppwr->recv.process) { |
| 123 | mutex_lock(&subdev->mutex); |
| 124 | if (process == ppwr->recv.process && |
| 125 | message == ppwr->recv.message) { |
| 126 | ppwr->recv.data[0] = data0; |
| 127 | ppwr->recv.data[1] = data1; |
| 128 | ppwr->recv.process = 0; |
| 129 | #ifdef __NetBSD__ |
| 130 | DRM_WAKEUP_ONE(&ppwr->recv.wait, &subdev->mutex); |
| 131 | #else |
| 132 | wake_up(&ppwr->recv.wait); |
| 133 | #endif |
| 134 | return; |
| 135 | } |
| 136 | mutex_unlock(&subdev->mutex); |
| 137 | } |
| 138 | |
| 139 | /* right now there's no other expected responses from the engine, |
| 140 | * so assume that any unexpected message is an error. |
| 141 | */ |
| 142 | nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n" , |
| 143 | (char)((process & 0x000000ff) >> 0), |
| 144 | (char)((process & 0x0000ff00) >> 8), |
| 145 | (char)((process & 0x00ff0000) >> 16), |
| 146 | (char)((process & 0xff000000) >> 24), |
| 147 | process, message, data0, data1); |
| 148 | } |
| 149 | |
| 150 | static void |
| 151 | nouveau_pwr_intr(struct nouveau_subdev *subdev) |
| 152 | { |
| 153 | struct nouveau_pwr *ppwr = (void *)subdev; |
| 154 | u32 disp = nv_rd32(ppwr, 0x10a01c); |
| 155 | u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16); |
| 156 | |
| 157 | if (intr & 0x00000020) { |
| 158 | u32 stat = nv_rd32(ppwr, 0x10a16c); |
| 159 | if (stat & 0x80000000) { |
| 160 | nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n" , |
| 161 | stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168)); |
| 162 | nv_wr32(ppwr, 0x10a16c, 0x00000000); |
| 163 | intr &= ~0x00000020; |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | if (intr & 0x00000040) { |
| 168 | schedule_work(&ppwr->recv.work); |
| 169 | nv_wr32(ppwr, 0x10a004, 0x00000040); |
| 170 | intr &= ~0x00000040; |
| 171 | } |
| 172 | |
| 173 | if (intr & 0x00000080) { |
| 174 | nv_info(ppwr, "wr32 0x%06x 0x%08x\n" , nv_rd32(ppwr, 0x10a7a0), |
| 175 | nv_rd32(ppwr, 0x10a7a4)); |
| 176 | nv_wr32(ppwr, 0x10a004, 0x00000080); |
| 177 | intr &= ~0x00000080; |
| 178 | } |
| 179 | |
| 180 | if (intr) { |
| 181 | nv_error(ppwr, "intr 0x%08x\n" , intr); |
| 182 | nv_wr32(ppwr, 0x10a004, intr); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | int |
| 187 | _nouveau_pwr_fini(struct nouveau_object *object, bool suspend) |
| 188 | { |
| 189 | struct nouveau_pwr *ppwr = (void *)object; |
| 190 | |
| 191 | nv_wr32(ppwr, 0x10a014, 0x00000060); |
| 192 | flush_work(&ppwr->recv.work); |
| 193 | |
| 194 | return nouveau_subdev_fini(&ppwr->base, suspend); |
| 195 | } |
| 196 | |
| 197 | int |
| 198 | _nouveau_pwr_init(struct nouveau_object *object) |
| 199 | { |
| 200 | struct nouveau_pwr *ppwr = (void *)object; |
| 201 | int ret, i; |
| 202 | |
| 203 | ret = nouveau_subdev_init(&ppwr->base); |
| 204 | if (ret) |
| 205 | return ret; |
| 206 | |
| 207 | nv_subdev(ppwr)->intr = nouveau_pwr_intr; |
| 208 | ppwr->message = nouveau_pwr_send; |
| 209 | |
| 210 | /* prevent previous ucode from running, wait for idle, reset */ |
| 211 | nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ |
| 212 | nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000); |
| 213 | nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000); |
| 214 | nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000); |
| 215 | |
| 216 | /* upload data segment */ |
| 217 | nv_wr32(ppwr, 0x10a1c0, 0x01000000); |
| 218 | for (i = 0; i < ppwr->data.size / 4; i++) |
| 219 | nv_wr32(ppwr, 0x10a1c4, ppwr->data.data[i]); |
| 220 | |
| 221 | /* upload code segment */ |
| 222 | nv_wr32(ppwr, 0x10a180, 0x01000000); |
| 223 | for (i = 0; i < ppwr->code.size / 4; i++) { |
| 224 | if ((i & 0x3f) == 0) |
| 225 | nv_wr32(ppwr, 0x10a188, i >> 6); |
| 226 | nv_wr32(ppwr, 0x10a184, ppwr->code.data[i]); |
| 227 | } |
| 228 | |
| 229 | /* start it running */ |
| 230 | nv_wr32(ppwr, 0x10a10c, 0x00000000); |
| 231 | nv_wr32(ppwr, 0x10a104, 0x00000000); |
| 232 | nv_wr32(ppwr, 0x10a100, 0x00000002); |
| 233 | |
| 234 | /* wait for valid host->pwr ring configuration */ |
| 235 | if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000)) |
| 236 | return -EBUSY; |
| 237 | ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff; |
| 238 | ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16; |
| 239 | |
| 240 | /* wait for valid pwr->host ring configuration */ |
| 241 | if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000)) |
| 242 | return -EBUSY; |
| 243 | ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff; |
| 244 | ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16; |
| 245 | |
| 246 | nv_wr32(ppwr, 0x10a010, 0x000000e0); |
| 247 | return 0; |
| 248 | } |
| 249 | |
| 250 | int |
| 251 | nouveau_pwr_create_(struct nouveau_object *parent, |
| 252 | struct nouveau_object *engine, |
| 253 | struct nouveau_oclass *oclass, int length, void **pobject) |
| 254 | { |
| 255 | struct nouveau_pwr *ppwr; |
| 256 | int ret; |
| 257 | |
| 258 | ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR" , |
| 259 | "pwr" , length, pobject); |
| 260 | ppwr = *pobject; |
| 261 | if (ret) |
| 262 | return ret; |
| 263 | |
| 264 | INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv); |
| 265 | #ifdef __NetBSD__ |
| 266 | DRM_INIT_WAITQUEUE(&ppwr->recv.wait, "nvppwr" ); |
| 267 | #else |
| 268 | init_waitqueue_head(&ppwr->recv.wait); |
| 269 | #endif |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | #ifdef __NetBSD__ |
| 274 | void |
| 275 | _nouveau_pwr_dtor(struct nouveau_object *object) |
| 276 | { |
| 277 | struct nouveau_pwr *ppwr = (void *)object; |
| 278 | |
| 279 | DRM_DESTROY_WAITQUEUE(&ppwr->recv.wait); |
| 280 | |
| 281 | _nouveau_subdev_dtor(object); |
| 282 | } |
| 283 | #endif |
| 284 | |