| 1 | /* $NetBSD: cs4281reg.h,v 1.6 2005/12/11 12:22:48 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by Tatoku Ogaito |
| 17 | * for the NetBSD Project. |
| 18 | * 4. The name of the author may not be used to endorse or promote products |
| 19 | * derived from this software without specific prior written permission |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 31 | */ |
| 32 | |
| 33 | |
| 34 | #define CS4281_BA0_SIZE |
| 35 | #define CS4281_BA1_SIZE 0x10000 |
| 36 | #define CS4281_BUFFER_SIZE 0x10000 |
| 37 | |
| 38 | /* Base Address 0 */ |
| 39 | |
| 40 | /* Interrupt Reporting Registers */ |
| 41 | #define CS4281_HISR 0x000 /* Host Interrupt Status Register*/ |
| 42 | #define HISR_INTENA 0x80000000 |
| 43 | #define HISR_MIDI 0x00400000 |
| 44 | #define HISR_FIFOI 0x00100000 |
| 45 | #define HISR_DMAI 0x00040000 |
| 46 | #define HISR_FIFO3 0x00008000 |
| 47 | #define HISR_FIFO2 0x00004000 |
| 48 | #define HISR_FIFO1 0x00002000 |
| 49 | #define HISR_FIFO0 0x00001000 |
| 50 | #define HISR_DMA3 0x00000800 |
| 51 | #define HISR_DMA2 0x00000400 |
| 52 | #define HISR_DMA1 0x00000200 |
| 53 | #define HISR_DMA0 0x00000100 |
| 54 | #define HISR_GPPI 0x00000020 |
| 55 | #define HISR_GPSI 0x00000010 |
| 56 | #define HISR_GP3I 0x00000008 |
| 57 | #define HISR_GP1I 0x00000004 |
| 58 | #define HISR_VUPI 0x00000002 |
| 59 | #define HISR_VDNI 0x00000001 |
| 60 | |
| 61 | #define CS4281_HICR 0x008 /* Host Interrupt Control Register */ |
| 62 | #define HICR_CHGM 0x00000002 |
| 63 | #define HICR_IEV 0x00000001 |
| 64 | |
| 65 | #define CS4281_HIMR 0x00C /* Host Interrupt Mask Register */ |
| 66 | #define HIMR_MIDIM 0x00400000 |
| 67 | #define HIMR_FIFOIM 0x00100000 |
| 68 | #define HIMR_DMAIM 0x00040000 |
| 69 | #define HIMR_F3IM 0x00008000 |
| 70 | #define HIMR_F2IM 0x00004000 |
| 71 | #define HIMR_F1IM 0x00002000 |
| 72 | #define HIMR_F0IM 0x00001000 |
| 73 | #define HIMR_D3IM 0x00000800 |
| 74 | #define HIMR_D2IM 0x00000400 |
| 75 | #define HIMR_D1IM 0x00000200 |
| 76 | #define HIMR_D0IM 0x00000100 |
| 77 | #define HIMR_GPPIM 0x00000020 |
| 78 | #define HIMR_GPSIM 0x00000010 |
| 79 | #define HIMR_GP3IM 0x00000008 |
| 80 | #define HIMR_GP1IM 0x00000004 |
| 81 | #define HIMR_VUPIM 0x00000002 |
| 82 | #define HIMR_VDNIM 0x00000001 |
| 83 | |
| 84 | #define CS4281_IIER 0x010 /* ISA Interrupt Enable Register */ |
| 85 | |
| 86 | #define CS4281_HDSR0 0x0F0 /* Host DMA Engine 0 Status Register */ |
| 87 | #define CS4281_HDSR1 0x0F4 /* Host DMA Engine 1 Status Register */ |
| 88 | #define CS4281_HDSR2 0x0F8 /* Host DMA Engine 2 Status Register */ |
| 89 | #define CS4281_HDSR3 0x0FC /* Host DMA Engine 3 Status Register */ |
| 90 | #define CS4281_DCA0 0x110 /* DMA Engine 0 Current Address Register */ |
| 91 | #define CS4281_DCC0 0x114 /* DMA Engine 0 Current Count Register */ |
| 92 | #define CS4281_DBA0 0x118 /* DMA Engine 0 Base Address Register */ |
| 93 | #define CS4281_DBC0 0x11C /* DMA Engine 0 Base Count Register */ |
| 94 | #define CS4281_DCA1 0x120 /* DMA Engine 1 Current Address Register */ |
| 95 | #define CS4281_DCC1 0x124 /* DMA Engine 1 Current Count Register */ |
| 96 | #define CS4281_DBA1 0x128 /* DMA Engine 1 Base Address Register */ |
| 97 | #define CS4281_DBC1 0x12C /* DMA Engine 1 Base Count Register */ |
| 98 | #define CS4281_DCA2 0x130 /* DMA Engine 2 Current Address Register */ |
| 99 | #define CS4281_DCC2 0x134 /* DMA Engine 2 Current Count Register */ |
| 100 | #define CS4281_DBA2 0x138 /* DMA Engine 2 Base Address Register */ |
| 101 | #define CS4281_DBC2 0x13C /* DMA Engine 2 Base Count Register */ |
| 102 | #define CS4281_DCA3 0x140 /* DMA Engine 3 Current Address Register */ |
| 103 | #define CS4281_DCC3 0x144 /* DMA Engine 3 Current Count Register */ |
| 104 | #define CS4281_DBA3 0x148 /* DMA Engine 3 Base Address Register */ |
| 105 | #define CS4281_DBC3 0x14C /* DMA Engine 3 Base Count Register */ |
| 106 | #define CS4281_DMR0 0x150 /* DMA Engine 0 Mode Register */ |
| 107 | #define CS4281_DCR0 0x154 /* DMA Engine 0 Command Register */ |
| 108 | #define CS4281_DMR1 0x158 /* DMA Engine 1 Mode Register */ |
| 109 | #define CS4281_DCR1 0x15C /* DMA Engine 1 Command Register */ |
| 110 | #define CS4281_DMR2 0x160 /* DMA Engine 2 Mode Register */ |
| 111 | #define CS4281_DCR2 0x164 /* DMA Engine 2 Command Register */ |
| 112 | #define CS4281_DMR3 0x168 /* DMA Engine 3 Mode Register */ |
| 113 | #define CS4281_DCR3 0x16C /* DMA Engine 3 Command Register */ |
| 114 | /* DMRn common bit description*/ |
| 115 | #define DMRn_DMA 0x20000000 |
| 116 | #define DMRn_POLL 0x10000000 |
| 117 | #define DMRn_TBC 0x02000000 |
| 118 | #define DMRn_CBC 0x01000000 |
| 119 | #define DMRn_SWAPC 0x00400000 |
| 120 | #define DMRn_SIZE20 0x00100000 |
| 121 | #define DMRn_USIGN 0x00080000 |
| 122 | #define DMRn_BEND 0x00040000 |
| 123 | #define DMRn_MONO 0x00020000 |
| 124 | #define DMRn_SIZE8 0x00010000 |
| 125 | #define DMRn_FMTMSK ( DMRn_SWAPC | DMRn_SIZE20 | DMRn_USIGN | DMRn_BEND | DMRn_MONO | DMRn_SIZE8 ) |
| 126 | #define DMRn_TYPE1 0x00000080 |
| 127 | #define DMRn_TYPE0 0x00000040 |
| 128 | #define DMRn_DEC 0x00000020 |
| 129 | #define DMRn_AUTO 0x00000010 |
| 130 | #define DMRn_TR_MASK 0x0000000c |
| 131 | #define DMRn_TR_READ 0x00000008 |
| 132 | #define DMRn_TR_WRITE 0x00000004 |
| 133 | /* DCRn common bit description*/ |
| 134 | #define DCRn_HTCIE 0x00020000 /* Half Terminal Count Interrupt Enable */ |
| 135 | #define DCRn_TCIE 0x00010000 /* Terminal Count Interrupt Enable */ |
| 136 | #define DCRn_MSK 0x00000001 |
| 137 | |
| 138 | #define CS4281_FCR0 0x180 /* FIFO Control Register 0 */ |
| 139 | #define CS4281_FCR1 0x184 /* FIFO Control Register 1 */ |
| 140 | #define CS4281_FCR2 0x188 /* FIFO Control Register 2 */ |
| 141 | #define CS4281_FCR3 0x18C /* FIFO Control Register 3 */ |
| 142 | #define FCRn_FEN 0x80000000 |
| 143 | #define FCRn_DACZ 0x40000000 |
| 144 | #define FCRn_PSH 0x20000000 |
| 145 | |
| 146 | #define CS4281_FPDR0 0x190 /* FIFO Polled Data Register 0 */ |
| 147 | #define CS4281_FPDR1 0x194 /* FIFO Polled Data Register 1 */ |
| 148 | #define CS4281_FPDR2 0x198 /* FIFO Polled Data Register 2 */ |
| 149 | #define CS4281_FPDR3 0x19C /* FIFO Polled Data Register 3 */ |
| 150 | #define CS4281_FCHS 0x20C /* FIFO Channel Status */ |
| 151 | #define CS4281_FSIC0 0x210 /* FIFO Status and Interrupt Control Register 0 */ |
| 152 | #define CS4281_FSIC1 0x214 /* FIFO Status and Interrupt Control Register 1 */ |
| 153 | #define CS4281_FSIC2 0x218 /* FIFO Status and Interrupt Control Register 2 */ |
| 154 | #define CS4281_FSIC3 0x21C /* FIFO Status and Interrupt Control Register 3 */ |
| 155 | |
| 156 | #if 0 |
| 157 | 300h - 340h /* PCI Configuration Space Echo, offsets 00h - 42h, RO */ |
| 158 | #endif |
| 159 | #define CS4281_PCICFG00 0x300 |
| 160 | #define CS4281_PCICFG04 0x304 |
| 161 | |
| 162 | #define CS4281_PMCS 0x344 /* Power Management Control/Status */ |
| 163 | #define CS4281_CWPR 0x3E0 /* Configuration Write Protect Register */ |
| 164 | #define CS4281_EPPMC 0x3E4 /* Extended PCI Power Management Control */ |
| 165 | #define EPPMC_FPDN (0x1 << 14) |
| 166 | #define CS4281_GPIOR 0x3E8 /* GPIO Pin Interface Register */ |
| 167 | #define CS4281_SPMC 0x3EC /* Serial Port Power Management Control (& ASDIN2 enable) */ |
| 168 | #define SPMC_RSTN 0x00000001 |
| 169 | #define SPMC_ASYN 0x00000002 |
| 170 | #define SPMC_WUP1 0x00000004 |
| 171 | #define SPMC_WUP2 0x00000008 |
| 172 | #define SPMC_ASDO 0x00000080 |
| 173 | #define SPMC_ASDI2E 0x00000100 |
| 174 | #define SPMC_EESPD 0x00000200 |
| 175 | #define SPMC_GISPEN 0x00000400 |
| 176 | #define SPMC_GIPPEN 0x00008000 |
| 177 | #define CS4281_CFLR 0x3F0 /* Configuration Load Register (EEPROM or BIOS) */ |
| 178 | #define CS4281_IISR 0x3F4 /* ISA Interrupt Select Register */ |
| 179 | #define CS4281_TMS 0x3F8 /* Test Register - Reserved */ |
| 180 | |
| 181 | #define CS4281_SSVID 0x3FC /* Subsystem ID register (read-only version at 32Ch) */ |
| 182 | |
| 183 | #define CS4281_CLKCR1 0x400 /* Clock Control Register 1 */ |
| 184 | #define CLKCR1_DLLSS0 0x00000004 |
| 185 | #define CLKCR1_DLLSS1 0x00000008 |
| 186 | #define CLKCR1_DLLP 0x00000010 |
| 187 | #define CLKCR1_SWCE 0x00000020 |
| 188 | #define CLKCR1_DLLOS 0x00000040 |
| 189 | #define CLKCR1_CKRA 0x00010000 |
| 190 | #define CLKCR1_CKRN 0x00020000 |
| 191 | #define CLKCR1_DLLRDY 0x01000000 |
| 192 | #define CLKCR1_CLKON 0x02000000 |
| 193 | |
| 194 | #define CS4281_FRR 0x410 /* Feature Reporting Register */ |
| 195 | #define CS4281_SLT12O 0x41C /* Slot 12 GPIO Output Register for AC Link */ |
| 196 | |
| 197 | #define CS4281_SERMC 0x420 /* Serial Port Master Control Register */ |
| 198 | #define SERMC_MSPE 0x00000001 |
| 199 | #define SERMC_PTCMASK 0x0000000E |
| 200 | #define SERMC_PTCAC97 0x00000002 |
| 201 | #define SERMC_PLB 0x00000100 |
| 202 | #define SERMC_PXLB 0x00000200 |
| 203 | #define SERMC_TCID0 0x00010000 |
| 204 | #define SERMC_TICD1 0x00020000 |
| 205 | #define SERMC_LOVF 0x00080000 |
| 206 | #define SERMC_SLB 0x00100000 |
| 207 | #define SERMC_SXLB 0x00200000 |
| 208 | #define SERMC_ODSEN1 0x01000000 |
| 209 | #define SERMC_ODSEN2 0x02000000 |
| 210 | #define SERMC_FCRN 0x08000000 |
| 211 | #define CS4281_SERC1 0x428 /* Serial Port Configuration Register 1 - RO */ |
| 212 | #define CS4281_SERC2 0x42C /* Serial Port Configuration Register 2 - RO */ |
| 213 | |
| 214 | #define CS4281_SLT12M 0x45C /* Slot 12 Monitor Register for Primary AC Link */ |
| 215 | |
| 216 | /* |
| 217 | * AC97 Registers are moved to cs428xreg.h since |
| 218 | * they are common for CS4280 and CS4281 |
| 219 | */ |
| 220 | |
| 221 | #define CS4281_JSPT 0x480 /* Joystick Poll/Trigger Register */ |
| 222 | #define CS4281_JSCTL 0x484 /* Joystick Control Register */ |
| 223 | #define CS4281_MIDCR 0x490 /* MIDI Control Register */ |
| 224 | #define CS4281_MIDCMD 0x494 /* MIDI Command Register - WO */ |
| 225 | #define CS4281_MIDSR 0x494 /* MIDI Status Register - RO */ |
| 226 | #define CS4281_MIDWP 0x498 /* MIDI Write Port */ |
| 227 | #define CS4281_MIDRP 0x49C /* MIDI Read Port - RO */ |
| 228 | #define CS4281_AODSD1 0x4A8 /* AC `97 On-Demand Slot Disable for primary link - RO */ |
| 229 | #define CS4281_AODSD2 0x4AC /* AC `97 On-Demand Slot Disable for secondary link - RO */ |
| 230 | #define CS4281_CFGI 0x4B0 /* Configuration Interface Register (EEPROM interface) */ |
| 231 | #define CS4281_SLT12M2 0x4DC /* Slot 12 Monitor Register 2 for Secondary AC Link */ |
| 232 | #define CS4281_ACSTS2 0x4E4 /* AC 97 Status Register 2 */ |
| 233 | #define ACSTS2_CRDY2 0x00000001 |
| 234 | #define ACSTS2_BSYS2 0x00000002 |
| 235 | #define CS4281_ACISV2 0x4F4 /* AC 97 Input Slot Valid Register 2 */ |
| 236 | #define CS4281_ACSAD2 0x4F8 /* AC 97 Status Address Register 2 */ |
| 237 | #define CS4281_ACSDA2 0x4FC /* AC 97 Status Data Register 2 */ |
| 238 | #define CS4281_FMSR 0x730 /* FM Synthesis Status Register - RO */ |
| 239 | #define CS4281_B0AP 0x730 /* FM Bank 0 Address Port - WO */ |
| 240 | #define CS4281_FMDP 0x734 /* FM Data Port */ |
| 241 | #define CS4281_B1AP 0x738 /* FM Bank 1 Address Port */ |
| 242 | #define CS4281_B1DP 0x73C /* FM Bank 1 Data Port */ |
| 243 | #define CS4281_SSPM 0x740 /* Sound System Power Management */ |
| 244 | #define SSPM_ALL 0x0000007E |
| 245 | #define SSPM_MIXEN 0x00000040 /* p167 */ |
| 246 | #define SSPM_CSRCEN 0x00000020 |
| 247 | #define SSPM_PSRCEN 0x00000010 |
| 248 | #define SSPM_JSEN 0x00000008 |
| 249 | #define SSPM_ACLEN 0x00000004 |
| 250 | #define SSPM_FMEN 0x00000002 |
| 251 | |
| 252 | #define CS4281_DACSR 0x744 /* DAC Sample Rate - Playback SRC */ |
| 253 | #define CS4281_ADCSR 0x748 /* ADC Sample Rate - Capture SRC */ |
| 254 | #define CS4281_SSCR 0x74C /* Sound System Control Register */ |
| 255 | #define SSCR_HVS1 0x00800000 /* Hardware Volume step by 1 */ |
| 256 | #define SSCR_MVCS 0x00080000 /* Master Volume Codec Select */ |
| 257 | #define SSCR_MVLD 0x00040000 /* Master Volume Line Out Disable */ |
| 258 | #define SSCR_MVAD 0x00020000 /* Master Volume Alternate Out Disable */ |
| 259 | #define SSCR_MVMD 0x00010000 /* Master Volume Mono Out Disable */ |
| 260 | #define SSCR_XLPSRC 0x00000100 /* External SRC loopback mode */ |
| 261 | #define SSCR_LPSRC 0x00000080 /* SRC loopback mode */ |
| 262 | #define SSCR_CDTX 0x00000020 /* CD Transfer Data */ |
| 263 | #define SSCR_HVC 0x00000008 /* Hardware Volume Control Enable */ |
| 264 | #define CS4281_FMLVC 0x754 /* FM Synthesis Left Volume Control */ |
| 265 | #define CS4281_FMRVC 0x758 /* FM Synthesis Right Volume Control */ |
| 266 | #define CS4281_SRCSA 0x75C /* SRC Slot Assignments */ |
| 267 | #define CS4281_PPLVC 0x760 /* PCM Playback Left Volume Control */ |
| 268 | #define CS4281_PPRVC 0x764 /* PCM Playback Right Volume Control */ |
| 269 | |
| 270 | /* Base Address 1 Direct Memory Map */ |
| 271 | |
| 272 | #if 0 |
| 273 | 0000h - 03FFh FIFO RAM Audio Sample RAM Memory Block - FIFOs |
| 274 | Logical Size: 256 x 32 bits (1 kbytes stereo double words) |
| 275 | 0400h - D51Fh Reserved Reserved internal memory |
| 276 | D600h - FFFFh Reserved Reserved for future use |
| 277 | #endif |
| 278 | |
| 279 | /* for AC97_REG_POWER */ |
| 280 | #define CS4281_POWER_DOWN_ALL 0x7f0f |
| 281 | |