| 1 | /* $NetBSD: nouveau_engine_xtensa.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2013 Ilia Mirkin |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include <sys/cdefs.h> |
| 26 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_xtensa.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $" ); |
| 27 | |
| 28 | #include <engine/xtensa.h> |
| 29 | |
| 30 | u32 |
| 31 | _nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr) |
| 32 | { |
| 33 | struct nouveau_xtensa *xtensa = (void *)object; |
| 34 | return nv_rd32(xtensa, xtensa->addr + addr); |
| 35 | } |
| 36 | |
| 37 | void |
| 38 | _nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data) |
| 39 | { |
| 40 | struct nouveau_xtensa *xtensa = (void *)object; |
| 41 | nv_wr32(xtensa, xtensa->addr + addr, data); |
| 42 | } |
| 43 | |
| 44 | int |
| 45 | _nouveau_xtensa_engctx_ctor(struct nouveau_object *parent, |
| 46 | struct nouveau_object *engine, |
| 47 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 48 | struct nouveau_object **pobject) |
| 49 | { |
| 50 | struct nouveau_engctx *engctx; |
| 51 | int ret; |
| 52 | |
| 53 | ret = nouveau_engctx_create(parent, engine, oclass, NULL, |
| 54 | 0x10000, 0x1000, |
| 55 | NVOBJ_FLAG_ZERO_ALLOC, &engctx); |
| 56 | *pobject = nv_object(engctx); |
| 57 | return ret; |
| 58 | } |
| 59 | |
| 60 | void |
| 61 | _nouveau_xtensa_intr(struct nouveau_subdev *subdev) |
| 62 | { |
| 63 | struct nouveau_xtensa *xtensa = (void *)subdev; |
| 64 | u32 unk104 = nv_ro32(xtensa, 0xd04); |
| 65 | u32 intr = nv_ro32(xtensa, 0xc20); |
| 66 | u32 chan = nv_ro32(xtensa, 0xc28); |
| 67 | u32 unk10c = nv_ro32(xtensa, 0xd0c); |
| 68 | |
| 69 | if (intr & 0x10) |
| 70 | nv_warn(xtensa, "Watchdog interrupt, engine hung.\n" ); |
| 71 | nv_wo32(xtensa, 0xc20, intr); |
| 72 | intr = nv_ro32(xtensa, 0xc20); |
| 73 | if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { |
| 74 | nv_debug(xtensa, "Enabling FIFO_CTRL\n" ); |
| 75 | nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val); |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | int |
| 80 | nouveau_xtensa_create_(struct nouveau_object *parent, |
| 81 | struct nouveau_object *engine, |
| 82 | struct nouveau_oclass *oclass, u32 addr, bool enable, |
| 83 | const char *iname, const char *fname, |
| 84 | int length, void **pobject) |
| 85 | { |
| 86 | struct nouveau_xtensa *xtensa; |
| 87 | int ret; |
| 88 | |
| 89 | ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, |
| 90 | fname, length, pobject); |
| 91 | xtensa = *pobject; |
| 92 | if (ret) |
| 93 | return ret; |
| 94 | |
| 95 | nv_subdev(xtensa)->intr = _nouveau_xtensa_intr; |
| 96 | |
| 97 | xtensa->addr = addr; |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | int |
| 103 | _nouveau_xtensa_init(struct nouveau_object *object) |
| 104 | { |
| 105 | struct nouveau_device *device = nv_device(object); |
| 106 | struct nouveau_xtensa *xtensa = (void *)object; |
| 107 | const struct firmware *fw; |
| 108 | char name[32]; |
| 109 | int i, ret; |
| 110 | u32 tmp; |
| 111 | |
| 112 | ret = nouveau_engine_init(&xtensa->base); |
| 113 | if (ret) |
| 114 | return ret; |
| 115 | |
| 116 | if (!xtensa->gpu_fw) { |
| 117 | snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x" , |
| 118 | xtensa->addr >> 12); |
| 119 | |
| 120 | ret = request_firmware(&fw, name, nv_device_base(device)); |
| 121 | if (ret) { |
| 122 | nv_warn(xtensa, "unable to load firmware %s\n" , name); |
| 123 | return ret; |
| 124 | } |
| 125 | |
| 126 | if (fw->size > 0x40000) { |
| 127 | nv_warn(xtensa, "firmware %s too large\n" , name); |
| 128 | release_firmware(fw); |
| 129 | return -EINVAL; |
| 130 | } |
| 131 | |
| 132 | ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, |
| 133 | &xtensa->gpu_fw); |
| 134 | if (ret) { |
| 135 | release_firmware(fw); |
| 136 | return ret; |
| 137 | } |
| 138 | |
| 139 | nv_debug(xtensa, "Loading firmware to address: 0x%" PRIxMAX"\n" , |
| 140 | (uintmax_t)xtensa->gpu_fw->addr); |
| 141 | |
| 142 | for (i = 0; i < fw->size / 4; i++) |
| 143 | nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); |
| 144 | release_firmware(fw); |
| 145 | } |
| 146 | |
| 147 | nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ |
| 148 | nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ |
| 149 | |
| 150 | nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ |
| 151 | nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ |
| 152 | nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ |
| 153 | |
| 154 | nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ |
| 155 | nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ |
| 156 | nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ |
| 157 | |
| 158 | tmp = nv_rd32(xtensa, 0x0); |
| 159 | nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ |
| 160 | |
| 161 | nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ |
| 162 | |
| 163 | nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ |
| 164 | nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | int |
| 170 | _nouveau_xtensa_fini(struct nouveau_object *object, bool suspend) |
| 171 | { |
| 172 | struct nouveau_xtensa *xtensa = (void *)object; |
| 173 | |
| 174 | nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ |
| 175 | nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ |
| 176 | |
| 177 | if (!suspend) |
| 178 | nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw); |
| 179 | |
| 180 | return nouveau_engine_fini(&xtensa->base, suspend); |
| 181 | } |
| 182 | |