| 1 | /* $NetBSD: bhareg.h,v 1.20 2008/04/28 20:23:49 martin Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace |
| 9 | * Simulation Facility, NASA Ames Research Center. |
| 10 | * |
| 11 | * Redistribution and use in source and binary forms, with or without |
| 12 | * modification, are permitted provided that the following conditions |
| 13 | * are met: |
| 14 | * 1. Redistributions of source code must retain the above copyright |
| 15 | * notice, this list of conditions and the following disclaimer. |
| 16 | * 2. Redistributions in binary form must reproduce the above copyright |
| 17 | * notice, this list of conditions and the following disclaimer in the |
| 18 | * documentation and/or other materials provided with the distribution. |
| 19 | * |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 30 | * POSSIBILITY OF SUCH DAMAGE. |
| 31 | */ |
| 32 | |
| 33 | /* |
| 34 | * Originally written by Julian Elischer (julian@tfs.com) |
| 35 | * for TRW Financial Systems for use under the MACH(2.5) operating system. |
| 36 | * |
| 37 | * TRW Financial Systems, in accordance with their agreement with Carnegie |
| 38 | * Mellon University, makes this software available to CMU to distribute |
| 39 | * or use in any manner that they see fit as long as this message is kept with |
| 40 | * the software. For this reason TFS also grants any other persons or |
| 41 | * organisations permission to use or modify this software. |
| 42 | * |
| 43 | * TFS supplies this software to be publicly redistributed |
| 44 | * on the understanding that TFS is not responsible for the correct |
| 45 | * functioning of this software in any circumstances. |
| 46 | */ |
| 47 | |
| 48 | typedef u_int8_t physaddr[4]; |
| 49 | typedef u_int8_t physlen[4]; |
| 50 | #define ltophys _lto4l |
| 51 | #define phystol _4ltol |
| 52 | |
| 53 | /* |
| 54 | * I/O port offsets |
| 55 | */ |
| 56 | #define BHA_CTRL_PORT 0 /* control (wo) */ |
| 57 | #define BHA_STAT_PORT 0 /* status (ro) */ |
| 58 | #define BHA_CMD_PORT 1 /* command (wo) */ |
| 59 | #define BHA_DATA_PORT 1 /* data (ro) */ |
| 60 | #define BHA_INTR_PORT 2 /* interrupt status (ro) */ |
| 61 | #define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */ |
| 62 | |
| 63 | /* |
| 64 | * BHA_CTRL bits |
| 65 | */ |
| 66 | #define BHA_CTRL_HRST 0x80 /* Hardware reset */ |
| 67 | #define BHA_CTRL_SRST 0x40 /* Software reset */ |
| 68 | #define BHA_CTRL_IRST 0x20 /* Interrupt reset */ |
| 69 | #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */ |
| 70 | |
| 71 | /* |
| 72 | * BHA_STAT bits |
| 73 | */ |
| 74 | #define BHA_STAT_STST 0x80 /* Self test in Progress */ |
| 75 | #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ |
| 76 | #define BHA_STAT_INIT 0x20 /* Mbx Init required */ |
| 77 | #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */ |
| 78 | #define BHA_STAT_CDF 0x08 /* cmd/data out port full */ |
| 79 | #define BHA_STAT_DF 0x04 /* Data in port full */ |
| 80 | #define BHA_STAT_INVDCMD 0x01 /* Invalid command */ |
| 81 | |
| 82 | /* |
| 83 | * BHA_CMD opcodes |
| 84 | */ |
| 85 | #define BHA_NOP 0x00 /* No operation */ |
| 86 | #define BHA_MBX_INIT 0x01 /* Mbx initialization */ |
| 87 | #define BHA_START_SCSI 0x02 /* start scsi command */ |
| 88 | #define BHA_EXECUTE_BIOS_CMD 0x03 /* execute BIOS command */ |
| 89 | #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ |
| 90 | #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ |
| 91 | #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ |
| 92 | #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ |
| 93 | #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ |
| 94 | #define BHA_BUS_SPEED_SET 0x09 /* set bus transfer speed */ |
| 95 | #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ |
| 96 | #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */ |
| 97 | #define BHA_TARGET_EN 0x0c /* enable target mode */ |
| 98 | #define BHA_INQUIRE_SETUP 0x0d /* return setup data */ |
| 99 | #define BHA_WRITE_LRAM 0x1a /* write adapter local RAM */ |
| 100 | #define BHA_READ_LRAM 0x1b /* read adapter local RAM */ |
| 101 | #define BHA_WRITE_CHIP_FIFO 0x1c /* write bus master chip FIFO */ |
| 102 | #define BHA_READ_CHIP_FIFO 0x1d /* read bus master chip FIFO */ |
| 103 | #define BHA_ECHO 0x1f /* Echo command byte */ |
| 104 | #define BHA_ADAPTER_DIAGNOSTICS 0x20 /* host adapter diagnostics */ |
| 105 | #define BHA_SET_ADAPTER_OPTIONS 0x21 /* set adapter options */ |
| 106 | #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ |
| 107 | #define BHA_INQUIRE_TARG_DEVS 0x24 /* inquire target devices */ |
| 108 | #define BHA_DISABLE_HAC_INTR 0x25 /* disable host adapter interrupt */ |
| 109 | #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */ |
| 110 | #define BHA_EXECUTE_SCSI_CMD 0x83 /* execute SCSI command */ |
| 111 | #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */ |
| 112 | #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */ |
| 113 | #define BHA_INQUIRE_PCI_INFO 0x86 /* get PCI host adapter information */ |
| 114 | #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */ |
| 115 | #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */ |
| 116 | #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */ |
| 117 | #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) |
| 118 | round robin */ |
| 119 | #define BHA_STORE_LRAM 0x90 /* store host adapter local RAM */ |
| 120 | #define BHA_FETCH_LRAM 0x91 /* fetch host adapter local RAM */ |
| 121 | #define BHA_SAVE_TO_EEPROM 0x92 /* store local RAM data in EEPROM */ |
| 122 | #define BHA_UPLOAD_AUTOSCSI 0x94 /* upload AutoSCSI code */ |
| 123 | #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */ |
| 124 | #define BHA_SET_CCB_FORMAT 0x96 /* set CCB format (legacy/wide lun) */ |
| 125 | #define BHA_WRITE_INQUIRY_BUF 0x9a /* write inquiry buffer */ |
| 126 | #define BHA_READ_INQUIRY_BUF 0x9b /* read inquiry buffer */ |
| 127 | #define BHA_FLASH_UP_DOWNLOAD 0xa7 /* flash upload/downlod */ |
| 128 | #define BHA_READ_SCAM_DATA 0xa8 /* read SCAM data */ |
| 129 | #define BHA_WRITE_SCAM_DATA 0xa9 /* write SCAM data */ |
| 130 | |
| 131 | /* |
| 132 | * BHA_INTR bits |
| 133 | */ |
| 134 | #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */ |
| 135 | #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */ |
| 136 | #define BHA_INTR_HACC 0x04 /* Command complete */ |
| 137 | #define BHA_INTR_MBOA 0x02 /* MBX out empty */ |
| 138 | #define BHA_INTR_MBIF 0x01 /* MBX in full */ |
| 139 | |
| 140 | struct bha_mbx_out { |
| 141 | physaddr ccb_addr; |
| 142 | u_int8_t reserved[3]; |
| 143 | u_int8_t cmd; |
| 144 | }; |
| 145 | |
| 146 | struct bha_mbx_in { |
| 147 | physaddr ccb_addr; |
| 148 | u_int8_t host_stat; |
| 149 | u_int8_t target_stat; |
| 150 | u_int8_t reserved; |
| 151 | u_int8_t comp_stat; |
| 152 | }; |
| 153 | |
| 154 | /* |
| 155 | * mbo.cmd values |
| 156 | */ |
| 157 | #define BHA_MBO_FREE 0x0 /* MBO entry is free */ |
| 158 | #define BHA_MBO_START 0x1 /* MBO activate entry */ |
| 159 | #define BHA_MBO_ABORT 0x2 /* MBO abort entry */ |
| 160 | |
| 161 | /* |
| 162 | * mbi.comp_stat values |
| 163 | */ |
| 164 | #define BHA_MBI_FREE 0x0 /* MBI entry is free */ |
| 165 | #define BHA_MBI_OK 0x1 /* completed without error */ |
| 166 | #define BHA_MBI_ABORT 0x2 /* aborted ccb */ |
| 167 | #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ |
| 168 | #define BHA_MBI_ERROR 0x4 /* Completed with error */ |
| 169 | |
| 170 | #if defined(BIG_DMA) |
| 171 | WARNING...THIS WON'T WORK(won't fit on 1 page) |
| 172 | #if 0 |
| 173 | #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */ |
| 174 | #endif |
| 175 | #define BHA_NSEG 128 |
| 176 | #else |
| 177 | #define BHA_NSEG 33 |
| 178 | #endif /* BIG_DMA */ |
| 179 | |
| 180 | struct bha_scat_gath { |
| 181 | physlen seg_len; |
| 182 | physaddr seg_addr; |
| 183 | }; |
| 184 | |
| 185 | struct bha_ccb { |
| 186 | u_int8_t opcode; |
| 187 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 188 | u_int8_t :3, |
| 189 | data_in :1, |
| 190 | data_out :1, |
| 191 | wide_tag_enable :1, /* Wide Lun CCB format */ |
| 192 | wide_tag_type :2; /* Wide Lun CCB format */ |
| 193 | #else |
| 194 | u_int8_t wide_tag_type :2, /* Wide Lun CCB format */ |
| 195 | wide_tag_enable :1, /* Wide Lun CCB format */ |
| 196 | data_out :1, |
| 197 | data_in :1, |
| 198 | :3; |
| 199 | #endif |
| 200 | u_int8_t scsi_cmd_length; |
| 201 | u_int8_t req_sense_length; |
| 202 | /*------------------------------------longword boundary */ |
| 203 | physlen data_length; |
| 204 | /*------------------------------------longword boundary */ |
| 205 | physaddr data_addr; |
| 206 | /*------------------------------------longword boundary */ |
| 207 | u_int8_t reserved1[2]; |
| 208 | u_int8_t host_stat; |
| 209 | u_int8_t target_stat; |
| 210 | /*------------------------------------longword boundary */ |
| 211 | u_int8_t target; |
| 212 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 213 | u_int8_t lun :5, |
| 214 | tag_enable :1, |
| 215 | tag_type :2; |
| 216 | #else |
| 217 | u_int8_t tag_type :2, |
| 218 | tag_enable :1, |
| 219 | lun :5; |
| 220 | #endif |
| 221 | u_int8_t scsi_cmd[12]; |
| 222 | u_int8_t reserved2[1]; |
| 223 | u_int8_t link_id; |
| 224 | /*------------------------------------longword boundary */ |
| 225 | physaddr link_addr; |
| 226 | /*------------------------------------longword boundary */ |
| 227 | physaddr sense_ptr; |
| 228 | /*-----end of HW fields-----------------------longword boundary */ |
| 229 | struct scsi_sense_data scsi_sense; |
| 230 | /*------------------------------------longword boundary */ |
| 231 | struct bha_scat_gath scat_gath[BHA_NSEG]; |
| 232 | /*------------------------------------longword boundary */ |
| 233 | TAILQ_ENTRY(bha_ccb) chain; |
| 234 | struct bha_ccb *nexthash; |
| 235 | bus_addr_t hashkey; |
| 236 | |
| 237 | struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ |
| 238 | |
| 239 | int flags; |
| 240 | #define CCB_ALLOC 0x01 |
| 241 | #define CCB_ABORT 0x02 |
| 242 | #ifdef BHADIAG |
| 243 | #define CCB_SENDING 0x04 |
| 244 | #endif |
| 245 | int timeout; |
| 246 | |
| 247 | /* |
| 248 | * This DMA map maps the buffer involved in the transfer. |
| 249 | * Its contents are loaded into "scat_gath" above. |
| 250 | */ |
| 251 | bus_dmamap_t dmamap_xfer; |
| 252 | }; |
| 253 | |
| 254 | /* |
| 255 | * opcode fields |
| 256 | */ |
| 257 | #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ |
| 258 | #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */ |
| 259 | #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with S/G */ |
| 260 | #define BHA_INIT_RESID_CCB 0x03 /* SCSI Initiator w/ residual */ |
| 261 | #define BHA_INIT_RESID_SG_CCB 0x04 /* SCSI Initiator w/ residual and S/G */ |
| 262 | #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */ |
| 263 | |
| 264 | /* |
| 265 | * bha_ccb.host_stat values |
| 266 | */ |
| 267 | #define BHA_OK 0x00 /* cmd ok */ |
| 268 | #define BHA_LINK_OK 0x0a /* Link cmd ok */ |
| 269 | #define BHA_LINK_IT 0x0b /* Link cmd ok + int */ |
| 270 | #define BHA_DATA_UNDRN 0x0c /* data underrun error */ |
| 271 | #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */ |
| 272 | #define BHA_OVER_UNDER 0x12 /* Data over/under run */ |
| 273 | #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ |
| 274 | #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ |
| 275 | #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ |
| 276 | #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ |
| 277 | #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */ |
| 278 | #define BHA_INV_TARGET 0x18 /* Invalid target direction */ |
| 279 | #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */ |
| 280 | #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */ |
| 281 | #define BHA_AUTOSENSE_FAILED 0x1b /* auto REQUEST SENSE failed */ |
| 282 | #define BHA_TAGGED_MSG_REJ 0x1c /* tagged queueing message rejected */ |
| 283 | #define BHA_UNSUP_MSG_RECVD 0x1d /* unsupported message received */ |
| 284 | #define BHA_HARDWARE_FAILURE 0x20 /* host adapter hardware failure */ |
| 285 | #define BHA_TARG_IGNORED_ATN 0x21 /* target ignored ATN signal */ |
| 286 | #define BHA_HA_SCSI_BUS_RESET 0x22 /* host adapter asserted RST */ |
| 287 | #define BHA_OTHER_SCSI_BUS_RESET 0x23 /* other device asserted RST */ |
| 288 | #define BHA_BAD_RECONNECT 0x24 /* target reconnected improperly */ |
| 289 | #define BHA_HA_BUS_DEVICE_RESET 0x25 /* host adapter performed BDR */ |
| 290 | #define BHA_ABORT_QUEUE 0x26 /* abort queue generated */ |
| 291 | #define BHA_SOFTWARE_FAILURE 0x27 /* host adapter software failure */ |
| 292 | #define BHA_HARDWARE_WATCHDOG 0x30 /* host adapter watchdog timer fired */ |
| 293 | #define BHA_SCSI_PARITY_ERROR 0x34 /* SCSI parity error detected */ |
| 294 | |
| 295 | struct bha_extended_inquire { |
| 296 | struct { |
| 297 | u_char opcode; |
| 298 | u_char len; |
| 299 | } cmd; |
| 300 | struct { |
| 301 | u_char bus_type; /* Type of bus connected to */ |
| 302 | #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */ |
| 303 | #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */ |
| 304 | #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */ |
| 305 | u_char bios_address; /* Address of adapter BIOS */ |
| 306 | u_short sg_limit; |
| 307 | u_char mbox_count; |
| 308 | u_char mbox_baseaddr[4]; /* packed/unaligned u_int32_t */ |
| 309 | u_char intrflags; |
| 310 | #define BHA_INTR_FASTEISA 0x04 |
| 311 | #define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */ |
| 312 | u_char firmware_level[3]; /* last 3 digits of firmware rev */ |
| 313 | u_char scsi_flags; /* supported SCSI features */ |
| 314 | #define BHA_SCSI_WIDE 0x01 /* host adapter is wide */ |
| 315 | #define BHA_SCSI_DIFFERENTIAL 0x02 /* host adapter is differential */ |
| 316 | #define BHA_SCSI_SCAM 0x04 /* host adapter supports SCAM */ |
| 317 | #define BHA_SCSI_ULTRA 0x08 /* host adapter supports Ultra */ |
| 318 | #define BHA_SCSI_TERMINATION 0x10 /* host adapter supports smart |
| 319 | termination */ |
| 320 | } reply; |
| 321 | }; |
| 322 | |
| 323 | struct bha_config { |
| 324 | struct { |
| 325 | u_char opcode; |
| 326 | } cmd; |
| 327 | struct { |
| 328 | u_char chan; |
| 329 | u_char intr; |
| 330 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 331 | u_char scsi_dev :3, |
| 332 | :5; |
| 333 | #else |
| 334 | u_char :5, |
| 335 | scsi_dev :3; |
| 336 | #endif |
| 337 | } reply; |
| 338 | }; |
| 339 | |
| 340 | struct bha_toggle { |
| 341 | struct { |
| 342 | u_char opcode; |
| 343 | u_char enable; |
| 344 | } cmd; |
| 345 | }; |
| 346 | |
| 347 | struct bha_mailbox { |
| 348 | struct { |
| 349 | u_char opcode; |
| 350 | u_char nmbx; |
| 351 | physaddr addr; |
| 352 | } cmd; |
| 353 | }; |
| 354 | |
| 355 | struct bha_model { |
| 356 | struct { |
| 357 | u_char opcode; |
| 358 | u_char len; |
| 359 | } cmd; |
| 360 | struct { |
| 361 | u_char id[4]; /* i.e bt742a -> '7','4','2','A' */ |
| 362 | u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */ |
| 363 | } reply; |
| 364 | }; |
| 365 | |
| 366 | struct bha_revision { |
| 367 | struct { |
| 368 | u_char opcode; |
| 369 | } cmd; |
| 370 | struct { |
| 371 | u_char board_type; |
| 372 | u_char custom_feature; |
| 373 | char firm_revision; |
| 374 | u_char firm_version; |
| 375 | } reply; |
| 376 | }; |
| 377 | |
| 378 | struct bha_digit { |
| 379 | struct { |
| 380 | u_char opcode; |
| 381 | } cmd; |
| 382 | struct { |
| 383 | u_char digit; |
| 384 | } reply; |
| 385 | }; |
| 386 | |
| 387 | struct bha_devices { |
| 388 | struct { |
| 389 | u_char opcode; |
| 390 | } cmd; |
| 391 | struct { |
| 392 | u_char lun_map[8]; |
| 393 | } reply; |
| 394 | }; |
| 395 | |
| 396 | struct bha_sync { |
| 397 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 398 | u_char offset :4, |
| 399 | period :3, |
| 400 | valid :1; |
| 401 | #else |
| 402 | u_char valid :1, |
| 403 | period :3, |
| 404 | offset :4; |
| 405 | #endif |
| 406 | }; |
| 407 | |
| 408 | struct bha_setup_reply { |
| 409 | #if BYTE_ORDER == LITTLE_ENDIAN |
| 410 | u_int8_t sync_neg :1, |
| 411 | parity :1, |
| 412 | :6; |
| 413 | #else |
| 414 | u_int8_t :6, |
| 415 | parity :1, |
| 416 | sync_neg :1; |
| 417 | #endif |
| 418 | u_int8_t speed; |
| 419 | u_int8_t bus_on; |
| 420 | u_int8_t bus_off; |
| 421 | u_int8_t num_mbx; |
| 422 | u_int8_t mbx[3]; /*XXX */ |
| 423 | /* doesn't make sense with 32bit addresses */ |
| 424 | struct bha_sync sync_low[8]; |
| 425 | u_int8_t low_disc_info; |
| 426 | }; |
| 427 | |
| 428 | /* additional reply data supplied by wide controllers */ |
| 429 | struct bha_setup_reply_wide { |
| 430 | u_int8_t signature; |
| 431 | u_int8_t letter_d; |
| 432 | u_int8_t ha_type; |
| 433 | u_int8_t low_wide_allowed; |
| 434 | u_int8_t low_wide_active; |
| 435 | struct bha_sync sync_high[8]; |
| 436 | u_int8_t high_disc_info; |
| 437 | u_int8_t reserved; |
| 438 | u_int8_t high_wide_allowed; |
| 439 | u_int8_t high_wide_active; |
| 440 | }; |
| 441 | |
| 442 | struct bha_setup { |
| 443 | struct { |
| 444 | u_char opcode; |
| 445 | u_char len; |
| 446 | } cmd; |
| 447 | struct bha_setup_reply reply; |
| 448 | struct bha_setup_reply_wide reply_w; /* for wide controllers */ |
| 449 | }; |
| 450 | |
| 451 | struct bha_period_reply { |
| 452 | u_char period[8]; |
| 453 | }; |
| 454 | |
| 455 | struct bha_period { |
| 456 | struct { |
| 457 | u_char opcode; |
| 458 | u_char len; |
| 459 | } cmd; |
| 460 | struct bha_period_reply reply; |
| 461 | struct bha_period_reply reply_w; /* for wide controllers */ |
| 462 | }; |
| 463 | |
| 464 | struct bha_isadisable { |
| 465 | struct { |
| 466 | u_char opcode; |
| 467 | u_char modifier; |
| 468 | } cmd; |
| 469 | }; |
| 470 | |
| 471 | /* |
| 472 | * bha_isadisable.modifier parameters |
| 473 | */ |
| 474 | #define BHA_IOMODIFY_330 0x00 |
| 475 | #define BHA_IOMODIFY_334 0x01 |
| 476 | #define BHA_IOMODIFY_DISABLE1 0x06 |
| 477 | #define BHA_IOMODIFY_DISABLE2 0x07 |
| 478 | |
| 479 | #define INT9 0x01 |
| 480 | #define INT10 0x02 |
| 481 | #define INT11 0x04 |
| 482 | #define INT12 0x08 |
| 483 | #define INT14 0x20 |
| 484 | #define INT15 0x40 |
| 485 | |
| 486 | #define EISADMA 0x00 |
| 487 | #define CHAN0 0x01 |
| 488 | #define CHAN5 0x20 |
| 489 | #define CHAN6 0x40 |
| 490 | #define CHAN7 0x80 |
| 491 | |