| 1 | /* $NetBSD: com.c,v 1.339 2016/05/27 20:01:49 bouyer Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Charles M. Hannum. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * Copyright (c) 1991 The Regents of the University of California. |
| 34 | * All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * 1. Redistributions of source code must retain the above copyright |
| 40 | * notice, this list of conditions and the following disclaimer. |
| 41 | * 2. Redistributions in binary form must reproduce the above copyright |
| 42 | * notice, this list of conditions and the following disclaimer in the |
| 43 | * documentation and/or other materials provided with the distribution. |
| 44 | * 3. Neither the name of the University nor the names of its contributors |
| 45 | * may be used to endorse or promote products derived from this software |
| 46 | * without specific prior written permission. |
| 47 | * |
| 48 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 49 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 50 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 51 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 52 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 53 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 54 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 55 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 56 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 57 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 58 | * SUCH DAMAGE. |
| 59 | * |
| 60 | * @(#)com.c 7.5 (Berkeley) 5/16/91 |
| 61 | */ |
| 62 | |
| 63 | /* |
| 64 | * COM driver, uses National Semiconductor NS16450/NS16550AF UART |
| 65 | * Supports automatic hardware flow control on StarTech ST16C650A UART |
| 66 | */ |
| 67 | |
| 68 | #include <sys/cdefs.h> |
| 69 | __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.339 2016/05/27 20:01:49 bouyer Exp $" ); |
| 70 | |
| 71 | #include "opt_com.h" |
| 72 | #include "opt_ddb.h" |
| 73 | #include "opt_kgdb.h" |
| 74 | #include "opt_lockdebug.h" |
| 75 | #include "opt_multiprocessor.h" |
| 76 | #include "opt_ntp.h" |
| 77 | |
| 78 | /* The COM16650 option was renamed to COM_16650. */ |
| 79 | #ifdef COM16650 |
| 80 | #error Obsolete COM16650 option; use COM_16650 instead. |
| 81 | #endif |
| 82 | |
| 83 | /* |
| 84 | * Override cnmagic(9) macro before including <sys/systm.h>. |
| 85 | * We need to know if cn_check_magic triggered debugger, so set a flag. |
| 86 | * Callers of cn_check_magic must declare int cn_trapped = 0; |
| 87 | * XXX: this is *ugly*! |
| 88 | */ |
| 89 | #define cn_trap() \ |
| 90 | do { \ |
| 91 | console_debugger(); \ |
| 92 | cn_trapped = 1; \ |
| 93 | (void)cn_trapped; \ |
| 94 | } while (/* CONSTCOND */ 0) |
| 95 | |
| 96 | #include <sys/param.h> |
| 97 | #include <sys/systm.h> |
| 98 | #include <sys/ioctl.h> |
| 99 | #include <sys/select.h> |
| 100 | #include <sys/poll.h> |
| 101 | #include <sys/tty.h> |
| 102 | #include <sys/proc.h> |
| 103 | #include <sys/conf.h> |
| 104 | #include <sys/file.h> |
| 105 | #include <sys/uio.h> |
| 106 | #include <sys/kernel.h> |
| 107 | #include <sys/syslog.h> |
| 108 | #include <sys/device.h> |
| 109 | #include <sys/malloc.h> |
| 110 | #include <sys/timepps.h> |
| 111 | #include <sys/vnode.h> |
| 112 | #include <sys/kauth.h> |
| 113 | #include <sys/intr.h> |
| 114 | #ifdef RND_COM |
| 115 | #include <sys/rndsource.h> |
| 116 | #endif |
| 117 | |
| 118 | |
| 119 | #include <sys/bus.h> |
| 120 | |
| 121 | #include <dev/ic/comreg.h> |
| 122 | #include <dev/ic/comvar.h> |
| 123 | #include <dev/ic/ns16550reg.h> |
| 124 | #include <dev/ic/st16650reg.h> |
| 125 | #ifdef COM_HAYESP |
| 126 | #include <dev/ic/hayespreg.h> |
| 127 | #endif |
| 128 | #define com_lcr com_cfcr |
| 129 | #include <dev/cons.h> |
| 130 | |
| 131 | #ifdef COM_REGMAP |
| 132 | #define CSR_WRITE_1(r, o, v) \ |
| 133 | bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) |
| 134 | #define CSR_READ_1(r, o) \ |
| 135 | bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) |
| 136 | #define CSR_WRITE_2(r, o, v) \ |
| 137 | bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) |
| 138 | #define CSR_READ_2(r, o) \ |
| 139 | bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) |
| 140 | #define CSR_WRITE_MULTI(r, o, p, n) \ |
| 141 | bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) |
| 142 | #else |
| 143 | #define CSR_WRITE_1(r, o, v) \ |
| 144 | bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) |
| 145 | #define CSR_READ_1(r, o) \ |
| 146 | bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) |
| 147 | #define CSR_WRITE_2(r, o, v) \ |
| 148 | bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) |
| 149 | #define CSR_READ_2(r, o) \ |
| 150 | bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) |
| 151 | #define CSR_WRITE_MULTI(r, o, p, n) \ |
| 152 | bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) |
| 153 | #endif |
| 154 | |
| 155 | |
| 156 | static void com_enable_debugport(struct com_softc *); |
| 157 | |
| 158 | void com_config(struct com_softc *); |
| 159 | void com_shutdown(struct com_softc *); |
| 160 | int comspeed(long, long, int); |
| 161 | static u_char cflag2lcr(tcflag_t); |
| 162 | int comparam(struct tty *, struct termios *); |
| 163 | void comstart(struct tty *); |
| 164 | int comhwiflow(struct tty *, int); |
| 165 | |
| 166 | void com_loadchannelregs(struct com_softc *); |
| 167 | void com_hwiflow(struct com_softc *); |
| 168 | void com_break(struct com_softc *, int); |
| 169 | void com_modem(struct com_softc *, int); |
| 170 | void tiocm_to_com(struct com_softc *, u_long, int); |
| 171 | int com_to_tiocm(struct com_softc *); |
| 172 | void com_iflush(struct com_softc *); |
| 173 | |
| 174 | int com_common_getc(dev_t, struct com_regs *); |
| 175 | static void com_common_putc(dev_t, struct com_regs *, int); |
| 176 | |
| 177 | int cominit(struct com_regs *, int, int, int, tcflag_t); |
| 178 | |
| 179 | static int comcnreattach(void); |
| 180 | |
| 181 | int comcngetc(dev_t); |
| 182 | void comcnputc(dev_t, int); |
| 183 | void comcnpollc(dev_t, int); |
| 184 | |
| 185 | #define integrate static inline |
| 186 | void comsoft(void *); |
| 187 | integrate void com_rxsoft(struct com_softc *, struct tty *); |
| 188 | integrate void com_txsoft(struct com_softc *, struct tty *); |
| 189 | integrate void com_stsoft(struct com_softc *, struct tty *); |
| 190 | integrate void com_schedrx(struct com_softc *); |
| 191 | void comdiag(void *); |
| 192 | |
| 193 | extern struct cfdriver com_cd; |
| 194 | |
| 195 | dev_type_open(comopen); |
| 196 | dev_type_close(comclose); |
| 197 | dev_type_read(comread); |
| 198 | dev_type_write(comwrite); |
| 199 | dev_type_ioctl(comioctl); |
| 200 | dev_type_stop(comstop); |
| 201 | dev_type_tty(comtty); |
| 202 | dev_type_poll(compoll); |
| 203 | |
| 204 | static struct comcons_info comcons_info; |
| 205 | |
| 206 | /* |
| 207 | * Following are all routines needed for COM to act as console |
| 208 | */ |
| 209 | static struct consdev comcons = { |
| 210 | NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, |
| 211 | NODEV, CN_NORMAL |
| 212 | }; |
| 213 | |
| 214 | |
| 215 | const struct cdevsw com_cdevsw = { |
| 216 | .d_open = comopen, |
| 217 | .d_close = comclose, |
| 218 | .d_read = comread, |
| 219 | .d_write = comwrite, |
| 220 | .d_ioctl = comioctl, |
| 221 | .d_stop = comstop, |
| 222 | .d_tty = comtty, |
| 223 | .d_poll = compoll, |
| 224 | .d_mmap = nommap, |
| 225 | .d_kqfilter = ttykqfilter, |
| 226 | .d_discard = nodiscard, |
| 227 | .d_flag = D_TTY |
| 228 | }; |
| 229 | |
| 230 | /* |
| 231 | * Make this an option variable one can patch. |
| 232 | * But be warned: this must be a power of 2! |
| 233 | */ |
| 234 | u_int com_rbuf_size = COM_RING_SIZE; |
| 235 | |
| 236 | /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ |
| 237 | u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; |
| 238 | u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; |
| 239 | |
| 240 | static int comconsattached; |
| 241 | static struct cnm_state com_cnm_state; |
| 242 | |
| 243 | #ifdef KGDB |
| 244 | #include <sys/kgdb.h> |
| 245 | |
| 246 | static struct com_regs comkgdbregs; |
| 247 | static int com_kgdb_attached; |
| 248 | |
| 249 | int com_kgdb_getc(void *); |
| 250 | void com_kgdb_putc(void *, int); |
| 251 | #endif /* KGDB */ |
| 252 | |
| 253 | #ifdef COM_REGMAP |
| 254 | /* initializer for typical 16550-ish hardware */ |
| 255 | #define COM_REG_16550 { \ |
| 256 | com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ |
| 257 | com_efr, com_lcr, com_mcr, com_lsr, com_msr } |
| 258 | /* 16750-specific register set, additional UART status register */ |
| 259 | #define COM_REG_16750 { \ |
| 260 | com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ |
| 261 | com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 262 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } |
| 263 | |
| 264 | #ifdef COM_16750 |
| 265 | const bus_size_t com_std_map[32] = COM_REG_16750; |
| 266 | #else |
| 267 | const bus_size_t com_std_map[16] = COM_REG_16550; |
| 268 | #endif /* COM_16750 */ |
| 269 | #endif /* COM_REGMAP */ |
| 270 | |
| 271 | #define COMDIALOUT_MASK TTDIALOUT_MASK |
| 272 | |
| 273 | #define COMUNIT(x) TTUNIT(x) |
| 274 | #define COMDIALOUT(x) TTDIALOUT(x) |
| 275 | |
| 276 | #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ |
| 277 | device_is_active((sc)->sc_dev)) |
| 278 | |
| 279 | #define BR BUS_SPACE_BARRIER_READ |
| 280 | #define BW BUS_SPACE_BARRIER_WRITE |
| 281 | #define COM_BARRIER(r, f) \ |
| 282 | bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) |
| 283 | |
| 284 | /*ARGSUSED*/ |
| 285 | int |
| 286 | comspeed(long speed, long frequency, int type) |
| 287 | { |
| 288 | #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ |
| 289 | |
| 290 | int x, err; |
| 291 | int divisor = 16; |
| 292 | |
| 293 | if ((type == COM_TYPE_OMAP) && (speed > 230400)) { |
| 294 | divisor = 13; |
| 295 | } |
| 296 | |
| 297 | if (speed == 0) |
| 298 | return (0); |
| 299 | if (speed < 0) |
| 300 | return (-1); |
| 301 | x = divrnd(frequency / divisor, speed); |
| 302 | if (x <= 0) |
| 303 | return (-1); |
| 304 | err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; |
| 305 | if (err < 0) |
| 306 | err = -err; |
| 307 | if (err > COM_TOLERANCE) |
| 308 | return (-1); |
| 309 | return (x); |
| 310 | |
| 311 | #undef divrnd |
| 312 | } |
| 313 | |
| 314 | #ifdef COM_DEBUG |
| 315 | int com_debug = 0; |
| 316 | |
| 317 | void comstatus(struct com_softc *, const char *); |
| 318 | void |
| 319 | comstatus(struct com_softc *sc, const char *str) |
| 320 | { |
| 321 | struct tty *tp = sc->sc_tty; |
| 322 | |
| 323 | aprint_normal_dev(sc->sc_dev, |
| 324 | "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n" , |
| 325 | str, |
| 326 | ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', |
| 327 | ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', |
| 328 | ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', |
| 329 | ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', |
| 330 | sc->sc_tx_stopped ? '+' : '-'); |
| 331 | |
| 332 | aprint_normal_dev(sc->sc_dev, |
| 333 | "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n" , |
| 334 | str, |
| 335 | ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', |
| 336 | ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', |
| 337 | ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', |
| 338 | ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', |
| 339 | sc->sc_rx_flags); |
| 340 | } |
| 341 | #endif |
| 342 | |
| 343 | int |
| 344 | com_probe_subr(struct com_regs *regs) |
| 345 | { |
| 346 | |
| 347 | /* force access to id reg */ |
| 348 | CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); |
| 349 | CSR_WRITE_1(regs, COM_REG_IIR, 0); |
| 350 | if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || |
| 351 | (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) |
| 352 | return (0); |
| 353 | |
| 354 | return (1); |
| 355 | } |
| 356 | |
| 357 | int |
| 358 | comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) |
| 359 | { |
| 360 | struct com_regs regs; |
| 361 | |
| 362 | regs.cr_iot = iot; |
| 363 | regs.cr_ioh = ioh; |
| 364 | #ifdef COM_REGMAP |
| 365 | memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); |
| 366 | #endif |
| 367 | |
| 368 | return com_probe_subr(®s); |
| 369 | } |
| 370 | |
| 371 | /* |
| 372 | * No locking in this routine; it is only called during attach, |
| 373 | * or with the port already locked. |
| 374 | */ |
| 375 | static void |
| 376 | com_enable_debugport(struct com_softc *sc) |
| 377 | { |
| 378 | |
| 379 | /* Turn on line break interrupt, set carrier. */ |
| 380 | sc->sc_ier = IER_ERLS; |
| 381 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 382 | sc->sc_ier |= IER_EUART | IER_ERXTOUT; |
| 383 | if (sc->sc_type == COM_TYPE_INGENIC || |
| 384 | sc->sc_type == COM_TYPE_TEGRA) |
| 385 | sc->sc_ier |= IER_ERXTOUT; |
| 386 | CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); |
| 387 | SET(sc->sc_mcr, MCR_DTR | MCR_RTS); |
| 388 | CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); |
| 389 | } |
| 390 | |
| 391 | void |
| 392 | com_attach_subr(struct com_softc *sc) |
| 393 | { |
| 394 | struct com_regs *regsp = &sc->sc_regs; |
| 395 | struct tty *tp; |
| 396 | #if defined(COM_16650) || defined(COM_16750) |
| 397 | u_int8_t lcr; |
| 398 | #endif |
| 399 | const char *fifo_msg = NULL; |
| 400 | prop_dictionary_t dict; |
| 401 | bool is_console = true; |
| 402 | |
| 403 | aprint_naive("\n" ); |
| 404 | |
| 405 | dict = device_properties(sc->sc_dev); |
| 406 | prop_dictionary_get_bool(dict, "is_console" , &is_console); |
| 407 | callout_init(&sc->sc_diag_callout, 0); |
| 408 | mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); |
| 409 | |
| 410 | /* Disable interrupts before configuring the device. */ |
| 411 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 412 | sc->sc_ier = IER_EUART; |
| 413 | else |
| 414 | sc->sc_ier = 0; |
| 415 | |
| 416 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 417 | |
| 418 | if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && |
| 419 | regsp->cr_iobase == comcons_info.regs.cr_iobase) { |
| 420 | comconsattached = 1; |
| 421 | |
| 422 | if (cn_tab == NULL && comcnreattach() != 0) { |
| 423 | printf("can't re-init serial console @%lx\n" , |
| 424 | (u_long)comcons_info.regs.cr_iobase); |
| 425 | } |
| 426 | |
| 427 | #if defined(COM_16750) || defined(COM_AWIN) |
| 428 | /* Use in comintr(). */ |
| 429 | sc->sc_lcr = cflag2lcr(comcons_info.cflag); |
| 430 | #endif |
| 431 | |
| 432 | /* Make sure the console is always "hardwired". */ |
| 433 | delay(10000); /* wait for output to finish */ |
| 434 | if (is_console) { |
| 435 | SET(sc->sc_hwflags, COM_HW_CONSOLE); |
| 436 | } |
| 437 | |
| 438 | SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); |
| 439 | } |
| 440 | |
| 441 | /* Probe for FIFO */ |
| 442 | switch (sc->sc_type) { |
| 443 | case COM_TYPE_HAYESP: |
| 444 | goto fifodone; |
| 445 | |
| 446 | case COM_TYPE_AU1x00: |
| 447 | sc->sc_fifolen = 16; |
| 448 | fifo_msg = "Au1X00 UART, working fifo" ; |
| 449 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 450 | goto fifodelay; |
| 451 | |
| 452 | case COM_TYPE_16550_NOERS: |
| 453 | sc->sc_fifolen = 16; |
| 454 | fifo_msg = "ns16650, no ERS, working fifo" ; |
| 455 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 456 | goto fifodelay; |
| 457 | |
| 458 | case COM_TYPE_OMAP: |
| 459 | sc->sc_fifolen = 64; |
| 460 | fifo_msg = "OMAP UART, working fifo" ; |
| 461 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 462 | goto fifodelay; |
| 463 | |
| 464 | case COM_TYPE_INGENIC: |
| 465 | sc->sc_fifolen = 16; |
| 466 | fifo_msg = "Ingenic UART, working fifo" ; |
| 467 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 468 | SET(sc->sc_hwflags, COM_HW_NOIEN); |
| 469 | goto fifodelay; |
| 470 | |
| 471 | case COM_TYPE_TEGRA: |
| 472 | sc->sc_fifolen = 8; |
| 473 | fifo_msg = "Tegra UART, working fifo" ; |
| 474 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 475 | CSR_WRITE_1(regsp, COM_REG_FIFO, |
| 476 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); |
| 477 | goto fifodelay; |
| 478 | } |
| 479 | |
| 480 | sc->sc_fifolen = 1; |
| 481 | /* look for a NS 16550AF UART with FIFOs */ |
| 482 | if (sc->sc_type == COM_TYPE_INGENIC) { |
| 483 | CSR_WRITE_1(regsp, COM_REG_FIFO, |
| 484 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | |
| 485 | FIFO_TRIGGER_14 | FIFO_UART_ON); |
| 486 | } else |
| 487 | CSR_WRITE_1(regsp, COM_REG_FIFO, |
| 488 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); |
| 489 | delay(100); |
| 490 | if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) |
| 491 | == IIR_FIFO_MASK) |
| 492 | if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) |
| 493 | == FIFO_TRIGGER_14) { |
| 494 | SET(sc->sc_hwflags, COM_HW_FIFO); |
| 495 | |
| 496 | #ifdef COM_16650 |
| 497 | /* |
| 498 | * IIR changes into the EFR if LCR is set to LCR_EERS |
| 499 | * on 16650s. We also know IIR != 0 at this point. |
| 500 | * Write 0 into the EFR, and read it. If the result |
| 501 | * is 0, we have a 16650. |
| 502 | * |
| 503 | * Older 16650s were broken; the test to detect them |
| 504 | * is taken from the Linux driver. Apparently |
| 505 | * setting DLAB enable gives access to the EFR on |
| 506 | * these chips. |
| 507 | */ |
| 508 | lcr = CSR_READ_1(regsp, COM_REG_LCR); |
| 509 | CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); |
| 510 | CSR_WRITE_1(regsp, COM_REG_EFR, 0); |
| 511 | if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { |
| 512 | CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); |
| 513 | if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { |
| 514 | CLR(sc->sc_hwflags, COM_HW_FIFO); |
| 515 | sc->sc_fifolen = 0; |
| 516 | } else { |
| 517 | SET(sc->sc_hwflags, COM_HW_FLOW); |
| 518 | sc->sc_fifolen = 32; |
| 519 | } |
| 520 | } else |
| 521 | #endif |
| 522 | sc->sc_fifolen = 16; |
| 523 | |
| 524 | #ifdef COM_16750 |
| 525 | /* |
| 526 | * TL16C750 can enable 64byte FIFO, only when DLAB |
| 527 | * is 1. However, some 16750 may always enable. For |
| 528 | * example, restrictions according to DLAB in a data |
| 529 | * sheet for SC16C750 were not described. |
| 530 | * Please enable 'options COM_16650', supposing you |
| 531 | * use SC16C750. Probably 32 bytes of FIFO and HW FLOW |
| 532 | * should become effective. |
| 533 | */ |
| 534 | uint8_t iir1, iir2; |
| 535 | uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; |
| 536 | |
| 537 | if (sc->sc_type == COM_TYPE_INGENIC) |
| 538 | fcr |= FIFO_UART_ON; |
| 539 | |
| 540 | lcr = CSR_READ_1(regsp, COM_REG_LCR); |
| 541 | CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); |
| 542 | CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); |
| 543 | iir1 = CSR_READ_1(regsp, COM_REG_IIR); |
| 544 | CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); |
| 545 | CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); |
| 546 | CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); |
| 547 | iir2 = CSR_READ_1(regsp, COM_REG_IIR); |
| 548 | |
| 549 | CSR_WRITE_1(regsp, COM_REG_LCR, lcr); |
| 550 | |
| 551 | if (!ISSET(iir1, IIR_64B_FIFO) && |
| 552 | ISSET(iir2, IIR_64B_FIFO)) { |
| 553 | /* It is TL16C750. */ |
| 554 | sc->sc_fifolen = 64; |
| 555 | SET(sc->sc_hwflags, COM_HW_AFE); |
| 556 | } else |
| 557 | CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); |
| 558 | #endif |
| 559 | |
| 560 | #ifdef COM_16650 |
| 561 | CSR_WRITE_1(regsp, COM_REG_LCR, lcr); |
| 562 | if (sc->sc_fifolen == 0) |
| 563 | fifo_msg = "st16650, broken fifo" ; |
| 564 | else if (sc->sc_fifolen == 32) |
| 565 | fifo_msg = "st16650a, working fifo" ; |
| 566 | else |
| 567 | #endif |
| 568 | #ifdef COM_16750 |
| 569 | if (sc->sc_fifolen == 64) |
| 570 | fifo_msg = "tl16c750, working fifo" ; |
| 571 | else |
| 572 | #endif |
| 573 | fifo_msg = "ns16550a, working fifo" ; |
| 574 | } else |
| 575 | fifo_msg = "ns16550, broken fifo" ; |
| 576 | else |
| 577 | fifo_msg = "ns8250 or ns16450, no fifo" ; |
| 578 | if (sc->sc_type == COM_TYPE_INGENIC) { |
| 579 | CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON); |
| 580 | } else |
| 581 | CSR_WRITE_1(regsp, COM_REG_FIFO, 0); |
| 582 | fifodelay: |
| 583 | /* |
| 584 | * Some chips will clear down both Tx and Rx FIFOs when zero is |
| 585 | * written to com_fifo. If this chip is the console, writing zero |
| 586 | * results in some of the chip/FIFO description being lost, so delay |
| 587 | * printing it until now. |
| 588 | */ |
| 589 | delay(10); |
| 590 | aprint_normal(": %s\n" , fifo_msg); |
| 591 | if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { |
| 592 | sc->sc_fifolen = 1; |
| 593 | aprint_normal_dev(sc->sc_dev, "txfifo disabled\n" ); |
| 594 | } |
| 595 | |
| 596 | fifodone: |
| 597 | |
| 598 | tp = tty_alloc(); |
| 599 | tp->t_oproc = comstart; |
| 600 | tp->t_param = comparam; |
| 601 | tp->t_hwiflow = comhwiflow; |
| 602 | tp->t_softc = sc; |
| 603 | |
| 604 | sc->sc_tty = tp; |
| 605 | sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); |
| 606 | sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; |
| 607 | sc->sc_rbavail = com_rbuf_size; |
| 608 | if (sc->sc_rbuf == NULL) { |
| 609 | aprint_error_dev(sc->sc_dev, |
| 610 | "unable to allocate ring buffer\n" ); |
| 611 | return; |
| 612 | } |
| 613 | sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); |
| 614 | |
| 615 | tty_attach(tp); |
| 616 | |
| 617 | if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) |
| 618 | SET(sc->sc_mcr, MCR_IENABLE); |
| 619 | |
| 620 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 621 | int maj; |
| 622 | |
| 623 | /* locate the major number */ |
| 624 | maj = cdevsw_lookup_major(&com_cdevsw); |
| 625 | |
| 626 | tp->t_dev = cn_tab->cn_dev = makedev(maj, |
| 627 | device_unit(sc->sc_dev)); |
| 628 | |
| 629 | aprint_normal_dev(sc->sc_dev, "console\n" ); |
| 630 | } |
| 631 | |
| 632 | #ifdef KGDB |
| 633 | /* |
| 634 | * Allow kgdb to "take over" this port. If this is |
| 635 | * not the console and is the kgdb device, it has |
| 636 | * exclusive use. If it's the console _and_ the |
| 637 | * kgdb device, it doesn't. |
| 638 | */ |
| 639 | if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && |
| 640 | regsp->cr_iobase == comkgdbregs.cr_iobase) { |
| 641 | if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 642 | com_kgdb_attached = 1; |
| 643 | |
| 644 | SET(sc->sc_hwflags, COM_HW_KGDB); |
| 645 | } |
| 646 | aprint_normal_dev(sc->sc_dev, "kgdb\n" ); |
| 647 | } |
| 648 | #endif |
| 649 | |
| 650 | sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); |
| 651 | |
| 652 | #ifdef RND_COM |
| 653 | rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), |
| 654 | RND_TYPE_TTY, RND_FLAG_DEFAULT); |
| 655 | #endif |
| 656 | |
| 657 | /* if there are no enable/disable functions, assume the device |
| 658 | is always enabled */ |
| 659 | if (!sc->enable) |
| 660 | sc->enabled = 1; |
| 661 | |
| 662 | com_config(sc); |
| 663 | |
| 664 | SET(sc->sc_hwflags, COM_HW_DEV_OK); |
| 665 | } |
| 666 | |
| 667 | void |
| 668 | com_config(struct com_softc *sc) |
| 669 | { |
| 670 | struct com_regs *regsp = &sc->sc_regs; |
| 671 | |
| 672 | /* Disable interrupts before configuring the device. */ |
| 673 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 674 | sc->sc_ier = IER_EUART; |
| 675 | else |
| 676 | sc->sc_ier = 0; |
| 677 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 678 | (void) CSR_READ_1(regsp, COM_REG_IIR); |
| 679 | |
| 680 | #ifdef COM_HAYESP |
| 681 | /* Look for a Hayes ESP board. */ |
| 682 | if (sc->sc_type == COM_TYPE_HAYESP) { |
| 683 | |
| 684 | /* Set 16550 compatibility mode */ |
| 685 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, |
| 686 | HAYESP_SETMODE); |
| 687 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 688 | HAYESP_MODE_FIFO|HAYESP_MODE_RTS| |
| 689 | HAYESP_MODE_SCALE); |
| 690 | |
| 691 | /* Set RTS/CTS flow control */ |
| 692 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, |
| 693 | HAYESP_SETFLOWTYPE); |
| 694 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 695 | HAYESP_FLOW_RTS); |
| 696 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 697 | HAYESP_FLOW_CTS); |
| 698 | |
| 699 | /* Set flow control levels */ |
| 700 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, |
| 701 | HAYESP_SETRXFLOW); |
| 702 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 703 | HAYESP_HIBYTE(HAYESP_RXHIWMARK)); |
| 704 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 705 | HAYESP_LOBYTE(HAYESP_RXHIWMARK)); |
| 706 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 707 | HAYESP_HIBYTE(HAYESP_RXLOWMARK)); |
| 708 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 709 | HAYESP_LOBYTE(HAYESP_RXLOWMARK)); |
| 710 | } |
| 711 | #endif |
| 712 | |
| 713 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) |
| 714 | com_enable_debugport(sc); |
| 715 | } |
| 716 | |
| 717 | #if 0 |
| 718 | static int |
| 719 | comcngetc_detached(dev_t dev) |
| 720 | { |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | static void |
| 725 | comcnputc_detached(dev_t dev, int c) |
| 726 | { |
| 727 | } |
| 728 | #endif |
| 729 | |
| 730 | int |
| 731 | com_detach(device_t self, int flags) |
| 732 | { |
| 733 | struct com_softc *sc = device_private(self); |
| 734 | int maj, mn; |
| 735 | |
| 736 | if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) |
| 737 | return EBUSY; |
| 738 | |
| 739 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && |
| 740 | (flags & DETACH_SHUTDOWN) != 0) |
| 741 | return EBUSY; |
| 742 | |
| 743 | if (sc->disable != NULL && sc->enabled != 0) { |
| 744 | (*sc->disable)(sc); |
| 745 | sc->enabled = 0; |
| 746 | } |
| 747 | |
| 748 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 749 | comconsattached = 0; |
| 750 | cn_tab = NULL; |
| 751 | } |
| 752 | |
| 753 | /* locate the major number */ |
| 754 | maj = cdevsw_lookup_major(&com_cdevsw); |
| 755 | |
| 756 | /* Nuke the vnodes for any open instances. */ |
| 757 | mn = device_unit(self); |
| 758 | vdevgone(maj, mn, mn, VCHR); |
| 759 | |
| 760 | mn |= COMDIALOUT_MASK; |
| 761 | vdevgone(maj, mn, mn, VCHR); |
| 762 | |
| 763 | if (sc->sc_rbuf == NULL) { |
| 764 | /* |
| 765 | * Ring buffer allocation failed in the com_attach_subr, |
| 766 | * only the tty is allocated, and nothing else. |
| 767 | */ |
| 768 | tty_free(sc->sc_tty); |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | /* Free the receive buffer. */ |
| 773 | free(sc->sc_rbuf, M_DEVBUF); |
| 774 | |
| 775 | /* Detach and free the tty. */ |
| 776 | tty_detach(sc->sc_tty); |
| 777 | tty_free(sc->sc_tty); |
| 778 | |
| 779 | /* Unhook the soft interrupt handler. */ |
| 780 | softint_disestablish(sc->sc_si); |
| 781 | |
| 782 | #ifdef RND_COM |
| 783 | /* Unhook the entropy source. */ |
| 784 | rnd_detach_source(&sc->rnd_source); |
| 785 | #endif |
| 786 | callout_destroy(&sc->sc_diag_callout); |
| 787 | |
| 788 | /* Destroy the lock. */ |
| 789 | mutex_destroy(&sc->sc_lock); |
| 790 | |
| 791 | return (0); |
| 792 | } |
| 793 | |
| 794 | void |
| 795 | com_shutdown(struct com_softc *sc) |
| 796 | { |
| 797 | struct tty *tp = sc->sc_tty; |
| 798 | |
| 799 | mutex_spin_enter(&sc->sc_lock); |
| 800 | |
| 801 | /* If we were asserting flow control, then deassert it. */ |
| 802 | SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); |
| 803 | com_hwiflow(sc); |
| 804 | |
| 805 | /* Clear any break condition set with TIOCSBRK. */ |
| 806 | com_break(sc, 0); |
| 807 | |
| 808 | /* |
| 809 | * Hang up if necessary. Wait a bit, so the other side has time to |
| 810 | * notice even if we immediately open the port again. |
| 811 | * Avoid tsleeping above splhigh(). |
| 812 | */ |
| 813 | if (ISSET(tp->t_cflag, HUPCL)) { |
| 814 | com_modem(sc, 0); |
| 815 | mutex_spin_exit(&sc->sc_lock); |
| 816 | /* XXX will only timeout */ |
| 817 | (void) kpause(ttclos, false, hz, NULL); |
| 818 | mutex_spin_enter(&sc->sc_lock); |
| 819 | } |
| 820 | |
| 821 | /* Turn off interrupts. */ |
| 822 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 823 | sc->sc_ier = IER_ERLS; /* interrupt on line break */ |
| 824 | if ((sc->sc_type == COM_TYPE_PXA2x0) || |
| 825 | (sc->sc_type == COM_TYPE_INGENIC) || |
| 826 | (sc->sc_type == COM_TYPE_TEGRA)) |
| 827 | sc->sc_ier |= IER_ERXTOUT; |
| 828 | } else |
| 829 | sc->sc_ier = 0; |
| 830 | |
| 831 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 832 | sc->sc_ier |= IER_EUART; |
| 833 | |
| 834 | CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); |
| 835 | |
| 836 | mutex_spin_exit(&sc->sc_lock); |
| 837 | |
| 838 | if (sc->disable) { |
| 839 | #ifdef DIAGNOSTIC |
| 840 | if (!sc->enabled) |
| 841 | panic("com_shutdown: not enabled?" ); |
| 842 | #endif |
| 843 | (*sc->disable)(sc); |
| 844 | sc->enabled = 0; |
| 845 | } |
| 846 | } |
| 847 | |
| 848 | int |
| 849 | comopen(dev_t dev, int flag, int mode, struct lwp *l) |
| 850 | { |
| 851 | struct com_softc *sc; |
| 852 | struct tty *tp; |
| 853 | int s; |
| 854 | int error; |
| 855 | |
| 856 | sc = device_lookup_private(&com_cd, COMUNIT(dev)); |
| 857 | if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || |
| 858 | sc->sc_rbuf == NULL) |
| 859 | return (ENXIO); |
| 860 | |
| 861 | if (!device_is_active(sc->sc_dev)) |
| 862 | return (ENXIO); |
| 863 | |
| 864 | #ifdef KGDB |
| 865 | /* |
| 866 | * If this is the kgdb port, no other use is permitted. |
| 867 | */ |
| 868 | if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) |
| 869 | return (EBUSY); |
| 870 | #endif |
| 871 | |
| 872 | tp = sc->sc_tty; |
| 873 | |
| 874 | if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) |
| 875 | return (EBUSY); |
| 876 | |
| 877 | s = spltty(); |
| 878 | |
| 879 | /* |
| 880 | * Do the following iff this is a first open. |
| 881 | */ |
| 882 | if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { |
| 883 | struct termios t; |
| 884 | |
| 885 | tp->t_dev = dev; |
| 886 | |
| 887 | if (sc->enable) { |
| 888 | if ((*sc->enable)(sc)) { |
| 889 | splx(s); |
| 890 | aprint_error_dev(sc->sc_dev, |
| 891 | "device enable failed\n" ); |
| 892 | return (EIO); |
| 893 | } |
| 894 | mutex_spin_enter(&sc->sc_lock); |
| 895 | sc->enabled = 1; |
| 896 | com_config(sc); |
| 897 | } else { |
| 898 | mutex_spin_enter(&sc->sc_lock); |
| 899 | } |
| 900 | |
| 901 | /* Turn on interrupts. */ |
| 902 | sc->sc_ier = IER_ERXRDY | IER_ERLS; |
| 903 | if (!ISSET(tp->t_cflag, CLOCAL)) |
| 904 | sc->sc_ier |= IER_EMSC; |
| 905 | |
| 906 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 907 | sc->sc_ier |= IER_EUART | IER_ERXTOUT; |
| 908 | else if (sc->sc_type == COM_TYPE_INGENIC || |
| 909 | sc->sc_type == COM_TYPE_TEGRA) |
| 910 | sc->sc_ier |= IER_ERXTOUT; |
| 911 | CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); |
| 912 | |
| 913 | /* Fetch the current modem control status, needed later. */ |
| 914 | sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); |
| 915 | |
| 916 | /* Clear PPS capture state on first open. */ |
| 917 | mutex_spin_enter(&timecounter_lock); |
| 918 | memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); |
| 919 | sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; |
| 920 | pps_init(&sc->sc_pps_state); |
| 921 | mutex_spin_exit(&timecounter_lock); |
| 922 | |
| 923 | mutex_spin_exit(&sc->sc_lock); |
| 924 | |
| 925 | /* |
| 926 | * Initialize the termios status to the defaults. Add in the |
| 927 | * sticky bits from TIOCSFLAGS. |
| 928 | */ |
| 929 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 930 | t.c_ospeed = comcons_info.rate; |
| 931 | t.c_cflag = comcons_info.cflag; |
| 932 | } else { |
| 933 | t.c_ospeed = TTYDEF_SPEED; |
| 934 | t.c_cflag = TTYDEF_CFLAG; |
| 935 | } |
| 936 | t.c_ispeed = t.c_ospeed; |
| 937 | if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) |
| 938 | SET(t.c_cflag, CLOCAL); |
| 939 | if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) |
| 940 | SET(t.c_cflag, CRTSCTS); |
| 941 | if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) |
| 942 | SET(t.c_cflag, MDMBUF); |
| 943 | /* Make sure comparam() will do something. */ |
| 944 | tp->t_ospeed = 0; |
| 945 | (void) comparam(tp, &t); |
| 946 | tp->t_iflag = TTYDEF_IFLAG; |
| 947 | tp->t_oflag = TTYDEF_OFLAG; |
| 948 | tp->t_lflag = TTYDEF_LFLAG; |
| 949 | ttychars(tp); |
| 950 | ttsetwater(tp); |
| 951 | |
| 952 | mutex_spin_enter(&sc->sc_lock); |
| 953 | |
| 954 | /* |
| 955 | * Turn on DTR. We must always do this, even if carrier is not |
| 956 | * present, because otherwise we'd have to use TIOCSDTR |
| 957 | * immediately after setting CLOCAL, which applications do not |
| 958 | * expect. We always assert DTR while the device is open |
| 959 | * unless explicitly requested to deassert it. |
| 960 | */ |
| 961 | com_modem(sc, 1); |
| 962 | |
| 963 | /* Clear the input ring, and unblock. */ |
| 964 | sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; |
| 965 | sc->sc_rbavail = com_rbuf_size; |
| 966 | com_iflush(sc); |
| 967 | CLR(sc->sc_rx_flags, RX_ANY_BLOCK); |
| 968 | com_hwiflow(sc); |
| 969 | |
| 970 | #ifdef COM_DEBUG |
| 971 | if (com_debug) |
| 972 | comstatus(sc, "comopen " ); |
| 973 | #endif |
| 974 | |
| 975 | mutex_spin_exit(&sc->sc_lock); |
| 976 | } |
| 977 | |
| 978 | splx(s); |
| 979 | |
| 980 | error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); |
| 981 | if (error) |
| 982 | goto bad; |
| 983 | |
| 984 | error = (*tp->t_linesw->l_open)(dev, tp); |
| 985 | if (error) |
| 986 | goto bad; |
| 987 | |
| 988 | return (0); |
| 989 | |
| 990 | bad: |
| 991 | if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { |
| 992 | /* |
| 993 | * We failed to open the device, and nobody else had it opened. |
| 994 | * Clean up the state as appropriate. |
| 995 | */ |
| 996 | com_shutdown(sc); |
| 997 | } |
| 998 | |
| 999 | return (error); |
| 1000 | } |
| 1001 | |
| 1002 | int |
| 1003 | comclose(dev_t dev, int flag, int mode, struct lwp *l) |
| 1004 | { |
| 1005 | struct com_softc *sc = |
| 1006 | device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1007 | struct tty *tp = sc->sc_tty; |
| 1008 | |
| 1009 | /* XXX This is for cons.c. */ |
| 1010 | if (!ISSET(tp->t_state, TS_ISOPEN)) |
| 1011 | return (0); |
| 1012 | |
| 1013 | (*tp->t_linesw->l_close)(tp, flag); |
| 1014 | ttyclose(tp); |
| 1015 | |
| 1016 | if (COM_ISALIVE(sc) == 0) |
| 1017 | return (0); |
| 1018 | |
| 1019 | if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { |
| 1020 | /* |
| 1021 | * Although we got a last close, the device may still be in |
| 1022 | * use; e.g. if this was the dialout node, and there are still |
| 1023 | * processes waiting for carrier on the non-dialout node. |
| 1024 | */ |
| 1025 | com_shutdown(sc); |
| 1026 | } |
| 1027 | |
| 1028 | return (0); |
| 1029 | } |
| 1030 | |
| 1031 | int |
| 1032 | comread(dev_t dev, struct uio *uio, int flag) |
| 1033 | { |
| 1034 | struct com_softc *sc = |
| 1035 | device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1036 | struct tty *tp = sc->sc_tty; |
| 1037 | |
| 1038 | if (COM_ISALIVE(sc) == 0) |
| 1039 | return (EIO); |
| 1040 | |
| 1041 | return ((*tp->t_linesw->l_read)(tp, uio, flag)); |
| 1042 | } |
| 1043 | |
| 1044 | int |
| 1045 | comwrite(dev_t dev, struct uio *uio, int flag) |
| 1046 | { |
| 1047 | struct com_softc *sc = |
| 1048 | device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1049 | struct tty *tp = sc->sc_tty; |
| 1050 | |
| 1051 | if (COM_ISALIVE(sc) == 0) |
| 1052 | return (EIO); |
| 1053 | |
| 1054 | return ((*tp->t_linesw->l_write)(tp, uio, flag)); |
| 1055 | } |
| 1056 | |
| 1057 | int |
| 1058 | compoll(dev_t dev, int events, struct lwp *l) |
| 1059 | { |
| 1060 | struct com_softc *sc = |
| 1061 | device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1062 | struct tty *tp = sc->sc_tty; |
| 1063 | |
| 1064 | if (COM_ISALIVE(sc) == 0) |
| 1065 | return (POLLHUP); |
| 1066 | |
| 1067 | return ((*tp->t_linesw->l_poll)(tp, events, l)); |
| 1068 | } |
| 1069 | |
| 1070 | struct tty * |
| 1071 | comtty(dev_t dev) |
| 1072 | { |
| 1073 | struct com_softc *sc = |
| 1074 | device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1075 | struct tty *tp = sc->sc_tty; |
| 1076 | |
| 1077 | return (tp); |
| 1078 | } |
| 1079 | |
| 1080 | int |
| 1081 | comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) |
| 1082 | { |
| 1083 | struct com_softc *sc; |
| 1084 | struct tty *tp; |
| 1085 | int error; |
| 1086 | |
| 1087 | sc = device_lookup_private(&com_cd, COMUNIT(dev)); |
| 1088 | if (sc == NULL) |
| 1089 | return ENXIO; |
| 1090 | if (COM_ISALIVE(sc) == 0) |
| 1091 | return (EIO); |
| 1092 | |
| 1093 | tp = sc->sc_tty; |
| 1094 | |
| 1095 | error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); |
| 1096 | if (error != EPASSTHROUGH) |
| 1097 | return (error); |
| 1098 | |
| 1099 | error = ttioctl(tp, cmd, data, flag, l); |
| 1100 | if (error != EPASSTHROUGH) |
| 1101 | return (error); |
| 1102 | |
| 1103 | error = 0; |
| 1104 | switch (cmd) { |
| 1105 | case TIOCSFLAGS: |
| 1106 | error = kauth_authorize_device_tty(l->l_cred, |
| 1107 | KAUTH_DEVICE_TTY_PRIVSET, tp); |
| 1108 | break; |
| 1109 | default: |
| 1110 | /* nothing */ |
| 1111 | break; |
| 1112 | } |
| 1113 | if (error) { |
| 1114 | return error; |
| 1115 | } |
| 1116 | |
| 1117 | mutex_spin_enter(&sc->sc_lock); |
| 1118 | |
| 1119 | switch (cmd) { |
| 1120 | case TIOCSBRK: |
| 1121 | com_break(sc, 1); |
| 1122 | break; |
| 1123 | |
| 1124 | case TIOCCBRK: |
| 1125 | com_break(sc, 0); |
| 1126 | break; |
| 1127 | |
| 1128 | case TIOCSDTR: |
| 1129 | com_modem(sc, 1); |
| 1130 | break; |
| 1131 | |
| 1132 | case TIOCCDTR: |
| 1133 | com_modem(sc, 0); |
| 1134 | break; |
| 1135 | |
| 1136 | case TIOCGFLAGS: |
| 1137 | *(int *)data = sc->sc_swflags; |
| 1138 | break; |
| 1139 | |
| 1140 | case TIOCSFLAGS: |
| 1141 | sc->sc_swflags = *(int *)data; |
| 1142 | break; |
| 1143 | |
| 1144 | case TIOCMSET: |
| 1145 | case TIOCMBIS: |
| 1146 | case TIOCMBIC: |
| 1147 | tiocm_to_com(sc, cmd, *(int *)data); |
| 1148 | break; |
| 1149 | |
| 1150 | case TIOCMGET: |
| 1151 | *(int *)data = com_to_tiocm(sc); |
| 1152 | break; |
| 1153 | |
| 1154 | case PPS_IOC_CREATE: |
| 1155 | case PPS_IOC_DESTROY: |
| 1156 | case PPS_IOC_GETPARAMS: |
| 1157 | case PPS_IOC_SETPARAMS: |
| 1158 | case PPS_IOC_GETCAP: |
| 1159 | case PPS_IOC_FETCH: |
| 1160 | #ifdef PPS_SYNC |
| 1161 | case PPS_IOC_KCBIND: |
| 1162 | #endif |
| 1163 | mutex_spin_enter(&timecounter_lock); |
| 1164 | error = pps_ioctl(cmd, data, &sc->sc_pps_state); |
| 1165 | mutex_spin_exit(&timecounter_lock); |
| 1166 | break; |
| 1167 | |
| 1168 | case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ |
| 1169 | mutex_spin_enter(&timecounter_lock); |
| 1170 | #ifndef PPS_TRAILING_EDGE |
| 1171 | TIMESPEC_TO_TIMEVAL((struct timeval *)data, |
| 1172 | &sc->sc_pps_state.ppsinfo.assert_timestamp); |
| 1173 | #else |
| 1174 | TIMESPEC_TO_TIMEVAL((struct timeval *)data, |
| 1175 | &sc->sc_pps_state.ppsinfo.clear_timestamp); |
| 1176 | #endif |
| 1177 | mutex_spin_exit(&timecounter_lock); |
| 1178 | break; |
| 1179 | |
| 1180 | default: |
| 1181 | error = EPASSTHROUGH; |
| 1182 | break; |
| 1183 | } |
| 1184 | |
| 1185 | mutex_spin_exit(&sc->sc_lock); |
| 1186 | |
| 1187 | #ifdef COM_DEBUG |
| 1188 | if (com_debug) |
| 1189 | comstatus(sc, "comioctl " ); |
| 1190 | #endif |
| 1191 | |
| 1192 | return (error); |
| 1193 | } |
| 1194 | |
| 1195 | integrate void |
| 1196 | com_schedrx(struct com_softc *sc) |
| 1197 | { |
| 1198 | |
| 1199 | sc->sc_rx_ready = 1; |
| 1200 | |
| 1201 | /* Wake up the poller. */ |
| 1202 | softint_schedule(sc->sc_si); |
| 1203 | } |
| 1204 | |
| 1205 | void |
| 1206 | com_break(struct com_softc *sc, int onoff) |
| 1207 | { |
| 1208 | |
| 1209 | if (onoff) |
| 1210 | SET(sc->sc_lcr, LCR_SBREAK); |
| 1211 | else |
| 1212 | CLR(sc->sc_lcr, LCR_SBREAK); |
| 1213 | |
| 1214 | if (!sc->sc_heldchange) { |
| 1215 | if (sc->sc_tx_busy) { |
| 1216 | sc->sc_heldtbc = sc->sc_tbc; |
| 1217 | sc->sc_tbc = 0; |
| 1218 | sc->sc_heldchange = 1; |
| 1219 | } else |
| 1220 | com_loadchannelregs(sc); |
| 1221 | } |
| 1222 | } |
| 1223 | |
| 1224 | void |
| 1225 | com_modem(struct com_softc *sc, int onoff) |
| 1226 | { |
| 1227 | |
| 1228 | if (sc->sc_mcr_dtr == 0) |
| 1229 | return; |
| 1230 | |
| 1231 | if (onoff) |
| 1232 | SET(sc->sc_mcr, sc->sc_mcr_dtr); |
| 1233 | else |
| 1234 | CLR(sc->sc_mcr, sc->sc_mcr_dtr); |
| 1235 | |
| 1236 | if (!sc->sc_heldchange) { |
| 1237 | if (sc->sc_tx_busy) { |
| 1238 | sc->sc_heldtbc = sc->sc_tbc; |
| 1239 | sc->sc_tbc = 0; |
| 1240 | sc->sc_heldchange = 1; |
| 1241 | } else |
| 1242 | com_loadchannelregs(sc); |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | void |
| 1247 | tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) |
| 1248 | { |
| 1249 | u_char combits; |
| 1250 | |
| 1251 | combits = 0; |
| 1252 | if (ISSET(ttybits, TIOCM_DTR)) |
| 1253 | SET(combits, MCR_DTR); |
| 1254 | if (ISSET(ttybits, TIOCM_RTS)) |
| 1255 | SET(combits, MCR_RTS); |
| 1256 | |
| 1257 | switch (how) { |
| 1258 | case TIOCMBIC: |
| 1259 | CLR(sc->sc_mcr, combits); |
| 1260 | break; |
| 1261 | |
| 1262 | case TIOCMBIS: |
| 1263 | SET(sc->sc_mcr, combits); |
| 1264 | break; |
| 1265 | |
| 1266 | case TIOCMSET: |
| 1267 | CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); |
| 1268 | SET(sc->sc_mcr, combits); |
| 1269 | break; |
| 1270 | } |
| 1271 | |
| 1272 | if (!sc->sc_heldchange) { |
| 1273 | if (sc->sc_tx_busy) { |
| 1274 | sc->sc_heldtbc = sc->sc_tbc; |
| 1275 | sc->sc_tbc = 0; |
| 1276 | sc->sc_heldchange = 1; |
| 1277 | } else |
| 1278 | com_loadchannelregs(sc); |
| 1279 | } |
| 1280 | } |
| 1281 | |
| 1282 | int |
| 1283 | com_to_tiocm(struct com_softc *sc) |
| 1284 | { |
| 1285 | u_char combits; |
| 1286 | int ttybits = 0; |
| 1287 | |
| 1288 | combits = sc->sc_mcr; |
| 1289 | if (ISSET(combits, MCR_DTR)) |
| 1290 | SET(ttybits, TIOCM_DTR); |
| 1291 | if (ISSET(combits, MCR_RTS)) |
| 1292 | SET(ttybits, TIOCM_RTS); |
| 1293 | |
| 1294 | combits = sc->sc_msr; |
| 1295 | if (sc->sc_type == COM_TYPE_INGENIC) { |
| 1296 | SET(ttybits, TIOCM_CD); |
| 1297 | } else { |
| 1298 | if (ISSET(combits, MSR_DCD)) |
| 1299 | SET(ttybits, TIOCM_CD); |
| 1300 | } |
| 1301 | if (ISSET(combits, MSR_CTS)) |
| 1302 | SET(ttybits, TIOCM_CTS); |
| 1303 | if (ISSET(combits, MSR_DSR)) |
| 1304 | SET(ttybits, TIOCM_DSR); |
| 1305 | if (ISSET(combits, MSR_RI | MSR_TERI)) |
| 1306 | SET(ttybits, TIOCM_RI); |
| 1307 | |
| 1308 | if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) |
| 1309 | SET(ttybits, TIOCM_LE); |
| 1310 | |
| 1311 | return (ttybits); |
| 1312 | } |
| 1313 | |
| 1314 | static u_char |
| 1315 | cflag2lcr(tcflag_t cflag) |
| 1316 | { |
| 1317 | u_char lcr = 0; |
| 1318 | |
| 1319 | switch (ISSET(cflag, CSIZE)) { |
| 1320 | case CS5: |
| 1321 | SET(lcr, LCR_5BITS); |
| 1322 | break; |
| 1323 | case CS6: |
| 1324 | SET(lcr, LCR_6BITS); |
| 1325 | break; |
| 1326 | case CS7: |
| 1327 | SET(lcr, LCR_7BITS); |
| 1328 | break; |
| 1329 | case CS8: |
| 1330 | SET(lcr, LCR_8BITS); |
| 1331 | break; |
| 1332 | } |
| 1333 | if (ISSET(cflag, PARENB)) { |
| 1334 | SET(lcr, LCR_PENAB); |
| 1335 | if (!ISSET(cflag, PARODD)) |
| 1336 | SET(lcr, LCR_PEVEN); |
| 1337 | } |
| 1338 | if (ISSET(cflag, CSTOPB)) |
| 1339 | SET(lcr, LCR_STOPB); |
| 1340 | |
| 1341 | return (lcr); |
| 1342 | } |
| 1343 | |
| 1344 | int |
| 1345 | comparam(struct tty *tp, struct termios *t) |
| 1346 | { |
| 1347 | struct com_softc *sc = |
| 1348 | device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); |
| 1349 | int ospeed; |
| 1350 | u_char lcr; |
| 1351 | |
| 1352 | if (COM_ISALIVE(sc) == 0) |
| 1353 | return (EIO); |
| 1354 | |
| 1355 | #ifdef COM_HAYESP |
| 1356 | if (sc->sc_type == COM_TYPE_HAYESP) { |
| 1357 | int prescaler, speed; |
| 1358 | |
| 1359 | /* |
| 1360 | * Calculate UART clock prescaler. It should be in |
| 1361 | * range of 0 .. 3. |
| 1362 | */ |
| 1363 | for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; |
| 1364 | prescaler++, speed /= 2) |
| 1365 | if ((ospeed = comspeed(speed, sc->sc_frequency, |
| 1366 | sc->sc_type)) > 0) |
| 1367 | break; |
| 1368 | |
| 1369 | if (prescaler == 4) |
| 1370 | return (EINVAL); |
| 1371 | sc->sc_prescaler = prescaler; |
| 1372 | } else |
| 1373 | #endif |
| 1374 | ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); |
| 1375 | |
| 1376 | /* Check requested parameters. */ |
| 1377 | if (ospeed < 0) |
| 1378 | return (EINVAL); |
| 1379 | if (t->c_ispeed && t->c_ispeed != t->c_ospeed) |
| 1380 | return (EINVAL); |
| 1381 | |
| 1382 | /* |
| 1383 | * For the console, always force CLOCAL and !HUPCL, so that the port |
| 1384 | * is always active. |
| 1385 | */ |
| 1386 | if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || |
| 1387 | ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { |
| 1388 | SET(t->c_cflag, CLOCAL); |
| 1389 | CLR(t->c_cflag, HUPCL); |
| 1390 | } |
| 1391 | |
| 1392 | /* |
| 1393 | * If there were no changes, don't do anything. This avoids dropping |
| 1394 | * input and improves performance when all we did was frob things like |
| 1395 | * VMIN and VTIME. |
| 1396 | */ |
| 1397 | if (tp->t_ospeed == t->c_ospeed && |
| 1398 | tp->t_cflag == t->c_cflag) |
| 1399 | return (0); |
| 1400 | |
| 1401 | lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); |
| 1402 | |
| 1403 | mutex_spin_enter(&sc->sc_lock); |
| 1404 | |
| 1405 | sc->sc_lcr = lcr; |
| 1406 | |
| 1407 | /* |
| 1408 | * If we're not in a mode that assumes a connection is present, then |
| 1409 | * ignore carrier changes. |
| 1410 | */ |
| 1411 | if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) |
| 1412 | sc->sc_msr_dcd = 0; |
| 1413 | else |
| 1414 | sc->sc_msr_dcd = MSR_DCD; |
| 1415 | /* |
| 1416 | * Set the flow control pins depending on the current flow control |
| 1417 | * mode. |
| 1418 | */ |
| 1419 | if (ISSET(t->c_cflag, CRTSCTS)) { |
| 1420 | sc->sc_mcr_dtr = MCR_DTR; |
| 1421 | sc->sc_mcr_rts = MCR_RTS; |
| 1422 | sc->sc_msr_cts = MSR_CTS; |
| 1423 | if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { |
| 1424 | SET(sc->sc_mcr, MCR_AFE); |
| 1425 | } else { |
| 1426 | sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; |
| 1427 | } |
| 1428 | } else if (ISSET(t->c_cflag, MDMBUF)) { |
| 1429 | /* |
| 1430 | * For DTR/DCD flow control, make sure we don't toggle DTR for |
| 1431 | * carrier detection. |
| 1432 | */ |
| 1433 | sc->sc_mcr_dtr = 0; |
| 1434 | sc->sc_mcr_rts = MCR_DTR; |
| 1435 | sc->sc_msr_cts = MSR_DCD; |
| 1436 | if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { |
| 1437 | CLR(sc->sc_mcr, MCR_AFE); |
| 1438 | } else { |
| 1439 | sc->sc_efr = 0; |
| 1440 | } |
| 1441 | } else { |
| 1442 | /* |
| 1443 | * If no flow control, then always set RTS. This will make |
| 1444 | * the other side happy if it mistakenly thinks we're doing |
| 1445 | * RTS/CTS flow control. |
| 1446 | */ |
| 1447 | sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; |
| 1448 | sc->sc_mcr_rts = 0; |
| 1449 | sc->sc_msr_cts = 0; |
| 1450 | if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { |
| 1451 | CLR(sc->sc_mcr, MCR_AFE); |
| 1452 | } else { |
| 1453 | sc->sc_efr = 0; |
| 1454 | } |
| 1455 | if (ISSET(sc->sc_mcr, MCR_DTR)) |
| 1456 | SET(sc->sc_mcr, MCR_RTS); |
| 1457 | else |
| 1458 | CLR(sc->sc_mcr, MCR_RTS); |
| 1459 | } |
| 1460 | sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; |
| 1461 | |
| 1462 | if (t->c_ospeed == 0 && tp->t_ospeed != 0) |
| 1463 | CLR(sc->sc_mcr, sc->sc_mcr_dtr); |
| 1464 | else if (t->c_ospeed != 0 && tp->t_ospeed == 0) |
| 1465 | SET(sc->sc_mcr, sc->sc_mcr_dtr); |
| 1466 | |
| 1467 | sc->sc_dlbl = ospeed; |
| 1468 | sc->sc_dlbh = ospeed >> 8; |
| 1469 | |
| 1470 | /* |
| 1471 | * Set the FIFO threshold based on the receive speed. |
| 1472 | * |
| 1473 | * * If it's a low speed, it's probably a mouse or some other |
| 1474 | * interactive device, so set the threshold low. |
| 1475 | * * If it's a high speed, trim the trigger level down to prevent |
| 1476 | * overflows. |
| 1477 | * * Otherwise set it a bit higher. |
| 1478 | */ |
| 1479 | if (sc->sc_type == COM_TYPE_HAYESP) { |
| 1480 | sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; |
| 1481 | } else if (sc->sc_type == COM_TYPE_TEGRA) { |
| 1482 | sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; |
| 1483 | } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { |
| 1484 | if (t->c_ospeed <= 1200) |
| 1485 | sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; |
| 1486 | else if (t->c_ospeed <= 38400) |
| 1487 | sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; |
| 1488 | else |
| 1489 | sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; |
| 1490 | } else { |
| 1491 | sc->sc_fifo = 0; |
| 1492 | } |
| 1493 | |
| 1494 | if (sc->sc_type == COM_TYPE_INGENIC) |
| 1495 | sc->sc_fifo |= FIFO_UART_ON; |
| 1496 | |
| 1497 | /* And copy to tty. */ |
| 1498 | tp->t_ispeed = t->c_ospeed; |
| 1499 | tp->t_ospeed = t->c_ospeed; |
| 1500 | tp->t_cflag = t->c_cflag; |
| 1501 | |
| 1502 | if (!sc->sc_heldchange) { |
| 1503 | if (sc->sc_tx_busy) { |
| 1504 | sc->sc_heldtbc = sc->sc_tbc; |
| 1505 | sc->sc_tbc = 0; |
| 1506 | sc->sc_heldchange = 1; |
| 1507 | } else |
| 1508 | com_loadchannelregs(sc); |
| 1509 | } |
| 1510 | |
| 1511 | if (!ISSET(t->c_cflag, CHWFLOW)) { |
| 1512 | /* Disable the high water mark. */ |
| 1513 | sc->sc_r_hiwat = 0; |
| 1514 | sc->sc_r_lowat = 0; |
| 1515 | if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { |
| 1516 | CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); |
| 1517 | com_schedrx(sc); |
| 1518 | } |
| 1519 | if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { |
| 1520 | CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); |
| 1521 | com_hwiflow(sc); |
| 1522 | } |
| 1523 | } else { |
| 1524 | sc->sc_r_hiwat = com_rbuf_hiwat; |
| 1525 | sc->sc_r_lowat = com_rbuf_lowat; |
| 1526 | } |
| 1527 | |
| 1528 | mutex_spin_exit(&sc->sc_lock); |
| 1529 | |
| 1530 | /* |
| 1531 | * Update the tty layer's idea of the carrier bit, in case we changed |
| 1532 | * CLOCAL or MDMBUF. We don't hang up here; we only do that by |
| 1533 | * explicit request. |
| 1534 | */ |
| 1535 | if (sc->sc_type == COM_TYPE_INGENIC) { |
| 1536 | /* no DCD here */ |
| 1537 | (void) (*tp->t_linesw->l_modem)(tp, 1); |
| 1538 | } else |
| 1539 | (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); |
| 1540 | |
| 1541 | #ifdef COM_DEBUG |
| 1542 | if (com_debug) |
| 1543 | comstatus(sc, "comparam " ); |
| 1544 | #endif |
| 1545 | |
| 1546 | if (!ISSET(t->c_cflag, CHWFLOW)) { |
| 1547 | if (sc->sc_tx_stopped) { |
| 1548 | sc->sc_tx_stopped = 0; |
| 1549 | comstart(tp); |
| 1550 | } |
| 1551 | } |
| 1552 | |
| 1553 | return (0); |
| 1554 | } |
| 1555 | |
| 1556 | void |
| 1557 | com_iflush(struct com_softc *sc) |
| 1558 | { |
| 1559 | struct com_regs *regsp = &sc->sc_regs; |
| 1560 | #ifdef DIAGNOSTIC |
| 1561 | int reg; |
| 1562 | #endif |
| 1563 | int timo; |
| 1564 | |
| 1565 | #ifdef DIAGNOSTIC |
| 1566 | reg = 0xffff; |
| 1567 | #endif |
| 1568 | timo = 50000; |
| 1569 | /* flush any pending I/O */ |
| 1570 | while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) |
| 1571 | && --timo) |
| 1572 | #ifdef DIAGNOSTIC |
| 1573 | reg = |
| 1574 | #else |
| 1575 | (void) |
| 1576 | #endif |
| 1577 | CSR_READ_1(regsp, COM_REG_RXDATA); |
| 1578 | #ifdef DIAGNOSTIC |
| 1579 | if (!timo) |
| 1580 | aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n" , reg); |
| 1581 | #endif |
| 1582 | |
| 1583 | #if defined(COM_16750) || defined(COM_AWIN) |
| 1584 | uint8_t fifo; |
| 1585 | /* |
| 1586 | * Reset all Rx/Tx FIFO, preserve current FIFO length. |
| 1587 | * This should prevent triggering busy interrupt while |
| 1588 | * manipulating divisors. |
| 1589 | */ |
| 1590 | fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | |
| 1591 | FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); |
| 1592 | CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | |
| 1593 | FIFO_XMT_RST); |
| 1594 | delay(100); |
| 1595 | #endif |
| 1596 | } |
| 1597 | |
| 1598 | void |
| 1599 | com_loadchannelregs(struct com_softc *sc) |
| 1600 | { |
| 1601 | struct com_regs *regsp = &sc->sc_regs; |
| 1602 | |
| 1603 | /* XXXXX necessary? */ |
| 1604 | com_iflush(sc); |
| 1605 | |
| 1606 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 1607 | CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); |
| 1608 | else |
| 1609 | CSR_WRITE_1(regsp, COM_REG_IER, 0); |
| 1610 | |
| 1611 | if (sc->sc_type == COM_TYPE_OMAP) { |
| 1612 | /* disable before changing settings */ |
| 1613 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); |
| 1614 | } |
| 1615 | |
| 1616 | if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { |
| 1617 | KASSERT(sc->sc_type != COM_TYPE_AU1x00); |
| 1618 | KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); |
| 1619 | /* no EFR on alchemy */ |
| 1620 | CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); |
| 1621 | CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); |
| 1622 | } |
| 1623 | if (sc->sc_type == COM_TYPE_AU1x00) { |
| 1624 | /* alchemy has single separate 16-bit clock divisor register */ |
| 1625 | CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + |
| 1626 | (sc->sc_dlbh << 8)); |
| 1627 | } else { |
| 1628 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); |
| 1629 | CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); |
| 1630 | CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); |
| 1631 | } |
| 1632 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); |
| 1633 | CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); |
| 1634 | CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); |
| 1635 | #ifdef COM_HAYESP |
| 1636 | if (sc->sc_type == COM_TYPE_HAYESP) { |
| 1637 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, |
| 1638 | HAYESP_SETPRESCALER); |
| 1639 | bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, |
| 1640 | sc->sc_prescaler); |
| 1641 | } |
| 1642 | #endif |
| 1643 | if (sc->sc_type == COM_TYPE_OMAP) { |
| 1644 | /* setup the fifos. the FCR value is not used as long |
| 1645 | as SCR[6] and SCR[7] are 0, which they are at reset |
| 1646 | and we never touch the SCR register */ |
| 1647 | uint8_t rx_fifo_trig = 40; |
| 1648 | uint8_t tx_fifo_trig = 60; |
| 1649 | uint8_t rx_start = 8; |
| 1650 | uint8_t rx_halt = 60; |
| 1651 | uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); |
| 1652 | uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); |
| 1653 | |
| 1654 | /* enable access to TCR & TLR */ |
| 1655 | CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); |
| 1656 | |
| 1657 | /* write tcr and tlr values */ |
| 1658 | CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); |
| 1659 | CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); |
| 1660 | |
| 1661 | /* disable access to TCR & TLR */ |
| 1662 | CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); |
| 1663 | |
| 1664 | /* enable again, but mode is based on speed */ |
| 1665 | if (sc->sc_tty->t_termios.c_ospeed > 230400) { |
| 1666 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); |
| 1667 | } else { |
| 1668 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); |
| 1669 | } |
| 1670 | } |
| 1671 | |
| 1672 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 1673 | } |
| 1674 | |
| 1675 | int |
| 1676 | comhwiflow(struct tty *tp, int block) |
| 1677 | { |
| 1678 | struct com_softc *sc = |
| 1679 | device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); |
| 1680 | |
| 1681 | if (COM_ISALIVE(sc) == 0) |
| 1682 | return (0); |
| 1683 | |
| 1684 | if (sc->sc_mcr_rts == 0) |
| 1685 | return (0); |
| 1686 | |
| 1687 | mutex_spin_enter(&sc->sc_lock); |
| 1688 | |
| 1689 | if (block) { |
| 1690 | if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { |
| 1691 | SET(sc->sc_rx_flags, RX_TTY_BLOCKED); |
| 1692 | com_hwiflow(sc); |
| 1693 | } |
| 1694 | } else { |
| 1695 | if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { |
| 1696 | CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); |
| 1697 | com_schedrx(sc); |
| 1698 | } |
| 1699 | if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { |
| 1700 | CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); |
| 1701 | com_hwiflow(sc); |
| 1702 | } |
| 1703 | } |
| 1704 | |
| 1705 | mutex_spin_exit(&sc->sc_lock); |
| 1706 | return (1); |
| 1707 | } |
| 1708 | |
| 1709 | /* |
| 1710 | * (un)block input via hw flowcontrol |
| 1711 | */ |
| 1712 | void |
| 1713 | com_hwiflow(struct com_softc *sc) |
| 1714 | { |
| 1715 | struct com_regs *regsp= &sc->sc_regs; |
| 1716 | |
| 1717 | if (sc->sc_mcr_rts == 0) |
| 1718 | return; |
| 1719 | |
| 1720 | if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { |
| 1721 | CLR(sc->sc_mcr, sc->sc_mcr_rts); |
| 1722 | CLR(sc->sc_mcr_active, sc->sc_mcr_rts); |
| 1723 | } else { |
| 1724 | SET(sc->sc_mcr, sc->sc_mcr_rts); |
| 1725 | SET(sc->sc_mcr_active, sc->sc_mcr_rts); |
| 1726 | } |
| 1727 | CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); |
| 1728 | } |
| 1729 | |
| 1730 | |
| 1731 | void |
| 1732 | comstart(struct tty *tp) |
| 1733 | { |
| 1734 | struct com_softc *sc = |
| 1735 | device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); |
| 1736 | struct com_regs *regsp = &sc->sc_regs; |
| 1737 | int s; |
| 1738 | |
| 1739 | if (COM_ISALIVE(sc) == 0) |
| 1740 | return; |
| 1741 | |
| 1742 | s = spltty(); |
| 1743 | if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) |
| 1744 | goto out; |
| 1745 | if (sc->sc_tx_stopped) |
| 1746 | goto out; |
| 1747 | if (!ttypull(tp)) |
| 1748 | goto out; |
| 1749 | |
| 1750 | /* Grab the first contiguous region of buffer space. */ |
| 1751 | { |
| 1752 | u_char *tba; |
| 1753 | int tbc; |
| 1754 | |
| 1755 | tba = tp->t_outq.c_cf; |
| 1756 | tbc = ndqb(&tp->t_outq, 0); |
| 1757 | |
| 1758 | mutex_spin_enter(&sc->sc_lock); |
| 1759 | |
| 1760 | sc->sc_tba = tba; |
| 1761 | sc->sc_tbc = tbc; |
| 1762 | } |
| 1763 | |
| 1764 | SET(tp->t_state, TS_BUSY); |
| 1765 | sc->sc_tx_busy = 1; |
| 1766 | |
| 1767 | /* Enable transmit completion interrupts if necessary. */ |
| 1768 | if (!ISSET(sc->sc_ier, IER_ETXRDY)) { |
| 1769 | SET(sc->sc_ier, IER_ETXRDY); |
| 1770 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 1771 | } |
| 1772 | |
| 1773 | /* Output the first chunk of the contiguous buffer. */ |
| 1774 | if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { |
| 1775 | u_int n; |
| 1776 | |
| 1777 | n = sc->sc_tbc; |
| 1778 | if (n > sc->sc_fifolen) |
| 1779 | n = sc->sc_fifolen; |
| 1780 | CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); |
| 1781 | sc->sc_tbc -= n; |
| 1782 | sc->sc_tba += n; |
| 1783 | } |
| 1784 | |
| 1785 | mutex_spin_exit(&sc->sc_lock); |
| 1786 | out: |
| 1787 | splx(s); |
| 1788 | return; |
| 1789 | } |
| 1790 | |
| 1791 | /* |
| 1792 | * Stop output on a line. |
| 1793 | */ |
| 1794 | void |
| 1795 | comstop(struct tty *tp, int flag) |
| 1796 | { |
| 1797 | struct com_softc *sc = |
| 1798 | device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); |
| 1799 | |
| 1800 | mutex_spin_enter(&sc->sc_lock); |
| 1801 | if (ISSET(tp->t_state, TS_BUSY)) { |
| 1802 | /* Stop transmitting at the next chunk. */ |
| 1803 | sc->sc_tbc = 0; |
| 1804 | sc->sc_heldtbc = 0; |
| 1805 | if (!ISSET(tp->t_state, TS_TTSTOP)) |
| 1806 | SET(tp->t_state, TS_FLUSH); |
| 1807 | } |
| 1808 | mutex_spin_exit(&sc->sc_lock); |
| 1809 | } |
| 1810 | |
| 1811 | void |
| 1812 | comdiag(void *arg) |
| 1813 | { |
| 1814 | struct com_softc *sc = arg; |
| 1815 | int overflows, floods; |
| 1816 | |
| 1817 | mutex_spin_enter(&sc->sc_lock); |
| 1818 | overflows = sc->sc_overflows; |
| 1819 | sc->sc_overflows = 0; |
| 1820 | floods = sc->sc_floods; |
| 1821 | sc->sc_floods = 0; |
| 1822 | sc->sc_errors = 0; |
| 1823 | mutex_spin_exit(&sc->sc_lock); |
| 1824 | |
| 1825 | log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n" , |
| 1826 | device_xname(sc->sc_dev), |
| 1827 | overflows, overflows == 1 ? "" : "s" , |
| 1828 | floods, floods == 1 ? "" : "s" ); |
| 1829 | } |
| 1830 | |
| 1831 | integrate void |
| 1832 | com_rxsoft(struct com_softc *sc, struct tty *tp) |
| 1833 | { |
| 1834 | int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; |
| 1835 | u_char *get, *end; |
| 1836 | u_int cc, scc; |
| 1837 | u_char lsr; |
| 1838 | int code; |
| 1839 | |
| 1840 | end = sc->sc_ebuf; |
| 1841 | get = sc->sc_rbget; |
| 1842 | scc = cc = com_rbuf_size - sc->sc_rbavail; |
| 1843 | |
| 1844 | if (cc == com_rbuf_size) { |
| 1845 | sc->sc_floods++; |
| 1846 | if (sc->sc_errors++ == 0) |
| 1847 | callout_reset(&sc->sc_diag_callout, 60 * hz, |
| 1848 | comdiag, sc); |
| 1849 | } |
| 1850 | |
| 1851 | /* If not yet open, drop the entire buffer content here */ |
| 1852 | if (!ISSET(tp->t_state, TS_ISOPEN)) { |
| 1853 | get += cc << 1; |
| 1854 | if (get >= end) |
| 1855 | get -= com_rbuf_size << 1; |
| 1856 | cc = 0; |
| 1857 | } |
| 1858 | while (cc) { |
| 1859 | code = get[0]; |
| 1860 | lsr = get[1]; |
| 1861 | if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { |
| 1862 | if (ISSET(lsr, LSR_OE)) { |
| 1863 | sc->sc_overflows++; |
| 1864 | if (sc->sc_errors++ == 0) |
| 1865 | callout_reset(&sc->sc_diag_callout, |
| 1866 | 60 * hz, comdiag, sc); |
| 1867 | } |
| 1868 | if (ISSET(lsr, LSR_BI | LSR_FE)) |
| 1869 | SET(code, TTY_FE); |
| 1870 | if (ISSET(lsr, LSR_PE)) |
| 1871 | SET(code, TTY_PE); |
| 1872 | } |
| 1873 | if ((*rint)(code, tp) == -1) { |
| 1874 | /* |
| 1875 | * The line discipline's buffer is out of space. |
| 1876 | */ |
| 1877 | if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { |
| 1878 | /* |
| 1879 | * We're either not using flow control, or the |
| 1880 | * line discipline didn't tell us to block for |
| 1881 | * some reason. Either way, we have no way to |
| 1882 | * know when there's more space available, so |
| 1883 | * just drop the rest of the data. |
| 1884 | */ |
| 1885 | get += cc << 1; |
| 1886 | if (get >= end) |
| 1887 | get -= com_rbuf_size << 1; |
| 1888 | cc = 0; |
| 1889 | } else { |
| 1890 | /* |
| 1891 | * Don't schedule any more receive processing |
| 1892 | * until the line discipline tells us there's |
| 1893 | * space available (through comhwiflow()). |
| 1894 | * Leave the rest of the data in the input |
| 1895 | * buffer. |
| 1896 | */ |
| 1897 | SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); |
| 1898 | } |
| 1899 | break; |
| 1900 | } |
| 1901 | get += 2; |
| 1902 | if (get >= end) |
| 1903 | get = sc->sc_rbuf; |
| 1904 | cc--; |
| 1905 | } |
| 1906 | |
| 1907 | if (cc != scc) { |
| 1908 | sc->sc_rbget = get; |
| 1909 | mutex_spin_enter(&sc->sc_lock); |
| 1910 | |
| 1911 | cc = sc->sc_rbavail += scc - cc; |
| 1912 | /* Buffers should be ok again, release possible block. */ |
| 1913 | if (cc >= sc->sc_r_lowat) { |
| 1914 | if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { |
| 1915 | CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); |
| 1916 | SET(sc->sc_ier, IER_ERXRDY); |
| 1917 | #ifdef COM_PXA2X0 |
| 1918 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 1919 | SET(sc->sc_ier, IER_ERXTOUT); |
| 1920 | #endif |
| 1921 | if (sc->sc_type == COM_TYPE_INGENIC || |
| 1922 | sc->sc_type == COM_TYPE_TEGRA) |
| 1923 | SET(sc->sc_ier, IER_ERXTOUT); |
| 1924 | |
| 1925 | CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, |
| 1926 | sc->sc_ier); |
| 1927 | } |
| 1928 | if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { |
| 1929 | CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); |
| 1930 | com_hwiflow(sc); |
| 1931 | } |
| 1932 | } |
| 1933 | mutex_spin_exit(&sc->sc_lock); |
| 1934 | } |
| 1935 | } |
| 1936 | |
| 1937 | integrate void |
| 1938 | com_txsoft(struct com_softc *sc, struct tty *tp) |
| 1939 | { |
| 1940 | |
| 1941 | CLR(tp->t_state, TS_BUSY); |
| 1942 | if (ISSET(tp->t_state, TS_FLUSH)) |
| 1943 | CLR(tp->t_state, TS_FLUSH); |
| 1944 | else |
| 1945 | ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); |
| 1946 | (*tp->t_linesw->l_start)(tp); |
| 1947 | } |
| 1948 | |
| 1949 | integrate void |
| 1950 | com_stsoft(struct com_softc *sc, struct tty *tp) |
| 1951 | { |
| 1952 | u_char msr, delta; |
| 1953 | |
| 1954 | mutex_spin_enter(&sc->sc_lock); |
| 1955 | msr = sc->sc_msr; |
| 1956 | delta = sc->sc_msr_delta; |
| 1957 | sc->sc_msr_delta = 0; |
| 1958 | mutex_spin_exit(&sc->sc_lock); |
| 1959 | |
| 1960 | if (ISSET(delta, sc->sc_msr_dcd)) { |
| 1961 | /* |
| 1962 | * Inform the tty layer that carrier detect changed. |
| 1963 | */ |
| 1964 | (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); |
| 1965 | } |
| 1966 | |
| 1967 | if (ISSET(delta, sc->sc_msr_cts)) { |
| 1968 | /* Block or unblock output according to flow control. */ |
| 1969 | if (ISSET(msr, sc->sc_msr_cts)) { |
| 1970 | sc->sc_tx_stopped = 0; |
| 1971 | (*tp->t_linesw->l_start)(tp); |
| 1972 | } else { |
| 1973 | sc->sc_tx_stopped = 1; |
| 1974 | } |
| 1975 | } |
| 1976 | |
| 1977 | #ifdef COM_DEBUG |
| 1978 | if (com_debug) |
| 1979 | comstatus(sc, "com_stsoft" ); |
| 1980 | #endif |
| 1981 | } |
| 1982 | |
| 1983 | void |
| 1984 | comsoft(void *arg) |
| 1985 | { |
| 1986 | struct com_softc *sc = arg; |
| 1987 | struct tty *tp; |
| 1988 | |
| 1989 | if (COM_ISALIVE(sc) == 0) |
| 1990 | return; |
| 1991 | |
| 1992 | tp = sc->sc_tty; |
| 1993 | |
| 1994 | if (sc->sc_rx_ready) { |
| 1995 | sc->sc_rx_ready = 0; |
| 1996 | com_rxsoft(sc, tp); |
| 1997 | } |
| 1998 | |
| 1999 | if (sc->sc_st_check) { |
| 2000 | sc->sc_st_check = 0; |
| 2001 | com_stsoft(sc, tp); |
| 2002 | } |
| 2003 | |
| 2004 | if (sc->sc_tx_done) { |
| 2005 | sc->sc_tx_done = 0; |
| 2006 | com_txsoft(sc, tp); |
| 2007 | } |
| 2008 | } |
| 2009 | |
| 2010 | int |
| 2011 | comintr(void *arg) |
| 2012 | { |
| 2013 | struct com_softc *sc = arg; |
| 2014 | struct com_regs *regsp = &sc->sc_regs; |
| 2015 | |
| 2016 | u_char *put, *end; |
| 2017 | u_int cc; |
| 2018 | u_char lsr, iir; |
| 2019 | |
| 2020 | if (COM_ISALIVE(sc) == 0) |
| 2021 | return (0); |
| 2022 | |
| 2023 | KASSERT(regsp != NULL); |
| 2024 | |
| 2025 | mutex_spin_enter(&sc->sc_lock); |
| 2026 | iir = CSR_READ_1(regsp, COM_REG_IIR); |
| 2027 | |
| 2028 | /* Handle ns16750-specific busy interrupt. */ |
| 2029 | #ifdef COM_16750 |
| 2030 | #ifdef COM_AWIN |
| 2031 | #error "COM_16750 and COM_AWIN are exclusive" |
| 2032 | #endif |
| 2033 | int timeout; |
| 2034 | if ((iir & IIR_BUSY) == IIR_BUSY) { |
| 2035 | for (timeout = 10000; |
| 2036 | (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) |
| 2037 | if (timeout <= 0) { |
| 2038 | aprint_error_dev(sc->sc_dev, |
| 2039 | "timeout while waiting for BUSY interrupt " |
| 2040 | "acknowledge\n" ); |
| 2041 | mutex_spin_exit(&sc->sc_lock); |
| 2042 | return (0); |
| 2043 | } |
| 2044 | |
| 2045 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); |
| 2046 | iir = CSR_READ_1(regsp, COM_REG_IIR); |
| 2047 | } |
| 2048 | #endif /* COM_16750 */ |
| 2049 | #ifdef COM_AWIN |
| 2050 | /* Allwinner BUSY interrupt */ |
| 2051 | if ((iir & IIR_BUSY) == IIR_BUSY) { |
| 2052 | if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { |
| 2053 | CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); |
| 2054 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); |
| 2055 | CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); |
| 2056 | CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); |
| 2057 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); |
| 2058 | CSR_WRITE_1(regsp, COM_REG_HALT, |
| 2059 | HALT_CHCFG_EN | HALT_CHCFG_UD); |
| 2060 | for (int timeout = 10000000; |
| 2061 | (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; |
| 2062 | timeout--) { |
| 2063 | if (timeout <= 0) { |
| 2064 | aprint_error_dev(sc->sc_dev, |
| 2065 | "timeout while waiting for HALT " |
| 2066 | "update acknowledge 0x%x 0x%x\n" , |
| 2067 | CSR_READ_1(regsp, COM_REG_HALT), |
| 2068 | CSR_READ_1(regsp, COM_REG_USR)); |
| 2069 | break; |
| 2070 | } |
| 2071 | } |
| 2072 | CSR_WRITE_1(regsp, COM_REG_HALT, 0); |
| 2073 | (void)CSR_READ_1(regsp, COM_REG_USR); |
| 2074 | } else { |
| 2075 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); |
| 2076 | CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); |
| 2077 | CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); |
| 2078 | CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); |
| 2079 | } |
| 2080 | } |
| 2081 | #endif /* COM_AWIN */ |
| 2082 | |
| 2083 | if (ISSET(iir, IIR_NOPEND)) { |
| 2084 | mutex_spin_exit(&sc->sc_lock); |
| 2085 | return (0); |
| 2086 | } |
| 2087 | |
| 2088 | end = sc->sc_ebuf; |
| 2089 | put = sc->sc_rbput; |
| 2090 | cc = sc->sc_rbavail; |
| 2091 | |
| 2092 | again: do { |
| 2093 | u_char msr, delta; |
| 2094 | |
| 2095 | lsr = CSR_READ_1(regsp, COM_REG_LSR); |
| 2096 | if (ISSET(lsr, LSR_BI)) { |
| 2097 | int cn_trapped = 0; /* see above: cn_trap() */ |
| 2098 | |
| 2099 | cn_check_magic(sc->sc_tty->t_dev, |
| 2100 | CNC_BREAK, com_cnm_state); |
| 2101 | if (cn_trapped) |
| 2102 | continue; |
| 2103 | #if defined(KGDB) && !defined(DDB) |
| 2104 | if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { |
| 2105 | kgdb_connect(1); |
| 2106 | continue; |
| 2107 | } |
| 2108 | #endif |
| 2109 | } |
| 2110 | |
| 2111 | if (ISSET(lsr, LSR_RCV_MASK) && |
| 2112 | !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { |
| 2113 | while (cc > 0) { |
| 2114 | int cn_trapped = 0; |
| 2115 | put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); |
| 2116 | put[1] = lsr; |
| 2117 | cn_check_magic(sc->sc_tty->t_dev, |
| 2118 | put[0], com_cnm_state); |
| 2119 | if (cn_trapped) |
| 2120 | goto next; |
| 2121 | put += 2; |
| 2122 | if (put >= end) |
| 2123 | put = sc->sc_rbuf; |
| 2124 | cc--; |
| 2125 | next: |
| 2126 | lsr = CSR_READ_1(regsp, COM_REG_LSR); |
| 2127 | if (!ISSET(lsr, LSR_RCV_MASK)) |
| 2128 | break; |
| 2129 | } |
| 2130 | |
| 2131 | /* |
| 2132 | * Current string of incoming characters ended because |
| 2133 | * no more data was available or we ran out of space. |
| 2134 | * Schedule a receive event if any data was received. |
| 2135 | * If we're out of space, turn off receive interrupts. |
| 2136 | */ |
| 2137 | sc->sc_rbput = put; |
| 2138 | sc->sc_rbavail = cc; |
| 2139 | if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) |
| 2140 | sc->sc_rx_ready = 1; |
| 2141 | |
| 2142 | /* |
| 2143 | * See if we are in danger of overflowing a buffer. If |
| 2144 | * so, use hardware flow control to ease the pressure. |
| 2145 | */ |
| 2146 | if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && |
| 2147 | cc < sc->sc_r_hiwat) { |
| 2148 | SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); |
| 2149 | com_hwiflow(sc); |
| 2150 | } |
| 2151 | |
| 2152 | /* |
| 2153 | * If we're out of space, disable receive interrupts |
| 2154 | * until the queue has drained a bit. |
| 2155 | */ |
| 2156 | if (!cc) { |
| 2157 | SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); |
| 2158 | #ifdef COM_PXA2X0 |
| 2159 | if (sc->sc_type == COM_TYPE_PXA2x0) |
| 2160 | CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); |
| 2161 | else |
| 2162 | #endif |
| 2163 | if (sc->sc_type == COM_TYPE_INGENIC || |
| 2164 | sc->sc_type == COM_TYPE_TEGRA) |
| 2165 | CLR(sc->sc_ier, |
| 2166 | IER_ERXRDY | IER_ERXTOUT); |
| 2167 | else |
| 2168 | CLR(sc->sc_ier, IER_ERXRDY); |
| 2169 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 2170 | } |
| 2171 | } else { |
| 2172 | if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { |
| 2173 | (void) CSR_READ_1(regsp, COM_REG_RXDATA); |
| 2174 | continue; |
| 2175 | } |
| 2176 | } |
| 2177 | |
| 2178 | msr = CSR_READ_1(regsp, COM_REG_MSR); |
| 2179 | delta = msr ^ sc->sc_msr; |
| 2180 | sc->sc_msr = msr; |
| 2181 | if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && |
| 2182 | (delta & MSR_DCD)) { |
| 2183 | mutex_spin_enter(&timecounter_lock); |
| 2184 | pps_capture(&sc->sc_pps_state); |
| 2185 | pps_event(&sc->sc_pps_state, |
| 2186 | (msr & MSR_DCD) ? |
| 2187 | PPS_CAPTUREASSERT : |
| 2188 | PPS_CAPTURECLEAR); |
| 2189 | mutex_spin_exit(&timecounter_lock); |
| 2190 | } |
| 2191 | |
| 2192 | /* |
| 2193 | * Process normal status changes |
| 2194 | */ |
| 2195 | if (ISSET(delta, sc->sc_msr_mask)) { |
| 2196 | SET(sc->sc_msr_delta, delta); |
| 2197 | |
| 2198 | /* |
| 2199 | * Stop output immediately if we lose the output |
| 2200 | * flow control signal or carrier detect. |
| 2201 | */ |
| 2202 | if (ISSET(~msr, sc->sc_msr_mask)) { |
| 2203 | sc->sc_tbc = 0; |
| 2204 | sc->sc_heldtbc = 0; |
| 2205 | #ifdef COM_DEBUG |
| 2206 | if (com_debug) |
| 2207 | comstatus(sc, "comintr " ); |
| 2208 | #endif |
| 2209 | } |
| 2210 | |
| 2211 | sc->sc_st_check = 1; |
| 2212 | } |
| 2213 | } while (!ISSET((iir = |
| 2214 | CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && |
| 2215 | /* |
| 2216 | * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY |
| 2217 | * by IIR read, so we can't do this way: `process all interrupts, |
| 2218 | * then do TX if possible'. |
| 2219 | */ |
| 2220 | (iir & IIR_IMASK) != IIR_TXRDY); |
| 2221 | |
| 2222 | /* |
| 2223 | * Read LSR again, since there may be an interrupt between |
| 2224 | * the last LSR read and IIR read above. |
| 2225 | */ |
| 2226 | lsr = CSR_READ_1(regsp, COM_REG_LSR); |
| 2227 | |
| 2228 | /* |
| 2229 | * See if data can be transmitted as well. |
| 2230 | * Schedule tx done event if no data left |
| 2231 | * and tty was marked busy. |
| 2232 | */ |
| 2233 | if (ISSET(lsr, LSR_TXRDY)) { |
| 2234 | /* |
| 2235 | * If we've delayed a parameter change, do it now, and restart |
| 2236 | * output. |
| 2237 | */ |
| 2238 | if (sc->sc_heldchange) { |
| 2239 | com_loadchannelregs(sc); |
| 2240 | sc->sc_heldchange = 0; |
| 2241 | sc->sc_tbc = sc->sc_heldtbc; |
| 2242 | sc->sc_heldtbc = 0; |
| 2243 | } |
| 2244 | |
| 2245 | /* Output the next chunk of the contiguous buffer, if any. */ |
| 2246 | if (sc->sc_tbc > 0) { |
| 2247 | u_int n; |
| 2248 | |
| 2249 | n = sc->sc_tbc; |
| 2250 | if (n > sc->sc_fifolen) |
| 2251 | n = sc->sc_fifolen; |
| 2252 | CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); |
| 2253 | sc->sc_tbc -= n; |
| 2254 | sc->sc_tba += n; |
| 2255 | } else { |
| 2256 | /* Disable transmit completion interrupts if necessary. */ |
| 2257 | if (ISSET(sc->sc_ier, IER_ETXRDY)) { |
| 2258 | CLR(sc->sc_ier, IER_ETXRDY); |
| 2259 | CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); |
| 2260 | } |
| 2261 | if (sc->sc_tx_busy) { |
| 2262 | sc->sc_tx_busy = 0; |
| 2263 | sc->sc_tx_done = 1; |
| 2264 | } |
| 2265 | } |
| 2266 | } |
| 2267 | |
| 2268 | if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) |
| 2269 | goto again; |
| 2270 | |
| 2271 | mutex_spin_exit(&sc->sc_lock); |
| 2272 | |
| 2273 | /* Wake up the poller. */ |
| 2274 | softint_schedule(sc->sc_si); |
| 2275 | |
| 2276 | #ifdef RND_COM |
| 2277 | rnd_add_uint32(&sc->rnd_source, iir | lsr); |
| 2278 | #endif |
| 2279 | |
| 2280 | return (1); |
| 2281 | } |
| 2282 | |
| 2283 | /* |
| 2284 | * The following functions are polled getc and putc routines, shared |
| 2285 | * by the console and kgdb glue. |
| 2286 | * |
| 2287 | * The read-ahead code is so that you can detect pending in-band |
| 2288 | * cn_magic in polled mode while doing output rather than having to |
| 2289 | * wait until the kernel decides it needs input. |
| 2290 | */ |
| 2291 | |
| 2292 | #define MAX_READAHEAD 20 |
| 2293 | static int com_readahead[MAX_READAHEAD]; |
| 2294 | static int com_readaheadcount = 0; |
| 2295 | |
| 2296 | int |
| 2297 | com_common_getc(dev_t dev, struct com_regs *regsp) |
| 2298 | { |
| 2299 | int s = splserial(); |
| 2300 | u_char stat, c; |
| 2301 | |
| 2302 | /* got a character from reading things earlier */ |
| 2303 | if (com_readaheadcount > 0) { |
| 2304 | int i; |
| 2305 | |
| 2306 | c = com_readahead[0]; |
| 2307 | for (i = 1; i < com_readaheadcount; i++) { |
| 2308 | com_readahead[i-1] = com_readahead[i]; |
| 2309 | } |
| 2310 | com_readaheadcount--; |
| 2311 | splx(s); |
| 2312 | return (c); |
| 2313 | } |
| 2314 | |
| 2315 | /* don't block until a character becomes available */ |
| 2316 | if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { |
| 2317 | splx(s); |
| 2318 | return -1; |
| 2319 | } |
| 2320 | |
| 2321 | c = CSR_READ_1(regsp, COM_REG_RXDATA); |
| 2322 | stat = CSR_READ_1(regsp, COM_REG_IIR); |
| 2323 | { |
| 2324 | int cn_trapped = 0; /* required by cn_trap, see above */ |
| 2325 | #ifdef DDB |
| 2326 | extern int db_active; |
| 2327 | if (!db_active) |
| 2328 | #endif |
| 2329 | cn_check_magic(dev, c, com_cnm_state); |
| 2330 | } |
| 2331 | splx(s); |
| 2332 | return (c); |
| 2333 | } |
| 2334 | |
| 2335 | static void |
| 2336 | com_common_putc(dev_t dev, struct com_regs *regsp, int c) |
| 2337 | { |
| 2338 | int s = splserial(); |
| 2339 | int cin, stat, timo; |
| 2340 | |
| 2341 | if (com_readaheadcount < MAX_READAHEAD |
| 2342 | && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { |
| 2343 | int cn_trapped = 0; |
| 2344 | cin = CSR_READ_1(regsp, COM_REG_RXDATA); |
| 2345 | stat = CSR_READ_1(regsp, COM_REG_IIR); |
| 2346 | cn_check_magic(dev, cin, com_cnm_state); |
| 2347 | com_readahead[com_readaheadcount++] = cin; |
| 2348 | } |
| 2349 | |
| 2350 | /* wait for any pending transmission to finish */ |
| 2351 | timo = 150000; |
| 2352 | while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) |
| 2353 | continue; |
| 2354 | |
| 2355 | CSR_WRITE_1(regsp, COM_REG_TXDATA, c); |
| 2356 | COM_BARRIER(regsp, BR | BW); |
| 2357 | |
| 2358 | splx(s); |
| 2359 | } |
| 2360 | |
| 2361 | /* |
| 2362 | * Initialize UART for use as console or KGDB line. |
| 2363 | */ |
| 2364 | int |
| 2365 | cominit(struct com_regs *regsp, int rate, int frequency, int type, |
| 2366 | tcflag_t cflag) |
| 2367 | { |
| 2368 | |
| 2369 | if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, |
| 2370 | ®sp->cr_ioh)) |
| 2371 | return (ENOMEM); /* ??? */ |
| 2372 | |
| 2373 | if (type == COM_TYPE_OMAP) { |
| 2374 | /* disable before changing settings */ |
| 2375 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); |
| 2376 | } |
| 2377 | |
| 2378 | rate = comspeed(rate, frequency, type); |
| 2379 | if (__predict_true(rate != -1)) { |
| 2380 | if (type == COM_TYPE_AU1x00) { |
| 2381 | CSR_WRITE_2(regsp, COM_REG_DLBL, rate); |
| 2382 | } else { |
| 2383 | /* no EFR on alchemy */ |
| 2384 | if ((type != COM_TYPE_16550_NOERS) && |
| 2385 | (type != COM_TYPE_INGENIC)) { |
| 2386 | CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); |
| 2387 | CSR_WRITE_1(regsp, COM_REG_EFR, 0); |
| 2388 | } |
| 2389 | CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); |
| 2390 | CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); |
| 2391 | CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); |
| 2392 | } |
| 2393 | } |
| 2394 | CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); |
| 2395 | CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); |
| 2396 | |
| 2397 | if (type == COM_TYPE_INGENIC) { |
| 2398 | CSR_WRITE_1(regsp, COM_REG_FIFO, |
| 2399 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | |
| 2400 | FIFO_TRIGGER_1 | FIFO_UART_ON); |
| 2401 | } else { |
| 2402 | CSR_WRITE_1(regsp, COM_REG_FIFO, |
| 2403 | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | |
| 2404 | FIFO_TRIGGER_1); |
| 2405 | } |
| 2406 | |
| 2407 | if (type == COM_TYPE_OMAP) { |
| 2408 | /* setup the fifos. the FCR value is not used as long |
| 2409 | as SCR[6] and SCR[7] are 0, which they are at reset |
| 2410 | and we never touch the SCR register */ |
| 2411 | uint8_t rx_fifo_trig = 40; |
| 2412 | uint8_t tx_fifo_trig = 60; |
| 2413 | uint8_t rx_start = 8; |
| 2414 | uint8_t rx_halt = 60; |
| 2415 | uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); |
| 2416 | uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); |
| 2417 | |
| 2418 | /* enable access to TCR & TLR */ |
| 2419 | CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); |
| 2420 | |
| 2421 | /* write tcr and tlr values */ |
| 2422 | CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); |
| 2423 | CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); |
| 2424 | |
| 2425 | /* disable access to TCR & TLR */ |
| 2426 | CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); |
| 2427 | |
| 2428 | /* enable again, but mode is based on speed */ |
| 2429 | if (rate > 230400) { |
| 2430 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); |
| 2431 | } else { |
| 2432 | CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); |
| 2433 | } |
| 2434 | } |
| 2435 | |
| 2436 | #ifdef COM_PXA2X0 |
| 2437 | if (type == COM_TYPE_PXA2x0) |
| 2438 | CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); |
| 2439 | else |
| 2440 | #endif |
| 2441 | CSR_WRITE_1(regsp, COM_REG_IER, 0); |
| 2442 | |
| 2443 | return (0); |
| 2444 | } |
| 2445 | |
| 2446 | int |
| 2447 | comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, |
| 2448 | tcflag_t cflag) |
| 2449 | { |
| 2450 | int res; |
| 2451 | |
| 2452 | comcons_info.regs = *regsp; |
| 2453 | |
| 2454 | res = cominit(&comcons_info.regs, rate, frequency, type, cflag); |
| 2455 | if (res) |
| 2456 | return (res); |
| 2457 | |
| 2458 | cn_tab = &comcons; |
| 2459 | cn_init_magic(&com_cnm_state); |
| 2460 | cn_set_magic("\047\001" ); /* default magic is BREAK */ |
| 2461 | |
| 2462 | comcons_info.frequency = frequency; |
| 2463 | comcons_info.type = type; |
| 2464 | comcons_info.rate = rate; |
| 2465 | comcons_info.cflag = cflag; |
| 2466 | |
| 2467 | return (0); |
| 2468 | } |
| 2469 | |
| 2470 | int |
| 2471 | comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, |
| 2472 | int type, tcflag_t cflag) |
| 2473 | { |
| 2474 | struct com_regs regs; |
| 2475 | |
| 2476 | memset(®s, 0, sizeof regs); |
| 2477 | regs.cr_iot = iot; |
| 2478 | regs.cr_iobase = iobase; |
| 2479 | regs.cr_nports = COM_NPORTS; |
| 2480 | #ifdef COM_REGMAP |
| 2481 | memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); |
| 2482 | #endif |
| 2483 | |
| 2484 | return comcnattach1(®s, rate, frequency, type, cflag); |
| 2485 | } |
| 2486 | |
| 2487 | static int |
| 2488 | comcnreattach(void) |
| 2489 | { |
| 2490 | return comcnattach1(&comcons_info.regs, comcons_info.rate, |
| 2491 | comcons_info.frequency, comcons_info.type, comcons_info.cflag); |
| 2492 | } |
| 2493 | |
| 2494 | int |
| 2495 | comcngetc(dev_t dev) |
| 2496 | { |
| 2497 | |
| 2498 | return (com_common_getc(dev, &comcons_info.regs)); |
| 2499 | } |
| 2500 | |
| 2501 | /* |
| 2502 | * Console kernel output character routine. |
| 2503 | */ |
| 2504 | void |
| 2505 | comcnputc(dev_t dev, int c) |
| 2506 | { |
| 2507 | |
| 2508 | com_common_putc(dev, &comcons_info.regs, c); |
| 2509 | } |
| 2510 | |
| 2511 | void |
| 2512 | comcnpollc(dev_t dev, int on) |
| 2513 | { |
| 2514 | |
| 2515 | com_readaheadcount = 0; |
| 2516 | } |
| 2517 | |
| 2518 | #ifdef KGDB |
| 2519 | int |
| 2520 | com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, |
| 2521 | tcflag_t cflag) |
| 2522 | { |
| 2523 | int res; |
| 2524 | |
| 2525 | if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && |
| 2526 | regsp->cr_iobase == comcons_info.regs.cr_iobase) { |
| 2527 | #if !defined(DDB) |
| 2528 | return (EBUSY); /* cannot share with console */ |
| 2529 | #else |
| 2530 | comkgdbregs = *regsp; |
| 2531 | comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; |
| 2532 | #endif |
| 2533 | } else { |
| 2534 | comkgdbregs = *regsp; |
| 2535 | res = cominit(&comkgdbregs, rate, frequency, type, cflag); |
| 2536 | if (res) |
| 2537 | return (res); |
| 2538 | |
| 2539 | /* |
| 2540 | * XXXfvdl this shouldn't be needed, but the cn_magic goo |
| 2541 | * expects this to be initialized |
| 2542 | */ |
| 2543 | cn_init_magic(&com_cnm_state); |
| 2544 | cn_set_magic("\047\001" ); |
| 2545 | } |
| 2546 | |
| 2547 | kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); |
| 2548 | kgdb_dev = 123; /* unneeded, only to satisfy some tests */ |
| 2549 | |
| 2550 | return (0); |
| 2551 | } |
| 2552 | |
| 2553 | int |
| 2554 | com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, |
| 2555 | int frequency, int type, tcflag_t cflag) |
| 2556 | { |
| 2557 | struct com_regs regs; |
| 2558 | |
| 2559 | regs.cr_iot = iot; |
| 2560 | regs.cr_nports = COM_NPORTS; |
| 2561 | regs.cr_iobase = iobase; |
| 2562 | #ifdef COM_REGMAP |
| 2563 | memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); |
| 2564 | #endif |
| 2565 | |
| 2566 | return com_kgdb_attach1(®s, rate, frequency, type, cflag); |
| 2567 | } |
| 2568 | |
| 2569 | /* ARGSUSED */ |
| 2570 | int |
| 2571 | com_kgdb_getc(void *arg) |
| 2572 | { |
| 2573 | |
| 2574 | return (com_common_getc(NODEV, &comkgdbregs)); |
| 2575 | } |
| 2576 | |
| 2577 | /* ARGSUSED */ |
| 2578 | void |
| 2579 | com_kgdb_putc(void *arg, int c) |
| 2580 | { |
| 2581 | |
| 2582 | com_common_putc(NODEV, &comkgdbregs, c); |
| 2583 | } |
| 2584 | #endif /* KGDB */ |
| 2585 | |
| 2586 | /* helper function to identify the com ports used by |
| 2587 | console or KGDB (and not yet autoconf attached) */ |
| 2588 | int |
| 2589 | com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) |
| 2590 | { |
| 2591 | bus_space_handle_t help; |
| 2592 | |
| 2593 | if (!comconsattached && |
| 2594 | bus_space_is_equal(iot, comcons_info.regs.cr_iot) && |
| 2595 | iobase == comcons_info.regs.cr_iobase) |
| 2596 | help = comcons_info.regs.cr_ioh; |
| 2597 | #ifdef KGDB |
| 2598 | else if (!com_kgdb_attached && |
| 2599 | bus_space_is_equal(iot, comkgdbregs.cr_iot) && |
| 2600 | iobase == comkgdbregs.cr_iobase) |
| 2601 | help = comkgdbregs.cr_ioh; |
| 2602 | #endif |
| 2603 | else |
| 2604 | return (0); |
| 2605 | |
| 2606 | if (ioh) |
| 2607 | *ioh = help; |
| 2608 | return (1); |
| 2609 | } |
| 2610 | |
| 2611 | /* |
| 2612 | * this routine exists to serve as a shutdown hook for systems that |
| 2613 | * have firmware which doesn't interact properly with a com device in |
| 2614 | * FIFO mode. |
| 2615 | */ |
| 2616 | bool |
| 2617 | com_cleanup(device_t self, int how) |
| 2618 | { |
| 2619 | struct com_softc *sc = device_private(self); |
| 2620 | |
| 2621 | if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) |
| 2622 | CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); |
| 2623 | |
| 2624 | return true; |
| 2625 | } |
| 2626 | |
| 2627 | bool |
| 2628 | com_suspend(device_t self, const pmf_qual_t *qual) |
| 2629 | { |
| 2630 | struct com_softc *sc = device_private(self); |
| 2631 | |
| 2632 | #if 0 |
| 2633 | if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) |
| 2634 | cn_tab = &comcons_suspend; |
| 2635 | #endif |
| 2636 | |
| 2637 | CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); |
| 2638 | (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); |
| 2639 | |
| 2640 | return true; |
| 2641 | } |
| 2642 | |
| 2643 | bool |
| 2644 | com_resume(device_t self, const pmf_qual_t *qual) |
| 2645 | { |
| 2646 | struct com_softc *sc = device_private(self); |
| 2647 | |
| 2648 | mutex_spin_enter(&sc->sc_lock); |
| 2649 | com_loadchannelregs(sc); |
| 2650 | mutex_spin_exit(&sc->sc_lock); |
| 2651 | |
| 2652 | return true; |
| 2653 | } |
| 2654 | |