| 1 | /* $NetBSD: if_nfereg.h,v 1.7 2008/04/17 19:12:26 christos Exp $ */ |
| 2 | /* $OpenBSD: if_nfereg.h,v 1.22 2007/12/05 08:30:33 jsg Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org> |
| 6 | * |
| 7 | * Permission to use, copy, modify, and distribute this software for any |
| 8 | * purpose with or without fee is hereby granted, provided that the above |
| 9 | * copyright notice and this permission notice appear in all copies. |
| 10 | * |
| 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 18 | */ |
| 19 | |
| 20 | #define NFE_PCI_BA 0x10 |
| 21 | |
| 22 | #define NFE_RX_RING_COUNT 128 |
| 23 | #define NFE_TX_RING_COUNT 256 |
| 24 | |
| 25 | #define NFE_RX_NEXTDESC(x) (((x) + 1) & (NFE_RX_RING_COUNT - 1)) |
| 26 | #define NFE_TX_NEXTDESC(x) (((x) + 1) & (NFE_TX_RING_COUNT - 1)) |
| 27 | |
| 28 | #define ETHER_ALIGN 2 |
| 29 | |
| 30 | #define NFE_JUMBO_FRAMELEN 9018 |
| 31 | #define NFE_JUMBO_MTU (NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) |
| 32 | |
| 33 | #define NFE_JBYTES (NFE_JUMBO_FRAMELEN + ETHER_ALIGN) |
| 34 | #define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + 64) |
| 35 | #define NFE_JPOOL_SIZE (NFE_JPOOL_COUNT * NFE_JBYTES) |
| 36 | |
| 37 | #define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2) |
| 38 | |
| 39 | #define NFE_IRQ_STATUS 0x000 |
| 40 | #define NFE_IRQ_MASK 0x004 |
| 41 | #define NFE_SETUP_R6 0x008 |
| 42 | #define NFE_IMTIMER 0x00c |
| 43 | #define NFE_MAC_RESET 0x03c |
| 44 | #define NFE_MISC1 0x080 |
| 45 | #define NFE_TX_CTL 0x084 |
| 46 | #define NFE_TX_STATUS 0x088 |
| 47 | #define NFE_RXFILTER 0x08c |
| 48 | #define NFE_RXBUFSZ 0x090 |
| 49 | #define NFE_RX_CTL 0x094 |
| 50 | #define NFE_RX_STATUS 0x098 |
| 51 | #define NFE_RNDSEED 0x09c |
| 52 | #define NFE_SETUP_R1 0x0a0 |
| 53 | #define NFE_SETUP_R2 0x0a4 |
| 54 | #define NFE_MACADDR_HI 0x0a8 |
| 55 | #define NFE_MACADDR_LO 0x0ac |
| 56 | #define NFE_MULTIADDR_HI 0x0b0 |
| 57 | #define NFE_MULTIADDR_LO 0x0b4 |
| 58 | #define NFE_MULTIMASK_HI 0x0b8 |
| 59 | #define NFE_MULTIMASK_LO 0x0bc |
| 60 | #define NFE_PHY_IFACE 0x0c0 |
| 61 | #define NFE_TX_RING_ADDR_LO 0x100 |
| 62 | #define NFE_RX_RING_ADDR_LO 0x104 |
| 63 | #define NFE_RING_SIZE 0x108 |
| 64 | #define NFE_TX_UNK 0x10c |
| 65 | #define NFE_LINKSPEED 0x110 |
| 66 | #define NFE_SETUP_R5 0x130 |
| 67 | #define NFE_SETUP_R3 0x13C |
| 68 | #define NFE_SETUP_R7 0x140 |
| 69 | #define NFE_RXTX_CTL 0x144 |
| 70 | #define NFE_TX_RING_ADDR_HI 0x148 |
| 71 | #define NFE_RX_RING_ADDR_HI 0x14c |
| 72 | #define NFE_PHY_STATUS 0x180 |
| 73 | #define NFE_SETUP_R4 0x184 |
| 74 | #define NFE_STATUS 0x188 |
| 75 | #define NFE_PHY_SPEED 0x18c |
| 76 | #define NFE_PHY_CTL 0x190 |
| 77 | #define NFE_PHY_DATA 0x194 |
| 78 | #define NFE_WOL_CTL 0x200 |
| 79 | #define NFE_PATTERN_CRC 0x204 |
| 80 | #define NFE_PATTERN_MASK 0x208 |
| 81 | #define NFE_PWR_CAP 0x268 |
| 82 | #define NFE_PWR_STATE 0x26c |
| 83 | #define NFE_VTAG_CTL 0x300 |
| 84 | #define NFE_PWR2_CTL 0x600 |
| 85 | |
| 86 | #define NFE_PHY_ERROR 0x00001 |
| 87 | #define NFE_PHY_WRITE 0x00400 |
| 88 | #define NFE_PHY_BUSY 0x08000 |
| 89 | #define NFE_PHYADD_SHIFT 5 |
| 90 | |
| 91 | #define NFE_MAC_RESET_MAGIC 0x00f3 |
| 92 | |
| 93 | #define NFE_STATUS_MAGIC 0x140000 |
| 94 | |
| 95 | #define NFE_MAC_ADDR_INORDER 0x8000 |
| 96 | |
| 97 | #define NFE_R1_MAGIC 0x16070f |
| 98 | #define NFE_R2_MAGIC 0x16 |
| 99 | #define NFE_R4_MAGIC 0x08 |
| 100 | #define NFE_R6_MAGIC 0x03 |
| 101 | #define NFE_WOL_ENABLE 0x1111 |
| 102 | #define NFE_RX_START 0x01 |
| 103 | #define NFE_TX_START 0x01 |
| 104 | |
| 105 | #define NFE_IRQ_RXERR 0x0001 |
| 106 | #define NFE_IRQ_RX 0x0002 |
| 107 | #define NFE_IRQ_RX_NOBUF 0x0004 |
| 108 | #define NFE_IRQ_TXERR 0x0008 |
| 109 | #define NFE_IRQ_TX_DONE 0x0010 |
| 110 | #define NFE_IRQ_TIMER 0x0020 |
| 111 | #define NFE_IRQ_LINK 0x0040 |
| 112 | #define NFE_IRQ_TXERR2 0x0080 |
| 113 | #define NFE_IRQ_TX1 0x0100 |
| 114 | |
| 115 | #define NFE_IRQ_WANTED \ |
| 116 | (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ |
| 117 | NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ |
| 118 | NFE_IRQ_LINK) |
| 119 | |
| 120 | #define NFE_RXTX_KICKTX 0x0001 |
| 121 | #define NFE_RXTX_BIT1 0x0002 |
| 122 | #define NFE_RXTX_BIT2 0x0004 |
| 123 | #define NFE_RXTX_RESET 0x0010 |
| 124 | #define NFE_RXTX_VTAG_STRIP 0x0040 |
| 125 | #define NFE_RXTX_VTAG_INSERT 0x0080 |
| 126 | #define NFE_RXTX_RXCSUM 0x0400 |
| 127 | #define NFE_RXTX_V2MAGIC 0x2100 |
| 128 | #define NFE_RXTX_V3MAGIC 0x2200 |
| 129 | #define NFE_RXFILTER_MAGIC 0x007f0008 |
| 130 | #define NFE_U2M (1 << 5) |
| 131 | #define NFE_PROMISC (1 << 7) |
| 132 | |
| 133 | /* default interrupt moderation timer of 128us */ |
| 134 | #define NFE_IM_DEFAULT ((128 * 100) / 1024) |
| 135 | |
| 136 | #define NFE_VTAG_ENABLE (1 << 13) |
| 137 | |
| 138 | #define NFE_PWR_VALID (1 << 8) |
| 139 | #define NFE_PWR_WAKEUP (1 << 15) |
| 140 | #define NFE_PWR2_WAKEUP_MASK 0x0f11 |
| 141 | |
| 142 | #define NFE_MEDIA_SET 0x10000 |
| 143 | #define NFE_MEDIA_1000T 0x00032 |
| 144 | #define NFE_MEDIA_100TX 0x00064 |
| 145 | #define NFE_MEDIA_10T 0x003e8 |
| 146 | |
| 147 | #define NFE_PHY_100TX (1 << 0) |
| 148 | #define NFE_PHY_1000T (1 << 1) |
| 149 | #define NFE_PHY_HDX (1 << 8) |
| 150 | |
| 151 | #define NFE_MISC1_MAGIC 0x003b0f3c |
| 152 | #define NFE_MISC1_HDX (1 << 1) |
| 153 | |
| 154 | #define NFE_SEED_MASK 0x0003ff00 |
| 155 | #define NFE_SEED_10T 0x00007f00 |
| 156 | #define NFE_SEED_100TX 0x00002d00 |
| 157 | #define NFE_SEED_1000T 0x00007400 |
| 158 | |
| 159 | /* Rx/Tx descriptor */ |
| 160 | struct nfe_desc32 { |
| 161 | volatile uint32_t physaddr; |
| 162 | volatile uint16_t length; |
| 163 | volatile uint16_t flags; |
| 164 | #define NFE_RX_FIXME_V1 0x6004 |
| 165 | #define NFE_RX_VALID_V1 (1 << 0) |
| 166 | #define NFE_TX_ERROR_V1 0x7808 |
| 167 | #define NFE_TX_LASTFRAG_V1 (1 << 0) |
| 168 | } __packed; |
| 169 | |
| 170 | #define NFE_V1_TXERR "\020" \ |
| 171 | "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ |
| 172 | "\08FORCEDINT\03RETRY\00LASTPACKET" |
| 173 | |
| 174 | /* V2 Rx/Tx descriptor */ |
| 175 | struct nfe_desc64 { |
| 176 | volatile uint32_t physaddr[2]; |
| 177 | volatile uint32_t vtag; |
| 178 | #define NFE_RX_VTAG (1 << 16) |
| 179 | #define NFE_TX_VTAG (1 << 18) |
| 180 | volatile uint16_t length; |
| 181 | volatile uint16_t flags; |
| 182 | #define NFE_RX_FIXME_V2 0x4300 |
| 183 | #define NFE_RX_VALID_V2 (1 << 13) |
| 184 | #define NFE_TX_ERROR_V2 0x5c04 |
| 185 | #define NFE_TX_LASTFRAG_V2 (1 << 13) |
| 186 | } __packed; |
| 187 | |
| 188 | #define NFE_V2_TXERR "\020" \ |
| 189 | "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" |
| 190 | |
| 191 | /* flags common to V1/V2 descriptors */ |
| 192 | #define NFE_RX_UDP_CSUMOK (1 << 10) |
| 193 | #define NFE_RX_TCP_CSUMOK (1 << 11) |
| 194 | #define NFE_RX_IP_CSUMOK (1 << 12) |
| 195 | #define NFE_RX_ERROR (1 << 14) |
| 196 | #define NFE_RX_READY (1 << 15) |
| 197 | #define NFE_TX_TCP_UDP_CSUM (1 << 10) |
| 198 | #define NFE_TX_IP_CSUM (1 << 11) |
| 199 | #define NFE_TX_VALID (1 << 15) |
| 200 | |
| 201 | #define NFE_READ(sc, reg) \ |
| 202 | bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) |
| 203 | |
| 204 | #define NFE_WRITE(sc, reg, val) \ |
| 205 | bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val)) |
| 206 | |