| 1 | /* $NetBSD: nouveau_subdev_clock_nv50.c,v 1.3 2015/03/12 15:09:04 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2012 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_clock_nv50.c,v 1.3 2015/03/12 15:09:04 christos Exp $" ); |
| 29 | |
| 30 | #include <subdev/bios.h> |
| 31 | #include <subdev/bios/pll.h> |
| 32 | |
| 33 | #include "nv50.h" |
| 34 | #include "pll.h" |
| 35 | #include "seq.h" |
| 36 | |
| 37 | static u32 |
| 38 | read_div(struct nv50_clock_priv *priv) |
| 39 | { |
| 40 | switch (nv_device(priv)->chipset) { |
| 41 | case 0x50: /* it exists, but only has bit 31, not the dividers.. */ |
| 42 | case 0x84: |
| 43 | case 0x86: |
| 44 | case 0x98: |
| 45 | case 0xa0: |
| 46 | return nv_rd32(priv, 0x004700); |
| 47 | case 0x92: |
| 48 | case 0x94: |
| 49 | case 0x96: |
| 50 | return nv_rd32(priv, 0x004800); |
| 51 | default: |
| 52 | return 0x00000000; |
| 53 | } |
| 54 | } |
| 55 | |
| 56 | static u32 |
| 57 | read_pll_src(struct nv50_clock_priv *priv, u32 base) |
| 58 | { |
| 59 | struct nouveau_clock *clk = &priv->base; |
| 60 | u32 coef, ref = clk->read(clk, nv_clk_src_crystal); |
| 61 | u32 rsel = nv_rd32(priv, 0x00e18c); |
| 62 | int P, N, M, id; |
| 63 | |
| 64 | switch (nv_device(priv)->chipset) { |
| 65 | case 0x50: |
| 66 | case 0xa0: |
| 67 | switch (base) { |
| 68 | case 0x4020: |
| 69 | case 0x4028: id = !!(rsel & 0x00000004); break; |
| 70 | case 0x4008: id = !!(rsel & 0x00000008); break; |
| 71 | case 0x4030: id = 0; break; |
| 72 | default: |
| 73 | nv_error(priv, "ref: bad pll 0x%06x\n" , base); |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); |
| 78 | ref *= (coef & 0x01000000) ? 2 : 4; |
| 79 | P = (coef & 0x00070000) >> 16; |
| 80 | N = ((coef & 0x0000ff00) >> 8) + 1; |
| 81 | M = ((coef & 0x000000ff) >> 0) + 1; |
| 82 | break; |
| 83 | case 0x84: |
| 84 | case 0x86: |
| 85 | case 0x92: |
| 86 | coef = nv_rd32(priv, 0x00e81c); |
| 87 | P = (coef & 0x00070000) >> 16; |
| 88 | N = (coef & 0x0000ff00) >> 8; |
| 89 | M = (coef & 0x000000ff) >> 0; |
| 90 | break; |
| 91 | case 0x94: |
| 92 | case 0x96: |
| 93 | case 0x98: |
| 94 | rsel = nv_rd32(priv, 0x00c050); |
| 95 | switch (base) { |
| 96 | case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; |
| 97 | case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; |
| 98 | case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; |
| 99 | case 0x4030: rsel = 3; break; |
| 100 | default: |
| 101 | nv_error(priv, "ref: bad pll 0x%06x\n" , base); |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | switch (rsel) { |
| 106 | case 0: id = 1; break; |
| 107 | case 1: return clk->read(clk, nv_clk_src_crystal); |
| 108 | case 2: return clk->read(clk, nv_clk_src_href); |
| 109 | case 3: id = 0; break; |
| 110 | } |
| 111 | |
| 112 | coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); |
| 113 | P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; |
| 114 | P += (coef & 0x00070000) >> 16; |
| 115 | N = (coef & 0x0000ff00) >> 8; |
| 116 | M = (coef & 0x000000ff) >> 0; |
| 117 | break; |
| 118 | default: |
| 119 | BUG_ON(1); |
| 120 | M = 0; /* XXX GCC is stupid */ |
| 121 | N = 0; /* XXX GCC is stupid */ |
| 122 | P = 0; /* XXX GCC is stupid */ |
| 123 | } |
| 124 | |
| 125 | if (M) |
| 126 | return (ref * N / M) >> P; |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | static u32 |
| 131 | read_pll_ref(struct nv50_clock_priv *priv, u32 base) |
| 132 | { |
| 133 | struct nouveau_clock *clk = &priv->base; |
| 134 | u32 src, mast = nv_rd32(priv, 0x00c040); |
| 135 | |
| 136 | switch (base) { |
| 137 | case 0x004028: |
| 138 | src = !!(mast & 0x00200000); |
| 139 | break; |
| 140 | case 0x004020: |
| 141 | src = !!(mast & 0x00400000); |
| 142 | break; |
| 143 | case 0x004008: |
| 144 | src = !!(mast & 0x00010000); |
| 145 | break; |
| 146 | case 0x004030: |
| 147 | src = !!(mast & 0x02000000); |
| 148 | break; |
| 149 | case 0x00e810: |
| 150 | return clk->read(clk, nv_clk_src_crystal); |
| 151 | default: |
| 152 | nv_error(priv, "bad pll 0x%06x\n" , base); |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | if (src) |
| 157 | return clk->read(clk, nv_clk_src_href); |
| 158 | return read_pll_src(priv, base); |
| 159 | } |
| 160 | |
| 161 | static u32 |
| 162 | read_pll(struct nv50_clock_priv *priv, u32 base) |
| 163 | { |
| 164 | struct nouveau_clock *clk = &priv->base; |
| 165 | u32 mast = nv_rd32(priv, 0x00c040); |
| 166 | u32 ctrl = nv_rd32(priv, base + 0); |
| 167 | u32 coef = nv_rd32(priv, base + 4); |
| 168 | u32 ref = read_pll_ref(priv, base); |
| 169 | u32 freq = 0; |
| 170 | int N1, N2, M1, M2; |
| 171 | |
| 172 | if (base == 0x004028 && (mast & 0x00100000)) { |
| 173 | /* wtf, appears to only disable post-divider on nva0 */ |
| 174 | if (nv_device(priv)->chipset != 0xa0) |
| 175 | return clk->read(clk, nv_clk_src_dom6); |
| 176 | } |
| 177 | |
| 178 | N2 = (coef & 0xff000000) >> 24; |
| 179 | M2 = (coef & 0x00ff0000) >> 16; |
| 180 | N1 = (coef & 0x0000ff00) >> 8; |
| 181 | M1 = (coef & 0x000000ff); |
| 182 | if ((ctrl & 0x80000000) && M1) { |
| 183 | freq = ref * N1 / M1; |
| 184 | if ((ctrl & 0x40000100) == 0x40000000) { |
| 185 | if (M2) |
| 186 | freq = freq * N2 / M2; |
| 187 | else |
| 188 | freq = 0; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | return freq; |
| 193 | } |
| 194 | |
| 195 | static int |
| 196 | nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) |
| 197 | { |
| 198 | struct nv50_clock_priv *priv = (void *)clk; |
| 199 | u32 mast = nv_rd32(priv, 0x00c040); |
| 200 | u32 P = 0; |
| 201 | |
| 202 | switch (src) { |
| 203 | case nv_clk_src_crystal: |
| 204 | return nv_device(priv)->crystal; |
| 205 | case nv_clk_src_href: |
| 206 | return 100000; /* PCIE reference clock */ |
| 207 | case nv_clk_src_hclk: |
| 208 | return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); |
| 209 | case nv_clk_src_hclkm3: |
| 210 | return clk->read(clk, nv_clk_src_hclk) * 3; |
| 211 | case nv_clk_src_hclkm3d2: |
| 212 | return clk->read(clk, nv_clk_src_hclk) * 3 / 2; |
| 213 | case nv_clk_src_host: |
| 214 | switch (mast & 0x30000000) { |
| 215 | case 0x00000000: return clk->read(clk, nv_clk_src_href); |
| 216 | case 0x10000000: break; |
| 217 | case 0x20000000: /* !0x50 */ |
| 218 | case 0x30000000: return clk->read(clk, nv_clk_src_hclk); |
| 219 | } |
| 220 | break; |
| 221 | case nv_clk_src_core: |
| 222 | if (!(mast & 0x00100000)) |
| 223 | P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; |
| 224 | switch (mast & 0x00000003) { |
| 225 | case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; |
| 226 | case 0x00000001: return clk->read(clk, nv_clk_src_dom6); |
| 227 | case 0x00000002: return read_pll(priv, 0x004020) >> P; |
| 228 | case 0x00000003: return read_pll(priv, 0x004028) >> P; |
| 229 | } |
| 230 | break; |
| 231 | case nv_clk_src_shader: |
| 232 | P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; |
| 233 | switch (mast & 0x00000030) { |
| 234 | case 0x00000000: |
| 235 | if (mast & 0x00000080) |
| 236 | return clk->read(clk, nv_clk_src_host) >> P; |
| 237 | return clk->read(clk, nv_clk_src_crystal) >> P; |
| 238 | case 0x00000010: break; |
| 239 | case 0x00000020: return read_pll(priv, 0x004028) >> P; |
| 240 | case 0x00000030: return read_pll(priv, 0x004020) >> P; |
| 241 | } |
| 242 | break; |
| 243 | case nv_clk_src_mem: |
| 244 | P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; |
| 245 | if (nv_rd32(priv, 0x004008) & 0x00000200) { |
| 246 | switch (mast & 0x0000c000) { |
| 247 | case 0x00000000: |
| 248 | return clk->read(clk, nv_clk_src_crystal) >> P; |
| 249 | case 0x00008000: |
| 250 | case 0x0000c000: |
| 251 | return clk->read(clk, nv_clk_src_href) >> P; |
| 252 | } |
| 253 | } else { |
| 254 | return read_pll(priv, 0x004008) >> P; |
| 255 | } |
| 256 | break; |
| 257 | case nv_clk_src_vdec: |
| 258 | P = (read_div(priv) & 0x00000700) >> 8; |
| 259 | switch (nv_device(priv)->chipset) { |
| 260 | case 0x84: |
| 261 | case 0x86: |
| 262 | case 0x92: |
| 263 | case 0x94: |
| 264 | case 0x96: |
| 265 | case 0xa0: |
| 266 | switch (mast & 0x00000c00) { |
| 267 | case 0x00000000: |
| 268 | if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ |
| 269 | return clk->read(clk, nv_clk_src_core) >> P; |
| 270 | return clk->read(clk, nv_clk_src_crystal) >> P; |
| 271 | case 0x00000400: |
| 272 | return 0; |
| 273 | case 0x00000800: |
| 274 | if (mast & 0x01000000) |
| 275 | return read_pll(priv, 0x004028) >> P; |
| 276 | return read_pll(priv, 0x004030) >> P; |
| 277 | case 0x00000c00: |
| 278 | return clk->read(clk, nv_clk_src_core) >> P; |
| 279 | } |
| 280 | break; |
| 281 | case 0x98: |
| 282 | switch (mast & 0x00000c00) { |
| 283 | case 0x00000000: |
| 284 | return clk->read(clk, nv_clk_src_core) >> P; |
| 285 | case 0x00000400: |
| 286 | return 0; |
| 287 | case 0x00000800: |
| 288 | return clk->read(clk, nv_clk_src_hclkm3d2) >> P; |
| 289 | case 0x00000c00: |
| 290 | return clk->read(clk, nv_clk_src_mem) >> P; |
| 291 | } |
| 292 | break; |
| 293 | } |
| 294 | break; |
| 295 | case nv_clk_src_dom6: |
| 296 | switch (nv_device(priv)->chipset) { |
| 297 | case 0x50: |
| 298 | case 0xa0: |
| 299 | return read_pll(priv, 0x00e810) >> 2; |
| 300 | case 0x84: |
| 301 | case 0x86: |
| 302 | case 0x92: |
| 303 | case 0x94: |
| 304 | case 0x96: |
| 305 | case 0x98: |
| 306 | P = (read_div(priv) & 0x00000007) >> 0; |
| 307 | switch (mast & 0x0c000000) { |
| 308 | case 0x00000000: return clk->read(clk, nv_clk_src_href); |
| 309 | case 0x04000000: break; |
| 310 | case 0x08000000: return clk->read(clk, nv_clk_src_hclk); |
| 311 | case 0x0c000000: |
| 312 | return clk->read(clk, nv_clk_src_hclkm3) >> P; |
| 313 | } |
| 314 | break; |
| 315 | default: |
| 316 | break; |
| 317 | } |
| 318 | default: |
| 319 | break; |
| 320 | } |
| 321 | |
| 322 | nv_debug(priv, "unknown clock source %d 0x%08x\n" , src, mast); |
| 323 | return -EINVAL; |
| 324 | } |
| 325 | |
| 326 | static u32 |
| 327 | calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) |
| 328 | { |
| 329 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 330 | struct nvbios_pll pll; |
| 331 | int ret; |
| 332 | |
| 333 | ret = nvbios_pll_parse(bios, reg, &pll); |
| 334 | if (ret) |
| 335 | return 0; |
| 336 | |
| 337 | pll.vco2.max_freq = 0; |
| 338 | pll.refclk = read_pll_ref(priv, reg); |
| 339 | if (!pll.refclk) |
| 340 | return 0; |
| 341 | |
| 342 | return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); |
| 343 | } |
| 344 | |
| 345 | static inline u32 |
| 346 | calc_div(u32 src, u32 target, int *div) |
| 347 | { |
| 348 | u32 clk0 = src, clk1 = src; |
| 349 | for (*div = 0; *div <= 7; (*div)++) { |
| 350 | if (clk0 <= target) { |
| 351 | clk1 = clk0 << (*div ? 1 : 0); |
| 352 | break; |
| 353 | } |
| 354 | clk0 >>= 1; |
| 355 | } |
| 356 | |
| 357 | if (target - clk0 <= clk1 - target) |
| 358 | return clk0; |
| 359 | (*div)--; |
| 360 | return clk1; |
| 361 | } |
| 362 | |
| 363 | static inline u32 |
| 364 | clk_same(u32 a, u32 b) |
| 365 | { |
| 366 | return ((a / 1000) == (b / 1000)); |
| 367 | } |
| 368 | |
| 369 | static int |
| 370 | nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) |
| 371 | { |
| 372 | struct nv50_clock_priv *priv = (void *)clk; |
| 373 | struct nv50_clock_hwsq *hwsq = &priv->hwsq; |
| 374 | const int shader = cstate->domain[nv_clk_src_shader]; |
| 375 | const int core = cstate->domain[nv_clk_src_core]; |
| 376 | const int vdec = cstate->domain[nv_clk_src_vdec]; |
| 377 | const int dom6 = cstate->domain[nv_clk_src_dom6]; |
| 378 | u32 mastm = 0, mastv = 0; |
| 379 | u32 divsm = 0, divsv = 0; |
| 380 | int N, M, P1, P2; |
| 381 | int freq, out; |
| 382 | |
| 383 | /* prepare a hwsq script from which we'll perform the reclock */ |
| 384 | out = clk_init(hwsq, nv_subdev(clk)); |
| 385 | if (out) |
| 386 | return out; |
| 387 | |
| 388 | clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ |
| 389 | clk_nsec(hwsq, 8000); |
| 390 | clk_setf(hwsq, 0x10, 0x00); /* disable fb */ |
| 391 | clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ |
| 392 | |
| 393 | /* vdec: avoid modifying xpll until we know exactly how the other |
| 394 | * clock domains work, i suspect at least some of them can also be |
| 395 | * tied to xpll... |
| 396 | */ |
| 397 | if (vdec) { |
| 398 | /* see how close we can get using nvclk as a source */ |
| 399 | freq = calc_div(core, vdec, &P1); |
| 400 | |
| 401 | /* see how close we can get using xpll/hclk as a source */ |
| 402 | if (nv_device(priv)->chipset != 0x98) |
| 403 | out = read_pll(priv, 0x004030); |
| 404 | else |
| 405 | out = clk->read(clk, nv_clk_src_hclkm3d2); |
| 406 | out = calc_div(out, vdec, &P2); |
| 407 | |
| 408 | /* select whichever gets us closest */ |
| 409 | if (abs(vdec - freq) <= abs(vdec - out)) { |
| 410 | if (nv_device(priv)->chipset != 0x98) |
| 411 | mastv |= 0x00000c00; |
| 412 | divsv |= P1 << 8; |
| 413 | } else { |
| 414 | mastv |= 0x00000800; |
| 415 | divsv |= P2 << 8; |
| 416 | } |
| 417 | |
| 418 | mastm |= 0x00000c00; |
| 419 | divsm |= 0x00000700; |
| 420 | } |
| 421 | |
| 422 | /* dom6: nfi what this is, but we're limited to various combinations |
| 423 | * of the host clock frequency |
| 424 | */ |
| 425 | if (dom6) { |
| 426 | if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { |
| 427 | mastv |= 0x00000000; |
| 428 | } else |
| 429 | if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { |
| 430 | mastv |= 0x08000000; |
| 431 | } else { |
| 432 | freq = clk->read(clk, nv_clk_src_hclk) * 3; |
| 433 | freq = calc_div(freq, dom6, &P1); |
| 434 | |
| 435 | mastv |= 0x0c000000; |
| 436 | divsv |= P1; |
| 437 | } |
| 438 | |
| 439 | mastm |= 0x0c000000; |
| 440 | divsm |= 0x00000007; |
| 441 | } |
| 442 | |
| 443 | /* vdec/dom6: switch to "safe" clocks temporarily, update dividers |
| 444 | * and then switch to target clocks |
| 445 | */ |
| 446 | clk_mask(hwsq, mast, mastm, 0x00000000); |
| 447 | clk_mask(hwsq, divs, divsm, divsv); |
| 448 | clk_mask(hwsq, mast, mastm, mastv); |
| 449 | |
| 450 | /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, |
| 451 | * sclk to hclk) before reprogramming |
| 452 | */ |
| 453 | if (nv_device(priv)->chipset < 0x92) |
| 454 | clk_mask(hwsq, mast, 0x001000b0, 0x00100080); |
| 455 | else |
| 456 | clk_mask(hwsq, mast, 0x000000b3, 0x00000081); |
| 457 | |
| 458 | /* core: for the moment at least, always use nvpll */ |
| 459 | freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); |
| 460 | if (freq == 0) |
| 461 | return -ERANGE; |
| 462 | |
| 463 | clk_mask(hwsq, nvpll[0], 0xc03f0100, |
| 464 | 0x80000000 | (P1 << 19) | (P1 << 16)); |
| 465 | clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); |
| 466 | |
| 467 | /* shader: tie to nvclk if possible, otherwise use spll. have to be |
| 468 | * very careful that the shader clock is at least twice the core, or |
| 469 | * some chipsets will be very unhappy. i expect most or all of these |
| 470 | * cases will be handled by tying to nvclk, but it's possible there's |
| 471 | * corners |
| 472 | */ |
| 473 | if (P1-- && shader == (core << 1)) { |
| 474 | clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); |
| 475 | clk_mask(hwsq, mast, 0x00100033, 0x00000023); |
| 476 | } else { |
| 477 | freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); |
| 478 | if (freq == 0) |
| 479 | return -ERANGE; |
| 480 | |
| 481 | clk_mask(hwsq, spll[0], 0xc03f0100, |
| 482 | 0x80000000 | (P1 << 19) | (P1 << 16)); |
| 483 | clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); |
| 484 | clk_mask(hwsq, mast, 0x00100033, 0x00000033); |
| 485 | } |
| 486 | |
| 487 | /* restore normal operation */ |
| 488 | clk_setf(hwsq, 0x10, 0x01); /* enable fb */ |
| 489 | clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ |
| 490 | clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static int |
| 495 | nv50_clock_prog(struct nouveau_clock *clk) |
| 496 | { |
| 497 | struct nv50_clock_priv *priv = (void *)clk; |
| 498 | return clk_exec(&priv->hwsq, true); |
| 499 | } |
| 500 | |
| 501 | static void |
| 502 | nv50_clock_tidy(struct nouveau_clock *clk) |
| 503 | { |
| 504 | struct nv50_clock_priv *priv = (void *)clk; |
| 505 | clk_exec(&priv->hwsq, false); |
| 506 | } |
| 507 | |
| 508 | int |
| 509 | nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 510 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 511 | struct nouveau_object **pobject) |
| 512 | { |
| 513 | struct nv50_clock_oclass *pclass = (void *)oclass; |
| 514 | struct nv50_clock_priv *priv; |
| 515 | int ret; |
| 516 | |
| 517 | ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, |
| 518 | &priv); |
| 519 | *pobject = nv_object(priv); |
| 520 | if (ret) |
| 521 | return ret; |
| 522 | |
| 523 | priv->hwsq.r_fifo = hwsq_reg(0x002504); |
| 524 | priv->hwsq.r_spll[0] = hwsq_reg(0x004020); |
| 525 | priv->hwsq.r_spll[1] = hwsq_reg(0x004024); |
| 526 | priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); |
| 527 | priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); |
| 528 | switch (nv_device(priv)->chipset) { |
| 529 | case 0x92: |
| 530 | case 0x94: |
| 531 | case 0x96: |
| 532 | priv->hwsq.r_divs = hwsq_reg(0x004800); |
| 533 | break; |
| 534 | default: |
| 535 | priv->hwsq.r_divs = hwsq_reg(0x004700); |
| 536 | break; |
| 537 | } |
| 538 | priv->hwsq.r_mast = hwsq_reg(0x00c040); |
| 539 | |
| 540 | priv->base.read = nv50_clock_read; |
| 541 | priv->base.calc = nv50_clock_calc; |
| 542 | priv->base.prog = nv50_clock_prog; |
| 543 | priv->base.tidy = nv50_clock_tidy; |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | static struct nouveau_clocks |
| 548 | nv50_domains[] = { |
| 549 | { nv_clk_src_crystal, 0xff }, |
| 550 | { nv_clk_src_href , 0xff }, |
| 551 | { nv_clk_src_core , 0xff, 0, "core" , 1000 }, |
| 552 | { nv_clk_src_shader , 0xff, 0, "shader" , 1000 }, |
| 553 | { nv_clk_src_mem , 0xff, 0, "memory" , 1000 }, |
| 554 | { nv_clk_src_max } |
| 555 | }; |
| 556 | |
| 557 | struct nouveau_oclass * |
| 558 | nv50_clock_oclass = &(struct nv50_clock_oclass) { |
| 559 | .base.handle = NV_SUBDEV(CLOCK, 0x50), |
| 560 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 561 | .ctor = nv50_clock_ctor, |
| 562 | .dtor = _nouveau_clock_dtor, |
| 563 | .init = _nouveau_clock_init, |
| 564 | .fini = _nouveau_clock_fini, |
| 565 | }, |
| 566 | .domains = nv50_domains, |
| 567 | }.base; |
| 568 | |