| 1 | /* $NetBSD: rtsx.c,v 1.2 2014/10/29 14:24:09 nonaka Exp $ */ |
| 2 | /* $OpenBSD: rtsx.c,v 1.10 2014/08/19 17:55:03 phessler Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> |
| 6 | * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Realtek RTS5209/RTS5227/RTS5229/RTL8402/RTL8411/RTL8411B Card Reader driver. |
| 23 | */ |
| 24 | |
| 25 | #include <sys/cdefs.h> |
| 26 | __KERNEL_RCSID(0, "$NetBSD: rtsx.c,v 1.2 2014/10/29 14:24:09 nonaka Exp $" ); |
| 27 | |
| 28 | #include <sys/param.h> |
| 29 | #include <sys/device.h> |
| 30 | #include <sys/kernel.h> |
| 31 | #include <sys/systm.h> |
| 32 | #include <sys/proc.h> |
| 33 | #include <sys/mutex.h> |
| 34 | |
| 35 | #include <dev/ic/rtsxreg.h> |
| 36 | #include <dev/ic/rtsxvar.h> |
| 37 | |
| 38 | #include <dev/sdmmc/sdmmcvar.h> |
| 39 | #include <dev/sdmmc/sdmmc_ioreg.h> |
| 40 | |
| 41 | /* |
| 42 | * We use two DMA buffers, a command buffer and a data buffer. |
| 43 | * |
| 44 | * The command buffer contains a command queue for the host controller, |
| 45 | * which describes SD/MMC commands to run, and other parameters. The chip |
| 46 | * runs the command queue when a special bit in the RTSX_HCBAR register is set |
| 47 | * and signals completion with the TRANS_OK interrupt. |
| 48 | * Each command is encoded as a 4 byte sequence containing command number |
| 49 | * (read, write, or check a host controller register), a register address, |
| 50 | * and a data bit-mask and value. |
| 51 | * |
| 52 | * The data buffer is used to transfer data sectors to or from the SD card. |
| 53 | * Data transfer is controlled via the RTSX_HDBAR register. Completion is |
| 54 | * also signalled by the TRANS_OK interrupt. |
| 55 | * |
| 56 | * The chip is unable to perform DMA above 4GB. |
| 57 | * |
| 58 | * SD/MMC commands which do not transfer any data from/to the card only use |
| 59 | * the command buffer. |
| 60 | */ |
| 61 | |
| 62 | #define RTSX_DMA_MAX_SEGSIZE 0x80000 |
| 63 | #define RTSX_HOSTCMD_MAX 256 |
| 64 | #define RTSX_HOSTCMD_BUFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) |
| 65 | #define RTSX_DMA_DATA_BUFSIZE MAXPHYS |
| 66 | |
| 67 | #define READ4(sc, reg) \ |
| 68 | (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) |
| 69 | #define WRITE4(sc, reg, val) \ |
| 70 | bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) |
| 71 | |
| 72 | #define RTSX_READ(sc, reg, val) \ |
| 73 | do { \ |
| 74 | int err = rtsx_read((sc), (reg), (val)); \ |
| 75 | if (err) \ |
| 76 | return err; \ |
| 77 | } while (/*CONSTCOND*/0) |
| 78 | |
| 79 | #define RTSX_WRITE(sc, reg, val) \ |
| 80 | do { \ |
| 81 | int err = rtsx_write((sc), (reg), 0xff, (val)); \ |
| 82 | if (err) \ |
| 83 | return err; \ |
| 84 | } while (/*CONSTCOND*/0) |
| 85 | |
| 86 | #define RTSX_CLR(sc, reg, bits) \ |
| 87 | do { \ |
| 88 | int err = rtsx_write((sc), (reg), (bits), 0); \ |
| 89 | if (err) \ |
| 90 | return err; \ |
| 91 | } while (/*CONSTCOND*/0) |
| 92 | |
| 93 | #define RTSX_SET(sc, reg, bits) \ |
| 94 | do { \ |
| 95 | int err = rtsx_write((sc), (reg), (bits), 0xff);\ |
| 96 | if (err) \ |
| 97 | return err; \ |
| 98 | } while (/*CONSTCOND*/0) |
| 99 | |
| 100 | #define RTSX_BITOP(sc, reg, mask, bits) \ |
| 101 | do { \ |
| 102 | int err = rtsx_write((sc), (reg), (mask), (bits));\ |
| 103 | if (err) \ |
| 104 | return err; \ |
| 105 | } while (/*CONSTCOND*/0) |
| 106 | |
| 107 | static int rtsx_host_reset(sdmmc_chipset_handle_t); |
| 108 | static uint32_t rtsx_host_ocr(sdmmc_chipset_handle_t); |
| 109 | static int rtsx_host_maxblklen(sdmmc_chipset_handle_t); |
| 110 | static int rtsx_card_detect(sdmmc_chipset_handle_t); |
| 111 | static int rtsx_write_protect(sdmmc_chipset_handle_t); |
| 112 | static int rtsx_bus_power(sdmmc_chipset_handle_t, uint32_t); |
| 113 | static int rtsx_bus_clock(sdmmc_chipset_handle_t, int); |
| 114 | static int rtsx_bus_width(sdmmc_chipset_handle_t, int); |
| 115 | static int rtsx_bus_rod(sdmmc_chipset_handle_t, int); |
| 116 | static void rtsx_exec_command(sdmmc_chipset_handle_t, |
| 117 | struct sdmmc_command *); |
| 118 | static int rtsx_init(struct rtsx_softc *, int); |
| 119 | static void rtsx_soft_reset(struct rtsx_softc *); |
| 120 | static int rtsx_bus_power_off(struct rtsx_softc *); |
| 121 | static int rtsx_bus_power_on(struct rtsx_softc *); |
| 122 | static int rtsx_set_bus_width(struct rtsx_softc *, int); |
| 123 | static int rtsx_stop_sd_clock(struct rtsx_softc *); |
| 124 | static int rtsx_switch_sd_clock(struct rtsx_softc *, uint8_t, int, int); |
| 125 | static int rtsx_wait_intr(struct rtsx_softc *, int, int); |
| 126 | static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); |
| 127 | static int rtsx_write(struct rtsx_softc *, uint16_t, uint8_t, uint8_t); |
| 128 | #ifdef notyet |
| 129 | static int rtsx_read_phy(struct rtsx_softc *, uint8_t, uint16_t *); |
| 130 | #endif |
| 131 | static int rtsx_write_phy(struct rtsx_softc *, uint8_t, uint16_t); |
| 132 | static int rtsx_read_cfg(struct rtsx_softc *, uint8_t, uint16_t, |
| 133 | uint32_t *); |
| 134 | #ifdef notyet |
| 135 | static int rtsx_write_cfg(struct rtsx_softc *, uint8_t, uint16_t, uint32_t, |
| 136 | uint32_t); |
| 137 | #endif |
| 138 | static void rtsx_hostcmd(uint32_t *, int *, uint8_t, uint16_t, uint8_t, |
| 139 | uint8_t); |
| 140 | static int rtsx_hostcmd_send(struct rtsx_softc *, int); |
| 141 | static uint8_t rtsx_response_type(uint16_t); |
| 142 | static int rtsx_read_ppbuf(struct rtsx_softc *, struct sdmmc_command *, |
| 143 | uint32_t *); |
| 144 | static int rtsx_write_ppbuf(struct rtsx_softc *, struct sdmmc_command *, |
| 145 | uint32_t *); |
| 146 | static int rtsx_exec_short_xfer(struct rtsx_softc *, |
| 147 | struct sdmmc_command *, uint32_t *, uint8_t); |
| 148 | static int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, |
| 149 | uint32_t *); |
| 150 | static void rtsx_card_insert(struct rtsx_softc *); |
| 151 | static void rtsx_card_eject(struct rtsx_softc *); |
| 152 | static int rtsx_led_enable(struct rtsx_softc *); |
| 153 | static int rtsx_led_disable(struct rtsx_softc *); |
| 154 | static void rtsx_save_regs(struct rtsx_softc *); |
| 155 | static void rtsx_restore_regs(struct rtsx_softc *); |
| 156 | |
| 157 | #ifdef RTSX_DEBUG |
| 158 | int rtsxdebug = 0; |
| 159 | #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) |
| 160 | #else |
| 161 | #define DPRINTF(n,s) /**/ |
| 162 | #endif |
| 163 | |
| 164 | #define DEVNAME(sc) SDMMCDEVNAME(sc) |
| 165 | |
| 166 | static struct sdmmc_chip_functions rtsx_chip_functions = { |
| 167 | /* host controller reset */ |
| 168 | .host_reset = rtsx_host_reset, |
| 169 | |
| 170 | /* host controller capabilities */ |
| 171 | .host_ocr = rtsx_host_ocr, |
| 172 | .host_maxblklen = rtsx_host_maxblklen, |
| 173 | |
| 174 | /* card detection */ |
| 175 | .card_detect = rtsx_card_detect, |
| 176 | |
| 177 | /* write protect */ |
| 178 | .write_protect = rtsx_write_protect, |
| 179 | |
| 180 | /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ |
| 181 | .bus_power = rtsx_bus_power, |
| 182 | .bus_clock = rtsx_bus_clock, |
| 183 | .bus_width = rtsx_bus_width, |
| 184 | .bus_rod = rtsx_bus_rod, |
| 185 | |
| 186 | /* command execution */ |
| 187 | .exec_command = rtsx_exec_command, |
| 188 | |
| 189 | /* card interrupt */ |
| 190 | .card_enable_intr = NULL, |
| 191 | .card_intr_ack = NULL, |
| 192 | }; |
| 193 | |
| 194 | /* |
| 195 | * Called by attachment driver. |
| 196 | */ |
| 197 | int |
| 198 | rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, |
| 199 | bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) |
| 200 | { |
| 201 | struct sdmmcbus_attach_args saa; |
| 202 | uint32_t sdio_cfg; |
| 203 | |
| 204 | sc->sc_iot = iot; |
| 205 | sc->sc_ioh = ioh; |
| 206 | sc->sc_iosize = iosize; |
| 207 | sc->sc_dmat = dmat; |
| 208 | sc->sc_flags = flags; |
| 209 | |
| 210 | mutex_init(&sc->sc_host_mtx, MUTEX_DEFAULT, IPL_SDMMC); |
| 211 | mutex_init(&sc->sc_intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); |
| 212 | cv_init(&sc->sc_intr_cv, "rtsxintr" ); |
| 213 | |
| 214 | if (rtsx_init(sc, 1)) |
| 215 | goto error; |
| 216 | |
| 217 | if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { |
| 218 | if (sdio_cfg & (RTSX_SDIOCFG_SDIO_ONLY|RTSX_SDIOCFG_HAVE_SDIO)){ |
| 219 | sc->sc_flags |= RTSX_F_SDIO_SUPPORT; |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | if (bus_dmamap_create(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 1, |
| 224 | RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, |
| 225 | &sc->sc_dmap_cmd) != 0) |
| 226 | goto error; |
| 227 | |
| 228 | /* |
| 229 | * Attach the generic SD/MMC bus driver. (The bus driver must |
| 230 | * not invoke any chipset functions before it is attached.) |
| 231 | */ |
| 232 | memset(&saa, 0, sizeof(saa)); |
| 233 | saa.saa_busname = "sdmmc" ; |
| 234 | saa.saa_sct = &rtsx_chip_functions; |
| 235 | saa.saa_spi_sct = NULL; |
| 236 | saa.saa_sch = sc; |
| 237 | saa.saa_dmat = sc->sc_dmat; |
| 238 | saa.saa_clkmin = SDMMC_SDCLK_400K; |
| 239 | saa.saa_clkmax = 25000; |
| 240 | saa.saa_caps = SMC_CAPS_DMA|SMC_CAPS_4BIT_MODE; |
| 241 | |
| 242 | sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); |
| 243 | if (sc->sc_sdmmc == NULL) |
| 244 | goto destroy_dmamap_cmd; |
| 245 | |
| 246 | /* Now handle cards discovered during attachment. */ |
| 247 | if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) |
| 248 | rtsx_card_insert(sc); |
| 249 | |
| 250 | return 0; |
| 251 | |
| 252 | destroy_dmamap_cmd: |
| 253 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd); |
| 254 | error: |
| 255 | cv_destroy(&sc->sc_intr_cv); |
| 256 | mutex_destroy(&sc->sc_intr_mtx); |
| 257 | mutex_destroy(&sc->sc_host_mtx); |
| 258 | return 1; |
| 259 | } |
| 260 | |
| 261 | int |
| 262 | rtsx_detach(struct rtsx_softc *sc, int flags) |
| 263 | { |
| 264 | int rv; |
| 265 | |
| 266 | if (sc->sc_sdmmc != NULL) { |
| 267 | rv = config_detach(sc->sc_sdmmc, flags); |
| 268 | if (rv != 0) |
| 269 | return rv; |
| 270 | sc->sc_sdmmc = NULL; |
| 271 | } |
| 272 | |
| 273 | /* disable interrupts */ |
| 274 | if ((flags & DETACH_FORCE) == 0) { |
| 275 | WRITE4(sc, RTSX_BIER, 0); |
| 276 | rtsx_soft_reset(sc); |
| 277 | } |
| 278 | |
| 279 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd); |
| 280 | cv_destroy(&sc->sc_intr_cv); |
| 281 | mutex_destroy(&sc->sc_intr_mtx); |
| 282 | mutex_destroy(&sc->sc_host_mtx); |
| 283 | bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | bool |
| 289 | rtsx_suspend(device_t dev, const pmf_qual_t *qual) |
| 290 | { |
| 291 | struct rtsx_softc *sc = device_private(dev); |
| 292 | |
| 293 | /* Save the host controller state. */ |
| 294 | rtsx_save_regs(sc); |
| 295 | |
| 296 | return true; |
| 297 | } |
| 298 | |
| 299 | bool |
| 300 | rtsx_resume(device_t dev, const pmf_qual_t *qual) |
| 301 | { |
| 302 | struct rtsx_softc *sc = device_private(dev); |
| 303 | |
| 304 | /* Restore the host controller state. */ |
| 305 | rtsx_restore_regs(sc); |
| 306 | |
| 307 | if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) |
| 308 | rtsx_card_insert(sc); |
| 309 | else |
| 310 | rtsx_card_eject(sc); |
| 311 | |
| 312 | return true; |
| 313 | } |
| 314 | |
| 315 | bool |
| 316 | rtsx_shutdown(device_t dev, int flags) |
| 317 | { |
| 318 | struct rtsx_softc *sc = device_private(dev); |
| 319 | |
| 320 | /* XXX chip locks up if we don't disable it before reboot. */ |
| 321 | (void)rtsx_host_reset(sc); |
| 322 | |
| 323 | return true; |
| 324 | } |
| 325 | |
| 326 | static int |
| 327 | rtsx_init(struct rtsx_softc *sc, int attaching) |
| 328 | { |
| 329 | uint32_t status; |
| 330 | uint8_t reg; |
| 331 | int error; |
| 332 | |
| 333 | if (attaching) { |
| 334 | if (RTSX_IS_RTS5229(sc)) { |
| 335 | /* Read IC version from dummy register. */ |
| 336 | RTSX_READ(sc, RTSX_DUMMY_REG, ®); |
| 337 | switch (reg & 0x0f) { |
| 338 | case RTSX_IC_VERSION_A: |
| 339 | case RTSX_IC_VERSION_B: |
| 340 | case RTSX_IC_VERSION_D: |
| 341 | break; |
| 342 | case RTSX_IC_VERSION_C: |
| 343 | sc->sc_flags |= RTSX_F_5229_TYPE_C; |
| 344 | break; |
| 345 | default: |
| 346 | aprint_error_dev(sc->sc_dev, |
| 347 | "unknown RTS5229 version 0x%02x\n" , reg); |
| 348 | return 1; |
| 349 | } |
| 350 | } else if (RTSX_IS_RTL8411B(sc)) { |
| 351 | RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, ®); |
| 352 | if (reg & RTSX_RTL8411B_QFN48) |
| 353 | sc->sc_flags |= RTSX_F_8411B_QFN48; |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | /* Enable interrupt write-clear (default is read-clear). */ |
| 358 | RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); |
| 359 | |
| 360 | /* Clear any pending interrupts. */ |
| 361 | status = READ4(sc, RTSX_BIPR); |
| 362 | WRITE4(sc, RTSX_BIPR, status); |
| 363 | |
| 364 | /* Check for cards already inserted at attach time. */ |
| 365 | if (attaching && (status & RTSX_SD_EXIST)) |
| 366 | sc->sc_flags |= RTSX_F_CARD_PRESENT; |
| 367 | |
| 368 | /* Enable interrupts. */ |
| 369 | WRITE4(sc, RTSX_BIER, |
| 370 | RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); |
| 371 | |
| 372 | /* Power on SSC clock. */ |
| 373 | RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); |
| 374 | delay(200); |
| 375 | |
| 376 | /* XXX magic numbers from linux driver */ |
| 377 | if (RTSX_IS_RTS5209(sc)) |
| 378 | error = rtsx_write_phy(sc, 0x00, 0xB966); |
| 379 | else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) |
| 380 | error = rtsx_write_phy(sc, 0x00, 0xBA42); |
| 381 | else |
| 382 | error = 0; |
| 383 | if (error) { |
| 384 | aprint_error_dev(sc->sc_dev, "couldn't write phy register\n" ); |
| 385 | return 1; |
| 386 | } |
| 387 | |
| 388 | RTSX_SET(sc, RTSX_CLK_DIV, 0x07); |
| 389 | |
| 390 | /* Disable sleep mode. */ |
| 391 | RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, |
| 392 | RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); |
| 393 | |
| 394 | /* Disable card clock. */ |
| 395 | RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); |
| 396 | |
| 397 | RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, |
| 398 | RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); |
| 399 | RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); |
| 400 | |
| 401 | /* Enable SSC clock. */ |
| 402 | RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); |
| 403 | RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); |
| 404 | |
| 405 | RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); |
| 406 | RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); |
| 407 | |
| 408 | RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); |
| 409 | |
| 410 | /* Set RC oscillator to 400K. */ |
| 411 | RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); |
| 412 | |
| 413 | /* Request clock by driving CLKREQ pin to zero. */ |
| 414 | RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); |
| 415 | |
| 416 | /* Set up LED GPIO. */ |
| 417 | if (RTSX_IS_RTS5209(sc)) { |
| 418 | RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); |
| 419 | RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); |
| 420 | } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 421 | RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); |
| 422 | /* Switch LDO3318 source from DV33 to 3V3. */ |
| 423 | RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); |
| 424 | RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); |
| 425 | /* Set default OLT blink period. */ |
| 426 | RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); |
| 427 | } else if (RTSX_IS_RTL8402(sc) |
| 428 | || RTSX_IS_RTL8411(sc) |
| 429 | || RTSX_IS_RTL8411B(sc)) { |
| 430 | if (RTSX_IS_RTL8411B_QFN48(sc)) |
| 431 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); |
| 432 | /* Enable SD interrupt */ |
| 433 | RTSX_WRITE(sc, RTSX_CARD_PAD_CTL, 0x05); |
| 434 | RTSX_BITOP(sc, RTSX_EFUSE_CONTENT, 0xe0, 0x80); |
| 435 | if (RTSX_IS_RTL8411B(sc)) |
| 436 | RTSX_WRITE(sc, RTSX_FUNC_FORCE_CTL, 0x00); |
| 437 | } |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | int |
| 443 | rtsx_led_enable(struct rtsx_softc *sc) |
| 444 | { |
| 445 | |
| 446 | if (RTSX_IS_RTS5209(sc)) { |
| 447 | RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); |
| 448 | RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, |
| 449 | RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); |
| 450 | } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 451 | RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); |
| 452 | RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); |
| 453 | } else if (RTSX_IS_RTL8402(sc) |
| 454 | || RTSX_IS_RTL8411(sc) |
| 455 | || RTSX_IS_RTL8411B(sc)) { |
| 456 | RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); |
| 457 | RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, |
| 458 | RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); |
| 459 | } |
| 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | int |
| 465 | rtsx_led_disable(struct rtsx_softc *sc) |
| 466 | { |
| 467 | |
| 468 | if (RTSX_IS_RTS5209(sc)) { |
| 469 | RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); |
| 470 | RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); |
| 471 | } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 472 | RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); |
| 473 | RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); |
| 474 | } else if (RTSX_IS_RTL8402(sc) |
| 475 | || RTSX_IS_RTL8411(sc) |
| 476 | || RTSX_IS_RTL8411B(sc)) { |
| 477 | RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); |
| 478 | RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); |
| 479 | } |
| 480 | |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | /* |
| 485 | * Reset the host controller. Called during initialization, when |
| 486 | * cards are removed, upon resume, and during error recovery. |
| 487 | */ |
| 488 | int |
| 489 | rtsx_host_reset(sdmmc_chipset_handle_t sch) |
| 490 | { |
| 491 | struct rtsx_softc *sc = sch; |
| 492 | int error; |
| 493 | |
| 494 | DPRINTF(1,("%s: host reset\n" , DEVNAME(sc))); |
| 495 | |
| 496 | mutex_enter(&sc->sc_host_mtx); |
| 497 | |
| 498 | if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) |
| 499 | rtsx_soft_reset(sc); |
| 500 | |
| 501 | error = rtsx_init(sc, 0); |
| 502 | |
| 503 | mutex_exit(&sc->sc_host_mtx); |
| 504 | |
| 505 | return error; |
| 506 | } |
| 507 | |
| 508 | static uint32_t |
| 509 | rtsx_host_ocr(sdmmc_chipset_handle_t sch) |
| 510 | { |
| 511 | |
| 512 | return RTSX_SUPPORT_VOLTAGE; |
| 513 | } |
| 514 | |
| 515 | static int |
| 516 | rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) |
| 517 | { |
| 518 | |
| 519 | return 512; |
| 520 | } |
| 521 | |
| 522 | /* |
| 523 | * Return non-zero if the card is currently inserted. |
| 524 | */ |
| 525 | static int |
| 526 | rtsx_card_detect(sdmmc_chipset_handle_t sch) |
| 527 | { |
| 528 | struct rtsx_softc *sc = sch; |
| 529 | |
| 530 | return ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT); |
| 531 | } |
| 532 | |
| 533 | static int |
| 534 | rtsx_write_protect(sdmmc_chipset_handle_t sch) |
| 535 | { |
| 536 | |
| 537 | return 0; /* XXX */ |
| 538 | } |
| 539 | |
| 540 | /* |
| 541 | * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and |
| 542 | * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 |
| 543 | * it is a mask of *enabled* gates. |
| 544 | */ |
| 545 | |
| 546 | static int |
| 547 | rtsx_bus_power_off(struct rtsx_softc *sc) |
| 548 | { |
| 549 | int error; |
| 550 | uint8_t disable3; |
| 551 | |
| 552 | error = rtsx_stop_sd_clock(sc); |
| 553 | if (error) |
| 554 | return error; |
| 555 | |
| 556 | /* Disable SD output. */ |
| 557 | RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); |
| 558 | |
| 559 | /* Turn off power. */ |
| 560 | disable3 = RTSX_PULL_CTL_DISABLE3; |
| 561 | if (RTSX_IS_RTS5209(sc)) |
| 562 | RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); |
| 563 | else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 564 | RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | |
| 565 | RTSX_LDO3318_VCC2); |
| 566 | if (RTSX_IS_RTS5229_TYPE_C(sc)) |
| 567 | disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; |
| 568 | } else if (RTSX_IS_RTL8402(sc) |
| 569 | || RTSX_IS_RTL8411(sc) |
| 570 | || RTSX_IS_RTL8411B(sc)) { |
| 571 | RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, |
| 572 | RTSX_BPP_POWER_OFF); |
| 573 | RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, |
| 574 | RTSX_BPP_LDO_SUSPEND); |
| 575 | } |
| 576 | |
| 577 | RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); |
| 578 | RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); |
| 579 | |
| 580 | /* Disable pull control. */ |
| 581 | if (RTSX_IS_RTS5209(sc) || RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 582 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); |
| 583 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); |
| 584 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); |
| 585 | } else if (RTSX_IS_RTL8402(sc) || RTSX_IS_RTL8411(sc)) { |
| 586 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); |
| 587 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x65); |
| 588 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); |
| 589 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); |
| 590 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); |
| 591 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); |
| 592 | } else if (RTSX_IS_RTL8411B(sc)) { |
| 593 | if (RTSX_IS_RTL8411B_QFN48(sc)) { |
| 594 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); |
| 595 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); |
| 596 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); |
| 597 | } else { |
| 598 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); |
| 599 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); |
| 600 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); |
| 601 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); |
| 602 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); |
| 603 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | static int |
| 611 | rtsx_bus_power_on(struct rtsx_softc *sc) |
| 612 | { |
| 613 | uint8_t enable3; |
| 614 | |
| 615 | /* Select SD card. */ |
| 616 | RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); |
| 617 | RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); |
| 618 | RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); |
| 619 | |
| 620 | /* Enable pull control. */ |
| 621 | if (RTSX_IS_RTS5209(sc) || RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 622 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); |
| 623 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); |
| 624 | if (RTSX_IS_RTS5229_TYPE_C(sc)) |
| 625 | enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; |
| 626 | else |
| 627 | enable3 = RTSX_PULL_CTL_ENABLE3; |
| 628 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); |
| 629 | } else if (RTSX_IS_RTL8402(sc) || RTSX_IS_RTL8411(sc)) { |
| 630 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); |
| 631 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); |
| 632 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); |
| 633 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); |
| 634 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); |
| 635 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); |
| 636 | } else if (RTSX_IS_RTL8411B(sc)) { |
| 637 | if (RTSX_IS_RTL8411B_QFN48(sc)) { |
| 638 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); |
| 639 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); |
| 640 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); |
| 641 | } else { |
| 642 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); |
| 643 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); |
| 644 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); |
| 645 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); |
| 646 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x59); |
| 647 | RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | /* |
| 652 | * To avoid a current peak, enable card power in two phases with a |
| 653 | * delay in between. |
| 654 | */ |
| 655 | |
| 656 | if (RTSX_IS_RTS5209(sc) || RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) { |
| 657 | /* Partial power. */ |
| 658 | RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); |
| 659 | if (RTSX_IS_RTS5209(sc)) |
| 660 | RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); |
| 661 | else |
| 662 | RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); |
| 663 | |
| 664 | delay(200); |
| 665 | |
| 666 | /* Full power. */ |
| 667 | RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); |
| 668 | if (RTSX_IS_RTS5209(sc)) |
| 669 | RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); |
| 670 | else |
| 671 | RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); |
| 672 | } else if (RTSX_IS_RTL8402(sc) |
| 673 | || RTSX_IS_RTL8411(sc) |
| 674 | || RTSX_IS_RTL8411B(sc)) { |
| 675 | RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, |
| 676 | RTSX_BPP_POWER_5_PERCENT_ON); |
| 677 | RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, |
| 678 | RTSX_BPP_LDO_SUSPEND); |
| 679 | delay(150); |
| 680 | RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, |
| 681 | RTSX_BPP_POWER_10_PERCENT_ON); |
| 682 | delay(150); |
| 683 | RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, |
| 684 | RTSX_BPP_POWER_15_PERCENT_ON); |
| 685 | delay(150); |
| 686 | RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, |
| 687 | RTSX_BPP_POWER_ON); |
| 688 | RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, |
| 689 | RTSX_BPP_LDO_ON); |
| 690 | } |
| 691 | |
| 692 | /* Enable SD card output. */ |
| 693 | RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); |
| 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | static int |
| 699 | rtsx_set_bus_width(struct rtsx_softc *sc, int width) |
| 700 | { |
| 701 | uint32_t bus_width; |
| 702 | |
| 703 | DPRINTF(1,("%s: bus width=%d\n" , DEVNAME(sc), width)); |
| 704 | |
| 705 | switch (width) { |
| 706 | case 8: |
| 707 | bus_width = RTSX_BUS_WIDTH_8; |
| 708 | break; |
| 709 | case 4: |
| 710 | bus_width = RTSX_BUS_WIDTH_4; |
| 711 | break; |
| 712 | case 1: |
| 713 | bus_width = RTSX_BUS_WIDTH_1; |
| 714 | break; |
| 715 | default: |
| 716 | return EINVAL; |
| 717 | } |
| 718 | |
| 719 | if (bus_width == RTSX_BUS_WIDTH_1) |
| 720 | RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK); |
| 721 | else |
| 722 | RTSX_SET(sc, RTSX_SD_CFG1, bus_width); |
| 723 | |
| 724 | return 0; |
| 725 | } |
| 726 | |
| 727 | static int |
| 728 | rtsx_stop_sd_clock(struct rtsx_softc *sc) |
| 729 | { |
| 730 | |
| 731 | RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); |
| 732 | RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); |
| 733 | |
| 734 | return 0; |
| 735 | } |
| 736 | |
| 737 | static int |
| 738 | rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t n, int div, int mcu) |
| 739 | { |
| 740 | |
| 741 | /* Enable SD 2.0 mode. */ |
| 742 | RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); |
| 743 | |
| 744 | RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); |
| 745 | |
| 746 | RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, |
| 747 | RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); |
| 748 | RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); |
| 749 | RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); |
| 750 | RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); |
| 751 | RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); |
| 752 | RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); |
| 753 | RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); |
| 754 | RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); |
| 755 | delay(100); |
| 756 | |
| 757 | RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); |
| 758 | |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | /* |
| 763 | * Set or change SD bus voltage and enable or disable SD bus power. |
| 764 | * Return zero on success. |
| 765 | */ |
| 766 | static int |
| 767 | rtsx_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) |
| 768 | { |
| 769 | struct rtsx_softc *sc = sch; |
| 770 | int error = 0; |
| 771 | |
| 772 | DPRINTF(1,("%s: voltage change ocr=0x%x\n" , DEVNAME(sc), ocr)); |
| 773 | |
| 774 | mutex_enter(&sc->sc_host_mtx); |
| 775 | |
| 776 | /* |
| 777 | * Disable bus power before voltage change. |
| 778 | */ |
| 779 | error = rtsx_bus_power_off(sc); |
| 780 | if (error) |
| 781 | goto ret; |
| 782 | |
| 783 | delay(200); |
| 784 | |
| 785 | /* If power is disabled, reset the host and return now. */ |
| 786 | if (ocr == 0) { |
| 787 | mutex_exit(&sc->sc_host_mtx); |
| 788 | (void)rtsx_host_reset(sc); |
| 789 | return 0; |
| 790 | } |
| 791 | |
| 792 | if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { |
| 793 | /* Unsupported voltage level requested. */ |
| 794 | DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n" , |
| 795 | DEVNAME(sc), ocr)); |
| 796 | error = EINVAL; |
| 797 | goto ret; |
| 798 | } |
| 799 | |
| 800 | error = rtsx_set_bus_width(sc, 1); |
| 801 | if (error) |
| 802 | goto ret; |
| 803 | |
| 804 | error = rtsx_bus_power_on(sc); |
| 805 | ret: |
| 806 | mutex_exit(&sc->sc_host_mtx); |
| 807 | |
| 808 | return error; |
| 809 | } |
| 810 | |
| 811 | /* |
| 812 | * Set or change SDCLK frequency or disable the SD clock. |
| 813 | * Return zero on success. |
| 814 | */ |
| 815 | static int |
| 816 | rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq) |
| 817 | { |
| 818 | struct rtsx_softc *sc = sch; |
| 819 | uint8_t n; |
| 820 | int div; |
| 821 | int mcu; |
| 822 | int error = 0; |
| 823 | |
| 824 | DPRINTF(1,("%s: bus clock change freq=%d\n" , DEVNAME(sc), freq)); |
| 825 | |
| 826 | mutex_enter(&sc->sc_host_mtx); |
| 827 | |
| 828 | if (freq == SDMMC_SDCLK_OFF) { |
| 829 | error = rtsx_stop_sd_clock(sc); |
| 830 | goto ret; |
| 831 | } |
| 832 | |
| 833 | /* |
| 834 | * Configure the clock frequency. |
| 835 | */ |
| 836 | switch (freq) { |
| 837 | case SDMMC_SDCLK_400K: |
| 838 | n = 80; /* minimum */ |
| 839 | div = RTSX_CLK_DIV_8; |
| 840 | mcu = 7; |
| 841 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128, 0xff); |
| 842 | if (error) |
| 843 | goto ret; |
| 844 | break; |
| 845 | case 20000: |
| 846 | n = 80; |
| 847 | div = RTSX_CLK_DIV_4; |
| 848 | mcu = 7; |
| 849 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0); |
| 850 | if (error) |
| 851 | goto ret; |
| 852 | break; |
| 853 | case 25000: |
| 854 | n = 100; |
| 855 | div = RTSX_CLK_DIV_4; |
| 856 | mcu = 7; |
| 857 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0); |
| 858 | if (error) |
| 859 | goto ret; |
| 860 | break; |
| 861 | case 30000: |
| 862 | n = 120; |
| 863 | div = RTSX_CLK_DIV_4; |
| 864 | mcu = 7; |
| 865 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0); |
| 866 | if (error) |
| 867 | goto ret; |
| 868 | break; |
| 869 | case 40000: |
| 870 | n = 80; |
| 871 | div = RTSX_CLK_DIV_2; |
| 872 | mcu = 7; |
| 873 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0); |
| 874 | if (error) |
| 875 | goto ret; |
| 876 | break; |
| 877 | case 50000: |
| 878 | n = 100; |
| 879 | div = RTSX_CLK_DIV_2; |
| 880 | mcu = 6; |
| 881 | error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0); |
| 882 | if (error) |
| 883 | goto ret; |
| 884 | break; |
| 885 | default: |
| 886 | error = EINVAL; |
| 887 | goto ret; |
| 888 | } |
| 889 | |
| 890 | /* |
| 891 | * Enable SD clock. |
| 892 | */ |
| 893 | error = rtsx_switch_sd_clock(sc, n, div, mcu); |
| 894 | ret: |
| 895 | mutex_exit(&sc->sc_host_mtx); |
| 896 | |
| 897 | return error; |
| 898 | } |
| 899 | |
| 900 | static int |
| 901 | rtsx_bus_width(sdmmc_chipset_handle_t sch, int width) |
| 902 | { |
| 903 | struct rtsx_softc *sc = sch; |
| 904 | |
| 905 | return rtsx_set_bus_width(sc, width); |
| 906 | } |
| 907 | |
| 908 | static int |
| 909 | rtsx_bus_rod(sdmmc_chipset_handle_t sch, int on) |
| 910 | { |
| 911 | |
| 912 | /* Not support */ |
| 913 | return -1; |
| 914 | } |
| 915 | |
| 916 | static int |
| 917 | rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) |
| 918 | { |
| 919 | int tries = 1024; |
| 920 | uint32_t reg; |
| 921 | |
| 922 | WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | |
| 923 | (uint32_t)((addr & 0x3FFF) << 16)); |
| 924 | |
| 925 | while (tries--) { |
| 926 | reg = READ4(sc, RTSX_HAIMR); |
| 927 | if (!(reg & RTSX_HAIMR_BUSY)) |
| 928 | break; |
| 929 | } |
| 930 | |
| 931 | *val = (reg & 0xff); |
| 932 | return (tries == 0) ? ETIMEDOUT : 0; |
| 933 | } |
| 934 | |
| 935 | static int |
| 936 | rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) |
| 937 | { |
| 938 | int tries = 1024; |
| 939 | uint32_t reg; |
| 940 | |
| 941 | WRITE4(sc, RTSX_HAIMR, |
| 942 | RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | |
| 943 | (uint32_t)(((addr & 0x3FFF) << 16) | |
| 944 | (mask << 8) | val)); |
| 945 | |
| 946 | while (tries--) { |
| 947 | reg = READ4(sc, RTSX_HAIMR); |
| 948 | if (!(reg & RTSX_HAIMR_BUSY)) { |
| 949 | if (val != (reg & 0xff)) |
| 950 | return EIO; |
| 951 | return 0; |
| 952 | } |
| 953 | } |
| 954 | return ETIMEDOUT; |
| 955 | } |
| 956 | |
| 957 | #ifdef notyet |
| 958 | static int |
| 959 | rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) |
| 960 | { |
| 961 | int timeout = 100000; |
| 962 | uint8_t data0; |
| 963 | uint8_t data1; |
| 964 | uint8_t rwctl; |
| 965 | |
| 966 | RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); |
| 967 | RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); |
| 968 | |
| 969 | while (timeout--) { |
| 970 | RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); |
| 971 | if (!(rwctl & RTSX_PHY_BUSY)) |
| 972 | break; |
| 973 | } |
| 974 | if (timeout == 0) |
| 975 | return ETIMEDOUT; |
| 976 | |
| 977 | RTSX_READ(sc, RTSX_PHY_DATA0, &data0); |
| 978 | RTSX_READ(sc, RTSX_PHY_DATA1, &data1); |
| 979 | *val = data0 | (data1 << 8); |
| 980 | |
| 981 | return 0; |
| 982 | } |
| 983 | #endif |
| 984 | |
| 985 | static int |
| 986 | rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) |
| 987 | { |
| 988 | int timeout = 100000; |
| 989 | uint8_t rwctl; |
| 990 | |
| 991 | RTSX_WRITE(sc, RTSX_PHY_DATA0, val); |
| 992 | RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); |
| 993 | RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); |
| 994 | RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); |
| 995 | |
| 996 | while (timeout--) { |
| 997 | RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); |
| 998 | if (!(rwctl & RTSX_PHY_BUSY)) |
| 999 | break; |
| 1000 | } |
| 1001 | if (timeout == 0) |
| 1002 | return ETIMEDOUT; |
| 1003 | |
| 1004 | return 0; |
| 1005 | } |
| 1006 | |
| 1007 | static int |
| 1008 | rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) |
| 1009 | { |
| 1010 | int tries = 1024; |
| 1011 | uint8_t data0, data1, data2, data3, rwctl; |
| 1012 | |
| 1013 | RTSX_WRITE(sc, RTSX_CFGADDR0, addr); |
| 1014 | RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); |
| 1015 | RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); |
| 1016 | |
| 1017 | while (tries--) { |
| 1018 | RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); |
| 1019 | if (!(rwctl & RTSX_CFG_BUSY)) |
| 1020 | break; |
| 1021 | } |
| 1022 | if (tries == 0) |
| 1023 | return EIO; |
| 1024 | |
| 1025 | RTSX_READ(sc, RTSX_CFGDATA0, &data0); |
| 1026 | RTSX_READ(sc, RTSX_CFGDATA1, &data1); |
| 1027 | RTSX_READ(sc, RTSX_CFGDATA2, &data2); |
| 1028 | RTSX_READ(sc, RTSX_CFGDATA3, &data3); |
| 1029 | *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; |
| 1030 | |
| 1031 | return 0; |
| 1032 | } |
| 1033 | |
| 1034 | #ifdef notyet |
| 1035 | static int |
| 1036 | rtsx_write_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, |
| 1037 | uint32_t mask, uint32_t val) |
| 1038 | { |
| 1039 | uint32_t writemask = 0; |
| 1040 | int i, tries = 1024; |
| 1041 | uint8_t rwctl; |
| 1042 | |
| 1043 | for (i = 0; i < 4; i++) { |
| 1044 | if (mask & 0xff) { |
| 1045 | RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); |
| 1046 | writemask |= (1 << i); |
| 1047 | } |
| 1048 | mask >>= 8; |
| 1049 | val >>= 8; |
| 1050 | } |
| 1051 | |
| 1052 | if (writemask) { |
| 1053 | RTSX_WRITE(sc, RTSX_CFGADDR0, addr); |
| 1054 | RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); |
| 1055 | RTSX_WRITE(sc, RTSX_CFGRWCTL, |
| 1056 | RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); |
| 1057 | } |
| 1058 | |
| 1059 | while (tries--) { |
| 1060 | RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); |
| 1061 | if (!(rwctl & RTSX_CFG_BUSY)) |
| 1062 | break; |
| 1063 | } |
| 1064 | if (tries == 0) |
| 1065 | return EIO; |
| 1066 | |
| 1067 | return 0; |
| 1068 | } |
| 1069 | #endif |
| 1070 | |
| 1071 | /* Append a properly encoded host command to the host command buffer. */ |
| 1072 | static void |
| 1073 | rtsx_hostcmd(uint32_t *cmdbuf, int *n, uint8_t cmd, uint16_t reg, |
| 1074 | uint8_t mask, uint8_t data) |
| 1075 | { |
| 1076 | |
| 1077 | KASSERT(*n < RTSX_HOSTCMD_MAX); |
| 1078 | |
| 1079 | cmdbuf[(*n)++] = htole32((uint32_t)(cmd & 0x3) << 30) | |
| 1080 | ((uint32_t)(reg & 0x3fff) << 16) | |
| 1081 | ((uint32_t)(mask) << 8) | |
| 1082 | ((uint32_t)data); |
| 1083 | } |
| 1084 | |
| 1085 | static void |
| 1086 | rtsx_save_regs(struct rtsx_softc *sc) |
| 1087 | { |
| 1088 | int i; |
| 1089 | uint16_t reg; |
| 1090 | |
| 1091 | mutex_enter(&sc->sc_host_mtx); |
| 1092 | |
| 1093 | i = 0; |
| 1094 | for (reg = 0xFDA0; reg < 0xFDAE; reg++) |
| 1095 | (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); |
| 1096 | for (reg = 0xFD52; reg < 0xFD69; reg++) |
| 1097 | (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); |
| 1098 | for (reg = 0xFE20; reg < 0xFE34; reg++) |
| 1099 | (void)rtsx_read(sc, reg, &sc->sc_regs[i++]); |
| 1100 | |
| 1101 | sc->sc_regs4[0] = READ4(sc, RTSX_HCBAR); |
| 1102 | sc->sc_regs4[1] = READ4(sc, RTSX_HCBCTLR); |
| 1103 | sc->sc_regs4[2] = READ4(sc, RTSX_HDBAR); |
| 1104 | sc->sc_regs4[3] = READ4(sc, RTSX_HDBCTLR); |
| 1105 | sc->sc_regs4[4] = READ4(sc, RTSX_HAIMR); |
| 1106 | sc->sc_regs4[5] = READ4(sc, RTSX_BIER); |
| 1107 | /* Not saving RTSX_BIPR. */ |
| 1108 | |
| 1109 | mutex_exit(&sc->sc_host_mtx); |
| 1110 | } |
| 1111 | |
| 1112 | static void |
| 1113 | rtsx_restore_regs(struct rtsx_softc *sc) |
| 1114 | { |
| 1115 | int i; |
| 1116 | uint16_t reg; |
| 1117 | |
| 1118 | mutex_enter(&sc->sc_host_mtx); |
| 1119 | |
| 1120 | WRITE4(sc, RTSX_HCBAR, sc->sc_regs4[0]); |
| 1121 | WRITE4(sc, RTSX_HCBCTLR, sc->sc_regs4[1]); |
| 1122 | WRITE4(sc, RTSX_HDBAR, sc->sc_regs4[2]); |
| 1123 | WRITE4(sc, RTSX_HDBCTLR, sc->sc_regs4[3]); |
| 1124 | WRITE4(sc, RTSX_HAIMR, sc->sc_regs4[4]); |
| 1125 | WRITE4(sc, RTSX_BIER, sc->sc_regs4[5]); |
| 1126 | /* Not writing RTSX_BIPR since doing so would clear it. */ |
| 1127 | |
| 1128 | i = 0; |
| 1129 | for (reg = 0xFDA0; reg < 0xFDAE; reg++) |
| 1130 | (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); |
| 1131 | for (reg = 0xFD52; reg < 0xFD69; reg++) |
| 1132 | (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); |
| 1133 | for (reg = 0xFE20; reg < 0xFE34; reg++) |
| 1134 | (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]); |
| 1135 | |
| 1136 | mutex_exit(&sc->sc_host_mtx); |
| 1137 | } |
| 1138 | |
| 1139 | static uint8_t |
| 1140 | rtsx_response_type(uint16_t sdmmc_rsp) |
| 1141 | { |
| 1142 | static const struct rsp_type { |
| 1143 | uint16_t sdmmc_rsp; |
| 1144 | uint8_t rtsx_rsp; |
| 1145 | } rsp_types[] = { |
| 1146 | { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, |
| 1147 | { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, |
| 1148 | { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, |
| 1149 | { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, |
| 1150 | { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, |
| 1151 | { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, |
| 1152 | { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, |
| 1153 | { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, |
| 1154 | { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } |
| 1155 | }; |
| 1156 | size_t i; |
| 1157 | |
| 1158 | for (i = 0; i < __arraycount(rsp_types); i++) { |
| 1159 | if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) |
| 1160 | return rsp_types[i].rtsx_rsp; |
| 1161 | } |
| 1162 | return 0; |
| 1163 | } |
| 1164 | |
| 1165 | static int |
| 1166 | rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) |
| 1167 | { |
| 1168 | |
| 1169 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, |
| 1170 | BUS_DMASYNC_PREWRITE); |
| 1171 | |
| 1172 | mutex_enter(&sc->sc_host_mtx); |
| 1173 | |
| 1174 | /* Tell the chip where the command buffer is and run the commands. */ |
| 1175 | WRITE4(sc, RTSX_HCBAR, sc->sc_dmap_cmd->dm_segs[0].ds_addr); |
| 1176 | WRITE4(sc, RTSX_HCBCTLR, |
| 1177 | ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); |
| 1178 | |
| 1179 | mutex_exit(&sc->sc_host_mtx); |
| 1180 | |
| 1181 | return 0; |
| 1182 | } |
| 1183 | |
| 1184 | static int |
| 1185 | rtsx_read_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd, |
| 1186 | uint32_t *cmdbuf) |
| 1187 | { |
| 1188 | uint8_t *ptr; |
| 1189 | int ncmd, remain; |
| 1190 | uint16_t reg; |
| 1191 | int error; |
| 1192 | int i, j; |
| 1193 | |
| 1194 | DPRINTF(3,("%s: read %d bytes from ppbuf2\n" , DEVNAME(sc), |
| 1195 | cmd->c_datalen)); |
| 1196 | |
| 1197 | reg = RTSX_PPBUF_BASE2; |
| 1198 | ptr = cmd->c_data; |
| 1199 | remain = cmd->c_datalen; |
| 1200 | for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) { |
| 1201 | ncmd = 0; |
| 1202 | for (i = 0; i < RTSX_HOSTCMD_MAX; i++) { |
| 1203 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++, |
| 1204 | 0, 0); |
| 1205 | } |
| 1206 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1207 | if (error == 0) |
| 1208 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); |
| 1209 | if (error) |
| 1210 | goto ret; |
| 1211 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, |
| 1212 | RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD); |
| 1213 | memcpy(ptr, cmdbuf, RTSX_HOSTCMD_MAX); |
| 1214 | ptr += RTSX_HOSTCMD_MAX; |
| 1215 | remain -= RTSX_HOSTCMD_MAX; |
| 1216 | } |
| 1217 | if (remain > 0) { |
| 1218 | ncmd = 0; |
| 1219 | for (i = 0; i < remain; i++) { |
| 1220 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++, |
| 1221 | 0, 0); |
| 1222 | } |
| 1223 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1224 | if (error == 0) |
| 1225 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); |
| 1226 | if (error) |
| 1227 | goto ret; |
| 1228 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, |
| 1229 | RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD); |
| 1230 | memcpy(ptr, cmdbuf, remain); |
| 1231 | } |
| 1232 | ret: |
| 1233 | return error; |
| 1234 | } |
| 1235 | |
| 1236 | static int |
| 1237 | rtsx_write_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd, |
| 1238 | uint32_t *cmdbuf) |
| 1239 | { |
| 1240 | const uint8_t *ptr; |
| 1241 | int ncmd, remain; |
| 1242 | uint16_t reg; |
| 1243 | int error; |
| 1244 | int i, j; |
| 1245 | |
| 1246 | DPRINTF(3,("%s: write %d bytes to ppbuf2\n" , DEVNAME(sc), |
| 1247 | cmd->c_datalen)); |
| 1248 | |
| 1249 | reg = RTSX_PPBUF_BASE2; |
| 1250 | ptr = cmd->c_data; |
| 1251 | remain = cmd->c_datalen; |
| 1252 | for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) { |
| 1253 | ncmd = 0; |
| 1254 | for (i = 0; i < RTSX_HOSTCMD_MAX; i++) { |
| 1255 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++, |
| 1256 | 0xff, *ptr++); |
| 1257 | } |
| 1258 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1259 | if (error == 0) |
| 1260 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); |
| 1261 | if (error) |
| 1262 | goto ret; |
| 1263 | remain -= RTSX_HOSTCMD_MAX; |
| 1264 | } |
| 1265 | if (remain > 0) { |
| 1266 | ncmd = 0; |
| 1267 | for (i = 0; i < remain; i++) { |
| 1268 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++, |
| 1269 | 0xff, *ptr++); |
| 1270 | } |
| 1271 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1272 | if (error == 0) |
| 1273 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4); |
| 1274 | if (error) |
| 1275 | goto ret; |
| 1276 | } |
| 1277 | ret: |
| 1278 | return error; |
| 1279 | } |
| 1280 | |
| 1281 | static int |
| 1282 | rtsx_exec_short_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, |
| 1283 | uint32_t *cmdbuf, uint8_t rsp_type) |
| 1284 | { |
| 1285 | int read = ISSET(cmd->c_flags, SCF_CMD_READ); |
| 1286 | int ncmd; |
| 1287 | uint8_t tmode = read ? RTSX_TM_NORMAL_READ : RTSX_TM_AUTO_WRITE2; |
| 1288 | int error; |
| 1289 | |
| 1290 | DPRINTF(3,("%s: %s short xfer: %d bytes with block size %d\n" , |
| 1291 | DEVNAME(sc), read ? "read" : "write" , cmd->c_datalen, |
| 1292 | cmd->c_blklen)); |
| 1293 | |
| 1294 | if (cmd->c_datalen > 512) { |
| 1295 | DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n" , |
| 1296 | DEVNAME(sc), cmd->c_datalen, 512)); |
| 1297 | return ENOMEM; |
| 1298 | } |
| 1299 | |
| 1300 | if (!read && cmd->c_data != NULL && cmd->c_datalen > 0) { |
| 1301 | error = rtsx_write_ppbuf(sc, cmd, cmdbuf); |
| 1302 | if (error) |
| 1303 | goto ret; |
| 1304 | } |
| 1305 | |
| 1306 | /* The command buffer queues commands the host controller will |
| 1307 | * run asynchronously. */ |
| 1308 | ncmd = 0; |
| 1309 | |
| 1310 | /* Queue commands to set SD command index and argument. */ |
| 1311 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, |
| 1312 | 0xff, 0x40 | cmd->c_opcode); |
| 1313 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, |
| 1314 | 0xff, cmd->c_arg >> 24); |
| 1315 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, |
| 1316 | 0xff, cmd->c_arg >> 16); |
| 1317 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, |
| 1318 | 0xff, cmd->c_arg >> 8); |
| 1319 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, |
| 1320 | 0xff, cmd->c_arg); |
| 1321 | |
| 1322 | /* Queue commands to configure data transfer size. */ |
| 1323 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, |
| 1324 | 0xff, cmd->c_datalen); |
| 1325 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, |
| 1326 | 0xff, cmd->c_datalen >> 8); |
| 1327 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, |
| 1328 | 0xff, 0x01); |
| 1329 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, |
| 1330 | 0xff, 0x00); |
| 1331 | |
| 1332 | /* Queue command to set response type. */ |
| 1333 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, |
| 1334 | 0xff, rsp_type); |
| 1335 | |
| 1336 | if (tmode == RTSX_TM_NORMAL_READ) { |
| 1337 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, |
| 1338 | RTSX_CARD_DATA_SOURCE, 0x01, RTSX_PINGPONG_BUFFER); |
| 1339 | } |
| 1340 | |
| 1341 | /* Queue commands to perform SD transfer. */ |
| 1342 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, |
| 1343 | 0xff, tmode | RTSX_SD_TRANSFER_START); |
| 1344 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, |
| 1345 | RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); |
| 1346 | |
| 1347 | /* Run the command queue and wait for completion. */ |
| 1348 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1349 | if (error == 0) |
| 1350 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 2 * hz); |
| 1351 | if (error) |
| 1352 | goto ret; |
| 1353 | |
| 1354 | if (read && cmd->c_data != NULL && cmd->c_datalen > 0) |
| 1355 | error = rtsx_read_ppbuf(sc, cmd, cmdbuf); |
| 1356 | ret: |
| 1357 | DPRINTF(3,("%s: short xfer done, error=%d\n" , DEVNAME(sc), error)); |
| 1358 | return error; |
| 1359 | } |
| 1360 | |
| 1361 | static int |
| 1362 | rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, uint32_t *cmdbuf) |
| 1363 | { |
| 1364 | int ncmd, dma_dir, error, tmode; |
| 1365 | int read = ISSET(cmd->c_flags, SCF_CMD_READ); |
| 1366 | uint8_t cfg2; |
| 1367 | |
| 1368 | DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n" , DEVNAME(sc), |
| 1369 | read ? "read" : "write" , cmd->c_datalen, cmd->c_blklen)); |
| 1370 | |
| 1371 | if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { |
| 1372 | DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n" , |
| 1373 | DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); |
| 1374 | return ENOMEM; |
| 1375 | } |
| 1376 | |
| 1377 | /* Configure DMA transfer mode parameters. */ |
| 1378 | cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | |
| 1379 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; |
| 1380 | if (read) { |
| 1381 | dma_dir = RTSX_DMA_DIR_FROM_CARD; |
| 1382 | /* Use transfer mode AUTO_READ3, which assumes we've already |
| 1383 | * sent the read command and gotten the response, and will |
| 1384 | * send CMD 12 manually after reading multiple blocks. */ |
| 1385 | tmode = RTSX_TM_AUTO_READ3; |
| 1386 | cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; |
| 1387 | } else { |
| 1388 | dma_dir = RTSX_DMA_DIR_TO_CARD; |
| 1389 | /* Use transfer mode AUTO_WRITE3, which assumes we've already |
| 1390 | * sent the write command and gotten the response, and will |
| 1391 | * send CMD 12 manually after writing multiple blocks. */ |
| 1392 | tmode = RTSX_TM_AUTO_WRITE3; |
| 1393 | cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; |
| 1394 | } |
| 1395 | |
| 1396 | /* The command buffer queues commands the host controller will |
| 1397 | * run asynchronously. */ |
| 1398 | ncmd = 0; |
| 1399 | |
| 1400 | /* Queue command to set response type. */ |
| 1401 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, |
| 1402 | 0xff, cfg2); |
| 1403 | |
| 1404 | /* Queue commands to configure data transfer size. */ |
| 1405 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, |
| 1406 | 0xff, 0x00); |
| 1407 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, |
| 1408 | 0xff, 0x02); |
| 1409 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, |
| 1410 | 0xff, cmd->c_datalen / cmd->c_blklen); |
| 1411 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, |
| 1412 | 0xff, (cmd->c_datalen / cmd->c_blklen) >> 8); |
| 1413 | |
| 1414 | /* Use the DMA ring buffer for commands which transfer data. */ |
| 1415 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, |
| 1416 | 0x01, RTSX_RING_BUFFER); |
| 1417 | |
| 1418 | /* Configure DMA controller. */ |
| 1419 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, |
| 1420 | RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); |
| 1421 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC3, |
| 1422 | 0xff, cmd->c_datalen >> 24); |
| 1423 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC2, |
| 1424 | 0xff, cmd->c_datalen >> 16); |
| 1425 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC1, |
| 1426 | 0xff, cmd->c_datalen >> 8); |
| 1427 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC0, |
| 1428 | 0xff, cmd->c_datalen); |
| 1429 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMACTL, |
| 1430 | RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, |
| 1431 | RTSX_DMA_EN | dma_dir | RTSX_DMA_512); |
| 1432 | |
| 1433 | /* Queue commands to perform SD transfer. */ |
| 1434 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, |
| 1435 | 0xff, tmode | RTSX_SD_TRANSFER_START); |
| 1436 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, |
| 1437 | RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); |
| 1438 | |
| 1439 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1440 | if (error) |
| 1441 | goto ret; |
| 1442 | |
| 1443 | mutex_enter(&sc->sc_host_mtx); |
| 1444 | |
| 1445 | /* Tell the chip where the data buffer is and run the transfer. */ |
| 1446 | WRITE4(sc, RTSX_HDBAR, cmd->c_dmamap->dm_segs[0].ds_addr); |
| 1447 | WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | |
| 1448 | (cmd->c_dmamap->dm_segs[0].ds_len & 0x00ffffff)); |
| 1449 | |
| 1450 | mutex_exit(&sc->sc_host_mtx); |
| 1451 | |
| 1452 | /* Wait for completion. */ |
| 1453 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); |
| 1454 | ret: |
| 1455 | DPRINTF(3,("%s: xfer done, error=%d\n" , DEVNAME(sc), error)); |
| 1456 | return error; |
| 1457 | } |
| 1458 | |
| 1459 | static void |
| 1460 | rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) |
| 1461 | { |
| 1462 | struct rtsx_softc *sc = sch; |
| 1463 | bus_dma_segment_t segs[1]; |
| 1464 | int rsegs; |
| 1465 | void *cmdkvap; |
| 1466 | uint32_t *cmdbuf; |
| 1467 | uint8_t rsp_type; |
| 1468 | uint16_t r; |
| 1469 | int ncmd; |
| 1470 | int error = 0; |
| 1471 | |
| 1472 | DPRINTF(3,("%s: executing cmd %hu\n" , DEVNAME(sc), cmd->c_opcode)); |
| 1473 | |
| 1474 | /* Refuse SDIO probe if the chip doesn't support SDIO. */ |
| 1475 | if (cmd->c_opcode == SD_IO_SEND_OP_COND && |
| 1476 | !ISSET(sc->sc_flags, RTSX_F_SDIO_SUPPORT)) { |
| 1477 | error = ENOTSUP; |
| 1478 | goto ret; |
| 1479 | } |
| 1480 | |
| 1481 | rsp_type = rtsx_response_type(cmd->c_flags & SCF_RSP_MASK); |
| 1482 | if (rsp_type == 0) { |
| 1483 | aprint_error_dev(sc->sc_dev, "unknown response type 0x%x\n" , |
| 1484 | cmd->c_flags & SCF_RSP_MASK); |
| 1485 | error = EINVAL; |
| 1486 | goto ret; |
| 1487 | } |
| 1488 | |
| 1489 | /* Allocate and map the host command buffer. */ |
| 1490 | error = bus_dmamem_alloc(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, |
| 1491 | segs, 1, &rsegs, BUS_DMA_WAITOK); |
| 1492 | if (error) |
| 1493 | goto ret; |
| 1494 | error = bus_dmamem_map(sc->sc_dmat, segs, rsegs, RTSX_HOSTCMD_BUFSIZE, |
| 1495 | &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); |
| 1496 | if (error) |
| 1497 | goto free_cmdbuf; |
| 1498 | |
| 1499 | /* Load command DMA buffer. */ |
| 1500 | error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap_cmd, cmdkvap, |
| 1501 | RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); |
| 1502 | if (error) |
| 1503 | goto unmap_cmdbuf; |
| 1504 | |
| 1505 | /* Use another transfer method when data size < 512. */ |
| 1506 | if (cmd->c_data != NULL && cmd->c_datalen < 512) { |
| 1507 | error = rtsx_exec_short_xfer(sch, cmd, cmdkvap, rsp_type); |
| 1508 | goto unload_cmdbuf; |
| 1509 | } |
| 1510 | |
| 1511 | /* The command buffer queues commands the host controller will |
| 1512 | * run asynchronously. */ |
| 1513 | cmdbuf = cmdkvap; |
| 1514 | ncmd = 0; |
| 1515 | |
| 1516 | /* Queue commands to set SD command index and argument. */ |
| 1517 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, |
| 1518 | 0xff, 0x40 | cmd->c_opcode); |
| 1519 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, |
| 1520 | 0xff, cmd->c_arg >> 24); |
| 1521 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, |
| 1522 | 0xff, cmd->c_arg >> 16); |
| 1523 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, |
| 1524 | 0xff, cmd->c_arg >> 8); |
| 1525 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, |
| 1526 | 0xff, cmd->c_arg); |
| 1527 | |
| 1528 | /* Queue command to set response type. */ |
| 1529 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, |
| 1530 | 0xff, rsp_type); |
| 1531 | |
| 1532 | /* Use the ping-pong buffer for commands which do not transfer data. */ |
| 1533 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, |
| 1534 | 0x01, RTSX_PINGPONG_BUFFER); |
| 1535 | |
| 1536 | /* Queue commands to perform SD transfer. */ |
| 1537 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, |
| 1538 | 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); |
| 1539 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, |
| 1540 | RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE, |
| 1541 | RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE); |
| 1542 | |
| 1543 | /* Queue commands to read back card status response.*/ |
| 1544 | if (rsp_type == RTSX_SD_RSP_TYPE_R2) { |
| 1545 | for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) |
| 1546 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); |
| 1547 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, |
| 1548 | 0, 0); |
| 1549 | } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { |
| 1550 | for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) |
| 1551 | rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); |
| 1552 | } |
| 1553 | |
| 1554 | /* Run the command queue and wait for completion. */ |
| 1555 | error = rtsx_hostcmd_send(sc, ncmd); |
| 1556 | if (error == 0) |
| 1557 | error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); |
| 1558 | if (error) |
| 1559 | goto unload_cmdbuf; |
| 1560 | |
| 1561 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, |
| 1562 | BUS_DMASYNC_POSTREAD); |
| 1563 | |
| 1564 | /* Copy card response into sdmmc response buffer. */ |
| 1565 | if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { |
| 1566 | /* Copy bytes like sdhc(4), which on little-endian uses |
| 1567 | * different byte order for short and long responses... */ |
| 1568 | if (ISSET(cmd->c_flags, SCF_RSP_136)) { |
| 1569 | uint8_t *resp = cmdkvap; |
| 1570 | memcpy(cmd->c_resp, resp + 1, sizeof(cmd->c_resp)); |
| 1571 | } else { |
| 1572 | /* First byte is CHECK_REG_CMD return value, second |
| 1573 | * one is the command op code -- we skip those. */ |
| 1574 | cmd->c_resp[0] = |
| 1575 | ((be32toh(cmdbuf[0]) & 0x0000ffff) << 16) | |
| 1576 | ((be32toh(cmdbuf[1]) & 0xffff0000) >> 16); |
| 1577 | } |
| 1578 | } |
| 1579 | |
| 1580 | if (cmd->c_data) { |
| 1581 | error = rtsx_xfer(sc, cmd, cmdbuf); |
| 1582 | if (error) { |
| 1583 | uint8_t stat1; |
| 1584 | if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && |
| 1585 | (stat1 & RTSX_SD_CRC_ERR)) { |
| 1586 | aprint_error_dev(sc->sc_dev, |
| 1587 | "CRC error (stat=0x%x)\n" , stat1); |
| 1588 | } |
| 1589 | } |
| 1590 | } |
| 1591 | |
| 1592 | unload_cmdbuf: |
| 1593 | bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap_cmd); |
| 1594 | unmap_cmdbuf: |
| 1595 | bus_dmamem_unmap(sc->sc_dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); |
| 1596 | free_cmdbuf: |
| 1597 | bus_dmamem_free(sc->sc_dmat, segs, rsegs); |
| 1598 | ret: |
| 1599 | SET(cmd->c_flags, SCF_ITSDONE); |
| 1600 | cmd->c_error = error; |
| 1601 | } |
| 1602 | |
| 1603 | /* Prepare for another command. */ |
| 1604 | static void |
| 1605 | rtsx_soft_reset(struct rtsx_softc *sc) |
| 1606 | { |
| 1607 | |
| 1608 | DPRINTF(1,("%s: soft reset\n" , DEVNAME(sc))); |
| 1609 | |
| 1610 | /* Stop command transfer. */ |
| 1611 | WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); |
| 1612 | |
| 1613 | (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, |
| 1614 | RTSX_SD_STOP|RTSX_SD_CLR_ERR); |
| 1615 | |
| 1616 | /* Stop DMA transfer. */ |
| 1617 | WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); |
| 1618 | (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); |
| 1619 | |
| 1620 | (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); |
| 1621 | } |
| 1622 | |
| 1623 | static int |
| 1624 | rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) |
| 1625 | { |
| 1626 | int status; |
| 1627 | int error = 0; |
| 1628 | |
| 1629 | mask |= RTSX_TRANS_FAIL_INT; |
| 1630 | |
| 1631 | mutex_enter(&sc->sc_intr_mtx); |
| 1632 | |
| 1633 | status = sc->sc_intr_status & mask; |
| 1634 | while (status == 0) { |
| 1635 | if (cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_mtx, timo) |
| 1636 | == EWOULDBLOCK) { |
| 1637 | rtsx_soft_reset(sc); |
| 1638 | error = ETIMEDOUT; |
| 1639 | break; |
| 1640 | } |
| 1641 | status = sc->sc_intr_status & mask; |
| 1642 | } |
| 1643 | sc->sc_intr_status &= ~status; |
| 1644 | |
| 1645 | /* Has the card disappeared? */ |
| 1646 | if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) |
| 1647 | error = ENODEV; |
| 1648 | |
| 1649 | mutex_exit(&sc->sc_intr_mtx); |
| 1650 | |
| 1651 | if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) |
| 1652 | error = EIO; |
| 1653 | return error; |
| 1654 | } |
| 1655 | |
| 1656 | static void |
| 1657 | rtsx_card_insert(struct rtsx_softc *sc) |
| 1658 | { |
| 1659 | |
| 1660 | DPRINTF(1, ("%s: card inserted\n" , DEVNAME(sc))); |
| 1661 | |
| 1662 | sc->sc_flags |= RTSX_F_CARD_PRESENT; |
| 1663 | (void)rtsx_led_enable(sc); |
| 1664 | |
| 1665 | /* Schedule card discovery task. */ |
| 1666 | sdmmc_needs_discover(sc->sc_sdmmc); |
| 1667 | } |
| 1668 | |
| 1669 | static void |
| 1670 | rtsx_card_eject(struct rtsx_softc *sc) |
| 1671 | { |
| 1672 | |
| 1673 | DPRINTF(1, ("%s: card ejected\n" , DEVNAME(sc))); |
| 1674 | |
| 1675 | sc->sc_flags &= ~RTSX_F_CARD_PRESENT; |
| 1676 | (void)rtsx_led_disable(sc); |
| 1677 | |
| 1678 | /* Schedule card discovery task. */ |
| 1679 | sdmmc_needs_discover(sc->sc_sdmmc); |
| 1680 | } |
| 1681 | |
| 1682 | /* |
| 1683 | * Established by attachment driver at interrupt priority IPL_SDMMC. |
| 1684 | */ |
| 1685 | int |
| 1686 | rtsx_intr(void *arg) |
| 1687 | { |
| 1688 | struct rtsx_softc *sc = arg; |
| 1689 | uint32_t enabled, status; |
| 1690 | |
| 1691 | enabled = READ4(sc, RTSX_BIER); |
| 1692 | status = READ4(sc, RTSX_BIPR); |
| 1693 | |
| 1694 | /* Ack interrupts. */ |
| 1695 | WRITE4(sc, RTSX_BIPR, status); |
| 1696 | |
| 1697 | if (((enabled & status) == 0) || status == 0xffffffff) |
| 1698 | return 0; |
| 1699 | |
| 1700 | mutex_enter(&sc->sc_intr_mtx); |
| 1701 | |
| 1702 | if (status & RTSX_SD_INT) { |
| 1703 | if (status & RTSX_SD_EXIST) { |
| 1704 | if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT)) |
| 1705 | rtsx_card_insert(sc); |
| 1706 | } else { |
| 1707 | rtsx_card_eject(sc); |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { |
| 1712 | sc->sc_intr_status |= status; |
| 1713 | cv_broadcast(&sc->sc_intr_cv); |
| 1714 | } |
| 1715 | |
| 1716 | mutex_exit(&sc->sc_intr_mtx); |
| 1717 | |
| 1718 | return 1; |
| 1719 | } |
| 1720 | |