| 1 | /* |
| 2 | * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting |
| 3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | * |
| 17 | * $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar9285_reset.c,v 1.4 2010/08/14 15:29:21 adrian Exp $ |
| 18 | */ |
| 19 | |
| 20 | /* |
| 21 | * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and |
| 22 | * supports only 2Ghz operation. |
| 23 | */ |
| 24 | |
| 25 | #include "opt_ah.h" |
| 26 | |
| 27 | #include "ah.h" |
| 28 | #include "ah_internal.h" |
| 29 | #include "ah_devid.h" |
| 30 | |
| 31 | #include "ah_eeprom_v14.h" |
| 32 | #include "ah_eeprom_v4k.h" |
| 33 | |
| 34 | #include "ar5416/ar9285.h" |
| 35 | #include "ar5416/ar5416.h" |
| 36 | #include "ar5416/ar5416reg.h" |
| 37 | #include "ar5416/ar5416phy.h" |
| 38 | |
| 39 | /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ |
| 40 | #define EEP_MINOR(_ah) \ |
| 41 | (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) |
| 42 | #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) |
| 43 | #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) |
| 44 | |
| 45 | /* Additional Time delay to wait after activiting the Base band */ |
| 46 | #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ |
| 47 | #define PLL_SETTLE_DELAY 300 /* 300 usec */ |
| 48 | #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ |
| 49 | |
| 50 | static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, |
| 51 | struct ar5416eeprom_4k *pEepData, |
| 52 | HAL_CHANNEL_INTERNAL *chan, int16_t *ratesArray, |
| 53 | uint16_t cfgCtl, uint16_t AntennaReduction, |
| 54 | uint16_t twiceMaxRegulatoryPower, |
| 55 | uint16_t powerLimit); |
| 56 | static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, |
| 57 | struct ar5416eeprom_4k *pEepData, |
| 58 | HAL_CHANNEL_INTERNAL *chan, |
| 59 | int16_t *pTxPowerIndexOffset); |
| 60 | static int16_t interpolate(uint16_t target, uint16_t srcLeft, |
| 61 | uint16_t srcRight, int16_t targetLeft, int16_t targetRight); |
| 62 | static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *, |
| 63 | uint16_t, uint8_t *); |
| 64 | static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, |
| 65 | HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, |
| 66 | uint8_t * bChans, uint16_t availPiers, |
| 67 | uint16_t tPdGainOverlap, int16_t *pMinCalPower, |
| 68 | uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, |
| 69 | uint16_t numXpdGains); |
| 70 | static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList, |
| 71 | uint16_t listSize, uint16_t *indexL, uint16_t *indexR); |
| 72 | static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *); |
| 73 | |
| 74 | /* XXX gag, this is sick */ |
| 75 | typedef enum Ar5416_Rates { |
| 76 | rate6mb, rate9mb, rate12mb, rate18mb, |
| 77 | rate24mb, rate36mb, rate48mb, rate54mb, |
| 78 | rate1l, rate2l, rate2s, rate5_5l, |
| 79 | rate5_5s, rate11l, rate11s, rateXr, |
| 80 | rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, |
| 81 | rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, |
| 82 | rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, |
| 83 | rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, |
| 84 | rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, |
| 85 | Ar5416RateSize |
| 86 | } AR5416_RATES; |
| 87 | |
| 88 | HAL_BOOL |
| 89 | ar9285SetTransmitPower(struct ath_hal *ah, |
| 90 | HAL_CHANNEL *chan, uint16_t *rfXpdGain) |
| 91 | { |
| 92 | #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) |
| 93 | #define N(a) (sizeof (a) / sizeof (a[0])) |
| 94 | |
| 95 | HAL_CHANNEL_INTERNAL *ichan; |
| 96 | MODAL_EEP4K_HEADER *pModal; |
| 97 | struct ath_hal_5212 *ahp = AH5212(ah); |
| 98 | int16_t ratesArray[Ar5416RateSize]; |
| 99 | int16_t txPowerIndexOffset = 0; |
| 100 | uint8_t ht40PowerIncForPdadc = 2; |
| 101 | int i; |
| 102 | |
| 103 | uint16_t cfgCtl; |
| 104 | uint16_t powerLimit; |
| 105 | uint16_t twiceAntennaReduction; |
| 106 | uint16_t twiceMaxRegulatoryPower; |
| 107 | int16_t maxPower; |
| 108 | HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; |
| 109 | struct ar5416eeprom_4k *pEepData = &ee->ee_base; |
| 110 | |
| 111 | HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); |
| 112 | ichan = ath_hal_checkchannel(ah, chan); |
| 113 | |
| 114 | /* Setup info for the actual eeprom */ |
| 115 | OS_MEMZERO(ratesArray, sizeof(ratesArray)); |
| 116 | cfgCtl = ath_hal_getctl(ah, chan); |
| 117 | powerLimit = ichan->maxRegTxPower * 2; |
| 118 | twiceAntennaReduction = ichan->antennaMax; |
| 119 | twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); |
| 120 | pModal = &pEepData->modalHeader; |
| 121 | HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n" , |
| 122 | __func__,chan->channel, cfgCtl ); |
| 123 | |
| 124 | if (IS_EEP_MINOR_V2(ah)) { |
| 125 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; |
| 126 | } |
| 127 | |
| 128 | if (!ar9285SetPowerPerRateTable(ah, pEepData, ichan, |
| 129 | &ratesArray[0],cfgCtl, |
| 130 | twiceAntennaReduction, |
| 131 | twiceMaxRegulatoryPower, powerLimit)) { |
| 132 | HALDEBUG(ah, HAL_DEBUG_ANY, |
| 133 | "%s: unable to set tx power per rate table\n" , __func__); |
| 134 | return AH_FALSE; |
| 135 | } |
| 136 | |
| 137 | if (!ar9285SetPowerCalTable(ah, pEepData, ichan, &txPowerIndexOffset)) { |
| 138 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n" , |
| 139 | __func__); |
| 140 | return AH_FALSE; |
| 141 | } |
| 142 | |
| 143 | maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); |
| 144 | maxPower = AH_MAX(maxPower, ratesArray[rate1l]); |
| 145 | |
| 146 | if (IS_CHAN_HT40(chan)) { |
| 147 | maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); |
| 148 | } |
| 149 | |
| 150 | ahp->ah_tx6PowerInHalfDbm = maxPower; |
| 151 | AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; |
| 152 | ahp->ah_txPowerIndexOffset = txPowerIndexOffset; |
| 153 | |
| 154 | /* |
| 155 | * txPowerIndexOffset is set by the SetPowerTable() call - |
| 156 | * adjust the rate table (0 offset if rates EEPROM not loaded) |
| 157 | */ |
| 158 | for (i = 0; i < N(ratesArray); i++) { |
| 159 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
| 160 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) |
| 161 | ratesArray[i] = AR5416_MAX_RATE_POWER; |
| 162 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; |
| 163 | } |
| 164 | |
| 165 | #ifdef AH_EEPROM_DUMP |
| 166 | ar5416PrintPowerPerRate(ah, ratesArray); |
| 167 | #endif |
| 168 | |
| 169 | /* Write the OFDM power per rate set */ |
| 170 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, |
| 171 | POW_SM(ratesArray[rate18mb], 24) |
| 172 | | POW_SM(ratesArray[rate12mb], 16) |
| 173 | | POW_SM(ratesArray[rate9mb], 8) |
| 174 | | POW_SM(ratesArray[rate6mb], 0) |
| 175 | ); |
| 176 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, |
| 177 | POW_SM(ratesArray[rate54mb], 24) |
| 178 | | POW_SM(ratesArray[rate48mb], 16) |
| 179 | | POW_SM(ratesArray[rate36mb], 8) |
| 180 | | POW_SM(ratesArray[rate24mb], 0) |
| 181 | ); |
| 182 | |
| 183 | /* Write the CCK power per rate set */ |
| 184 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, |
| 185 | POW_SM(ratesArray[rate2s], 24) |
| 186 | | POW_SM(ratesArray[rate2l], 16) |
| 187 | | POW_SM(ratesArray[rateXr], 8) /* XR target power */ |
| 188 | | POW_SM(ratesArray[rate1l], 0) |
| 189 | ); |
| 190 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, |
| 191 | POW_SM(ratesArray[rate11s], 24) |
| 192 | | POW_SM(ratesArray[rate11l], 16) |
| 193 | | POW_SM(ratesArray[rate5_5s], 8) |
| 194 | | POW_SM(ratesArray[rate5_5l], 0) |
| 195 | ); |
| 196 | HALDEBUG(ah, HAL_DEBUG_RESET, |
| 197 | "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n" , |
| 198 | __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), |
| 199 | OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); |
| 200 | |
| 201 | /* Write the HT20 power per rate set */ |
| 202 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, |
| 203 | POW_SM(ratesArray[rateHt20_3], 24) |
| 204 | | POW_SM(ratesArray[rateHt20_2], 16) |
| 205 | | POW_SM(ratesArray[rateHt20_1], 8) |
| 206 | | POW_SM(ratesArray[rateHt20_0], 0) |
| 207 | ); |
| 208 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, |
| 209 | POW_SM(ratesArray[rateHt20_7], 24) |
| 210 | | POW_SM(ratesArray[rateHt20_6], 16) |
| 211 | | POW_SM(ratesArray[rateHt20_5], 8) |
| 212 | | POW_SM(ratesArray[rateHt20_4], 0) |
| 213 | ); |
| 214 | |
| 215 | if (IS_CHAN_HT40(chan)) { |
| 216 | /* Write the HT40 power per rate set */ |
| 217 | /* Correct PAR difference between HT40 and HT20/LEGACY */ |
| 218 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, |
| 219 | POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) |
| 220 | | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) |
| 221 | | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) |
| 222 | | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) |
| 223 | ); |
| 224 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, |
| 225 | POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) |
| 226 | | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) |
| 227 | | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) |
| 228 | | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) |
| 229 | ); |
| 230 | /* Write the Dup/Ext 40 power per rate set */ |
| 231 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, |
| 232 | POW_SM(ratesArray[rateExtOfdm], 24) |
| 233 | | POW_SM(ratesArray[rateExtCck], 16) |
| 234 | | POW_SM(ratesArray[rateDupOfdm], 8) |
| 235 | | POW_SM(ratesArray[rateDupCck], 0) |
| 236 | ); |
| 237 | } |
| 238 | |
| 239 | return AH_TRUE; |
| 240 | #undef POW_SM |
| 241 | #undef N |
| 242 | } |
| 243 | |
| 244 | HAL_BOOL |
| 245 | ar9285SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *_chan) |
| 246 | { |
| 247 | HAL_CHANNEL_INTERNAL *chan; |
| 248 | const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; |
| 249 | const struct ar5416eeprom_4k *eep = &ee->ee_base; |
| 250 | const MODAL_EEP4K_HEADER *pModal; |
| 251 | uint8_t txRxAttenLocal = 23; |
| 252 | |
| 253 | HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); |
| 254 | chan = ath_hal_checkchannel(ah, _chan); |
| 255 | pModal = &eep->modalHeader; |
| 256 | |
| 257 | OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); |
| 258 | OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]); |
| 259 | OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, |
| 260 | (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & |
| 261 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | |
| 262 | SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | |
| 263 | SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); |
| 264 | |
| 265 | if (IS_EEP_MINOR_V3(ah)) { |
| 266 | if (IS_CHAN_HT40(chan)) { |
| 267 | /* Overwrite switch settling with HT40 value */ |
| 268 | OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, |
| 269 | pModal->swSettleHt40); |
| 270 | } |
| 271 | txRxAttenLocal = pModal->txRxAttenCh[0]; |
| 272 | |
| 273 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, |
| 274 | pModal->bswMargin[0]); |
| 275 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB, |
| 276 | pModal->bswAtten[0]); |
| 277 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, |
| 278 | pModal->xatten2Margin[0]); |
| 279 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB, |
| 280 | pModal->xatten2Db[0]); |
| 281 | |
| 282 | /* block 1 has the same values as block 0 */ |
| 283 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, |
| 284 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); |
| 285 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, |
| 286 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); |
| 287 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, |
| 288 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); |
| 289 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, |
| 290 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); |
| 291 | |
| 292 | } |
| 293 | OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
| 294 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); |
| 295 | OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
| 296 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); |
| 297 | |
| 298 | OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, |
| 299 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); |
| 300 | OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, |
| 301 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); |
| 302 | |
| 303 | if (AR_SREV_KITE_11(ah)) |
| 304 | OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); |
| 305 | |
| 306 | return AH_TRUE; |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * Helper functions common for AP/CB/XB |
| 311 | */ |
| 312 | |
| 313 | static HAL_BOOL |
| 314 | ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, |
| 315 | HAL_CHANNEL_INTERNAL *chan, |
| 316 | int16_t *ratesArray, uint16_t cfgCtl, |
| 317 | uint16_t AntennaReduction, |
| 318 | uint16_t twiceMaxRegulatoryPower, |
| 319 | uint16_t powerLimit) |
| 320 | { |
| 321 | #define N(a) (sizeof(a)/sizeof(a[0])) |
| 322 | /* Local defines to distinguish between extension and control CTL's */ |
| 323 | #define EXT_ADDITIVE (0x8000) |
| 324 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) |
| 325 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) |
| 326 | |
| 327 | uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
| 328 | int i; |
| 329 | int16_t twiceLargestAntenna; |
| 330 | CAL_CTL_DATA_4K *rep; |
| 331 | CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; |
| 332 | CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; |
| 333 | CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; |
| 334 | int16_t scaledPower, minCtlPower; |
| 335 | |
| 336 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ |
| 337 | static const uint16_t ctlModesFor11g[] = { |
| 338 | CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 |
| 339 | }; |
| 340 | const uint16_t *pCtlMode; |
| 341 | uint16_t numCtlModes, ctlMode, freq; |
| 342 | CHAN_CENTERS centers; |
| 343 | |
| 344 | ar5416GetChannelCenters(ah, chan, ¢ers); |
| 345 | |
| 346 | /* Compute TxPower reduction due to Antenna Gain */ |
| 347 | |
| 348 | twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; |
| 349 | twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); |
| 350 | |
| 351 | /* XXX setup for 5212 use (really used?) */ |
| 352 | ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); |
| 353 | |
| 354 | /* |
| 355 | * scaledPower is the minimum of the user input power level and |
| 356 | * the regulatory allowed power level |
| 357 | */ |
| 358 | scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); |
| 359 | |
| 360 | /* Get target powers from EEPROM - our baseline for TX Power */ |
| 361 | /* Setup for CTL modes */ |
| 362 | numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ |
| 363 | pCtlMode = ctlModesFor11g; |
| 364 | |
| 365 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, |
| 366 | AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); |
| 367 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, |
| 368 | AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); |
| 369 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, |
| 370 | AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); |
| 371 | |
| 372 | if (IS_CHAN_HT40(chan)) { |
| 373 | numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ |
| 374 | |
| 375 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, |
| 376 | AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); |
| 377 | /* Get target powers for extension channels */ |
| 378 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, |
| 379 | AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); |
| 380 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, |
| 381 | AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * For MIMO, need to apply regulatory caps individually across dynamically |
| 386 | * running modes: CCK, OFDM, HT20, HT40 |
| 387 | * |
| 388 | * The outer loop walks through each possible applicable runtime mode. |
| 389 | * The inner loop walks through each ctlIndex entry in EEPROM. |
| 390 | * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. |
| 391 | * |
| 392 | */ |
| 393 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { |
| 394 | HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || |
| 395 | (pCtlMode[ctlMode] == CTL_2GHT40); |
| 396 | if (isHt40CtlMode) { |
| 397 | freq = centers.ctl_center; |
| 398 | } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { |
| 399 | freq = centers.ext_center; |
| 400 | } else { |
| 401 | freq = centers.ctl_center; |
| 402 | } |
| 403 | |
| 404 | /* walk through each CTL index stored in EEPROM */ |
| 405 | for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { |
| 406 | uint16_t twiceMinEdgePower; |
| 407 | |
| 408 | /* compare test group from regulatory channel list with test mode from pCtlMode list */ |
| 409 | if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || |
| 410 | (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == |
| 411 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { |
| 412 | rep = &(pEepData->ctlData[i]); |
| 413 | twiceMinEdgePower = ar9285GetMaxEdgePower(freq, |
| 414 | rep->ctlEdges[ |
| 415 | owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]); |
| 416 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { |
| 417 | /* Find the minimum of all CTL edge powers that apply to this channel */ |
| 418 | twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); |
| 419 | } else { |
| 420 | /* specific */ |
| 421 | twiceMaxEdgePower = twiceMinEdgePower; |
| 422 | break; |
| 423 | } |
| 424 | } |
| 425 | } |
| 426 | minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); |
| 427 | /* Apply ctl mode to correct target power set */ |
| 428 | switch(pCtlMode[ctlMode]) { |
| 429 | case CTL_11B: |
| 430 | for (i = 0; i < N(targetPowerCck.tPow2x); i++) { |
| 431 | targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); |
| 432 | } |
| 433 | break; |
| 434 | case CTL_11A: |
| 435 | case CTL_11G: |
| 436 | for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { |
| 437 | targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); |
| 438 | } |
| 439 | break; |
| 440 | case CTL_5GHT20: |
| 441 | case CTL_2GHT20: |
| 442 | for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { |
| 443 | targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); |
| 444 | } |
| 445 | break; |
| 446 | case CTL_11B_EXT: |
| 447 | targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); |
| 448 | break; |
| 449 | case CTL_11G_EXT: |
| 450 | targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); |
| 451 | break; |
| 452 | case CTL_5GHT40: |
| 453 | case CTL_2GHT40: |
| 454 | for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { |
| 455 | targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); |
| 456 | } |
| 457 | break; |
| 458 | default: |
| 459 | return AH_FALSE; |
| 460 | break; |
| 461 | } |
| 462 | } /* end ctl mode checking */ |
| 463 | |
| 464 | /* Set rates Array from collected data */ |
| 465 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; |
| 466 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; |
| 467 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; |
| 468 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; |
| 469 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; |
| 470 | |
| 471 | for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { |
| 472 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; |
| 473 | } |
| 474 | |
| 475 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; |
| 476 | ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; |
| 477 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; |
| 478 | ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; |
| 479 | if (IS_CHAN_HT40(chan)) { |
| 480 | for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { |
| 481 | ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; |
| 482 | } |
| 483 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; |
| 484 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; |
| 485 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; |
| 486 | if (IS_CHAN_2GHZ(chan)) { |
| 487 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; |
| 488 | } |
| 489 | } |
| 490 | return AH_TRUE; |
| 491 | #undef EXT_ADDITIVE |
| 492 | #undef CTL_11G_EXT |
| 493 | #undef CTL_11B_EXT |
| 494 | #undef SUB_NUM_CTL_MODES_AT_2G_40 |
| 495 | #undef N |
| 496 | } |
| 497 | |
| 498 | /************************************************************************** |
| 499 | * fbin2freq |
| 500 | * |
| 501 | * Get channel value from binary representation held in eeprom |
| 502 | * RETURNS: the frequency in MHz |
| 503 | */ |
| 504 | static uint16_t |
| 505 | fbin2freq(uint8_t fbin) |
| 506 | { |
| 507 | /* |
| 508 | * Reserved value 0xFF provides an empty definition both as |
| 509 | * an fbin and as a frequency - do not convert |
| 510 | */ |
| 511 | if (fbin == AR5416_BCHAN_UNUSED) { |
| 512 | return fbin; |
| 513 | } |
| 514 | |
| 515 | return (uint16_t)(2300 + fbin); |
| 516 | } |
| 517 | |
| 518 | /* |
| 519 | * XXX almost the same as ar5416GetMaxEdgePower. |
| 520 | */ |
| 521 | static uint16_t |
| 522 | ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower) |
| 523 | { |
| 524 | uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
| 525 | int i; |
| 526 | |
| 527 | /* Get the edge power */ |
| 528 | for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { |
| 529 | /* |
| 530 | * If there's an exact channel match or an inband flag set |
| 531 | * on the lower channel use the given rdEdgePower |
| 532 | */ |
| 533 | if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) { |
| 534 | twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); |
| 535 | break; |
| 536 | } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) { |
| 537 | if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { |
| 538 | twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); |
| 539 | } |
| 540 | /* Leave loop - no more affecting edges possible in this monotonic increasing list */ |
| 541 | break; |
| 542 | } |
| 543 | } |
| 544 | HALASSERT(twiceMaxEdgePower > 0); |
| 545 | return twiceMaxEdgePower; |
| 546 | } |
| 547 | |
| 548 | |
| 549 | |
| 550 | static HAL_BOOL |
| 551 | ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, |
| 552 | HAL_CHANNEL_INTERNAL *chan, int16_t *pTxPowerIndexOffset) |
| 553 | { |
| 554 | CAL_DATA_PER_FREQ_4K *pRawDataset; |
| 555 | uint8_t *pCalBChans = AH_NULL; |
| 556 | uint16_t pdGainOverlap_t2; |
| 557 | static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; |
| 558 | uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
| 559 | uint16_t numPiers, i, j; |
| 560 | int16_t tMinCalPower; |
| 561 | uint16_t numXpdGain, xpdMask; |
| 562 | uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS]; |
| 563 | uint32_t reg32, regOffset, regChainOffset; |
| 564 | |
| 565 | OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); |
| 566 | |
| 567 | xpdMask = pEepData->modalHeader.xpdGain; |
| 568 | |
| 569 | if (IS_EEP_MINOR_V2(ah)) { |
| 570 | pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; |
| 571 | } else { |
| 572 | pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); |
| 573 | } |
| 574 | |
| 575 | pCalBChans = pEepData->calFreqPier2G; |
| 576 | numPiers = AR5416_4K_NUM_2G_CAL_PIERS; |
| 577 | numXpdGain = 0; |
| 578 | /* Calculate the value of xpdgains from the xpdGain Mask */ |
| 579 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
| 580 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { |
| 581 | if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { |
| 582 | HALASSERT(0); |
| 583 | break; |
| 584 | } |
| 585 | xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); |
| 586 | numXpdGain++; |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | /* Write the detector gain biases and their number */ |
| 591 | OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & |
| 592 | ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | |
| 593 | SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | |
| 594 | SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(0, AR_PHY_TPCRG1_PD_GAIN_3)); |
| 595 | |
| 596 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
| 597 | |
| 598 | if (AR_SREV_OWL_20_OR_LATER(ah) && |
| 599 | ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { |
| 600 | /* Regs are swapped from chain 2 to 1 for 5416 2_0 with |
| 601 | * only chains 0 and 2 populated |
| 602 | */ |
| 603 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; |
| 604 | } else { |
| 605 | regChainOffset = i * 0x1000; |
| 606 | } |
| 607 | |
| 608 | if (pEepData->baseEepHeader.txMask & (1 << i)) { |
| 609 | pRawDataset = pEepData->calPierData2G[i]; |
| 610 | |
| 611 | ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, |
| 612 | pCalBChans, numPiers, |
| 613 | pdGainOverlap_t2, |
| 614 | &tMinCalPower, gainBoundaries, |
| 615 | pdadcValues, numXpdGain); |
| 616 | |
| 617 | if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { |
| 618 | /* |
| 619 | * Note the pdadc table may not start at 0 dBm power, could be |
| 620 | * negative or greater than 0. Need to offset the power |
| 621 | * values by the amount of minPower for griffin |
| 622 | */ |
| 623 | |
| 624 | OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, |
| 625 | SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
| 626 | SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
| 627 | SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
| 628 | SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
| 629 | SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); |
| 630 | } |
| 631 | |
| 632 | /* Write the power values into the baseband power table */ |
| 633 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; |
| 634 | |
| 635 | for (j = 0; j < 32; j++) { |
| 636 | reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | |
| 637 | ((pdadcValues[4*j + 1] & 0xFF) << 8) | |
| 638 | ((pdadcValues[4*j + 2] & 0xFF) << 16) | |
| 639 | ((pdadcValues[4*j + 3] & 0xFF) << 24) ; |
| 640 | OS_REG_WRITE(ah, regOffset, reg32); |
| 641 | |
| 642 | #ifdef PDADC_DUMP |
| 643 | ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n" , |
| 644 | i, |
| 645 | 4*j, pdadcValues[4*j], |
| 646 | 4*j+1, pdadcValues[4*j + 1], |
| 647 | 4*j+2, pdadcValues[4*j + 2], |
| 648 | 4*j+3, pdadcValues[4*j + 3]); |
| 649 | #endif |
| 650 | regOffset += 4; |
| 651 | } |
| 652 | } |
| 653 | } |
| 654 | *pTxPowerIndexOffset = 0; |
| 655 | |
| 656 | return AH_TRUE; |
| 657 | } |
| 658 | |
| 659 | static void |
| 660 | ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, |
| 661 | HAL_CHANNEL_INTERNAL *chan, |
| 662 | CAL_DATA_PER_FREQ_4K *pRawDataSet, |
| 663 | uint8_t * bChans, uint16_t availPiers, |
| 664 | uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, |
| 665 | uint8_t * pPDADCValues, uint16_t numXpdGains) |
| 666 | { |
| 667 | |
| 668 | int i, j, k; |
| 669 | int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ |
| 670 | uint16_t idxL, idxR, numPiers; /* Pier indexes */ |
| 671 | |
| 672 | /* filled out Vpd table for all pdGains (chanL) */ |
| 673 | static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
| 674 | |
| 675 | /* filled out Vpd table for all pdGains (chanR) */ |
| 676 | static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
| 677 | |
| 678 | /* filled out Vpd table for all pdGains (interpolated) */ |
| 679 | static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
| 680 | |
| 681 | uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; |
| 682 | uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; |
| 683 | uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; |
| 684 | int16_t vpdStep; |
| 685 | int16_t tmpVal; |
| 686 | uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; |
| 687 | HAL_BOOL match; |
| 688 | int16_t minDelta = 0; |
| 689 | CHAN_CENTERS centers; |
| 690 | |
| 691 | ar5416GetChannelCenters(ah, chan, ¢ers); |
| 692 | |
| 693 | /* Trim numPiers for the number of populated channel Piers */ |
| 694 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
| 695 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { |
| 696 | break; |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | /* Find pier indexes around the current channel */ |
| 701 | match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), |
| 702 | bChans, numPiers, &idxL, &idxR); |
| 703 | |
| 704 | if (match) { |
| 705 | /* Directly fill both vpd tables from the matching index */ |
| 706 | for (i = 0; i < numXpdGains; i++) { |
| 707 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; |
| 708 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; |
| 709 | ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], |
| 710 | pRawDataSet[idxL].pwrPdg[i], |
| 711 | pRawDataSet[idxL].vpdPdg[i], |
| 712 | AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); |
| 713 | } |
| 714 | } else { |
| 715 | for (i = 0; i < numXpdGains; i++) { |
| 716 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; |
| 717 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; |
| 718 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; |
| 719 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; |
| 720 | |
| 721 | /* Start Vpd interpolation from the max of the minimum powers */ |
| 722 | minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); |
| 723 | |
| 724 | /* End Vpd interpolation from the min of the max powers */ |
| 725 | maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); |
| 726 | HALASSERT(maxPwrT4[i] > minPwrT4[i]); |
| 727 | |
| 728 | /* Fill pier Vpds */ |
| 729 | ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, |
| 730 | AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); |
| 731 | ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, |
| 732 | AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); |
| 733 | |
| 734 | /* Interpolate the final vpd */ |
| 735 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { |
| 736 | vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), |
| 737 | bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); |
| 738 | } |
| 739 | } |
| 740 | } |
| 741 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); |
| 742 | |
| 743 | k = 0; /* index for the final table */ |
| 744 | for (i = 0; i < numXpdGains; i++) { |
| 745 | if (i == (numXpdGains - 1)) { |
| 746 | pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); |
| 747 | } else { |
| 748 | pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); |
| 749 | } |
| 750 | |
| 751 | pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); |
| 752 | |
| 753 | /* NB: only applies to owl 1.0 */ |
| 754 | if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { |
| 755 | /* |
| 756 | * fix the gain delta, but get a delta that can be applied to min to |
| 757 | * keep the upper power values accurate, don't think max needs to |
| 758 | * be adjusted because should not be at that area of the table? |
| 759 | */ |
| 760 | minDelta = pPdGainBoundaries[0] - 23; |
| 761 | pPdGainBoundaries[0] = 23; |
| 762 | } |
| 763 | else { |
| 764 | minDelta = 0; |
| 765 | } |
| 766 | |
| 767 | /* Find starting index for this pdGain */ |
| 768 | if (i == 0) { |
| 769 | ss = 0; /* for the first pdGain, start from index 0 */ |
| 770 | } else { |
| 771 | /* need overlap entries extrapolated below. */ |
| 772 | ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); |
| 773 | } |
| 774 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); |
| 775 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); |
| 776 | /* |
| 777 | *-ve ss indicates need to extrapolate data below for this pdGain |
| 778 | */ |
| 779 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
| 780 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); |
| 781 | pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); |
| 782 | ss++; |
| 783 | } |
| 784 | |
| 785 | sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); |
| 786 | tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); |
| 787 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; |
| 788 | |
| 789 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
| 790 | pPDADCValues[k++] = vpdTableI[i][ss++]; |
| 791 | } |
| 792 | |
| 793 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); |
| 794 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); |
| 795 | /* |
| 796 | * for last gain, pdGainBoundary == Pmax_t2, so will |
| 797 | * have to extrapolate |
| 798 | */ |
| 799 | if (tgtIndex >= maxIndex) { /* need to extrapolate above */ |
| 800 | while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
| 801 | tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + |
| 802 | (ss - maxIndex +1) * vpdStep)); |
| 803 | pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); |
| 804 | ss++; |
| 805 | } |
| 806 | } /* extrapolated above */ |
| 807 | } /* for all pdGainUsed */ |
| 808 | |
| 809 | /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ |
| 810 | while (i < AR5416_PD_GAINS_IN_MASK) { |
| 811 | pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; |
| 812 | i++; |
| 813 | } |
| 814 | |
| 815 | while (k < AR5416_NUM_PDADC_VALUES) { |
| 816 | pPDADCValues[k] = pPDADCValues[k-1]; |
| 817 | k++; |
| 818 | } |
| 819 | return; |
| 820 | } |
| 821 | /* |
| 822 | * XXX same as ar5416FillVpdTable |
| 823 | */ |
| 824 | static HAL_BOOL |
| 825 | ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, |
| 826 | uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) |
| 827 | { |
| 828 | uint16_t i, k; |
| 829 | uint8_t currPwr = pwrMin; |
| 830 | uint16_t idxL, idxR; |
| 831 | |
| 832 | HALASSERT(pwrMax > pwrMin); |
| 833 | for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { |
| 834 | getLowerUpperIndex(currPwr, pPwrList, numIntercepts, |
| 835 | &(idxL), &(idxR)); |
| 836 | if (idxR < 1) |
| 837 | idxR = 1; /* extrapolate below */ |
| 838 | if (idxL == numIntercepts - 1) |
| 839 | idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ |
| 840 | if (pPwrList[idxL] == pPwrList[idxR]) |
| 841 | k = pVpdList[idxL]; |
| 842 | else |
| 843 | k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / |
| 844 | (pPwrList[idxR] - pPwrList[idxL]) ); |
| 845 | HALASSERT(k < 256); |
| 846 | pRetVpdList[i] = (uint8_t)k; |
| 847 | currPwr += 2; /* half dB steps */ |
| 848 | } |
| 849 | |
| 850 | return AH_TRUE; |
| 851 | } |
| 852 | static int16_t |
| 853 | interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, |
| 854 | int16_t targetLeft, int16_t targetRight) |
| 855 | { |
| 856 | int16_t rv; |
| 857 | |
| 858 | if (srcRight == srcLeft) { |
| 859 | rv = targetLeft; |
| 860 | } else { |
| 861 | rv = (int16_t)( ((target - srcLeft) * targetRight + |
| 862 | (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); |
| 863 | } |
| 864 | return rv; |
| 865 | } |
| 866 | |
| 867 | HAL_BOOL |
| 868 | getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, |
| 869 | uint16_t *indexL, uint16_t *indexR) |
| 870 | { |
| 871 | uint16_t i; |
| 872 | |
| 873 | /* |
| 874 | * Check first and last elements for beyond ordered array cases. |
| 875 | */ |
| 876 | if (target <= pList[0]) { |
| 877 | *indexL = *indexR = 0; |
| 878 | return AH_TRUE; |
| 879 | } |
| 880 | if (target >= pList[listSize-1]) { |
| 881 | *indexL = *indexR = (uint16_t)(listSize - 1); |
| 882 | return AH_TRUE; |
| 883 | } |
| 884 | |
| 885 | /* look for value being near or between 2 values in list */ |
| 886 | for (i = 0; i < listSize - 1; i++) { |
| 887 | /* |
| 888 | * If value is close to the current value of the list |
| 889 | * then target is not between values, it is one of the values |
| 890 | */ |
| 891 | if (pList[i] == target) { |
| 892 | *indexL = *indexR = i; |
| 893 | return AH_TRUE; |
| 894 | } |
| 895 | /* |
| 896 | * Look for value being between current value and next value |
| 897 | * if so return these 2 values |
| 898 | */ |
| 899 | if (target < pList[i + 1]) { |
| 900 | *indexL = i; |
| 901 | *indexR = (uint16_t)(i + 1); |
| 902 | return AH_FALSE; |
| 903 | } |
| 904 | } |
| 905 | HALASSERT(0); |
| 906 | *indexL = *indexR = 0; |
| 907 | return AH_FALSE; |
| 908 | } |
| 909 | |