| 1 | /* $NetBSD: midwayreg.h,v 1.14 2007/03/04 06:01:58 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * m i d w a y r e g . h |
| 5 | * |
| 6 | * this file contains the description of the ENI ATM midway chip |
| 7 | * data structures. see midway.c for more details. |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #if defined(__FreeBSD__) |
| 12 | typedef void *bus_space_tag_t; |
| 13 | typedef u_int32_t pci_chipset_tag_t; |
| 14 | typedef void *bus_space_handle_t; |
| 15 | typedef u_int32_t bus_size_t; |
| 16 | typedef void *bus_addr_t; |
| 17 | |
| 18 | #define bus_space_read_4(t, h, o) ((void) t, \ |
| 19 | (*(volatile u_int32_t *)((h) + (o)))) |
| 20 | #define bus_space_write_4(t, h, o, v) \ |
| 21 | ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v)))) |
| 22 | #endif |
| 23 | |
| 24 | #if defined(__sparc__) |
| 25 | #define vtophys(x) ((u_int32_t)(x)) /* sun4c dvma */ |
| 26 | #endif |
| 27 | |
| 28 | |
| 29 | #define MID_SZTOB(X) ((X) * 256 * 4) /* size to bytes */ |
| 30 | #define MID_BTOSZ(X) ((X) / 256 / 4) /* bytes to "size" */ |
| 31 | |
| 32 | #define MID_N_VC 1024 /* # of VCs we can use */ |
| 33 | #define MID_NTX_CH 8 /* 8 transmit channels (shared) */ |
| 34 | #define MID_ATMDATASZ 48 /* need data in 48 byte blocks */ |
| 35 | |
| 36 | /* |
| 37 | * card data structures, top down |
| 38 | * |
| 39 | * in order to have a portable driver, the netbsd guys will not let us |
| 40 | * use structs. we have a bus_space_handle_t which is the en_base address. |
| 41 | * everything else is an offset from that base. all card data must be |
| 42 | * accessed with bus_space_read_4()/bus_space_write_4(): |
| 43 | * |
| 44 | * rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET); |
| 45 | * bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE); |
| 46 | * |
| 47 | * en_card: the whole card (prom + phy + midway + obmem) |
| 48 | * obmem contains: vci tab + DMA queues (rx & tx) + service list + bufs |
| 49 | */ |
| 50 | |
| 51 | /* byte offsets from en_base of various items */ |
| 52 | #define MID_PHYOFF 0x030000 /* PHY offset */ |
| 53 | #define MID_MIDOFF 0x040000 /* midway regs offset */ |
| 54 | #define MID_RAMOFF 0x200000 /* RAM offset */ |
| 55 | #define MID_DRQOFF 0x204000 /* DRQ offset */ |
| 56 | #define MID_DRQEND MID_DTQOFF /* DRQ end */ |
| 57 | #define MID_DTQOFF 0x205000 /* DTQ offset */ |
| 58 | #define MID_DTQEND MID_SLOFF /* DTQ end */ |
| 59 | #define MID_SLOFF 0x206000 /* service list */ |
| 60 | #define MID_SLEND MID_BUFOFF /* service list end */ |
| 61 | #define MID_BUFOFF 0x207000 /* buffer area */ |
| 62 | #define MID_PROBEOFF 0x21fffc /* start probe here */ |
| 63 | #define MID_PROBSIZE 0x020000 /* 128 KB */ |
| 64 | #define MID_MAXOFF 0x3ffffc /* max offset */ |
| 65 | |
| 66 | /* |
| 67 | * prom & phy: not defined here |
| 68 | */ |
| 69 | #define MID_ADPMACOFF 0xffc0 /* mac address offset (adaptec only) */ |
| 70 | |
| 71 | /* |
| 72 | * midway regs (byte offsets from en_base) |
| 73 | */ |
| 74 | |
| 75 | #define MID_RESID 0x40000 /* write=reset reg, read=ID reg */ |
| 76 | |
| 77 | #define MID_VER(X) (((X) & 0xf0000000) >> 28) /* midway version # */ |
| 78 | #define MID_MID(X) (((X) & 0x700) >> 8) /* motherboard ID */ |
| 79 | #define MID_IS_SABRE(X) ((X) & 0x80) /* sabre controller? */ |
| 80 | #define MID_IS_SUNI(X) ((X) & 0x40) /* SUNI? vs utopia */ |
| 81 | #define MID_IS_UPIPE(X) ((X) & 0x20) /* utopia pipeline? */ |
| 82 | #define MID_DID(X) ((X) & 0x1f) /* daughterboard ID */ |
| 83 | |
| 84 | #define MID_INTACK 0x40004 /* interrupt ACK */ |
| 85 | #define MID_INTSTAT 0x40008 /* interrupt status */ |
| 86 | #define MID_INTENA 0x4000c /* interrupt enable */ |
| 87 | |
| 88 | #define MID_TXCHAN(N) (1 << ((N) + 9)) /* ack/status/enable xmit channel bit*/ |
| 89 | #define MID_INT_TX 0x1fe00 /* mask for any xmit interrupt */ |
| 90 | #define MID_INT_DMA_OVR 0x00100 /* DMA overflow interrupt */ |
| 91 | #define MID_INT_IDENT 0x00080 /* ident match error interrupt */ |
| 92 | #define MID_INT_LERR 0x00040 /* LERR interrupt (sbus?) */ |
| 93 | #define MID_INT_DMA_ERR 0x00020 /* DMA error interrupt */ |
| 94 | #define MID_INT_DMA_RX 0x00010 /* DMA recv interrupt */ |
| 95 | #define MID_INT_DMA_TX 0x00008 /* DMA xmit interrupt */ |
| 96 | #define MID_INT_SERVICE 0x00004 /* service list interrupt */ |
| 97 | #define MID_INT_SUNI 0x00002 /* SUNI interrupt */ |
| 98 | #define MID_INT_STATS 0x00001 /* stats overflow interrupt */ |
| 99 | |
| 100 | #define MID_INT_ANY 0x1ffff /* any interrupt? */ |
| 101 | |
| 102 | #define MID_INTBITS "\20\21T7\20T6\17T5\16T4\15T3\14T2\13T1\12T0\11DMAOVR\10ID\7LERR\6DMAERR\5RXDMA\4TXDMA\3SERV\2SUNI\1STAT" |
| 103 | |
| 104 | #define MID_MAST_CSR 0x40010 /* master CSR */ |
| 105 | |
| 106 | #define MID_IPL(X) (((X) & 0x1c0) >> 6) /* IPL */ |
| 107 | #define MID_SETIPL(I) ((I) << 6) |
| 108 | #define MID_MCSR_TXLOCK 0x20 /* lock on xmit overflow mode */ |
| 109 | /* NOTE: next 5 bits: write 1 means enable, write 0 means no change */ |
| 110 | #define MID_MCSR_ENDMA 0x10 /* DMA enable */ |
| 111 | #define MID_MCSR_ENTX 0x08 /* TX enable */ |
| 112 | #define MID_MCSR_ENRX 0x04 /* RX enable */ |
| 113 | #define MID_MCSR_W1MS 0x02 /* wait 1 msec */ |
| 114 | #define MID_MCSR_W500US 0x01 /* wait 500 usec */ |
| 115 | |
| 116 | #define MID_MCSRBITS "\20\6LCK\5DMAON\4TXON\3RXON\2W1MS\1W500US" |
| 117 | |
| 118 | #define MID_STAT 0x40014 /* stat register, clear on read */ |
| 119 | |
| 120 | #define MID_VTRASH(X) (((X) >> 16) & 0xffff) |
| 121 | /* # cells trashed due to VCI's mode */ |
| 122 | #define MID_OTRASH(X) ((X) & 0xffff) /* # cells trashed due to overflow */ |
| 123 | |
| 124 | #define MID_SERV_WRITE 0x40018 /* 10 bit service write pointer (r/o) */ |
| 125 | #define MID_DMA_ADDR 0x4001c /* VA of DMA (r/o) */ |
| 126 | |
| 127 | /* DMA queue pointers (bits 0 to 8) */ |
| 128 | #define MID_DMA_WRRX 0x40020 /* write ptr. for DMA recv queue */ |
| 129 | /* (for adaptor -> host xfers) */ |
| 130 | #define MID_DMA_RDRX 0x40024 /* read ptr for DMA recv queue (r/o) */ |
| 131 | /* (i.e. current adaptor->host xfer) */ |
| 132 | #define MID_DMA_WRTX 0x40028 /* write ptr for DMA xmit queue */ |
| 133 | /* (for host -> adaptor xfers) */ |
| 134 | #define MID_DMA_RDTX 0x4002c /* read ptr for DMA xmit queue (r/o) */ |
| 135 | /* (i.e. current host->adaptor xfer) */ |
| 136 | |
| 137 | /* xmit channel regs (1 per channel, MID_NTX_CH max channels) */ |
| 138 | |
| 139 | #define MIDX_PLACE(N) (0x40040+((N)*0x10)) /* xmit place */ |
| 140 | |
| 141 | #define MIDX_MKPLACE(SZ,LOC) ( ((SZ) << 11) | (LOC) ) |
| 142 | #define MIDX_LOC(X) ((X) & 0x7ff) /* location in obmem */ |
| 143 | #define MIDX_SZ(X) ((X) >> 11) /* (size of block / 256) in int32_t's*/ |
| 144 | #define MIDX_BASE(X) \ |
| 145 | (((MIDX_LOC(X) << MIDV_LOCTOPSHFT) * sizeof(u_int32_t)) + MID_RAMOFF) |
| 146 | |
| 147 | /* the following two regs are word offsets in the block */ |
| 148 | #define MIDX_READPTR(N) (0x40044+((N)*0x10)) /* xmit read pointer (r/o) */ |
| 149 | #define MIDX_DESCSTART(N) (0x40048+((N)*0x10)) /* seg currently in DMA (r/o) */ |
| 150 | |
| 151 | |
| 152 | /* |
| 153 | * obmem items |
| 154 | */ |
| 155 | |
| 156 | /* |
| 157 | * vci table in obmem (offset from MID_VCTOFF) |
| 158 | */ |
| 159 | |
| 160 | #define MID_VC(N) (MID_RAMOFF+((N)*0x10)) |
| 161 | |
| 162 | #define MIDV_TRASH 0x00000000 /* ignore VC */ |
| 163 | #define MIDV_AAL5 0x80000000 /* do AAL5 on it */ |
| 164 | #define MIDV_NOAAL 0x40000000 /* do per-cell stuff on it */ |
| 165 | #define MIDV_MASK 0xc0000000 /* mode mask */ |
| 166 | #define MIDV_SETMODE(VC,M) (((VC) & ~(MIDV_MASK)) | (M)) /* new mode */ |
| 167 | #define MIDV_PTI 0x20000000 /* save PTI cells? */ |
| 168 | #define MIDV_LOCTOPSHFT 8 /* shift to get top 11 bits of 19 */ |
| 169 | #define MIDV_LOCSHIFT 18 |
| 170 | #define MIDV_LOCMASK 0x7ff |
| 171 | #define MIDV_LOC(X) (((X) >> MIDV_LOCSHIFT) & MIDV_LOCMASK) |
| 172 | /* 11 most sig bits of addr */ |
| 173 | #define MIDV_SZSHIFT 15 |
| 174 | #define MIDV_SZ(X) (((X) >> MIDV_SZSHIFT) & 7) |
| 175 | /* size encoded the usual way */ |
| 176 | #define MIDV_INSERVICE 0x1 /* in service list */ |
| 177 | |
| 178 | #define MID_DST_RP(N) (MID_VC(N)|0x4) |
| 179 | |
| 180 | #define MIDV_DSTART_SHIFT 16 /* shift */ |
| 181 | #define MIDV_DSTART(X) (((X) >> MIDV_DSTART_SHIFT) & 0x7fff) |
| 182 | #define MIDV_READP_MASK 0x7fff /* valid bits, (shift = 0) */ |
| 183 | |
| 184 | #define MID_WP_ST_CNT(N) (MID_VC(N)|0x8) /* write pointer/state/count */ |
| 185 | |
| 186 | #define MIDV_WRITEP_MASK 0x7fff0000 /* mask for write ptr. */ |
| 187 | #define MIDV_WRITEP_SHIFT 16 |
| 188 | #define MIDV_ST_IDLE 0x0000 |
| 189 | #define MIDV_ST_TRASH 0xc000 |
| 190 | #define MIDV_ST_REASS 0x4000 |
| 191 | #define MIDV_CCOUNT 0x7ff /* cell count */ |
| 192 | |
| 193 | #define MID_CRC(N) (MID_VC(N)|0xc) /* CRC */ |
| 194 | |
| 195 | /* |
| 196 | * DMA recv q. |
| 197 | */ |
| 198 | |
| 199 | #define MID_DMA_END (1 << 5) /* for both tx and rx */ |
| 200 | #define MID_DMA_CNT(X) (((X) >> 16) & 0xffff) |
| 201 | #define MID_DMA_TXCHAN(X) (((X) >> 6) & 0x7) |
| 202 | #define MID_DMA_RXVCI(X) (((X) >> 6) & 0x3ff) |
| 203 | #define MID_DMA_TYPE(X) ((X) & 0xf) |
| 204 | |
| 205 | #define MID_DRQ_N 512 /* # of descriptors */ |
| 206 | #define MID_DRQ_A2REG(N) (((N) - MID_DRQOFF) >> 3) |
| 207 | /* convert byte offset to reg value */ |
| 208 | #define MID_DRQ_REG2A(N) (((N) << 3) + MID_DRQOFF) /* and back */ |
| 209 | |
| 210 | /* note: format of word 1 of RXQ is different between ENI and ADP cards */ |
| 211 | #define MID_MK_RXQ_ENI(CNT,VC,END,TYPE) \ |
| 212 | ( ((CNT) << 16)|((VC) << 6)|(END)|(TYPE) ) |
| 213 | |
| 214 | #define MID_MK_RXQ_ADP(CNT,VC,END,JK) \ |
| 215 | ( ((CNT) << 12)|((VC) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0)) |
| 216 | /* |
| 217 | * DMA xmit q. |
| 218 | */ |
| 219 | |
| 220 | #define MID_DTQ_N 512 /* # of descriptors */ |
| 221 | #define MID_DTQ_A2REG(N) (((N) - MID_DTQOFF) >> 3) |
| 222 | /* convert byte offset to reg value */ |
| 223 | #define MID_DTQ_REG2A(N) (((N) << 3) + MID_DTQOFF) /* and back */ |
| 224 | |
| 225 | |
| 226 | /* note: format of word 1 of TXQ is different between ENI and ADP cards */ |
| 227 | #define MID_MK_TXQ_ENI(CNT,CHN,END,TYPE) \ |
| 228 | ( ((CNT) << 16)|((CHN) << 6)|(END)|(TYPE) ) |
| 229 | |
| 230 | #define MID_MK_TXQ_ADP(CNT,CHN,END,JK) \ |
| 231 | ( ((CNT) << 12)|((CHN) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0) ) |
| 232 | |
| 233 | /* |
| 234 | * DMA types |
| 235 | */ |
| 236 | |
| 237 | #define MIDDMA_JK 0x3 /* just kidding */ |
| 238 | #define MIDDMA_BYTE 0x1 /* byte */ |
| 239 | #define MIDDMA_2BYTE 0x2 /* 2 bytes */ |
| 240 | #define MIDDMA_WORD 0x0 /* word */ |
| 241 | #define MIDDMA_2WORD 0x7 /* 2 words */ |
| 242 | #define MIDDMA_4WORD 0x4 /* 4 words */ |
| 243 | #define MIDDMA_8WORD 0x5 /* 8 words */ |
| 244 | #define MIDDMA_16WORD 0x6 /* 16 words!!! */ |
| 245 | #define MIDDMA_2WMAYBE 0xf /* 2 words, maybe */ |
| 246 | #define MIDDMA_4WMAYBE 0xc /* 4 words, maybe */ |
| 247 | #define MIDDMA_8WMAYBE 0xd /* 8 words, maybe */ |
| 248 | #define MIDDMA_16WMAYBE 0xe /* 16 words, maybe */ |
| 249 | |
| 250 | #define MIDDMA_MAYBE 0xc /* mask to detect WMAYBE DMA code */ |
| 251 | #define MIDDMA_MAXBURST (16 * sizeof(u_int32_t)) /* largest burst */ |
| 252 | |
| 253 | /* |
| 254 | * service list |
| 255 | */ |
| 256 | |
| 257 | #define MID_SL_N 1024 /* max # entries on slist */ |
| 258 | #define MID_SL_A2REG(N) (((N) - MID_SLOFF) >> 2) |
| 259 | /* convert byte offset to reg value */ |
| 260 | #define MID_SL_REG2A(N) (((N) << 2) + MID_SLOFF) /* and back */ |
| 261 | |
| 262 | /* |
| 263 | * data in the buffer area of obmem |
| 264 | */ |
| 265 | |
| 266 | /* |
| 267 | * recv buffer desc. (1 u_int32_t at start of buffer) |
| 268 | */ |
| 269 | |
| 270 | #define MID_RBD_SIZE 4 /* RBD size */ |
| 271 | #define MID_CHDR_SIZE 4 /* on aal0, cell header size */ |
| 272 | #define MID_RBD_ID(X) ((X) & 0xfe000000) /* get ID */ |
| 273 | #define MID_RBD_STDID 0x36000000 /* standard ID */ |
| 274 | #define MID_RBD_CLP 0x01000000 /* CLP: cell loss priority */ |
| 275 | #define MID_RBD_CE 0x00010000 /* CE: congestion experienced */ |
| 276 | #define MID_RBD_T 0x00001000 /* T: trashed due to overflow */ |
| 277 | #define MID_RBD_CRCERR 0x00000800 /* CRC error */ |
| 278 | #define MID_RBD_CNT(X) ((X) & 0x7ff) /* cell count */ |
| 279 | |
| 280 | /* |
| 281 | * xmit buffer desc. (2 u_int32_t's at start of buffer) |
| 282 | * (note we treat the PR & RATE as a single u_int8_t) |
| 283 | */ |
| 284 | |
| 285 | #define MID_TBD_SIZE 8 |
| 286 | #define MID_TBD_MK1(AAL,PR_RATE,CNT) \ |
| 287 | (MID_TBD_STDID|(AAL)|((PR_RATE) << 19)|(CNT)) |
| 288 | #define MID_TBD_STDID 0xb0000000 /* standard ID */ |
| 289 | #define MID_TBD_AAL5 0x08000000 /* AAL 5 */ |
| 290 | #define MID_TBD_NOAAL5 0x00000000 /* not AAL 5 */ |
| 291 | |
| 292 | #define MID_TBD_MK2(VCI,PTI,CLP) \ |
| 293 | (((VCI) << 4)|((PTI) << 1)|(CLP)) |
| 294 | |
| 295 | /* |
| 296 | * aal5 pdu tail, last 2 words of last cell of AAL5 frame |
| 297 | * (word 2 is CRC .. handled by hw) |
| 298 | */ |
| 299 | |
| 300 | #define MID_PDU_SIZE 8 |
| 301 | #define MID_PDU_MK1(UU,CPI,LEN) \ |
| 302 | (((UU) << 24)|((CPI) << 16)|(LEN)) |
| 303 | #define MID_PDU_LEN(X) ((X) & 0xffff) |
| 304 | |