| 1 | /* $NetBSD: optiide.c,v 1.25 2013/10/07 19:51:55 jakllsch Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2000 The NetBSD Foundation, Inc. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to The NetBSD Foundation |
| 8 | * by Steve C. Woodford. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
| 30 | */ |
| 31 | |
| 32 | #include <sys/cdefs.h> |
| 33 | __KERNEL_RCSID(0, "$NetBSD: optiide.c,v 1.25 2013/10/07 19:51:55 jakllsch Exp $" ); |
| 34 | |
| 35 | #include <sys/param.h> |
| 36 | #include <sys/systm.h> |
| 37 | |
| 38 | #include <dev/pci/pcivar.h> |
| 39 | #include <dev/pci/pcidevs.h> |
| 40 | #include <dev/pci/pciidereg.h> |
| 41 | #include <dev/pci/pciidevar.h> |
| 42 | #include <dev/pci/pciide_opti_reg.h> |
| 43 | |
| 44 | static void opti_chip_map(struct pciide_softc*, const struct pci_attach_args*); |
| 45 | static void opti_setup_channel(struct ata_channel*); |
| 46 | |
| 47 | static int optiide_match(device_t, cfdata_t, void *); |
| 48 | static void optiide_attach(device_t, device_t, void *); |
| 49 | |
| 50 | CFATTACH_DECL_NEW(optiide, sizeof(struct pciide_softc), |
| 51 | optiide_match, optiide_attach, pciide_detach, NULL); |
| 52 | |
| 53 | static const struct pciide_product_desc pciide_opti_products[] = { |
| 54 | { PCI_PRODUCT_OPTI_82C621, |
| 55 | 0, |
| 56 | "OPTi 82c621 PCI IDE controller" , |
| 57 | opti_chip_map, |
| 58 | }, |
| 59 | { PCI_PRODUCT_OPTI_82C568, |
| 60 | 0, |
| 61 | "OPTi 82c568 (82c621 compatible) PCI IDE controller" , |
| 62 | opti_chip_map, |
| 63 | }, |
| 64 | { PCI_PRODUCT_OPTI_82D568, |
| 65 | 0, |
| 66 | "OPTi 82d568 (82c621 compatible) PCI IDE controller" , |
| 67 | opti_chip_map, |
| 68 | }, |
| 69 | { 0, |
| 70 | 0, |
| 71 | NULL, |
| 72 | NULL |
| 73 | } |
| 74 | }; |
| 75 | |
| 76 | static int |
| 77 | optiide_match(device_t parent, cfdata_t match, void *aux) |
| 78 | { |
| 79 | struct pci_attach_args *pa = aux; |
| 80 | |
| 81 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI && |
| 82 | PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && |
| 83 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { |
| 84 | if (pciide_lookup_product(pa->pa_id, pciide_opti_products)) |
| 85 | return (2); |
| 86 | } |
| 87 | return (0); |
| 88 | } |
| 89 | |
| 90 | static void |
| 91 | optiide_attach(device_t parent, device_t self, void *aux) |
| 92 | { |
| 93 | struct pci_attach_args *pa = aux; |
| 94 | struct pciide_softc *sc = device_private(self); |
| 95 | |
| 96 | sc->sc_wdcdev.sc_atac.atac_dev = self; |
| 97 | |
| 98 | pciide_common_attach(sc, pa, |
| 99 | pciide_lookup_product(pa->pa_id, pciide_opti_products)); |
| 100 | |
| 101 | } |
| 102 | |
| 103 | static void |
| 104 | opti_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) |
| 105 | { |
| 106 | struct pciide_channel *cp; |
| 107 | pcireg_t interface; |
| 108 | u_int8_t init_ctrl; |
| 109 | int channel; |
| 110 | |
| 111 | if (pciide_chipen(sc, pa) == 0) |
| 112 | return; |
| 113 | |
| 114 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 115 | "bus-master DMA support present" ); |
| 116 | |
| 117 | /* |
| 118 | * XXXSCW: |
| 119 | * There seem to be a couple of buggy revisions/implementations |
| 120 | * of the OPTi pciide chipset. This kludge seems to fix one of |
| 121 | * the reported problems (PR/11644) but still fails for the |
| 122 | * other (PR/13151), although the latter may be due to other |
| 123 | * issues too... |
| 124 | */ |
| 125 | if (PCI_REVISION(pa->pa_class) <= 0x12) { |
| 126 | aprint_verbose(" but disabled due to chip rev. <= 0x12" ); |
| 127 | sc->sc_dma_ok = 0; |
| 128 | } else |
| 129 | pciide_mapreg_dma(sc, pa); |
| 130 | |
| 131 | aprint_verbose("\n" ); |
| 132 | |
| 133 | sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16; |
| 134 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
| 135 | if (sc->sc_dma_ok) { |
| 136 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; |
| 137 | sc->sc_wdcdev.irqack = pciide_irqack; |
| 138 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
| 139 | } |
| 140 | sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel; |
| 141 | |
| 142 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
| 143 | sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; |
| 144 | sc->sc_wdcdev.wdc_maxdrives = 2; |
| 145 | |
| 146 | init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, |
| 147 | OPTI_REG_INIT_CONTROL); |
| 148 | |
| 149 | interface = PCI_INTERFACE(pa->pa_class); |
| 150 | |
| 151 | wdc_allocate_regs(&sc->sc_wdcdev); |
| 152 | |
| 153 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
| 154 | channel++) { |
| 155 | cp = &sc->pciide_channels[channel]; |
| 156 | if (pciide_chansetup(sc, channel, interface) == 0) |
| 157 | continue; |
| 158 | if (channel == 1 && |
| 159 | (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { |
| 160 | aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
| 161 | "%s channel ignored (disabled)\n" , cp->name); |
| 162 | cp->ata_channel.ch_flags |= ATACH_DISABLED; |
| 163 | continue; |
| 164 | } |
| 165 | pciide_mapchan(pa, cp, interface, pciide_pci_intr); |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | static void |
| 170 | opti_setup_channel(struct ata_channel *chp) |
| 171 | { |
| 172 | struct ata_drive_datas *drvp; |
| 173 | struct pciide_channel *cp = CHAN_TO_PCHAN(chp); |
| 174 | struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); |
| 175 | int drive, spd, s; |
| 176 | int mode[2]; |
| 177 | u_int8_t rv, mr; |
| 178 | |
| 179 | /* |
| 180 | * The `Delay' and `Address Setup Time' fields of the |
| 181 | * Miscellaneous Register are always zero initially. |
| 182 | */ |
| 183 | mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; |
| 184 | mr &= ~(OPTI_MISC_DELAY_MASK | |
| 185 | OPTI_MISC_ADDR_SETUP_MASK | |
| 186 | OPTI_MISC_INDEX_MASK); |
| 187 | |
| 188 | /* Prime the control register before setting timing values */ |
| 189 | opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); |
| 190 | |
| 191 | /* Determine the clockrate of the PCIbus the chip is attached to */ |
| 192 | spd = (int) opti_read_config(chp, OPTI_REG_STRAP); |
| 193 | spd &= OPTI_STRAP_PCI_SPEED_MASK; |
| 194 | |
| 195 | /* setup DMA if needed */ |
| 196 | pciide_channel_dma_setup(cp); |
| 197 | |
| 198 | for (drive = 0; drive < 2; drive++) { |
| 199 | drvp = &chp->ch_drive[drive]; |
| 200 | /* If no drive, skip */ |
| 201 | if (drvp->drive_type == ATA_DRIVET_NONE) { |
| 202 | mode[drive] = -1; |
| 203 | continue; |
| 204 | } |
| 205 | |
| 206 | if ((drvp->drive_flags & ATA_DRIVE_DMA)) { |
| 207 | /* |
| 208 | * Timings will be used for both PIO and DMA, |
| 209 | * so adjust DMA mode if needed |
| 210 | */ |
| 211 | if (drvp->PIO_mode > (drvp->DMA_mode + 2)) |
| 212 | drvp->PIO_mode = drvp->DMA_mode + 2; |
| 213 | if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) |
| 214 | drvp->DMA_mode = (drvp->PIO_mode > 2) ? |
| 215 | drvp->PIO_mode - 2 : 0; |
| 216 | if (drvp->DMA_mode == 0) |
| 217 | drvp->PIO_mode = 0; |
| 218 | |
| 219 | mode[drive] = drvp->DMA_mode + 5; |
| 220 | } else |
| 221 | mode[drive] = drvp->PIO_mode; |
| 222 | |
| 223 | if (drive && mode[0] >= 0 && |
| 224 | (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { |
| 225 | /* |
| 226 | * Can't have two drives using different values |
| 227 | * for `Address Setup Time'. |
| 228 | * Slow down the faster drive to compensate. |
| 229 | */ |
| 230 | int d = (opti_tim_as[spd][mode[0]] > |
| 231 | opti_tim_as[spd][mode[1]]) ? 0 : 1; |
| 232 | |
| 233 | mode[d] = mode[1-d]; |
| 234 | chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; |
| 235 | chp->ch_drive[d].DMA_mode = 0; |
| 236 | s = splbio(); |
| 237 | chp->ch_drive[d].drive_flags &= ~ATA_DRIVE_DMA; |
| 238 | splx(s); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | for (drive = 0; drive < 2; drive++) { |
| 243 | int m; |
| 244 | if ((m = mode[drive]) < 0) |
| 245 | continue; |
| 246 | |
| 247 | /* Set the Address Setup Time and select appropriate index */ |
| 248 | rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; |
| 249 | rv |= OPTI_MISC_INDEX(drive); |
| 250 | opti_write_config(chp, OPTI_REG_MISC, mr | rv); |
| 251 | |
| 252 | /* Set the pulse width and recovery timing parameters */ |
| 253 | rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; |
| 254 | rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; |
| 255 | opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); |
| 256 | opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); |
| 257 | |
| 258 | /* Set the Enhanced Mode register appropriately */ |
| 259 | rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); |
| 260 | rv &= ~OPTI_ENH_MODE_MASK(chp->ch_channel, drive); |
| 261 | rv |= OPTI_ENH_MODE(chp->ch_channel, drive, opti_tim_em[m]); |
| 262 | pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); |
| 263 | } |
| 264 | |
| 265 | /* Finally, enable the timings */ |
| 266 | opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); |
| 267 | } |
| 268 | |