| 1 | /* $NetBSD: if_bcereg.h,v 1.4 2005/12/11 12:22:49 christos Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2003 Clifford Wright. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 23 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | /* Broadcom BCM440x */ |
| 31 | |
| 32 | /* PCI registers defined in the PCI 2.2 spec. */ |
| 33 | #define BCE_PCI_BAR0 0x10 |
| 34 | |
| 35 | /* Sonics SB register access */ |
| 36 | #define BCE_REG_WIN 0x80 |
| 37 | #define BCE_SONICS_WIN 0x18002000 |
| 38 | |
| 39 | /* Sonics PCI control */ |
| 40 | #define BCE_SPCI_TR2 0x0108 /* Sonics to PCI translation |
| 41 | * 2 */ |
| 42 | /* bit defines */ |
| 43 | #define SBTOPCI_PREF 0x4 /* prefetch enable */ |
| 44 | #define SBTOPCI_BURST 0x8 /* burst enable */ |
| 45 | #define BCE_SBINTVEC 0x0f94 |
| 46 | /* interrupt bits */ |
| 47 | #define SBIV_ENET0 0x02 /* enable for enet 0 */ |
| 48 | #define SBIV_ENET1 0x40 /* enable for enet 1 */ |
| 49 | |
| 50 | |
| 51 | /* Host Interface Registers */ |
| 52 | |
| 53 | #define BCE_DEVCTL 0x0000 /* device control */ |
| 54 | /* device control bits */ |
| 55 | #define BCE_DC_IP 0x00000400 /* internal phy present */ |
| 56 | #define BCE_DC_ER 0x00008000 /* ephy reset */ |
| 57 | /* Interrupt Control */ |
| 58 | #define BCE_INT_STS 0x0020 |
| 59 | #define BCE_INT_MASK 0x0024 |
| 60 | /* bits for both status, and mask */ |
| 61 | #define I_TO 0x00000080 /* general timeout */ |
| 62 | #define I_PC 0x00000400 /* descriptor error */ |
| 63 | #define I_PD 0x00000800 /* data error */ |
| 64 | #define I_DE 0x00001000 /* desc. protocol error */ |
| 65 | #define I_RU 0x00002000 /* rx desc. underflow */ |
| 66 | #define I_RO 0x00004000 /* rx fifo overflow */ |
| 67 | #define I_XU 0x00008000 /* tx fifo underflow */ |
| 68 | #define I_RI 0x00010000 /* receive interrupt */ |
| 69 | #define I_XI 0x01000000 /* transmit interrupt */ |
| 70 | |
| 71 | /* Ethernet MAC Control */ |
| 72 | #define BCE_MACCTL 0x00A8 /* ethernet mac control */ |
| 73 | /* mac control bits */ |
| 74 | #define BCE_EMC_CG 0x00000001 /* crc32 generation */ |
| 75 | |
| 76 | /* DMA Interrupt control */ |
| 77 | #define BCE_DMAI_CTL 0x0100 |
| 78 | |
| 79 | /* DMA registers */ |
| 80 | #define BCE_DMA_TXCTL 0x0200 /* transmit control */ |
| 81 | /* transmit control bits */ |
| 82 | #define XC_XE 0x1 /* transmit enable */ |
| 83 | #define XC_LE 0x4 /* loopback enable */ |
| 84 | #define BCE_DMA_TXADDR 0x0204 /* tx ring base address */ |
| 85 | #define BCE_DMA_DPTR 0x0208 /* last tx descriptor */ |
| 86 | #define BCE_DMA_TXSTATUS 0x020C /* active desc, etc */ |
| 87 | #define BCE_DMA_RXCTL 0x0210 /* enable, etc */ |
| 88 | #define BCE_DMA_RXADDR 0x0214 /* rx ring base address */ |
| 89 | #define BCE_DMA_RXDPTR 0x0218 /* last descriptor */ |
| 90 | #define BCE_DMA_RXSTATUS 0x021C /* active desc, etc */ |
| 91 | /* receive status bits */ |
| 92 | #define RS_CD_MASK 0x0fff /* current descriptor pointer */ |
| 93 | #define RS_DMA_IDLE 0x2000 /* DMA is idle */ |
| 94 | #define RS_ERROR 0xf0000 /* had an error */ |
| 95 | |
| 96 | /* Ethernet MAC control registers */ |
| 97 | #define BCE_RX_CTL 0x0400 /* receive config */ |
| 98 | /* config bits */ |
| 99 | #define ERC_DB 0x00000001 /* disable broadcast */ |
| 100 | #define ERC_AM 0x00000002 /* rx all multicast */ |
| 101 | #define ERC_PE 0x00000008 /* promiscuous enable */ |
| 102 | |
| 103 | #define BCE_RX_MAX 0x0404 /* max packet length */ |
| 104 | #define BCE_TX_MAX 0x0408 |
| 105 | #define BCE_MI_CTL 0x0410 |
| 106 | #define BCE_MI_COMM 0x0414 |
| 107 | #define BCE_MI_STS 0x041C |
| 108 | /* mii status bits */ |
| 109 | #define BCE_MIINTR 0x00000001 /* mii mdio interrupt */ |
| 110 | |
| 111 | #define BCE_FILT_LOW 0x0420 /* mac low 4 bytes */ |
| 112 | #define BCE_FILT_HI 0x0424 /* mac hi 2 bytes */ |
| 113 | #define BCE_FILT_CTL 0x0428 /* packet filter ctrl */ |
| 114 | #define BCE_ENET_CTL 0x042C |
| 115 | /* bits for mac control */ |
| 116 | #define EC_EE 0x00000001 /* emac enable */ |
| 117 | #define EC_ED 0x00000002 /* disable emac */ |
| 118 | #define EC_ES 0x00000004 /* soft reset emac */ |
| 119 | #define EC_EP 0x00000008 /* external phy */ |
| 120 | #define BCE_TX_CTL 0x0430 |
| 121 | /* bits for transmit control */ |
| 122 | #define EXC_FD 0x00000001 /* full duplex */ |
| 123 | #define BCE_TX_WATER 0x0434 /* tx watermark */ |
| 124 | |
| 125 | /* statistics counters */ |
| 126 | #define BCE_RX_PKTS 0x058C |
| 127 | |
| 128 | /* SiliconBackplane registers */ |
| 129 | #define BCE_SBIMSTATE 0x0f90 |
| 130 | #define BCE_SBTMSTATELOW 0x0f98 |
| 131 | #define BCE_SBTMSTATEHI 0x0f9C |
| 132 | #define SBTML_RESET 0x1 /* reset */ |
| 133 | #define SBTML_REJ 0x2 /* reject */ |
| 134 | #define SBTML_CLK 0x10000 /* clock enable */ |
| 135 | #define SBTML_FGC 0x20000 /* force gated clocks on */ |
| 136 | |
| 137 | /* MI communication register */ |
| 138 | #define BCE_MICOMM_DATA 0x0000FFFF |
| 139 | |
| 140 | #define BCE_MIREG(x) ((x & 0x1F) << 18) |
| 141 | #define BCE_MIPHY(x) ((x & 0x1F) << 23) |
| 142 | |
| 143 | /* Magic constants.... */ |
| 144 | #define BCE_MAGIC_PHYEMAC_BASE 0x1000 |
| 145 | #define BCE_MAGIC_PHY (BCE_MAGIC_PHYEMAC_BASE + 90) |
| 146 | #define BCE_MAGIC_ENET0 (BCE_MAGIC_PHYEMAC_BASE + 79) |
| 147 | #define BCE_MAGIC_ENET1 (BCE_MAGIC_PHYEMAC_BASE + 78) |
| 148 | #define BCE_MAGIC_ENET2 (BCE_MAGIC_PHYEMAC_BASE + 81) |
| 149 | #define BCE_MAGIC_ENET3 (BCE_MAGIC_PHYEMAC_BASE + 80) |
| 150 | #define BCE_MAGIC_ENET4 (BCE_MAGIC_PHYEMAC_BASE + 83) |
| 151 | #define BCE_MAGIC_ENET5 (BCE_MAGIC_PHYEMAC_BASE + 82) |
| 152 | |
| 153 | #define SBIM_MAGIC_ERRORBITS 0x60000 |
| 154 | |