| 1 | /* $NetBSD: nouveau_subdev_fb_ramnva3.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2013 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_fb_ramnva3.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $" ); |
| 29 | |
| 30 | #include <subdev/bios.h> |
| 31 | #include <subdev/bios/bit.h> |
| 32 | #include <subdev/bios/pll.h> |
| 33 | #include <subdev/bios/rammap.h> |
| 34 | #include <subdev/bios/timing.h> |
| 35 | |
| 36 | #include <subdev/clock/nva3.h> |
| 37 | #include <subdev/clock/pll.h> |
| 38 | |
| 39 | #include <core/option.h> |
| 40 | |
| 41 | #include "ramfuc.h" |
| 42 | |
| 43 | #include "nv50.h" |
| 44 | |
| 45 | struct nva3_ramfuc { |
| 46 | struct ramfuc base; |
| 47 | struct ramfuc_reg r_0x004000; |
| 48 | struct ramfuc_reg r_0x004004; |
| 49 | struct ramfuc_reg r_0x004018; |
| 50 | struct ramfuc_reg r_0x004128; |
| 51 | struct ramfuc_reg r_0x004168; |
| 52 | struct ramfuc_reg r_0x100200; |
| 53 | struct ramfuc_reg r_0x100210; |
| 54 | struct ramfuc_reg r_0x100220[9]; |
| 55 | struct ramfuc_reg r_0x1002d0; |
| 56 | struct ramfuc_reg r_0x1002d4; |
| 57 | struct ramfuc_reg r_0x1002dc; |
| 58 | struct ramfuc_reg r_0x10053c; |
| 59 | struct ramfuc_reg r_0x1005a0; |
| 60 | struct ramfuc_reg r_0x1005a4; |
| 61 | struct ramfuc_reg r_0x100714; |
| 62 | struct ramfuc_reg r_0x100718; |
| 63 | struct ramfuc_reg r_0x10071c; |
| 64 | struct ramfuc_reg r_0x100760; |
| 65 | struct ramfuc_reg r_0x1007a0; |
| 66 | struct ramfuc_reg r_0x1007e0; |
| 67 | struct ramfuc_reg r_0x10f804; |
| 68 | struct ramfuc_reg r_0x1110e0; |
| 69 | struct ramfuc_reg r_0x111100; |
| 70 | struct ramfuc_reg r_0x111104; |
| 71 | struct ramfuc_reg r_0x611200; |
| 72 | struct ramfuc_reg r_mr[4]; |
| 73 | }; |
| 74 | |
| 75 | struct nva3_ram { |
| 76 | struct nouveau_ram base; |
| 77 | struct nva3_ramfuc fuc; |
| 78 | }; |
| 79 | |
| 80 | static int |
| 81 | nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) |
| 82 | { |
| 83 | struct nouveau_bios *bios = nouveau_bios(pfb); |
| 84 | struct nva3_ram *ram = (void *)pfb->ram; |
| 85 | struct nva3_ramfuc *fuc = &ram->fuc; |
| 86 | struct nva3_clock_info mclk; |
| 87 | u8 ver, cnt, len, strap; |
| 88 | u32 data; |
| 89 | struct { |
| 90 | u32 data; |
| 91 | u8 size; |
| 92 | } rammap, ramcfg, timing; |
| 93 | u32 r004018, r100760, ctrl; |
| 94 | u32 unk714, unk718, unk71c; |
| 95 | int ret; |
| 96 | |
| 97 | /* lookup memory config data relevant to the target frequency */ |
| 98 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, |
| 99 | &cnt, &ramcfg.size); |
| 100 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { |
| 101 | nv_error(pfb, "invalid/missing rammap entry\n" ); |
| 102 | return -EINVAL; |
| 103 | } |
| 104 | |
| 105 | /* locate specific data set for the attached memory */ |
| 106 | strap = nvbios_ramcfg_index(nv_subdev(pfb)); |
| 107 | if (strap >= cnt) { |
| 108 | nv_error(pfb, "invalid ramcfg strap\n" ); |
| 109 | return -EINVAL; |
| 110 | } |
| 111 | |
| 112 | ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size); |
| 113 | if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { |
| 114 | nv_error(pfb, "invalid/missing ramcfg entry\n" ); |
| 115 | return -EINVAL; |
| 116 | } |
| 117 | |
| 118 | /* lookup memory timings, if bios says they're present */ |
| 119 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
| 120 | if (strap != 0xff) { |
| 121 | timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, |
| 122 | &cnt, &len); |
| 123 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { |
| 124 | nv_error(pfb, "invalid/missing timing entry\n" ); |
| 125 | return -EINVAL; |
| 126 | } |
| 127 | } else { |
| 128 | timing.data = 0; |
| 129 | } |
| 130 | |
| 131 | ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); |
| 132 | if (ret < 0) { |
| 133 | nv_error(pfb, "failed mclk calculation\n" ); |
| 134 | return ret; |
| 135 | } |
| 136 | |
| 137 | ret = ram_init(fuc, pfb); |
| 138 | if (ret) |
| 139 | return ret; |
| 140 | |
| 141 | /* XXX: where the fuck does 750MHz come from? */ |
| 142 | if (freq <= 750000) { |
| 143 | r004018 = 0x10000000; |
| 144 | r100760 = 0x22222222; |
| 145 | } else { |
| 146 | r004018 = 0x00000000; |
| 147 | r100760 = 0x00000000; |
| 148 | } |
| 149 | |
| 150 | ctrl = ram_rd32(fuc, 0x004000); |
| 151 | if (ctrl & 0x00000008) { |
| 152 | if (mclk.pll) { |
| 153 | ram_mask(fuc, 0x004128, 0x00000101, 0x00000101); |
| 154 | ram_wr32(fuc, 0x004004, mclk.pll); |
| 155 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001)); |
| 156 | ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef)); |
| 157 | ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000); |
| 158 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010)); |
| 159 | ram_wr32(fuc, 0x004018, 0x00005000 | r004018); |
| 160 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004)); |
| 161 | } |
| 162 | } else { |
| 163 | u32 ssel = 0x00000101; |
| 164 | if (mclk.clk) |
| 165 | ssel |= mclk.clk; |
| 166 | else |
| 167 | ssel |= 0x00080000; /* 324MHz, shouldn't matter... */ |
| 168 | ram_mask(fuc, 0x004168, 0x003f3141, ctrl); |
| 169 | } |
| 170 | |
| 171 | if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { |
| 172 | ram_mask(fuc, 0x111104, 0x00000600, 0x00000000); |
| 173 | } else { |
| 174 | ram_mask(fuc, 0x111100, 0x40000000, 0x40000000); |
| 175 | ram_mask(fuc, 0x111104, 0x00000180, 0x00000000); |
| 176 | } |
| 177 | |
| 178 | if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02)) |
| 179 | ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); |
| 180 | ram_wr32(fuc, 0x611200, 0x00003300); |
| 181 | if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) |
| 182 | ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/ |
| 183 | |
| 184 | ram_wr32(fuc, 0x1002d4, 0x00000001); |
| 185 | ram_wr32(fuc, 0x1002d0, 0x00000001); |
| 186 | ram_wr32(fuc, 0x1002d0, 0x00000001); |
| 187 | ram_wr32(fuc, 0x100210, 0x00000000); |
| 188 | ram_wr32(fuc, 0x1002dc, 0x00000001); |
| 189 | ram_nsec(fuc, 2000); |
| 190 | |
| 191 | ctrl = ram_rd32(fuc, 0x004000); |
| 192 | if (!(ctrl & 0x00000008) && mclk.pll) { |
| 193 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008)); |
| 194 | ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); |
| 195 | ram_wr32(fuc, 0x004018, 0x00001000); |
| 196 | ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001)); |
| 197 | ram_wr32(fuc, 0x004004, mclk.pll); |
| 198 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001)); |
| 199 | udelay(64); |
| 200 | ram_wr32(fuc, 0x004018, 0x00005000 | r004018); |
| 201 | udelay(20); |
| 202 | } else |
| 203 | if (!mclk.pll) { |
| 204 | ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk); |
| 205 | ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008)); |
| 206 | ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); |
| 207 | ram_wr32(fuc, 0x004018, 0x0000d000 | r004018); |
| 208 | } |
| 209 | |
| 210 | if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) { |
| 211 | u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) | |
| 212 | nv_ro08(bios, ramcfg.data + 0x05); |
| 213 | u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07)); |
| 214 | u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 | |
| 215 | (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 | |
| 216 | (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) | |
| 217 | 0x80000000; |
| 218 | ram_wr32(fuc, 0x1005a0, unk5a0); |
| 219 | ram_wr32(fuc, 0x1005a4, unk5a4); |
| 220 | ram_wr32(fuc, 0x10f804, unk804); |
| 221 | ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000); |
| 222 | } else { |
| 223 | ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000); |
| 224 | ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000); |
| 225 | ram_mask(fuc, 0x100760, 0x22222222, r100760); |
| 226 | ram_mask(fuc, 0x1007a0, 0x22222222, r100760); |
| 227 | ram_mask(fuc, 0x1007e0, 0x22222222, r100760); |
| 228 | } |
| 229 | |
| 230 | if (mclk.pll) { |
| 231 | ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000); |
| 232 | ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008)); |
| 233 | } |
| 234 | |
| 235 | /*XXX: LEAVE */ |
| 236 | ram_wr32(fuc, 0x1002dc, 0x00000000); |
| 237 | ram_wr32(fuc, 0x1002d4, 0x00000001); |
| 238 | ram_wr32(fuc, 0x100210, 0x80000000); |
| 239 | ram_nsec(fuc, 1000); |
| 240 | ram_nsec(fuc, 1000); |
| 241 | |
| 242 | ram_mask(fuc, mr[2], 0x00000000, 0x00000000); |
| 243 | ram_nsec(fuc, 1000); |
| 244 | ram_nuke(fuc, mr[0]); |
| 245 | ram_mask(fuc, mr[0], 0x00000000, 0x00000000); |
| 246 | ram_nsec(fuc, 1000); |
| 247 | |
| 248 | ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000); |
| 249 | ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000); |
| 250 | ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000); |
| 251 | ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000); |
| 252 | ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000); |
| 253 | ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000); |
| 254 | ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000); |
| 255 | ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000); |
| 256 | ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000); |
| 257 | |
| 258 | data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000; |
| 259 | ram_mask(fuc, 0x100200, 0x00001000, data); |
| 260 | |
| 261 | unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010; |
| 262 | unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100; |
| 263 | unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; |
| 264 | if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20)) |
| 265 | unk714 |= 0xf0000000; |
| 266 | if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04)) |
| 267 | unk714 |= 0x00000010; |
| 268 | ram_wr32(fuc, 0x100714, unk714); |
| 269 | |
| 270 | if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01) |
| 271 | unk71c |= 0x00000100; |
| 272 | ram_wr32(fuc, 0x10071c, unk71c); |
| 273 | |
| 274 | if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02) |
| 275 | unk718 |= 0x00000100; |
| 276 | ram_wr32(fuc, 0x100718, unk718); |
| 277 | |
| 278 | if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10) |
| 279 | ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/ |
| 280 | |
| 281 | ram_mask(fuc, mr[0], 0x100, 0x100); |
| 282 | ram_nsec(fuc, 1000); |
| 283 | ram_mask(fuc, mr[0], 0x100, 0x000); |
| 284 | ram_nsec(fuc, 1000); |
| 285 | |
| 286 | ram_nsec(fuc, 2000); |
| 287 | ram_nsec(fuc, 12000); |
| 288 | |
| 289 | ram_wr32(fuc, 0x611200, 0x00003330); |
| 290 | if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02)) |
| 291 | ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); |
| 292 | if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { |
| 293 | ram_mask(fuc, 0x111104, 0x00000180, 0x00000180); |
| 294 | ram_mask(fuc, 0x111100, 0x40000000, 0x00000000); |
| 295 | } else { |
| 296 | ram_mask(fuc, 0x111104, 0x00000600, 0x00000600); |
| 297 | } |
| 298 | |
| 299 | if (mclk.pll) { |
| 300 | ram_mask(fuc, 0x004168, 0x00000001, 0x00000000); |
| 301 | ram_mask(fuc, 0x004168, 0x00000100, 0x00000000); |
| 302 | } else { |
| 303 | ram_mask(fuc, 0x004000, 0x00000001, 0x00000000); |
| 304 | ram_mask(fuc, 0x004128, 0x00000001, 0x00000000); |
| 305 | ram_mask(fuc, 0x004128, 0x00000100, 0x00000000); |
| 306 | } |
| 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | static int |
| 312 | nva3_ram_prog(struct nouveau_fb *pfb) |
| 313 | { |
| 314 | struct nouveau_device *device = nv_device(pfb); |
| 315 | struct nva3_ram *ram = (void *)pfb->ram; |
| 316 | struct nva3_ramfuc *fuc = &ram->fuc; |
| 317 | ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec" , false)); |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static void |
| 322 | nva3_ram_tidy(struct nouveau_fb *pfb) |
| 323 | { |
| 324 | struct nva3_ram *ram = (void *)pfb->ram; |
| 325 | struct nva3_ramfuc *fuc = &ram->fuc; |
| 326 | ram_exec(fuc, false); |
| 327 | } |
| 328 | |
| 329 | static int |
| 330 | nva3_ram_init(struct nouveau_object *object) |
| 331 | { |
| 332 | struct nouveau_fb *pfb = (void *)object->parent; |
| 333 | struct nva3_ram *ram = (void *)object; |
| 334 | int ret, i; |
| 335 | |
| 336 | ret = nouveau_ram_init(&ram->base); |
| 337 | if (ret) |
| 338 | return ret; |
| 339 | |
| 340 | /* prepare for ddr link training, and load training patterns */ |
| 341 | switch (ram->base.type) { |
| 342 | case NV_MEM_TYPE_DDR3: { |
| 343 | if (nv_device(pfb)->chipset == 0xa8) { |
| 344 | static const u32 pattern[16] = { |
| 345 | 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, |
| 346 | 0x00000000, 0x11111111, 0x44444444, 0xdddddddd, |
| 347 | 0x33333333, 0x55555555, 0x77777777, 0x66666666, |
| 348 | 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, |
| 349 | }; |
| 350 | |
| 351 | nv_wr32(pfb, 0x100538, 0x10001ff6); /*XXX*/ |
| 352 | nv_wr32(pfb, 0x1005a8, 0x0000ffff); |
| 353 | nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001); |
| 354 | for (i = 0; i < 0x30; i++) { |
| 355 | nv_wr32(pfb, 0x10f8c0, (i << 8) | i); |
| 356 | nv_wr32(pfb, 0x10f8e0, (i << 8) | i); |
| 357 | nv_wr32(pfb, 0x10f900, pattern[i % 16]); |
| 358 | nv_wr32(pfb, 0x10f920, pattern[i % 16]); |
| 359 | } |
| 360 | } |
| 361 | } |
| 362 | break; |
| 363 | default: |
| 364 | break; |
| 365 | } |
| 366 | |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | static int |
| 371 | nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 372 | struct nouveau_oclass *oclass, void *data, u32 datasize, |
| 373 | struct nouveau_object **pobject) |
| 374 | { |
| 375 | struct nva3_ram *ram; |
| 376 | int ret, i; |
| 377 | |
| 378 | ret = nv50_ram_create(parent, engine, oclass, &ram); |
| 379 | *pobject = nv_object(ram); |
| 380 | if (ret) |
| 381 | return ret; |
| 382 | |
| 383 | switch (ram->base.type) { |
| 384 | case NV_MEM_TYPE_DDR3: |
| 385 | ram->base.calc = nva3_ram_calc; |
| 386 | ram->base.prog = nva3_ram_prog; |
| 387 | ram->base.tidy = nva3_ram_tidy; |
| 388 | break; |
| 389 | default: |
| 390 | nv_warn(ram, "reclocking of this ram type unsupported\n" ); |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | ram->fuc.r_0x004000 = ramfuc_reg(0x004000); |
| 395 | ram->fuc.r_0x004004 = ramfuc_reg(0x004004); |
| 396 | ram->fuc.r_0x004018 = ramfuc_reg(0x004018); |
| 397 | ram->fuc.r_0x004128 = ramfuc_reg(0x004128); |
| 398 | ram->fuc.r_0x004168 = ramfuc_reg(0x004168); |
| 399 | ram->fuc.r_0x100200 = ramfuc_reg(0x100200); |
| 400 | ram->fuc.r_0x100210 = ramfuc_reg(0x100210); |
| 401 | for (i = 0; i < 9; i++) |
| 402 | ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4)); |
| 403 | ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0); |
| 404 | ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4); |
| 405 | ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc); |
| 406 | ram->fuc.r_0x10053c = ramfuc_reg(0x10053c); |
| 407 | ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0); |
| 408 | ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4); |
| 409 | ram->fuc.r_0x100714 = ramfuc_reg(0x100714); |
| 410 | ram->fuc.r_0x100718 = ramfuc_reg(0x100718); |
| 411 | ram->fuc.r_0x10071c = ramfuc_reg(0x10071c); |
| 412 | ram->fuc.r_0x100760 = ramfuc_reg(0x100760); |
| 413 | ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0); |
| 414 | ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0); |
| 415 | ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804); |
| 416 | ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0); |
| 417 | ram->fuc.r_0x111100 = ramfuc_reg(0x111100); |
| 418 | ram->fuc.r_0x111104 = ramfuc_reg(0x111104); |
| 419 | ram->fuc.r_0x611200 = ramfuc_reg(0x611200); |
| 420 | |
| 421 | if (ram->base.ranks > 1) { |
| 422 | ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8); |
| 423 | ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc); |
| 424 | ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8); |
| 425 | ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec); |
| 426 | } else { |
| 427 | ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0); |
| 428 | ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4); |
| 429 | ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0); |
| 430 | ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4); |
| 431 | } |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | struct nouveau_oclass |
| 437 | nva3_ram_oclass = { |
| 438 | .ofuncs = &(struct nouveau_ofuncs) { |
| 439 | .ctor = nva3_ram_ctor, |
| 440 | .dtor = _nouveau_ram_dtor, |
| 441 | .init = nva3_ram_init, |
| 442 | .fini = _nouveau_ram_fini, |
| 443 | }, |
| 444 | }; |
| 445 | |