| 1 | /* $NetBSD: rtsxreg.h,v 1.2 2014/10/29 14:24:09 nonaka Exp $ */ |
| 2 | /* $OpenBSD: rtsxreg.h,v 1.3 2013/11/26 20:33:16 deraadt Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> |
| 6 | * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _RTSXREG_H_ |
| 22 | #define _RTSXREG_H_ |
| 23 | |
| 24 | /* Host command buffer control register. */ |
| 25 | #define RTSX_HCBAR 0x00 |
| 26 | #define RTSX_HCBCTLR 0x04 |
| 27 | #define RTSX_START_CMD (1U << 31) |
| 28 | #define RTSX_HW_AUTO_RSP (1U << 30) |
| 29 | #define RTSX_STOP_CMD (1U << 28) |
| 30 | |
| 31 | /* Host data buffer control register. */ |
| 32 | #define RTSX_HDBAR 0x08 |
| 33 | #define RTSX_HDBCTLR 0x0C |
| 34 | #define RTSX_TRIG_DMA (1U << 31) |
| 35 | #define RTSX_DMA_READ (1U << 29) |
| 36 | #define RTSX_STOP_DMA (1U << 28) |
| 37 | #define RTSX_ADMA_MODE (2U << 26) |
| 38 | |
| 39 | /* Interrupt pending register. */ |
| 40 | #define RTSX_BIPR 0x14 |
| 41 | #define RTSX_CMD_DONE_INT (1U << 31) |
| 42 | #define RTSX_DATA_DONE_INT (1U << 30) |
| 43 | #define RTSX_TRANS_OK_INT (1U << 29) |
| 44 | #define RTSX_TRANS_FAIL_INT (1U << 28) |
| 45 | #define RTSX_XD_INT (1U << 27) |
| 46 | #define RTSX_MS_INT (1U << 26) |
| 47 | #define RTSX_SD_INT (1U << 25) |
| 48 | #define RTSX_SD_WRITE_PROTECT (1U << 19) |
| 49 | #define RTSX_XD_EXIST (1U << 18) |
| 50 | #define RTSX_MS_EXIST (1U << 17) |
| 51 | #define RTSX_SD_EXIST (1U << 16) |
| 52 | #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) |
| 53 | #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) |
| 54 | |
| 55 | /* Chip register access. */ |
| 56 | #define RTSX_HAIMR 0x10 |
| 57 | #define RTSX_HAIMR_WRITE 0x40000000 |
| 58 | #define RTSX_HAIMR_BUSY 0x80000000 |
| 59 | |
| 60 | /* Interrupt enable register. */ |
| 61 | #define RTSX_BIER 0x18 |
| 62 | #define RTSX_CMD_DONE_INT_EN (1U << 31) |
| 63 | #define RTSX_DATA_DONE_INT_EN (1U << 30) |
| 64 | #define RTSX_TRANS_OK_INT_EN (1U << 29) |
| 65 | #define RTSX_TRANS_FAIL_INT_EN (1U << 28) |
| 66 | #define RTSX_XD_INT_EN (1U << 27) |
| 67 | #define RTSX_MS_INT_EN (1U << 26) |
| 68 | #define RTSX_SD_INT_EN (1U << 25) |
| 69 | #define RTSX_GPIO0_INT_EN (1U << 24) |
| 70 | #define RTSX_MS_OC_INT_EN (1U << 23) |
| 71 | #define RTSX_SD_OC_INT_EN (1U << 22) |
| 72 | |
| 73 | /* Power on/off. */ |
| 74 | #define RTSX_FPDCTL 0xFC00 |
| 75 | #define RTSX_SSC_POWER_DOWN 0x01 |
| 76 | #define RTSX_SD_OC_POWER_DOWN 0x02 |
| 77 | #define RTSX_MS_OC_POWER_DOWN 0x04 |
| 78 | #define RTSX_ALL_POWER_DOWN 0x07 |
| 79 | #define RTSX_OC_POWER_DOWN 0x06 |
| 80 | |
| 81 | /* Card power control register. */ |
| 82 | #define RTSX_CARD_PWR_CTL 0xFD50 |
| 83 | #define RTSX_SD_PWR_ON 0x00 |
| 84 | #define RTSX_SD_PARTIAL_PWR_ON 0x01 |
| 85 | #define RTSX_SD_PWR_OFF 0x03 |
| 86 | #define RTSX_SD_PWR_MASK 0x03 |
| 87 | #define RTSX_PMOS_STRG_MASK 0x10 |
| 88 | #define RTSX_PMOS_STRG_400mA 0x00 |
| 89 | #define RTSX_PMOS_STRG_800mA 0x10 |
| 90 | #define RTSX_BPP_POWER_MASK 0x0F |
| 91 | #define RTSX_BPP_POWER_OFF 0x0F |
| 92 | #define RTSX_BPP_POWER_5_PERCENT_ON 0x0E |
| 93 | #define RTSX_BPP_POWER_10_PERCENT_ON 0x0C |
| 94 | #define RTSX_BPP_POWER_15_PERCENT_ON 0x08 |
| 95 | #define RTSX_BPP_POWER_ON 0x00 |
| 96 | |
| 97 | #define RTSX_MS_PWR_OFF 0x0C |
| 98 | #define RTSX_MS_PWR_ON 0x00 |
| 99 | #define RTSX_MS_PARTIAL_PWR_ON 0x04 |
| 100 | |
| 101 | #define RTSX_RTL8411B_PACKAGE 0xFD51 |
| 102 | #define RTSX_RTL8411B_QFN48 0x02 |
| 103 | |
| 104 | #define RTSX_CARD_SHARE_MODE 0xFD52 |
| 105 | #define RTSX_CARD_SHARE_48_XD 0x02 |
| 106 | #define RTSX_CARD_SHARE_48_SD 0x04 |
| 107 | #define RTSX_CARD_SHARE_48_MS 0x08 |
| 108 | #define RTSX_CARD_DRIVE_SEL 0xFE53 |
| 109 | |
| 110 | /* Card clock. */ |
| 111 | #define RTSX_CARD_CLK_EN 0xFD69 |
| 112 | #define RTSX_XD_CLK_EN 0x02 |
| 113 | #define RTSX_SD_CLK_EN 0x04 |
| 114 | #define RTSX_MS_CLK_EN 0x08 |
| 115 | #define RTSX_SPI_CLK_EN 0x10 |
| 116 | #define RTSX_CARD_CLK_EN_ALL \ |
| 117 | (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) |
| 118 | |
| 119 | #define RTSX_SDIO_CTRL 0xFD6B |
| 120 | #define RTSX_SDIO_BUS_CTRL 0x01 |
| 121 | #define RTSX_SDIO_CD_CTRL 0x02 |
| 122 | |
| 123 | #define RTSX_CARD_PAD_CTL 0xFD73 |
| 124 | #define RTSX_CARD_XD_CARD 0x01 |
| 125 | #define RTSX_CARD_SD_CARD 0x02 |
| 126 | #define RTSX_CARD_MS_CARD 0x04 |
| 127 | #define RTSX_CARD_AUTO_DISABLE 0x40 |
| 128 | |
| 129 | /* Internal clock. */ |
| 130 | #define RTSX_CLK_CTL 0xFC02 |
| 131 | #define RTSX_CLK_LOW_FREQ 0x01 |
| 132 | |
| 133 | /* Internal clock divisor values. */ |
| 134 | #define RTSX_CLK_DIV 0xFC03 |
| 135 | #define RTSX_CLK_DIV_1 0x01 |
| 136 | #define RTSX_CLK_DIV_2 0x02 |
| 137 | #define RTSX_CLK_DIV_4 0x03 |
| 138 | #define RTSX_CLK_DIV_8 0x04 |
| 139 | |
| 140 | /* Internal clock selection. */ |
| 141 | #define RTSX_CLK_SEL 0xFC04 |
| 142 | #define RTSX_SSC_80 0 |
| 143 | #define RTSX_SSC_100 1 |
| 144 | #define RTSX_SSC_120 2 |
| 145 | #define RTSX_SSC_150 3 |
| 146 | #define RTSX_SSC_200 4 |
| 147 | |
| 148 | #define RTSX_SSC_DIV_N_0 0xFC0F |
| 149 | |
| 150 | #define RTSX_SSC_CTL1 0xFC11 |
| 151 | #define RTSX_RSTB 0x80 |
| 152 | #define RTSX_SSC_8X_EN 0x40 |
| 153 | #define RTSX_SSC_FIX_FRAC 0x20 |
| 154 | #define RTSX_SSC_SEL_1M 0x00 |
| 155 | #define RTSX_SSC_SEL_2M 0x08 |
| 156 | #define RTSX_SSC_SEL_2M 0x08 |
| 157 | #define RTSX_SSC_SEL_4M 0x10 |
| 158 | #define RTSX_SSC_SEL_8M 0x18 |
| 159 | #define RTSX_SSC_CTL2 0xFC12 |
| 160 | #define RTSX_SSC_DEPTH_MASK 0x07 |
| 161 | |
| 162 | /* RC oscillator, default is 2M */ |
| 163 | #define RTSX_RCCTL 0xFC14 |
| 164 | #define RTSX_RCCTL_F_400K 0x0 |
| 165 | #define RTSX_RCCTL_F_2M 0x1 |
| 166 | |
| 167 | /* RTS5229-only. */ |
| 168 | #define RTSX_OLT_LED_CTL 0xFC1E |
| 169 | #define RTSX_OLT_LED_PERIOD 0x02 |
| 170 | #define RTSX_OLT_LED_AUTOBLINK 0x08 |
| 171 | |
| 172 | #define RTSX_LDO_CTL 0xFC1E |
| 173 | #define RTSX_BPP_ASIC_3V3 0x07 |
| 174 | #define RTSX_BPP_ASIC_MASK 0x07 |
| 175 | #define RTSX_BPP_PAD_3V3 0x04 |
| 176 | #define RTSX_BPP_PAD_1V8 0x00 |
| 177 | #define RTSX_BPP_PAD_MASK 0x04 |
| 178 | #define RTSX_BPP_LDO_POWB 0x03 |
| 179 | #define RTSX_BPP_LDO_ON 0x00 |
| 180 | #define RTSX_BPP_LDO_SUSPEND 0x02 |
| 181 | #define RTSX_BPP_LDO_OFF 0x03 |
| 182 | |
| 183 | #define RTSX_GPIO_CTL 0xFC1F |
| 184 | #define RTSX_GPIO_LED_ON 0x02 |
| 185 | |
| 186 | /* Host controller commands. */ |
| 187 | #define RTSX_READ_REG_CMD 0 |
| 188 | #define RTSX_WRITE_REG_CMD 1 |
| 189 | #define RTSX_CHECK_REG_CMD 2 |
| 190 | |
| 191 | |
| 192 | #define RTSX_OCPCTL 0xFC15 |
| 193 | #define RTSX_OCPSTAT 0xFC16 |
| 194 | #define RTSX_OCPGLITCH 0xFC17 |
| 195 | #define RTSX_OCPPARA1 0xFC18 |
| 196 | #define RTSX_OCPPARA2 0xFC19 |
| 197 | |
| 198 | /* FPGA */ |
| 199 | #define RTSX_FPGA_PULL_CTL 0xFC1D |
| 200 | #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 |
| 201 | #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 |
| 202 | |
| 203 | #define RTSX_SYS_VER 0xFC32 |
| 204 | |
| 205 | /* Clock source configuration register. */ |
| 206 | #define RTSX_CARD_CLK_SOURCE 0xFC2E |
| 207 | #define RTSX_CRC_FIX_CLK (0x00 << 0) |
| 208 | #define RTSX_CRC_VAR_CLK0 (0x01 << 0) |
| 209 | #define RTSX_CRC_VAR_CLK1 (0x02 << 0) |
| 210 | #define RTSX_SD30_FIX_CLK (0x00 << 2) |
| 211 | #define RTSX_SD30_VAR_CLK0 (0x01 << 2) |
| 212 | #define RTSX_SD30_VAR_CLK1 (0x02 << 2) |
| 213 | #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) |
| 214 | #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) |
| 215 | #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) |
| 216 | |
| 217 | |
| 218 | /* ASIC */ |
| 219 | #define RTSX_CARD_PULL_CTL1 0xFD60 |
| 220 | #define RTSX_CARD_PULL_CTL2 0xFD61 |
| 221 | #define RTSX_CARD_PULL_CTL3 0xFD62 |
| 222 | #define RTSX_CARD_PULL_CTL4 0xFD63 |
| 223 | #define RTSX_CARD_PULL_CTL5 0xFD64 |
| 224 | #define RTSX_CARD_PULL_CTL6 0xFD65 |
| 225 | |
| 226 | #define RTSX_PULL_CTL_DISABLE12 0x55 |
| 227 | #define RTSX_PULL_CTL_DISABLE3 0xD5 |
| 228 | #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 |
| 229 | #define RTSX_PULL_CTL_ENABLE12 0xAA |
| 230 | #define RTSX_PULL_CTL_ENABLE3 0xE9 |
| 231 | #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 |
| 232 | |
| 233 | /* SD configuration register 1 (clock divider, bus mode and width). */ |
| 234 | #define RTSX_SD_CFG1 0xFDA0 |
| 235 | #define RTSX_CLK_DIVIDE_0 0x00 |
| 236 | #define RTSX_CLK_DIVIDE_128 0x80 |
| 237 | #define RTSX_CLK_DIVIDE_256 0xC0 |
| 238 | #define RTSX_CLK_DIVIDE_MASK 0xC0 |
| 239 | #define RTSX_SD20_MODE 0x00 |
| 240 | #define RTSX_SDDDR_MODE 0x04 |
| 241 | #define RTSX_SD30_MODE 0x08 |
| 242 | #define RTSX_SD_MODE_MASK 0x0C |
| 243 | #define RTSX_BUS_WIDTH_1 0x00 |
| 244 | #define RTSX_BUS_WIDTH_4 0x01 |
| 245 | #define RTSX_BUS_WIDTH_8 0x02 |
| 246 | #define RTSX_BUS_WIDTH_MASK 0x03 |
| 247 | |
| 248 | /* SD configuration register 2 (SD command response flags). */ |
| 249 | #define RTSX_SD_CFG2 0xFDA1 |
| 250 | #define RTSX_SD_CALCULATE_CRC7 0x00 |
| 251 | #define RTSX_SD_NO_CALCULATE_CRC7 0x80 |
| 252 | #define RTSX_SD_CHECK_CRC16 0x00 |
| 253 | #define RTSX_SD_NO_CHECK_CRC16 0x40 |
| 254 | #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 |
| 255 | #define RTSX_SD_WAIT_BUSY_END 0x08 |
| 256 | #define RTSX_SD_NO_WAIT_BUSY_END 0x00 |
| 257 | #define RTSX_SD_CHECK_CRC7 0x00 |
| 258 | #define RTSX_SD_NO_CHECK_CRC7 0x04 |
| 259 | #define RTSX_SD_RSP_LEN_0 0x00 |
| 260 | #define RTSX_SD_RSP_LEN_6 0x01 |
| 261 | #define RTSX_SD_RSP_LEN_17 0x02 |
| 262 | /* SD command response types. */ |
| 263 | #define RTSX_SD_RSP_TYPE_R0 0x04 |
| 264 | #define RTSX_SD_RSP_TYPE_R1 0x01 |
| 265 | #define RTSX_SD_RSP_TYPE_R1B 0x09 |
| 266 | #define RTSX_SD_RSP_TYPE_R2 0x02 |
| 267 | #define RTSX_SD_RSP_TYPE_R3 0x05 |
| 268 | #define RTSX_SD_RSP_TYPE_R4 0x05 |
| 269 | #define RTSX_SD_RSP_TYPE_R5 0x01 |
| 270 | #define RTSX_SD_RSP_TYPE_R6 0x01 |
| 271 | #define RTSX_SD_RSP_TYPE_R7 0x01 |
| 272 | |
| 273 | #define RTSX_SD_STAT1 0xFDA3 |
| 274 | #define RTSX_SD_CRC7_ERR 0x80 |
| 275 | #define RTSX_SD_CRC16_ERR 0x40 |
| 276 | #define RTSX_SD_CRC_WRITE_ERR 0x20 |
| 277 | #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C |
| 278 | #define RTSX_GET_CRC_TIME_OUT 0x02 |
| 279 | #define RTSX_SD_TUNING_COMPARE_ERR 0x01 |
| 280 | #define RTSX_SD_STAT2 0xFDA4 |
| 281 | #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 |
| 282 | |
| 283 | #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) |
| 284 | |
| 285 | /* SD bus status register. */ |
| 286 | #define RTSX_SD_BUS_STAT 0xFDA5 |
| 287 | #define RTSX_SD_CLK_TOGGLE_EN 0x80 |
| 288 | #define RTSX_SD_CLK_FORCE_STOP 0x40 |
| 289 | #define RTSX_SD_DAT3_STATUS 0x10 |
| 290 | #define RTSX_SD_DAT2_STATUS 0x08 |
| 291 | #define RTSX_SD_DAT1_STATUS 0x04 |
| 292 | #define RTSX_SD_DAT0_STATUS 0x02 |
| 293 | #define RTSX_SD_CMD_STATUS 0x01 |
| 294 | |
| 295 | #define RTSX_SD_PAD_CTL 0xFDA6 |
| 296 | #define RTSX_SD_IO_USING_1V8 0x80 |
| 297 | |
| 298 | /* Sample point control register. */ |
| 299 | #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 |
| 300 | #define RTSX_DDR_FIX_RX_DAT 0x00 |
| 301 | #define RTSX_DDR_VAR_RX_DAT 0x80 |
| 302 | #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 |
| 303 | #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 |
| 304 | #define RTSX_DDR_FIX_RX_CMD 0x00 |
| 305 | #define RTSX_DDR_VAR_RX_CMD 0x20 |
| 306 | #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 |
| 307 | #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 |
| 308 | #define RTSX_SD20_RX_POS_EDGE 0x00 |
| 309 | #define RTSX_SD20_RX_14_DELAY 0x08 |
| 310 | #define RTSX_SD20_RX_SEL_MASK 0x08 |
| 311 | |
| 312 | #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 |
| 313 | #define RTSX_SD20_TX_NEG_EDGE 0x00 |
| 314 | |
| 315 | #define RTSX_SD_CMD0 0xFDA9 |
| 316 | #define RTSX_SD_CMD1 0xFDAA |
| 317 | #define RTSX_SD_CMD2 0xFDAB |
| 318 | #define RTSX_SD_CMD3 0xFDAC |
| 319 | #define RTSX_SD_CMD4 0xFDAD |
| 320 | #define RTSX_SD_CMD5 0xFDAE |
| 321 | #define RTSX_SD_BYTE_CNT_L 0xFDAF |
| 322 | #define RTSX_SD_BYTE_CNT_H 0xFDB0 |
| 323 | #define RTSX_SD_BLOCK_CNT_L 0xFDB1 |
| 324 | #define RTSX_SD_BLOCK_CNT_H 0xFDB2 |
| 325 | |
| 326 | /* |
| 327 | * Transfer modes. |
| 328 | */ |
| 329 | #define RTSX_SD_TRANSFER 0xFDB3 |
| 330 | |
| 331 | /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ |
| 332 | #define RTSX_TM_NORMAL_WRITE 0x00 |
| 333 | |
| 334 | /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ |
| 335 | #define RTSX_TM_AUTO_WRITE3 0x01 |
| 336 | |
| 337 | /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. |
| 338 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ |
| 339 | #define RTSX_TM_AUTO_WRITE4 0x02 |
| 340 | |
| 341 | /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ |
| 342 | #define RTSX_TM_AUTO_READ3 0x05 |
| 343 | |
| 344 | /* Like AUTO_READ3, plus automatically send CMD 12 when done. |
| 345 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ |
| 346 | #define RTSX_TM_AUTO_READ4 0x06 |
| 347 | |
| 348 | /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put |
| 349 | * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put |
| 350 | * into ping-pong buffer 2 instead. */ |
| 351 | #define RTSX_TM_CMD_RSP 0x08 |
| 352 | |
| 353 | /* Send write command, get response from the card, write data from ring |
| 354 | * buffer to card, and send CMD 12 when done. |
| 355 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ |
| 356 | #define RTSX_TM_AUTO_WRITE1 0x09 |
| 357 | |
| 358 | /* Like AUTO_WRITE1 except no CMD 12 is sent. */ |
| 359 | #define RTSX_TM_AUTO_WRITE2 0x0A |
| 360 | |
| 361 | /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) |
| 362 | * from the card into the ring buffer or ping-pong buffer 2. */ |
| 363 | #define RTSX_TM_NORMAL_READ 0x0C |
| 364 | |
| 365 | /* Same as WRITE1, except data is read from the card to the ring buffer. */ |
| 366 | #define RTSX_TM_AUTO_READ1 0x0D |
| 367 | |
| 368 | /* Same as WRITE2, except data is read from the card to the ring buffer. */ |
| 369 | #define RTSX_TM_AUTO_READ2 0x0E |
| 370 | |
| 371 | /* Send CMD 19 and receive response and tuning pattern from card and |
| 372 | * report the result. */ |
| 373 | #define RTSX_TM_AUTO_TUNING 0x0F |
| 374 | |
| 375 | /* transfer control */ |
| 376 | #define RTSX_SD_TRANSFER_START 0x80 |
| 377 | #define RTSX_SD_TRANSFER_END 0x40 |
| 378 | #define RTSX_SD_STAT_IDLE 0x20 |
| 379 | #define RTSX_SD_TRANSFER_ERR 0x10 |
| 380 | |
| 381 | #define RTSX_SD_CMD_STATE 0xFDB5 |
| 382 | #define RTSX_CMD_IDLE 0x80 |
| 383 | #define RTSX_SD_DATA_STATE 0xFDB6 |
| 384 | #define RTSX_DATA_IDLE 0x80 |
| 385 | |
| 386 | #define RTSX_CARD_STOP 0xFD54 |
| 387 | #define RTSX_SPI_STOP 0x01 |
| 388 | #define RTSX_XD_STOP 0x02 |
| 389 | #define RTSX_SD_STOP 0x04 |
| 390 | #define RTSX_MS_STOP 0x08 |
| 391 | #define RTSX_SPI_CLR_ERR 0x10 |
| 392 | #define RTSX_XD_CLR_ERR 0x20 |
| 393 | #define RTSX_SD_CLR_ERR 0x40 |
| 394 | #define RTSX_MS_CLR_ERR 0x80 |
| 395 | #define RTSX_ALL_STOP 0x0F |
| 396 | #define RTSX_ALL_CLR_ERR 0xF0 |
| 397 | |
| 398 | #define RTSX_CARD_OE 0xFD55 |
| 399 | #define RTSX_XD_OUTPUT_EN 0x02 |
| 400 | #define RTSX_SD_OUTPUT_EN 0x04 |
| 401 | #define RTSX_MS_OUTPUT_EN 0x08 |
| 402 | #define RTSX_SPI_OUTPUT_EN 0x10 |
| 403 | #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ |
| 404 | RTSX_MS_OUTPUT_EN) |
| 405 | |
| 406 | #define RTSX_CARD_DATA_SOURCE 0xFD5B |
| 407 | #define RTSX_RING_BUFFER 0x00 |
| 408 | #define RTSX_PINGPONG_BUFFER 0x01 |
| 409 | #define RTSX_CARD_SELECT 0xFD5C |
| 410 | #define RTSX_XD_MOD_SEL 0x01 |
| 411 | #define RTSX_SD_MOD_SEL 0x02 |
| 412 | #define RTSX_MS_MOD_SEL 0x03 |
| 413 | #define RTSX_SPI_MOD_SEL 0x04 |
| 414 | |
| 415 | #define RTSX_CARD_GPIO_DIR 0xFD57 |
| 416 | #define RTSX_CARD_GPIO 0xFD58 |
| 417 | #define RTSX_CARD_GPIO_LED_OFF 0x01 |
| 418 | |
| 419 | /* ping-pong buffer 2 */ |
| 420 | #define RTSX_PPBUF_BASE2 0xFA00 |
| 421 | #define RTSX_PPBUF_SIZE 256 |
| 422 | |
| 423 | #define RTSX_SUPPORT_VOLTAGE (MMC_OCR_3_3V_3_4V \ |
| 424 | | MMC_OCR_3_2V_3_3V \ |
| 425 | | MMC_OCR_3_1V_3_2V \ |
| 426 | | MMC_OCR_3_0V_3_1V) |
| 427 | |
| 428 | #define RTSX_CFG_PCI 0x1C |
| 429 | #define RTSX_CFG_ASIC 0x10 |
| 430 | |
| 431 | #define RTSX_IRQEN0 0xFE20 |
| 432 | #define RTSX_LINK_DOWN_INT_EN 0x10 |
| 433 | #define RTSX_LINK_READY_INT_EN 0x20 |
| 434 | #define RTSX_SUSPEND_INT_EN 0x40 |
| 435 | #define RTSX_DMA_DONE_INT_EN 0x80 |
| 436 | #define RTSX_IRQSTAT0 0xFE21 |
| 437 | #define RTSX_LINK_DOWN_INT 0x10 |
| 438 | #define RTSX_LINK_READY_INT 0x20 |
| 439 | #define RTSX_SUSPEND_INT 0x40 |
| 440 | #define RTSX_DMA_DONE_INT 0x80 |
| 441 | |
| 442 | #define RTSX_DMATC0 0xFE28 |
| 443 | #define RTSX_DMATC1 0xFE29 |
| 444 | #define RTSX_DMATC2 0xFE2A |
| 445 | #define RTSX_DMATC3 0xFE2B |
| 446 | |
| 447 | #define RTSX_DMACTL 0xFE2C |
| 448 | #define RTSX_DMA_EN 0x01 |
| 449 | #define RTSX_DMA_DIR 0x02 |
| 450 | #define RTSX_DMA_DIR_TO_CARD 0x00 |
| 451 | #define RTSX_DMA_DIR_FROM_CARD 0x02 |
| 452 | #define RTSX_DMA_BUSY 0x04 |
| 453 | #define RTSX_DMA_RST 0x80 |
| 454 | #define RTSX_DMA_128 (0 << 4) |
| 455 | #define RTSX_DMA_256 (1 << 4) |
| 456 | #define RTSX_DMA_512 (2 << 4) |
| 457 | #define RTSX_DMA_1024 (3 << 4) |
| 458 | #define RTSX_DMA_PACK_SIZE_MASK 0x30 |
| 459 | |
| 460 | #define RTSX_RBCTL 0xFE34 |
| 461 | #define RTSX_RB_FLUSH 0x80 |
| 462 | |
| 463 | #define RTSX_CFGADDR0 0xFE35 |
| 464 | #define RTSX_CFGADDR1 0xFE36 |
| 465 | #define RTSX_CFGDATA0 0xFE37 |
| 466 | #define RTSX_CFGDATA1 0xFE38 |
| 467 | #define RTSX_CFGDATA2 0xFE39 |
| 468 | #define RTSX_CFGDATA3 0xFE3A |
| 469 | #define RTSX_CFGRWCTL 0xFE3B |
| 470 | #define RTSX_CFG_WRITE_DATA0 0x01 |
| 471 | #define RTSX_CFG_WRITE_DATA1 0x02 |
| 472 | #define RTSX_CFG_WRITE_DATA2 0x04 |
| 473 | #define RTSX_CFG_WRITE_DATA3 0x08 |
| 474 | #define RTSX_CFG_BUSY 0x80 |
| 475 | |
| 476 | #define RTSX_SDIOCFG_REG 0x724 |
| 477 | #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 |
| 478 | #define RTSX_SDIOCFG_HAVE_SDIO 0x04 |
| 479 | #define RTSX_SDIOCFG_SINGLE_LUN 0x08 |
| 480 | #define RTSX_SDIOCFG_SDIO_ONLY 0x80 |
| 481 | |
| 482 | #define RTSX_HOST_SLEEP_STATE 0xFE60 |
| 483 | #define RTSX_HOST_ENTER_S1 0x01 |
| 484 | #define RTSX_HOST_ENTER_S3 0x02 |
| 485 | |
| 486 | #define RTSX_SDIO_CFG 0xFE70 |
| 487 | #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 |
| 488 | |
| 489 | #define RTSX_NFTS_TX_CTRL 0xFE72 |
| 490 | #define RTSX_INT_READ_CLR 0x02 |
| 491 | |
| 492 | #define RTSX_PWR_GATE_CTRL 0xFE75 |
| 493 | #define RTSX_PWR_GATE_EN 0x01 |
| 494 | #define RTSX_LDO3318_ON 0x00 |
| 495 | #define RTSX_LDO3318_SUSPEND 0x04 |
| 496 | #define RTSX_LDO3318_OFF 0x06 |
| 497 | #define RTSX_LDO3318_VCC1 0x02 |
| 498 | #define RTSX_LDO3318_VCC2 0x04 |
| 499 | #define RTSX_PWD_SUSPEND_EN 0xFE76 |
| 500 | #define RTSX_LDO_PWR_SEL 0xFE78 |
| 501 | #define RTSX_LDO_PWR_SEL_3V3 0x01 |
| 502 | #define RTSX_LDO_PWR_SEL_DV33 0x03 |
| 503 | |
| 504 | #define RTSX_PHY_RWCTL 0xFE3C |
| 505 | #define RTSX_PHY_READ 0x00 |
| 506 | #define RTSX_PHY_WRITE 0x01 |
| 507 | #define RTSX_PHY_BUSY 0x80 |
| 508 | #define RTSX_PHY_DATA0 0xFE3D |
| 509 | #define RTSX_PHY_DATA1 0xFE3E |
| 510 | #define RTSX_PHY_ADDR 0xFE3F |
| 511 | |
| 512 | #define RTSX_PHY_VOLTAGE 0x08 |
| 513 | #define RTSX_PHY_VOLTAGE_MASK 0x3F |
| 514 | |
| 515 | #define RTSX_PETXCFG 0xFE49 |
| 516 | #define RTSX_PETXCFG_CLKREQ_PIN 0x08 |
| 517 | |
| 518 | #define RTSX_CARD_AUTO_BLINK 0xFD56 |
| 519 | #define RTSX_LED_BLINK_EN 0x08 |
| 520 | #define RTSX_LED_BLINK_SPEED 0x05 |
| 521 | |
| 522 | #define RTSX_SD30_CLK_DRIVE_SEL 0xFD5A |
| 523 | #define RTSX_SD30_CMD_DRIVE_SEL 0xFD5E |
| 524 | #define RTSX_SD30_DAT_DRIVE_SEL 0xFD5F |
| 525 | |
| 526 | #define RTSX_WAKE_SEL_CTL 0xFE54 |
| 527 | #define RTSX_PME_FORCE_CTL 0xFE56 |
| 528 | #define RTSX_FUNC_FORCE_CTL 0xFE59 |
| 529 | |
| 530 | #define RTSX_CHANGE_LINK_STATE 0xFE5B |
| 531 | #define RTSX_CD_RST_CORE_EN 0x01 |
| 532 | #define RTSX_FORCE_RST_CORE_EN 0x02 |
| 533 | #define RTSX_NON_STICKY_RST_N_DBG 0x08 |
| 534 | #define RTSX_MAC_PHY_RST_N_DBG 0x10 |
| 535 | |
| 536 | #define RTSX_PERST_GLITCH_WIDTH 0xFE5C |
| 537 | |
| 538 | #define RTSX_SD30_DRIVE_SEL 0xFE5E /* XXX 0xFD5E? */ |
| 539 | #define RTSX_SD30_DRIVE_SEL_3V3 0x01 |
| 540 | #define RTSX_SD30_DRIVE_SEL_1V8 0x03 |
| 541 | #define RTSX_SD30_DRIVE_SEL_MASK 0x07 |
| 542 | |
| 543 | #define RTSX_EFUSE_CONTENT 0xFE5F |
| 544 | |
| 545 | #define RTSX_DUMMY_REG 0xFE90 |
| 546 | |
| 547 | #define RTSX_SG_INT 0x04 |
| 548 | #define RTSX_SG_END 0x02 |
| 549 | #define RTSX_SG_VALID 0x01 |
| 550 | |
| 551 | #define RTSX_SG_NO_OP 0x00 |
| 552 | #define RTSX_SG_TRANS_DATA (0x02 << 4) |
| 553 | #define RTSX_SG_LINK_DESC (0x03 << 4) |
| 554 | |
| 555 | #define RTSX_IC_VERSION_A 0x00 |
| 556 | #define RTSX_IC_VERSION_B 0x01 |
| 557 | #define RTSX_IC_VERSION_C 0x02 |
| 558 | #define RTSX_IC_VERSION_D 0x03 |
| 559 | |
| 560 | #endif /* _RTSXREG_H_ */ |
| 561 | |