| 1 | /* $NetBSD: nouveau_engine_device_nv40.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2012 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nv40.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
| 29 | |
| 30 | #include <subdev/bios.h> |
| 31 | #include <subdev/bus.h> |
| 32 | #include <subdev/vm.h> |
| 33 | #include <subdev/gpio.h> |
| 34 | #include <subdev/i2c.h> |
| 35 | #include <subdev/clock.h> |
| 36 | #include <subdev/therm.h> |
| 37 | #include <subdev/devinit.h> |
| 38 | #include <subdev/mc.h> |
| 39 | #include <subdev/timer.h> |
| 40 | #include <subdev/fb.h> |
| 41 | #include <subdev/instmem.h> |
| 42 | #include <subdev/vm.h> |
| 43 | #include <subdev/volt.h> |
| 44 | |
| 45 | #include <engine/device.h> |
| 46 | #include <engine/dmaobj.h> |
| 47 | #include <engine/fifo.h> |
| 48 | #include <engine/software.h> |
| 49 | #include <engine/graph.h> |
| 50 | #include <engine/mpeg.h> |
| 51 | #include <engine/disp.h> |
| 52 | #include <engine/perfmon.h> |
| 53 | |
| 54 | int |
| 55 | nv40_identify(struct nouveau_device *device) |
| 56 | { |
| 57 | switch (device->chipset) { |
| 58 | case 0x40: |
| 59 | device->cname = "NV40" ; |
| 60 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 62 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 63 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 64 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 65 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 73 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 74 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 75 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 76 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 77 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 79 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 80 | break; |
| 81 | case 0x41: |
| 82 | device->cname = "NV41" ; |
| 83 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 84 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 85 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 86 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 87 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 88 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 89 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 90 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 96 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 97 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 98 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 99 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 100 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; |
| 101 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 102 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 103 | break; |
| 104 | case 0x42: |
| 105 | device->cname = "NV42" ; |
| 106 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 114 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 121 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 122 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 123 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; |
| 124 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 125 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 126 | break; |
| 127 | case 0x43: |
| 128 | device->cname = "NV43" ; |
| 129 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 130 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 140 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 141 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 142 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 143 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 144 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 145 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 146 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; |
| 147 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 148 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 149 | break; |
| 150 | case 0x45: |
| 151 | device->cname = "NV45" ; |
| 152 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 154 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 158 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 159 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 160 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 161 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 162 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 163 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 164 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 165 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 166 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 167 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 168 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 169 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 170 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 171 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 172 | break; |
| 173 | case 0x47: |
| 174 | device->cname = "G70" ; |
| 175 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 178 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 184 | device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; |
| 185 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 186 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 187 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 188 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 189 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 190 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 191 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 192 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 193 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 194 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 195 | break; |
| 196 | case 0x49: |
| 197 | device->cname = "G71" ; |
| 198 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 199 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 206 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 207 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 211 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 212 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 213 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 214 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 215 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 216 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 217 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 218 | break; |
| 219 | case 0x4b: |
| 220 | device->cname = "G73" ; |
| 221 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 222 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 223 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 224 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 225 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 226 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 227 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 229 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 230 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 231 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 232 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 233 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 234 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 235 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 236 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 237 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 238 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 239 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 240 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 241 | break; |
| 242 | case 0x44: |
| 243 | device->cname = "NV44" ; |
| 244 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 245 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 246 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 247 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 248 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 249 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 250 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 251 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 252 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 253 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 254 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 255 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 256 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 257 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 258 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 259 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 260 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 261 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 262 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 263 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 264 | break; |
| 265 | case 0x46: |
| 266 | device->cname = "G72" ; |
| 267 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 269 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 270 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 271 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 272 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 273 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 274 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 275 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 276 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 277 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 278 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 279 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 280 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 281 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 282 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 283 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 284 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 285 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 286 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 287 | break; |
| 288 | case 0x4a: |
| 289 | device->cname = "NV44A" ; |
| 290 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 291 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 298 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 299 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 300 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 301 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 302 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 303 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 304 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 305 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 306 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 307 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 308 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 309 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 310 | break; |
| 311 | case 0x4c: |
| 312 | device->cname = "C61" ; |
| 313 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 314 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 315 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 316 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 317 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 318 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 321 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 322 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 323 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 324 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 326 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 327 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 328 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 329 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 330 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 331 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 332 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 333 | break; |
| 334 | case 0x4e: |
| 335 | device->cname = "C51" ; |
| 336 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 337 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 338 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass; |
| 339 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 340 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 341 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 342 | device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; |
| 343 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 344 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 345 | device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; |
| 346 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 347 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 348 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 349 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 350 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 351 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 352 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 353 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 354 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 355 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 356 | break; |
| 357 | case 0x63: |
| 358 | device->cname = "C73" ; |
| 359 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 360 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 361 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 362 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 363 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 364 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 365 | device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; |
| 366 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 367 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 368 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 369 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 370 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 371 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 372 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 373 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 374 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 375 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 376 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 377 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 378 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 379 | break; |
| 380 | case 0x67: |
| 381 | device->cname = "C67" ; |
| 382 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 383 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 384 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 385 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 386 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 387 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 388 | device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; |
| 389 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 390 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 391 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 392 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 393 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 394 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 395 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 396 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 397 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 398 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 399 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 400 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 401 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 402 | break; |
| 403 | case 0x68: |
| 404 | device->cname = "C68" ; |
| 405 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 406 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 407 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 413 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 414 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 415 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 416 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 417 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 418 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 419 | device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; |
| 420 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
| 421 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; |
| 422 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; |
| 423 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
| 424 | device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; |
| 425 | break; |
| 426 | default: |
| 427 | nv_fatal(device, "unknown Curie chipset\n" ); |
| 428 | return -EINVAL; |
| 429 | } |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |