| 1 | /* $NetBSD: if_wpireg.h,v 1.13 2014/07/02 00:15:41 jakllsch Exp $ */ |
| 2 | /* $OpenBSD: if_wpireg.h,v 1.19 2007/09/10 20:53:22 damien Exp $ */ |
| 3 | |
| 4 | /*- |
| 5 | * Copyright (c) 2006, 2007 |
| 6 | * Damien Bergamini <damien.bergamini@free.fr> |
| 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | */ |
| 20 | |
| 21 | #define WPI_TX_RING_COUNT 256 |
| 22 | #define WPI_CMD_RING_COUNT 256 |
| 23 | #define WPI_RX_RING_COUNT 64 |
| 24 | |
| 25 | #define WPI_BUF_ALIGN 4096 |
| 26 | |
| 27 | /* |
| 28 | * Rings must be aligned on a 16K boundary. |
| 29 | * I had a hard time figuring this out. |
| 30 | */ |
| 31 | #define WPI_RING_DMA_ALIGN 0x4000 |
| 32 | |
| 33 | /* maximum scatter/gather */ |
| 34 | #define WPI_MAX_SCATTER 4 |
| 35 | |
| 36 | /* maximum Rx buffer size (larger than MCLBYTES) */ |
| 37 | #define WPI_RBUF_SIZE (3 * 1024) /* XXX 3000 but must be aligned! */ |
| 38 | |
| 39 | /* |
| 40 | * Control and status registers. |
| 41 | */ |
| 42 | #define WPI_HWCONFIG 0x000 |
| 43 | #define WPI_INTR 0x008 |
| 44 | #define WPI_MASK 0x00c |
| 45 | #define WPI_INTR_STATUS 0x010 |
| 46 | #define WPI_GPIO_STATUS 0x018 |
| 47 | #define WPI_RESET 0x020 |
| 48 | #define WPI_GPIO_CTL 0x024 |
| 49 | #define WPI_EEPROM_CTL 0x02c |
| 50 | #define WPI_EEPROM_STATUS 0x030 |
| 51 | #define WPI_UCODE_CLR 0x05c |
| 52 | #define WPI_TEMPERATURE 0x060 |
| 53 | #define WPI_CHICKEN 0x100 |
| 54 | #define WPI_PLL_CTL 0x20c |
| 55 | #define WPI_WRITE_MEM_ADDR 0x444 |
| 56 | #define WPI_READ_MEM_ADDR 0x448 |
| 57 | #define WPI_WRITE_MEM_DATA 0x44c |
| 58 | #define WPI_READ_MEM_DATA 0x450 |
| 59 | #define WPI_TX_WIDX 0x460 |
| 60 | #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) |
| 61 | #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) |
| 62 | #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) |
| 63 | #define WPI_RX_CONFIG 0xc00 |
| 64 | #define WPI_RX_BASE 0xc04 |
| 65 | #define WPI_RX_WIDX 0xc20 |
| 66 | #define WPI_RX_RIDX_PTR 0xc24 |
| 67 | #define WPI_RX_CTL 0xcc0 |
| 68 | #define WPI_RX_STATUS 0xcc4 |
| 69 | #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) |
| 70 | #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) |
| 71 | #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) |
| 72 | #define WPI_TX_BASE_PTR 0xe80 |
| 73 | #define WPI_MSG_CONFIG 0xe88 |
| 74 | #define WPI_TX_STATUS 0xe90 |
| 75 | |
| 76 | |
| 77 | /* |
| 78 | * NIC internal memory offsets. |
| 79 | */ |
| 80 | #define WPI_MEM_MODE 0x2e00 |
| 81 | #define WPI_MEM_RA 0x2e04 |
| 82 | #define WPI_MEM_TXCFG 0x2e10 |
| 83 | #define WPI_MEM_MAGIC4 0x2e14 |
| 84 | #define WPI_MEM_MAGIC5 0x2e20 |
| 85 | #define WPI_MEM_BYPASS1 0x2e2c |
| 86 | #define WPI_MEM_BYPASS2 0x2e30 |
| 87 | #define WPI_MEM_CLOCK1 0x3004 |
| 88 | #define WPI_MEM_CLOCK2 0x3008 |
| 89 | #define WPI_MEM_POWER 0x300c |
| 90 | #define WPI_MEM_PCIDEV 0x3010 |
| 91 | #define WPI_MEM_RFKILL 0x3014 |
| 92 | #define WPI_MEM_UCODE_CTL 0x3400 |
| 93 | #define WPI_MEM_UCODE_SRC 0x3404 |
| 94 | #define WPI_MEM_UCODE_DST 0x3408 |
| 95 | #define WPI_MEM_UCODE_SIZE 0x340c |
| 96 | #define WPI_MEM_UCODE_BASE 0x3800 |
| 97 | |
| 98 | #define WPI_MEM_TEXT_BASE 0x3490 |
| 99 | #define WPI_MEM_TEXT_SIZE 0x3494 |
| 100 | #define WPI_MEM_DATA_BASE 0x3498 |
| 101 | #define WPI_MEM_DATA_SIZE 0x349c |
| 102 | |
| 103 | |
| 104 | /* possible flags for register WPI_HWCONFIG */ |
| 105 | #define WPI_HW_ALM_MB (1 << 8) |
| 106 | #define WPI_HW_ALM_MM (1 << 9) |
| 107 | #define WPI_HW_SKU_MRC (1 << 10) |
| 108 | #define WPI_HW_REV_D (1 << 11) |
| 109 | #define WPI_HW_TYPE_B (1 << 12) |
| 110 | |
| 111 | /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ |
| 112 | #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) |
| 113 | |
| 114 | /* possible values for WPI_MEM_UCODE_DST */ |
| 115 | #define WPI_FW_TEXT 0x00000000 |
| 116 | |
| 117 | /* possible flags for WPI_GPIO_STATUS */ |
| 118 | #define WPI_POWERED (1 << 9) |
| 119 | |
| 120 | /* possible flags for register WPI_RESET */ |
| 121 | #define WPI_NEVO_RESET (1 << 0) |
| 122 | #define WPI_SW_RESET (1 << 7) |
| 123 | #define WPI_MASTER_DISABLED (1 << 8) |
| 124 | #define WPI_STOP_MASTER (1 << 9) |
| 125 | |
| 126 | /* possible flags for register WPI_GPIO_CTL */ |
| 127 | #define WPI_GPIO_CLOCK (1 << 0) |
| 128 | #define WPI_GPIO_INIT (1 << 2) |
| 129 | #define WPI_GPIO_MAC (1 << 3) |
| 130 | #define WPI_GPIO_SLEEP (1 << 4) |
| 131 | #define WPI_GPIO_PWR_STATUS 0x07000000 |
| 132 | #define WPI_GPIO_PWR_SLEEP (4 << 24) |
| 133 | |
| 134 | /* possible flags for register WPI_CHICKEN */ |
| 135 | #define WPI_CHICKEN_RXNOLOS (1 << 23) |
| 136 | |
| 137 | /* possible flags for register WPI_PLL_CTL */ |
| 138 | #define WPI_PLL_INIT (1 << 24) |
| 139 | |
| 140 | /* possible flags for register WPI_UCODE_CLR */ |
| 141 | #define WPI_RADIO_OFF (1 << 1) |
| 142 | #define WPI_DISABLE_CMD (1 << 2) |
| 143 | |
| 144 | /* possible flags for WPI_RX_STATUS */ |
| 145 | #define WPI_RX_IDLE (1 << 24) |
| 146 | |
| 147 | /* possible flags for register WPI_UC_CTL */ |
| 148 | #define WPI_UC_ENABLE (1 << 30) |
| 149 | #define WPI_UC_RUN (1 << 31) |
| 150 | |
| 151 | /* possible flags for register WPI_INTR_CSR */ |
| 152 | #define WPI_ALIVE_INTR (1 << 0) |
| 153 | #define WPI_WAKEUP_INTR (1 << 1) |
| 154 | #define WPI_SW_ERROR (1 << 25) |
| 155 | #define WPI_TX_INTR (1 << 27) |
| 156 | #define WPI_HW_ERROR (1 << 29) |
| 157 | #define WPI_RX_INTR (1 << 31) |
| 158 | |
| 159 | #define WPI_INTR_MASK \ |
| 160 | (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ |
| 161 | WPI_ALIVE_INTR | WPI_WAKEUP_INTR) |
| 162 | |
| 163 | /* possible flags for register WPI_TX_STATUS */ |
| 164 | #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) |
| 165 | |
| 166 | /* possible flags for register WPI_EEPROM_CTL */ |
| 167 | #define WPI_EEPROM_READY (1 << 0) |
| 168 | |
| 169 | /* possible flags for register WPI_EEPROM_STATUS */ |
| 170 | #define WPI_EEPROM_VERSION 0x00000007 |
| 171 | #define WPI_EEPROM_LOCKED 0x00000180 |
| 172 | |
| 173 | |
| 174 | struct wpi_shared { |
| 175 | uint32_t txbase[8]; |
| 176 | uint32_t next; |
| 177 | uint32_t reserved[2]; |
| 178 | } __packed; |
| 179 | |
| 180 | #define WPI_MAX_SEG_LEN 65520 |
| 181 | struct wpi_tx_desc { |
| 182 | uint32_t flags; |
| 183 | #define WPI_PAD32(x) ((((x) + 3) & ~3) - (x)) |
| 184 | |
| 185 | struct { |
| 186 | uint32_t addr; |
| 187 | uint32_t len; |
| 188 | } __packed segs[WPI_MAX_SCATTER]; |
| 189 | uint8_t reserved[28]; |
| 190 | } __packed; |
| 191 | |
| 192 | struct wpi_tx_stat { |
| 193 | uint8_t nrts; |
| 194 | uint8_t ntries; |
| 195 | uint8_t nkill; |
| 196 | uint8_t rate; |
| 197 | uint32_t duration; |
| 198 | uint32_t status; |
| 199 | } __packed; |
| 200 | |
| 201 | struct wpi_rx_desc { |
| 202 | uint32_t len; |
| 203 | uint8_t type; |
| 204 | #define WPI_UC_READY 1 |
| 205 | #define WPI_ADD_NODE_DONE 24 |
| 206 | #define WPI_RX_DONE 27 |
| 207 | #define WPI_TX_DONE 28 |
| 208 | #define WPI_START_SCAN 130 |
| 209 | #define WPI_STOP_SCAN 132 |
| 210 | #define WPI_STATE_CHANGED 161 |
| 211 | |
| 212 | uint8_t flags; |
| 213 | uint8_t idx; |
| 214 | uint8_t qid; |
| 215 | } __packed; |
| 216 | |
| 217 | struct wpi_rx_stat { |
| 218 | uint8_t len; |
| 219 | #define WPI_STAT_MAXLEN 20 |
| 220 | |
| 221 | uint8_t id; |
| 222 | uint8_t ; /* received signal strength */ |
| 223 | #define 95 |
| 224 | |
| 225 | uint8_t agc; /* access gain control */ |
| 226 | uint16_t signal; |
| 227 | uint16_t noise; |
| 228 | } __packed; |
| 229 | |
| 230 | struct wpi_rx_head { |
| 231 | uint16_t chan; |
| 232 | uint16_t flags; |
| 233 | uint8_t reserved; |
| 234 | uint8_t rate; |
| 235 | uint16_t len; |
| 236 | } __packed; |
| 237 | |
| 238 | struct wpi_rx_tail { |
| 239 | uint32_t flags; |
| 240 | #define WPI_RX_NO_CRC_ERR (1 << 0) |
| 241 | #define WPI_RX_NO_OVFL_ERR (1 << 1) |
| 242 | /* shortcut for the above */ |
| 243 | #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) |
| 244 | |
| 245 | uint64_t tstamp; |
| 246 | uint32_t tbeacon; |
| 247 | } __packed; |
| 248 | |
| 249 | struct wpi_tx_cmd { |
| 250 | uint8_t code; |
| 251 | #define WPI_CMD_CONFIGURE 16 |
| 252 | #define WPI_CMD_ASSOCIATE 17 |
| 253 | #define WPI_CMD_SET_WME 19 |
| 254 | #define WPI_CMD_TSF 20 |
| 255 | #define WPI_CMD_ADD_NODE 24 |
| 256 | #define WPI_CMD_TX_DATA 28 |
| 257 | #define WPI_CMD_MRR_SETUP 71 |
| 258 | #define WPI_CMD_SET_LED 72 |
| 259 | #define WPI_CMD_SET_POWER_MODE 119 |
| 260 | #define WPI_CMD_SCAN 128 |
| 261 | #define WPI_CMD_SET_BEACON 145 |
| 262 | #define WPI_CMD_TXPOWER 151 |
| 263 | #define WPI_CMD_BLUETOOTH 155 |
| 264 | |
| 265 | uint8_t flags; |
| 266 | uint8_t idx; |
| 267 | uint8_t qid; |
| 268 | uint8_t data[124]; |
| 269 | } __packed; |
| 270 | |
| 271 | /* structure for WPI_CMD_CONFIGURE */ |
| 272 | struct wpi_config { |
| 273 | uint8_t myaddr[IEEE80211_ADDR_LEN]; |
| 274 | uint16_t reserved1; |
| 275 | uint8_t bssid[IEEE80211_ADDR_LEN]; |
| 276 | uint16_t reserved2; |
| 277 | uint32_t reserved3[2]; |
| 278 | uint8_t mode; |
| 279 | #define WPI_MODE_HOSTAP 1 |
| 280 | #define WPI_MODE_STA 3 |
| 281 | #define WPI_MODE_IBSS 4 |
| 282 | #define WPI_MODE_MONITOR 6 |
| 283 | |
| 284 | uint8_t reserved4[3]; |
| 285 | uint8_t ofdm_mask; |
| 286 | uint8_t cck_mask; |
| 287 | uint16_t associd; |
| 288 | uint32_t flags; |
| 289 | #define WPI_CONFIG_24GHZ (1 << 0) |
| 290 | #define WPI_CONFIG_CCK (1 << 1) |
| 291 | #define WPI_CONFIG_AUTO (1 << 2) |
| 292 | #define WPI_CONFIG_SHSLOT (1 << 4) |
| 293 | #define WPI_CONFIG_SHPREAMBLE (1 << 5) |
| 294 | #define WPI_CONFIG_NODIVERSITY (1 << 7) |
| 295 | #define WPI_CONFIG_ANTENNA_A (1 << 8) |
| 296 | #define WPI_CONFIG_ANTENNA_B (1 << 9) |
| 297 | #define WPI_CONFIG_TSF (1 << 15) |
| 298 | |
| 299 | uint32_t filter; |
| 300 | #define WPI_FILTER_PROMISC (1 << 0) |
| 301 | #define WPI_FILTER_CTL (1 << 1) |
| 302 | #define WPI_FILTER_MULTICAST (1 << 2) |
| 303 | #define WPI_FILTER_NODECRYPT (1 << 3) |
| 304 | #define WPI_FILTER_BSS (1 << 5) |
| 305 | #define WPI_FILTER_BEACON (1 << 6) |
| 306 | |
| 307 | uint8_t chan; |
| 308 | uint8_t reserved6[3]; |
| 309 | } __packed; |
| 310 | |
| 311 | /* structure for command WPI_CMD_ASSOCIATE */ |
| 312 | struct wpi_assoc { |
| 313 | uint32_t flags; |
| 314 | uint32_t filter; |
| 315 | uint8_t ofdm_mask; |
| 316 | uint8_t cck_mask; |
| 317 | uint16_t reserved; |
| 318 | } __packed; |
| 319 | |
| 320 | /* structure for command WPI_CMD_SET_WME */ |
| 321 | struct wpi_wme_setup { |
| 322 | uint32_t flags; |
| 323 | struct { |
| 324 | uint16_t cwmin; |
| 325 | uint16_t cwmax; |
| 326 | uint8_t aifsn; |
| 327 | uint8_t reserved; |
| 328 | uint16_t txop; |
| 329 | } __packed ac[WME_NUM_AC]; |
| 330 | } __packed; |
| 331 | |
| 332 | /* structure for command WPI_CMD_TSF */ |
| 333 | struct wpi_cmd_tsf { |
| 334 | uint64_t tstamp; |
| 335 | uint16_t bintval; |
| 336 | uint16_t atim; |
| 337 | uint32_t binitval; |
| 338 | uint16_t lintval; |
| 339 | uint16_t reserved; |
| 340 | } __packed; |
| 341 | |
| 342 | /* structure for WPI_CMD_ADD_NODE */ |
| 343 | struct wpi_node_info { |
| 344 | uint8_t control; |
| 345 | #define WPI_NODE_UPDATE (1 << 0) |
| 346 | |
| 347 | uint8_t reserved1[3]; |
| 348 | uint8_t bssid[IEEE80211_ADDR_LEN]; |
| 349 | uint16_t reserved2; |
| 350 | uint8_t id; |
| 351 | #define WPI_ID_BSS 0 |
| 352 | #define WPI_ID_BROADCAST 24 |
| 353 | |
| 354 | uint8_t flags; |
| 355 | #define WPI_FLAG_SET_KEY (1 << 0) |
| 356 | |
| 357 | uint16_t reserved3; |
| 358 | uint16_t security; |
| 359 | uint8_t tkip; |
| 360 | uint8_t reserved4; |
| 361 | uint16_t ttak[5]; |
| 362 | uint16_t reserved5; |
| 363 | uint8_t key[IEEE80211_KEYBUF_SIZE]; |
| 364 | uint32_t action; |
| 365 | #define WPI_ACTION_SET_RATE (1 << 2) |
| 366 | |
| 367 | uint32_t mask; |
| 368 | uint16_t tid; |
| 369 | uint8_t rate; |
| 370 | uint8_t antenna; |
| 371 | #define WPI_ANTENNA_A (1 << 6) |
| 372 | #define WPI_ANTENNA_B (1 << 7) |
| 373 | #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) |
| 374 | |
| 375 | uint8_t add_imm; |
| 376 | uint8_t del_imm; |
| 377 | uint16_t add_imm_start; |
| 378 | } __packed; |
| 379 | |
| 380 | /* structure for command WPI_CMD_TX_DATA */ |
| 381 | struct wpi_cmd_data { |
| 382 | uint16_t len; |
| 383 | uint16_t lnext; |
| 384 | uint32_t flags; |
| 385 | #define WPI_TX_NEED_RTS (1 << 1) |
| 386 | #define WPI_TX_NEED_CTS (1 << 2) |
| 387 | #define WPI_TX_NEED_ACK (1 << 3) |
| 388 | #define WPI_TX_FULL_TXOP (1 << 7) |
| 389 | #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ |
| 390 | #define WPI_TX_AUTO_SEQ (1 << 13) |
| 391 | #define WPI_TX_INSERT_TSTAMP (1 << 16) |
| 392 | |
| 393 | uint8_t rate; |
| 394 | uint8_t id; |
| 395 | uint8_t tid; |
| 396 | uint8_t security; |
| 397 | #define WPI_CIPHER_WEP40 1 |
| 398 | #define WPI_CIPHER_CCMP 2 |
| 399 | #define WPI_CIPHER_TKIP 3 |
| 400 | #define WPI_CIPHER_WEP104 9 |
| 401 | |
| 402 | uint8_t key[IEEE80211_KEYBUF_SIZE]; |
| 403 | uint8_t tkip[IEEE80211_WEP_MICLEN]; |
| 404 | uint32_t fnext; |
| 405 | uint32_t lifetime; |
| 406 | #define WPI_LIFETIME_INFINITE 0xffffffff |
| 407 | |
| 408 | uint8_t ofdm_mask; |
| 409 | uint8_t cck_mask; |
| 410 | uint8_t rts_ntries; |
| 411 | uint8_t data_ntries; |
| 412 | uint16_t timeout; |
| 413 | uint16_t txop; |
| 414 | } __packed; |
| 415 | |
| 416 | /* structure for command WPI_CMD_SET_BEACON */ |
| 417 | struct wpi_cmd_beacon { |
| 418 | uint16_t len; |
| 419 | uint16_t reserved1; |
| 420 | uint32_t flags; /* same as wpi_cmd_data */ |
| 421 | uint8_t rate; |
| 422 | uint8_t id; |
| 423 | uint8_t reserved2[30]; |
| 424 | uint32_t lifetime; |
| 425 | uint8_t ofdm_mask; |
| 426 | uint8_t cck_mask; |
| 427 | uint16_t reserved3[3]; |
| 428 | uint16_t tim; |
| 429 | uint8_t timsz; |
| 430 | uint8_t reserved4; |
| 431 | struct ieee80211_frame wh; |
| 432 | } __packed; |
| 433 | |
| 434 | /* structure for WPI_CMD_MRR_SETUP */ |
| 435 | struct wpi_mrr_setup { |
| 436 | uint32_t which; |
| 437 | #define WPI_MRR_CTL 0 |
| 438 | #define WPI_MRR_DATA 1 |
| 439 | |
| 440 | struct { |
| 441 | uint8_t plcp; |
| 442 | uint8_t flags; |
| 443 | uint8_t ntries; |
| 444 | uint8_t next; |
| 445 | #define WPI_OFDM6 0 |
| 446 | #define WPI_OFDM54 7 |
| 447 | #define WPI_CCK1 8 |
| 448 | #define WPI_CCK2 9 |
| 449 | #define WPI_CCK11 11 |
| 450 | |
| 451 | } __packed rates[WPI_CCK11 + 1]; |
| 452 | } __packed; |
| 453 | |
| 454 | /* structure for WPI_CMD_SET_LED */ |
| 455 | struct wpi_cmd_led { |
| 456 | uint32_t unit; /* multiplier (in usecs) */ |
| 457 | uint8_t which; |
| 458 | #define WPI_LED_ACTIVITY 1 |
| 459 | #define WPI_LED_LINK 2 |
| 460 | |
| 461 | uint8_t off; |
| 462 | uint8_t on; |
| 463 | uint8_t reserved; |
| 464 | } __packed; |
| 465 | |
| 466 | /* structure for WPI_CMD_SET_POWER_MODE */ |
| 467 | struct wpi_power { |
| 468 | uint32_t flags; |
| 469 | #define WPI_POWER_CAM 0 /* constantly awake mode */ |
| 470 | |
| 471 | uint32_t rx_timeout; |
| 472 | uint32_t tx_timeout; |
| 473 | uint32_t sleep[5]; |
| 474 | } __packed; |
| 475 | |
| 476 | /* structures for command WPI_CMD_SCAN */ |
| 477 | struct wpi_scan_essid { |
| 478 | uint8_t id; |
| 479 | uint8_t len; |
| 480 | uint8_t data[IEEE80211_NWID_LEN]; |
| 481 | } __packed; |
| 482 | |
| 483 | struct wpi_scan_hdr { |
| 484 | uint16_t len; |
| 485 | uint8_t reserved1; |
| 486 | uint8_t nchan; |
| 487 | uint16_t quiet; |
| 488 | uint16_t plcp_threshold; |
| 489 | uint16_t crc_threshold; |
| 490 | uint16_t reserved2; |
| 491 | uint32_t max_svc; /* background scans */ |
| 492 | uint32_t pause_svc; /* background scans */ |
| 493 | uint32_t flags; |
| 494 | uint32_t filter; |
| 495 | |
| 496 | /* followed by a struct wpi_cmd_data */ |
| 497 | struct wpi_cmd_data cmd; |
| 498 | |
| 499 | /* followed by an array of 4x struct wpi_scan_essid */ |
| 500 | struct wpi_scan_essid essid[4]; |
| 501 | |
| 502 | /* followed by probe request body */ |
| 503 | /* followed by nchan x wpi_scan_chan */ |
| 504 | } __packed; |
| 505 | |
| 506 | struct wpi_scan_chan { |
| 507 | uint8_t flags; |
| 508 | #define WPI_CHAN_ACTIVE (1 << 0) |
| 509 | #define WPI_CHAN_DIRECT (1 << 1) |
| 510 | |
| 511 | uint8_t chan; |
| 512 | uint8_t rf_gain; |
| 513 | uint8_t dsp_gain; |
| 514 | uint16_t active; /* msecs */ |
| 515 | uint16_t passive; /* msecs */ |
| 516 | } __packed; |
| 517 | |
| 518 | /* structure for WPI_CMD_TXPOWER */ |
| 519 | struct wpi_cmd_txpower { |
| 520 | uint8_t band; |
| 521 | #define WPI_BAND_5GHZ 0 |
| 522 | #define WPI_BAND_2GHZ 1 |
| 523 | |
| 524 | uint8_t reserved; |
| 525 | uint16_t chan; |
| 526 | struct { |
| 527 | uint8_t plcp; |
| 528 | uint8_t rf_gain; |
| 529 | uint8_t dsp_gain; |
| 530 | uint8_t reserved; |
| 531 | } __packed rates[WPI_CCK11 + 1]; |
| 532 | } __packed; |
| 533 | |
| 534 | /* structure for WPI_CMD_BLUETOOTH */ |
| 535 | struct wpi_bluetooth { |
| 536 | uint8_t flags; |
| 537 | uint8_t lead; |
| 538 | uint8_t kill; |
| 539 | uint8_t reserved; |
| 540 | uint32_t ack; |
| 541 | uint32_t cts; |
| 542 | } __packed; |
| 543 | |
| 544 | |
| 545 | /* structure for WPI_UC_READY notification */ |
| 546 | struct wpi_ucode_info { |
| 547 | uint32_t version; |
| 548 | uint8_t revision[8]; |
| 549 | uint8_t type; |
| 550 | uint8_t subtype; |
| 551 | uint16_t reserved; |
| 552 | uint32_t logptr; |
| 553 | uint32_t errorptr; |
| 554 | uint32_t timestamp; |
| 555 | uint32_t valid; |
| 556 | } __packed; |
| 557 | |
| 558 | /* structure for WPI_START_SCAN notification */ |
| 559 | struct wpi_start_scan { |
| 560 | uint64_t tstamp; |
| 561 | uint32_t tbeacon; |
| 562 | uint8_t chan; |
| 563 | uint8_t band; |
| 564 | uint16_t reserved; |
| 565 | uint32_t status; |
| 566 | } __packed; |
| 567 | |
| 568 | /* structure for WPI_STOP_SCAN notification */ |
| 569 | struct wpi_stop_scan { |
| 570 | uint8_t nchan; |
| 571 | uint8_t status; |
| 572 | uint8_t reserved; |
| 573 | uint8_t chan; |
| 574 | uint64_t tsf; |
| 575 | } __packed; |
| 576 | |
| 577 | |
| 578 | /* firmware image header */ |
| 579 | struct wpi_firmware_hdr { |
| 580 | uint32_t version; |
| 581 | uint32_t main_textsz; |
| 582 | uint32_t main_datasz; |
| 583 | uint32_t init_textsz; |
| 584 | uint32_t init_datasz; |
| 585 | uint32_t boot_textsz; |
| 586 | } __packed; |
| 587 | |
| 588 | #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024) |
| 589 | #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024) |
| 590 | #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024) |
| 591 | #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024) |
| 592 | #define WPI_FW_BOOT_TEXT_MAXSZ 1024 |
| 593 | |
| 594 | #define WPI_FW_UPDATED (1 << 31) |
| 595 | |
| 596 | /* |
| 597 | * Offsets into EEPROM. |
| 598 | */ |
| 599 | #define WPI_EEPROM_MAC 0x015 |
| 600 | #define WPI_EEPROM_REVISION 0x035 |
| 601 | #define WPI_EEPROM_CAPABILITIES 0x045 |
| 602 | #define WPI_EEPROM_TYPE 0x04a |
| 603 | #define WPI_EEPROM_DOMAIN 0x060 |
| 604 | #define WPI_EEPROM_BAND1 0x063 |
| 605 | #define WPI_EEPROM_BAND2 0x072 |
| 606 | #define WPI_EEPROM_BAND3 0x080 |
| 607 | #define WPI_EEPROM_BAND4 0x08d |
| 608 | #define WPI_EEPROM_BAND5 0x099 |
| 609 | #define WPI_EEPROM_POWER_GRP 0x100 |
| 610 | |
| 611 | struct wpi_eeprom_chan { |
| 612 | uint8_t flags; |
| 613 | #define WPI_EEPROM_CHAN_VALID (1 << 0) |
| 614 | #define WPI_EEPROM_CHAN_IBSS (1 << 1) |
| 615 | #define WPI_EEPROM_CHAN_ACTIVE (1 << 3) |
| 616 | #define WPI_EEPROM_CHAN_RADAR (1 << 4) |
| 617 | |
| 618 | int8_t maxpwr; |
| 619 | } __packed; |
| 620 | |
| 621 | struct wpi_eeprom_sample { |
| 622 | uint8_t index; |
| 623 | int8_t power; |
| 624 | uint16_t volt; |
| 625 | } __packed; |
| 626 | |
| 627 | #define WPI_POWER_GROUPS_COUNT 5 |
| 628 | struct wpi_eeprom_group { |
| 629 | struct wpi_eeprom_sample samples[5]; |
| 630 | int32_t coef[5]; |
| 631 | int32_t corr[5]; |
| 632 | int8_t maxpwr; |
| 633 | uint8_t chan; |
| 634 | int16_t temp; |
| 635 | } __packed; |
| 636 | |
| 637 | #define WPI_CHAN_BANDS_COUNT 5 |
| 638 | #define WPI_MAX_CHAN_PER_BAND 14 |
| 639 | static const struct wpi_chan_band { |
| 640 | uint32_t addr; /* offset in EEPROM */ |
| 641 | uint8_t nchan; |
| 642 | uint8_t chan[WPI_MAX_CHAN_PER_BAND]; |
| 643 | } wpi_bands[5] = { |
| 644 | { WPI_EEPROM_BAND1, 14, |
| 645 | { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, |
| 646 | { WPI_EEPROM_BAND2, 13, |
| 647 | { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, |
| 648 | { WPI_EEPROM_BAND3, 12, |
| 649 | { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, |
| 650 | { WPI_EEPROM_BAND4, 11, |
| 651 | { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, |
| 652 | { WPI_EEPROM_BAND5, 6, |
| 653 | { 145, 149, 153, 157, 161, 165 } } |
| 654 | }; |
| 655 | |
| 656 | /* convert rate index (device view) into rate in 500Kbps unit */ |
| 657 | static const uint8_t wpi_ridx_to_rate[] = { |
| 658 | 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */ |
| 659 | 2, 4, 11, 22 /* CCK */ |
| 660 | }; |
| 661 | |
| 662 | /* convert rate index (device view) into PLCP code */ |
| 663 | static const uint8_t wpi_ridx_to_plcp[] = { |
| 664 | 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, /* OFDM R1-R4 */ |
| 665 | 10, 20, 55, 110 /* CCK */ |
| 666 | }; |
| 667 | |
| 668 | #define WPI_MAX_PWR_INDEX 77 |
| 669 | /* |
| 670 | * RF Tx gain values from highest to lowest power (values obtained from |
| 671 | * the reference driver.) |
| 672 | */ |
| 673 | static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { |
| 674 | 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, |
| 675 | 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, |
| 676 | 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, |
| 677 | 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, |
| 678 | 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, |
| 679 | 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, |
| 680 | 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, |
| 681 | 0x03 |
| 682 | }; |
| 683 | |
| 684 | static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { |
| 685 | 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, |
| 686 | 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, |
| 687 | 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, |
| 688 | 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, |
| 689 | 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, |
| 690 | 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, |
| 691 | 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, |
| 692 | 0x03 |
| 693 | }; |
| 694 | |
| 695 | /* |
| 696 | * DSP pre-DAC gain values from highest to lowest power (values obtained |
| 697 | * from the reference driver.) |
| 698 | */ |
| 699 | static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { |
| 700 | 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, |
| 701 | 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, |
| 702 | 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, |
| 703 | 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, |
| 704 | 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, |
| 705 | 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, |
| 706 | 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, |
| 707 | 0x5f |
| 708 | }; |
| 709 | |
| 710 | static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { |
| 711 | 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, |
| 712 | 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, |
| 713 | 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, |
| 714 | 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, |
| 715 | 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, |
| 716 | 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, |
| 717 | 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, |
| 718 | 0x78 |
| 719 | }; |
| 720 | |
| 721 | #define WPI_READ(sc, reg) \ |
| 722 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
| 723 | |
| 724 | #define WPI_WRITE(sc, reg, val) \ |
| 725 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
| 726 | |
| 727 | #define WPI_WRITE_REGION_4(sc, offset, datap, count) \ |
| 728 | bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ |
| 729 | (datap), (count)) |
| 730 | |