| 1 | /* $NetBSD: if_ath_cardbus.c,v 1.45 2011/10/07 20:47:42 dyoung Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 2003 |
| 4 | * Ichiro FUKUHARA <ichiro@ichiro.org>. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR |
| 17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 18 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 19 | * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR |
| 20 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | /* |
| 29 | * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus. |
| 30 | */ |
| 31 | |
| 32 | #include <sys/cdefs.h> |
| 33 | __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.45 2011/10/07 20:47:42 dyoung Exp $" ); |
| 34 | |
| 35 | #include "opt_inet.h" |
| 36 | |
| 37 | #include <sys/param.h> |
| 38 | #include <sys/systm.h> |
| 39 | #include <sys/mbuf.h> |
| 40 | #include <sys/malloc.h> |
| 41 | #include <sys/kernel.h> |
| 42 | #include <sys/socket.h> |
| 43 | #include <sys/ioctl.h> |
| 44 | #include <sys/errno.h> |
| 45 | #include <sys/device.h> |
| 46 | |
| 47 | #include <machine/endian.h> |
| 48 | |
| 49 | #include <net/if.h> |
| 50 | #include <net/if_dl.h> |
| 51 | #include <net/if_media.h> |
| 52 | #include <net/if_ether.h> |
| 53 | |
| 54 | #include <net80211/ieee80211_netbsd.h> |
| 55 | #include <net80211/ieee80211_var.h> |
| 56 | |
| 57 | #ifdef INET |
| 58 | #include <netinet/in.h> |
| 59 | #include <netinet/if_inarp.h> |
| 60 | #endif |
| 61 | |
| 62 | |
| 63 | #include <sys/bus.h> |
| 64 | #include <sys/intr.h> |
| 65 | |
| 66 | #include <dev/mii/miivar.h> |
| 67 | #include <dev/mii/mii_bitbang.h> |
| 68 | |
| 69 | #include <dev/ic/ath_netbsd.h> |
| 70 | #include <dev/ic/athvar.h> |
| 71 | |
| 72 | #include <external/isc/atheros_hal/dist/ah.h> |
| 73 | |
| 74 | #include <dev/pci/pcivar.h> |
| 75 | #include <dev/pci/pcireg.h> |
| 76 | #include <dev/pci/pcidevs.h> |
| 77 | |
| 78 | #include <dev/cardbus/cardbusvar.h> |
| 79 | #include <dev/pci/pcidevs.h> |
| 80 | |
| 81 | /* |
| 82 | * PCI configuration space registers |
| 83 | */ |
| 84 | #define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */ |
| 85 | |
| 86 | struct ath_cardbus_softc { |
| 87 | struct ath_softc sc_ath; |
| 88 | |
| 89 | /* CardBus-specific goo. */ |
| 90 | void *sc_ih; /* interrupt handle */ |
| 91 | cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ |
| 92 | pcitag_t sc_tag; /* our CardBus tag */ |
| 93 | bus_size_t sc_mapsize; /* the size of mapped bus space region */ |
| 94 | |
| 95 | pcireg_t sc_bar_val; /* value of the BAR */ |
| 96 | |
| 97 | bus_space_tag_t sc_iot; |
| 98 | bus_space_handle_t sc_ioh; |
| 99 | }; |
| 100 | |
| 101 | int ath_cardbus_match(device_t, cfdata_t, void *); |
| 102 | void ath_cardbus_attach(device_t, device_t, void *); |
| 103 | int ath_cardbus_detach(device_t, int); |
| 104 | |
| 105 | CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc), |
| 106 | ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL); |
| 107 | |
| 108 | void ath_cardbus_setup(struct ath_cardbus_softc *); |
| 109 | |
| 110 | static bool |
| 111 | ath_cardbus_suspend(device_t self, const pmf_qual_t *qual) |
| 112 | { |
| 113 | struct ath_cardbus_softc *csc = device_private(self); |
| 114 | |
| 115 | ath_suspend(&csc->sc_ath); |
| 116 | if (csc->sc_ih != NULL) { |
| 117 | Cardbus_intr_disestablish(csc->sc_ct, csc->sc_ih); |
| 118 | csc->sc_ih = NULL; |
| 119 | } |
| 120 | return true; |
| 121 | } |
| 122 | |
| 123 | static bool |
| 124 | ath_cardbus_resume(device_t self, const pmf_qual_t *qual) |
| 125 | { |
| 126 | struct ath_cardbus_softc *csc = device_private(self); |
| 127 | |
| 128 | csc->sc_ih = Cardbus_intr_establish(csc->sc_ct, |
| 129 | IPL_NET, ath_intr, &csc->sc_ath); |
| 130 | |
| 131 | if (csc->sc_ih == NULL) { |
| 132 | aprint_error_dev(self, |
| 133 | "unable to establish interrupt\n" ); |
| 134 | return false; |
| 135 | } |
| 136 | |
| 137 | return ath_resume(&csc->sc_ath); |
| 138 | } |
| 139 | |
| 140 | int |
| 141 | ath_cardbus_match(device_t parent, cfdata_t match, void *aux) |
| 142 | { |
| 143 | struct cardbus_attach_args *ca = aux; |
| 144 | const char *devname; |
| 145 | |
| 146 | devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id)); |
| 147 | |
| 148 | if (devname) |
| 149 | return 1; |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | void |
| 155 | ath_cardbus_attach(device_t parent, device_t self, void *aux) |
| 156 | { |
| 157 | struct ath_cardbus_softc *csc = device_private(self); |
| 158 | struct ath_softc *sc = &csc->sc_ath; |
| 159 | struct cardbus_attach_args *ca = aux; |
| 160 | cardbus_devfunc_t ct = ca->ca_ct; |
| 161 | bus_addr_t adr; |
| 162 | |
| 163 | sc->sc_dev = self; |
| 164 | sc->sc_dmat = ca->ca_dmat; |
| 165 | csc->sc_ct = ct; |
| 166 | csc->sc_tag = ca->ca_tag; |
| 167 | |
| 168 | aprint_normal("\n" ); |
| 169 | |
| 170 | /* |
| 171 | * Map the device. |
| 172 | */ |
| 173 | if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, |
| 174 | &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) { |
| 175 | csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; |
| 176 | } else { |
| 177 | aprint_error_dev(self, "unable to map device registers\n" ); |
| 178 | return; |
| 179 | } |
| 180 | |
| 181 | sc->sc_st = HALTAG(csc->sc_iot); |
| 182 | sc->sc_sh = HALHANDLE(csc->sc_ioh); |
| 183 | |
| 184 | /* |
| 185 | * Set up the PCI configuration registers. |
| 186 | */ |
| 187 | ath_cardbus_setup(csc); |
| 188 | |
| 189 | /* |
| 190 | * Finish off the attach. |
| 191 | */ |
| 192 | if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0) |
| 193 | return; |
| 194 | |
| 195 | if (pmf_device_register(self, |
| 196 | ath_cardbus_suspend, ath_cardbus_resume)) { |
| 197 | pmf_class_network_register(self, &sc->sc_if); |
| 198 | pmf_device_suspend(self, &sc->sc_qual); |
| 199 | } else |
| 200 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 201 | } |
| 202 | |
| 203 | int |
| 204 | ath_cardbus_detach(device_t self, int flags) |
| 205 | { |
| 206 | struct ath_cardbus_softc *csc = device_private(self); |
| 207 | struct ath_softc *sc = &csc->sc_ath; |
| 208 | struct cardbus_devfunc *ct = csc->sc_ct; |
| 209 | int rv; |
| 210 | |
| 211 | #if defined(DIAGNOSTIC) |
| 212 | if (ct == NULL) |
| 213 | panic("%s: data structure lacks" , device_xname(sc->sc_dev)); |
| 214 | #endif |
| 215 | |
| 216 | rv = ath_detach(sc); |
| 217 | if (rv) |
| 218 | return (rv); |
| 219 | |
| 220 | pmf_device_deregister(self); |
| 221 | |
| 222 | /* |
| 223 | * Unhook the interrupt handler. |
| 224 | */ |
| 225 | if (csc->sc_ih != NULL) { |
| 226 | Cardbus_intr_disestablish(ct, csc->sc_ih); |
| 227 | csc->sc_ih = NULL; |
| 228 | } |
| 229 | |
| 230 | /* |
| 231 | * Release bus space and close window. |
| 232 | */ |
| 233 | Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh, |
| 234 | csc->sc_mapsize); |
| 235 | |
| 236 | return (0); |
| 237 | } |
| 238 | |
| 239 | void |
| 240 | ath_cardbus_setup(struct ath_cardbus_softc *csc) |
| 241 | { |
| 242 | cardbus_devfunc_t ct = csc->sc_ct; |
| 243 | int rc; |
| 244 | pcireg_t reg; |
| 245 | |
| 246 | if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0) |
| 247 | aprint_debug("%s: cardbus_set_powerstate %d\n" , __func__, rc); |
| 248 | |
| 249 | /* Program the BAR. */ |
| 250 | Cardbus_conf_write(ct, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val); |
| 251 | |
| 252 | /* Enable the appropriate bits in the PCI CSR. */ |
| 253 | reg = Cardbus_conf_read(ct, csc->sc_tag, |
| 254 | PCI_COMMAND_STATUS_REG); |
| 255 | reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; |
| 256 | Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg); |
| 257 | } |
| 258 | |