| 1 | /* $NetBSD: nouveau_subdev_vm_nv50.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright 2010 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Ben Skeggs |
| 25 | */ |
| 26 | |
| 27 | #include <sys/cdefs.h> |
| 28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_vm_nv50.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $" ); |
| 29 | |
| 30 | #include <core/device.h> |
| 31 | #include <core/gpuobj.h> |
| 32 | |
| 33 | #include <subdev/timer.h> |
| 34 | #include <subdev/fb.h> |
| 35 | #include <subdev/bar.h> |
| 36 | #include <subdev/vm.h> |
| 37 | |
| 38 | struct nv50_vmmgr_priv { |
| 39 | struct nouveau_vmmgr base; |
| 40 | }; |
| 41 | |
| 42 | static void |
| 43 | nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, |
| 44 | struct nouveau_gpuobj *pgt[2]) |
| 45 | { |
| 46 | u64 phys = 0xdeadcafe00000000ULL; |
| 47 | u32 coverage = 0; |
| 48 | |
| 49 | if (pgt[0]) { |
| 50 | phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ |
| 51 | coverage = (pgt[0]->size >> 3) << 12; |
| 52 | } else |
| 53 | if (pgt[1]) { |
| 54 | phys = 0x00000001 | pgt[1]->addr; /* present */ |
| 55 | coverage = (pgt[1]->size >> 3) << 16; |
| 56 | } |
| 57 | |
| 58 | if (phys & 1) { |
| 59 | if (coverage <= 32 * 1024 * 1024) |
| 60 | phys |= 0x60; |
| 61 | else if (coverage <= 64 * 1024 * 1024) |
| 62 | phys |= 0x40; |
| 63 | else if (coverage <= 128 * 1024 * 1024) |
| 64 | phys |= 0x20; |
| 65 | } |
| 66 | |
| 67 | nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); |
| 68 | nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); |
| 69 | } |
| 70 | |
| 71 | static inline u64 |
| 72 | vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) |
| 73 | { |
| 74 | phys |= 1; /* present */ |
| 75 | phys |= (u64)memtype << 40; |
| 76 | phys |= target << 4; |
| 77 | if (vma->access & NV_MEM_ACCESS_SYS) |
| 78 | phys |= (1 << 6); |
| 79 | if (!(vma->access & NV_MEM_ACCESS_WO)) |
| 80 | phys |= (1 << 3); |
| 81 | return phys; |
| 82 | } |
| 83 | |
| 84 | static void |
| 85 | nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, |
| 86 | struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) |
| 87 | { |
| 88 | u32 comp = (mem->memtype & 0x180) >> 7; |
| 89 | u32 block, target; |
| 90 | int i; |
| 91 | |
| 92 | /* IGPs don't have real VRAM, re-target to stolen system memory */ |
| 93 | target = 0; |
| 94 | if (nouveau_fb(vma->vm->vmm)->ram->stolen) { |
| 95 | phys += nouveau_fb(vma->vm->vmm)->ram->stolen; |
| 96 | target = 3; |
| 97 | } |
| 98 | |
| 99 | phys = vm_addr(vma, phys, mem->memtype, target); |
| 100 | pte <<= 3; |
| 101 | cnt <<= 3; |
| 102 | |
| 103 | while (cnt) { |
| 104 | u32 offset_h = upper_32_bits(phys); |
| 105 | u32 offset_l = lower_32_bits(phys); |
| 106 | |
| 107 | for (i = 7; i >= 0; i--) { |
| 108 | block = 1 << (i + 3); |
| 109 | if (cnt >= block && !(pte & (block - 1))) |
| 110 | break; |
| 111 | } |
| 112 | offset_l |= (i << 7); |
| 113 | |
| 114 | phys += block << (vma->node->type - 3); |
| 115 | cnt -= block; |
| 116 | if (comp) { |
| 117 | u32 tag = mem->tag->offset + ((delta >> 16) * comp); |
| 118 | offset_h |= (tag << 17); |
| 119 | delta += block << (vma->node->type - 3); |
| 120 | } |
| 121 | |
| 122 | while (block) { |
| 123 | nv_wo32(pgt, pte + 0, offset_l); |
| 124 | nv_wo32(pgt, pte + 4, offset_h); |
| 125 | pte += 8; |
| 126 | block -= 8; |
| 127 | } |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | static void |
| 132 | nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, |
| 133 | struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) |
| 134 | { |
| 135 | u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; |
| 136 | pte <<= 3; |
| 137 | while (cnt--) { |
| 138 | u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); |
| 139 | nv_wo32(pgt, pte + 0, lower_32_bits(phys)); |
| 140 | nv_wo32(pgt, pte + 4, upper_32_bits(phys)); |
| 141 | pte += 8; |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static void |
| 146 | nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) |
| 147 | { |
| 148 | pte <<= 3; |
| 149 | while (cnt--) { |
| 150 | nv_wo32(pgt, pte + 0, 0x00000000); |
| 151 | nv_wo32(pgt, pte + 4, 0x00000000); |
| 152 | pte += 8; |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | static void |
| 157 | nv50_vm_flush(struct nouveau_vm *vm) |
| 158 | { |
| 159 | struct nv50_vmmgr_priv *priv = (void *)vm->vmm; |
| 160 | struct nouveau_bar *bar = nouveau_bar(priv); |
| 161 | struct nouveau_engine *engine; |
| 162 | int i, vme; |
| 163 | |
| 164 | bar->flush(bar); |
| 165 | |
| 166 | mutex_lock(&nv_subdev(priv)->mutex); |
| 167 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { |
| 168 | if (!atomic_read(&vm->engref[i])) |
| 169 | continue; |
| 170 | |
| 171 | /* unfortunate hw bug workaround... */ |
| 172 | engine = nouveau_engine(priv, i); |
| 173 | if (engine && engine->tlb_flush) { |
| 174 | engine->tlb_flush(engine); |
| 175 | continue; |
| 176 | } |
| 177 | |
| 178 | switch (i) { |
| 179 | case NVDEV_ENGINE_GR : vme = 0x00; break; |
| 180 | case NVDEV_ENGINE_VP : vme = 0x01; break; |
| 181 | case NVDEV_SUBDEV_BAR : vme = 0x06; break; |
| 182 | case NVDEV_ENGINE_PPP : |
| 183 | case NVDEV_ENGINE_MPEG : vme = 0x08; break; |
| 184 | case NVDEV_ENGINE_BSP : vme = 0x09; break; |
| 185 | case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; |
| 186 | case NVDEV_ENGINE_COPY0: vme = 0x0d; break; |
| 187 | default: |
| 188 | continue; |
| 189 | } |
| 190 | |
| 191 | nv_wr32(priv, 0x100c80, (vme << 16) | 1); |
| 192 | if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) |
| 193 | nv_error(priv, "vm flush timeout: engine %d\n" , vme); |
| 194 | } |
| 195 | mutex_unlock(&nv_subdev(priv)->mutex); |
| 196 | } |
| 197 | |
| 198 | static int |
| 199 | nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, |
| 200 | u64 mm_offset, struct nouveau_vm **pvm) |
| 201 | { |
| 202 | u32 block = (1 << (vmm->pgt_bits + 12)); |
| 203 | if (block > length) |
| 204 | block = length; |
| 205 | |
| 206 | return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); |
| 207 | } |
| 208 | |
| 209 | static int |
| 210 | nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 211 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 212 | struct nouveau_object **pobject) |
| 213 | { |
| 214 | struct nv50_vmmgr_priv *priv; |
| 215 | int ret; |
| 216 | |
| 217 | ret = nouveau_vmmgr_create(parent, engine, oclass, "VM" , "vm" , &priv); |
| 218 | *pobject = nv_object(priv); |
| 219 | if (ret) |
| 220 | return ret; |
| 221 | |
| 222 | priv->base.limit = 1ULL << 40; |
| 223 | priv->base.dma_bits = 40; |
| 224 | priv->base.pgt_bits = 29 - 12; |
| 225 | priv->base.spg_shift = 12; |
| 226 | priv->base.lpg_shift = 16; |
| 227 | priv->base.create = nv50_vm_create; |
| 228 | priv->base.map_pgt = nv50_vm_map_pgt; |
| 229 | priv->base.map = nv50_vm_map; |
| 230 | priv->base.map_sg = nv50_vm_map_sg; |
| 231 | priv->base.unmap = nv50_vm_unmap; |
| 232 | priv->base.flush = nv50_vm_flush; |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | struct nouveau_oclass |
| 237 | nv50_vmmgr_oclass = { |
| 238 | .handle = NV_SUBDEV(VM, 0x50), |
| 239 | .ofuncs = &(struct nouveau_ofuncs) { |
| 240 | .ctor = nv50_vmmgr_ctor, |
| 241 | .dtor = _nouveau_vmmgr_dtor, |
| 242 | .init = _nouveau_vmmgr_init, |
| 243 | .fini = _nouveau_vmmgr_fini, |
| 244 | }, |
| 245 | }; |
| 246 | |