| 1 | /* $NetBSD: mvsata_pci.c,v 1.8 2014/03/29 19:28:25 christos Exp $ */ |
| 2 | /* |
| 3 | * Copyright (c) 2008 KIYOHARA Takashi |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 17 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 18 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, |
| 19 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 20 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 21 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 23 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| 24 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 25 | * POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <sys/cdefs.h> |
| 29 | __KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.8 2014/03/29 19:28:25 christos Exp $" ); |
| 30 | |
| 31 | #include <sys/param.h> |
| 32 | #include <sys/bus.h> |
| 33 | #include <sys/device.h> |
| 34 | #include <sys/errno.h> |
| 35 | #include <sys/pmf.h> |
| 36 | |
| 37 | #include <dev/pci/pcivar.h> |
| 38 | #include <dev/pci/pcidevs.h> |
| 39 | #include <dev/pci/pciidereg.h> |
| 40 | #include <dev/pci/pciidevar.h> |
| 41 | |
| 42 | #include <dev/ic/mvsatareg.h> |
| 43 | #include <dev/ic/mvsatavar.h> |
| 44 | |
| 45 | #define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000 |
| 46 | |
| 47 | #define MVSATA_PCI_COMMAND 0x00c00 |
| 48 | #define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4) |
| 49 | #define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5) |
| 50 | #define MVSATA_PCI_SERRMASK 0x00c28 |
| 51 | #define MVSATA_PCI_MSITRIGGER 0x00c38 |
| 52 | #define MVSATA_PCI_MODE 0x00d00 |
| 53 | #define MVSATA_PCI_DISCTIMER 0x00d04 |
| 54 | #define MVSATA_PCI_EROMBAR 0x00d2c |
| 55 | #define MVSATA_PCI_MAINCS 0x00d30 |
| 56 | #define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */ |
| 57 | #define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */ |
| 58 | #define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */ |
| 59 | #define MVSATA_PCI_E_IRQCAUSE 0x01900 |
| 60 | #define MVSATA_PCI_E_IRQMASK 0x01910 |
| 61 | #define MVSATA_PCI_XBARTIMEOUT 0x01d04 |
| 62 | #define MVSATA_PCI_ERRLOWADDR 0x01d40 |
| 63 | #define MVSATA_PCI_ERRHIGHADDR 0x01d44 |
| 64 | #define MVSATA_PCI_ERRATTRIBUTE 0x01d48 |
| 65 | #define MVSATA_PCI_ERRCOMMAND 0x01d50 |
| 66 | #define MVSATA_PCI_IRQCAUSE 0x01d58 |
| 67 | #define MVSATA_PCI_IRQMASK 0x01d5c |
| 68 | #define MVSATA_PCI_MAINIRQCAUSE 0x01d60 |
| 69 | #define MVSATA_PCI_MAINIRQMASK 0x01d64 |
| 70 | #define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \ |
| 71 | (1 << (((port) << 1) + (hc) * 9)) |
| 72 | #define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \ |
| 73 | (1 << (((port) << 1) + (hc) * 9 + 1)) |
| 74 | #define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8)) |
| 75 | #define MVSATA_PCI_MAINIRQ_PCI (1 << 18) |
| 76 | #define MVSATA_PCI_FLASHCTL 0x1046c |
| 77 | #define MVSATA_PCI_GPIOPORTCTL 0x104f0 |
| 78 | #define MVSATA_PCI_RESETCFG 0x180d8 |
| 79 | |
| 80 | #define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev) |
| 81 | |
| 82 | |
| 83 | struct mvsata_pci_softc { |
| 84 | struct mvsata_softc psc_sc; |
| 85 | |
| 86 | pci_chipset_tag_t psc_pc; |
| 87 | pcitag_t psc_tag; |
| 88 | |
| 89 | bus_space_tag_t psc_iot; |
| 90 | bus_space_handle_t psc_ioh; |
| 91 | |
| 92 | void *psc_ih; |
| 93 | }; |
| 94 | |
| 95 | |
| 96 | static int mvsata_pci_match(device_t, struct cfdata *, void *); |
| 97 | static void mvsata_pci_attach(device_t, device_t, void *); |
| 98 | static int mvsata_pci_detach(device_t, int); |
| 99 | |
| 100 | static int mvsata_pci_intr(void *); |
| 101 | static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual); |
| 102 | |
| 103 | static int mvsata_pci_sreset(struct mvsata_softc *); |
| 104 | static int mvsata_pci_misc_reset(struct mvsata_softc *); |
| 105 | static void mvsata_pci_enable_intr(struct mvsata_port *, int); |
| 106 | |
| 107 | |
| 108 | CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc), |
| 109 | mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL); |
| 110 | |
| 111 | struct mvsata_product mvsata_pci_products[] = { |
| 112 | #define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p |
| 113 | { PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 }, |
| 114 | { PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 }, |
| 115 | { PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 }, |
| 116 | { PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 }, |
| 117 | { PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 }, |
| 118 | { PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 }, |
| 119 | { PCI_VP(ADP2, 1420SA), 1, 4, gen2, 0 }, /* 88SX6041 */ |
| 120 | { PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 }, |
| 121 | { PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE }, |
| 122 | { PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE }, |
| 123 | { PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 }, |
| 124 | { PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, /* 88SX7042 */ |
| 125 | { PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 }, |
| 126 | #undef PCI_VP |
| 127 | }; |
| 128 | |
| 129 | |
| 130 | /* |
| 131 | * mvsata_pci_match() |
| 132 | * This function returns 2, because mvsata is high priority more than pciide. |
| 133 | */ |
| 134 | static int |
| 135 | mvsata_pci_match(device_t parent, struct cfdata *match, void *aux) |
| 136 | { |
| 137 | struct pci_attach_args *pa = aux; |
| 138 | int i; |
| 139 | |
| 140 | for (i = 0; i < __arraycount(mvsata_pci_products); i++) |
| 141 | if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && |
| 142 | PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) |
| 143 | return 2; |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | static void |
| 148 | mvsata_pci_attach(device_t parent, device_t self, void *aux) |
| 149 | { |
| 150 | struct pci_attach_args *pa = aux; |
| 151 | struct mvsata_pci_softc *psc = device_private(self); |
| 152 | struct mvsata_softc *sc = &psc->psc_sc; |
| 153 | pci_intr_handle_t intrhandle; |
| 154 | pcireg_t csr; |
| 155 | bus_size_t size; |
| 156 | uint32_t reg, mask; |
| 157 | int read_pre_amps, hc, port, rv, i; |
| 158 | const char *intrstr; |
| 159 | char intrbuf[PCI_INTRSTR_LEN]; |
| 160 | |
| 161 | sc->sc_wdcdev.sc_atac.atac_dev = self; |
| 162 | sc->sc_model = PCI_PRODUCT(pa->pa_id); |
| 163 | sc->sc_rev = PCI_REVISION(pa->pa_class); |
| 164 | sc->sc_dmat = pa->pa_dmat; |
| 165 | sc->sc_enable_intr = mvsata_pci_enable_intr; |
| 166 | |
| 167 | pci_aprint_devinfo(pa, "Marvell Serial-ATA Host Controller" ); |
| 168 | |
| 169 | /* Map I/O register */ |
| 170 | if (pci_mapreg_map(pa, PCI_MAPREG_START, |
| 171 | PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, |
| 172 | &psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) { |
| 173 | aprint_error_dev(self, "can't map registers\n" ); |
| 174 | return; |
| 175 | } |
| 176 | psc->psc_pc = pa->pa_pc; |
| 177 | psc->psc_tag = pa->pa_tag; |
| 178 | |
| 179 | if (bus_space_subregion(psc->psc_iot, psc->psc_ioh, |
| 180 | MVSATA_PCI_HCARBITER_SPACE_OFFSET, |
| 181 | size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) { |
| 182 | aprint_error_dev(self, "can't subregion registers\n" ); |
| 183 | return; |
| 184 | } |
| 185 | sc->sc_iot = psc->psc_iot; |
| 186 | |
| 187 | /* Enable device */ |
| 188 | csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); |
| 189 | csr |= PCI_COMMAND_MASTER_ENABLE; |
| 190 | pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr); |
| 191 | |
| 192 | if (pci_intr_map(pa, &intrhandle) != 0) { |
| 193 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
| 194 | return; |
| 195 | } |
| 196 | intrstr = pci_intr_string(psc->psc_pc, intrhandle, intrbuf, sizeof(intrbuf)); |
| 197 | psc->psc_ih = pci_intr_establish(psc->psc_pc, intrhandle, IPL_BIO, |
| 198 | mvsata_pci_intr, sc); |
| 199 | if (psc->psc_ih == NULL) { |
| 200 | aprint_error_dev(self, "couldn't establish interrupt\n" ); |
| 201 | return; |
| 202 | } |
| 203 | aprint_normal_dev(self, "interrupting at %s\n" , |
| 204 | intrstr ? intrstr : "unknown interrupt" ); |
| 205 | |
| 206 | /* |
| 207 | * Check if TWSI serial ROM initialization was triggered. |
| 208 | * If so, then PRE/AMP configuration probably are set after |
| 209 | * reset by serial ROM. If not then override the PRE/AMP |
| 210 | * values. |
| 211 | */ |
| 212 | reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG); |
| 213 | read_pre_amps = (reg & 0x00000001) ? 1 : 0; |
| 214 | |
| 215 | for (i = 0; i < __arraycount(mvsata_pci_products); i++) |
| 216 | if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && |
| 217 | PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) |
| 218 | break; |
| 219 | KASSERT(i < __arraycount(mvsata_pci_products)); |
| 220 | |
| 221 | rv = mvsata_attach(sc, &mvsata_pci_products[i], |
| 222 | mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps); |
| 223 | if (rv != 0) { |
| 224 | pci_intr_disestablish(psc->psc_pc, psc->psc_ih); |
| 225 | return; |
| 226 | } |
| 227 | |
| 228 | mask = MVSATA_PCI_MAINIRQ_PCI; |
| 229 | for (hc = 0; hc < sc->sc_hc; hc++) |
| 230 | for (port = 0; port < sc->sc_port; port++) |
| 231 | mask |= |
| 232 | MVSATA_PCI_MAINIRQ_SATAERR(hc, port) | |
| 233 | MVSATA_PCI_MAINIRQ_SATADONE(hc, port); |
| 234 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, |
| 235 | mask); |
| 236 | |
| 237 | if (!pmf_device_register(self, NULL, mvsata_pci_resume)) |
| 238 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
| 239 | } |
| 240 | |
| 241 | static int |
| 242 | mvsata_pci_detach(device_t self, int flags) |
| 243 | { |
| 244 | struct mvsata_pci_softc *psc = device_private(self); |
| 245 | |
| 246 | /* XXXX: needs reset ? */ |
| 247 | |
| 248 | pci_intr_disestablish(psc->psc_pc, psc->psc_ih); |
| 249 | pmf_device_deregister(self); |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static int |
| 254 | mvsata_pci_intr(void *arg) |
| 255 | { |
| 256 | struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg; |
| 257 | struct mvsata_softc *sc = &psc->psc_sc; |
| 258 | uint32_t cause; |
| 259 | int hc, port, handled = 0; |
| 260 | |
| 261 | cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 262 | MVSATA_PCI_MAINIRQCAUSE); |
| 263 | for (hc = 0; hc < sc->sc_hc; hc++) |
| 264 | for (port = 0; port < sc->sc_port; port++) |
| 265 | if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) { |
| 266 | struct mvsata_port *mvport; |
| 267 | |
| 268 | mvport = sc->sc_hcs[hc].hc_ports[port]; |
| 269 | handled |= mvsata_error(mvport); |
| 270 | } |
| 271 | for (hc = 0; hc < sc->sc_hc; hc++) |
| 272 | if (cause & |
| 273 | (MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) | |
| 274 | MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) | |
| 275 | MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) | |
| 276 | MVSATA_PCI_MAINIRQ_SATADONE(hc, 3))) |
| 277 | handled |= mvsata_intr(&sc->sc_hcs[hc]); |
| 278 | |
| 279 | if (cause & MVSATA_PCI_MAINIRQ_PCI) { |
| 280 | uint32_t pe_cause; |
| 281 | |
| 282 | if (sc->sc_flags & MVSATA_FLAGS_PCIE) { |
| 283 | pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 284 | MVSATA_PCI_E_IRQCAUSE); |
| 285 | aprint_error_dev(MVSATA_PCI_DEV(psc), |
| 286 | "PCIe error: 0x%x\n" , pe_cause); |
| 287 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 288 | MVSATA_PCI_E_IRQCAUSE, ~pe_cause); |
| 289 | } else { |
| 290 | pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 291 | MVSATA_PCI_IRQCAUSE); |
| 292 | aprint_error_dev(MVSATA_PCI_DEV(psc), |
| 293 | "PCI error: 0x%x\n" , pe_cause); |
| 294 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 295 | MVSATA_PCI_IRQCAUSE, ~pe_cause); |
| 296 | } |
| 297 | |
| 298 | handled = 1; /* XXXXX */ |
| 299 | } |
| 300 | |
| 301 | return handled; |
| 302 | } |
| 303 | |
| 304 | static bool |
| 305 | mvsata_pci_resume(device_t dev, const pmf_qual_t *qual) |
| 306 | { |
| 307 | |
| 308 | /* not yet... */ |
| 309 | |
| 310 | return true; |
| 311 | } |
| 312 | |
| 313 | |
| 314 | static int |
| 315 | mvsata_pci_sreset(struct mvsata_softc *sc) |
| 316 | { |
| 317 | struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; |
| 318 | uint32_t val; |
| 319 | int i; |
| 320 | |
| 321 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); |
| 322 | val |= MVSATA_PCI_MAINCS_SPM; |
| 323 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); |
| 324 | |
| 325 | for (i = 0; i < 1000; i++) { |
| 326 | delay(1); |
| 327 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 328 | MVSATA_PCI_MAINCS); |
| 329 | if (val & MVSATA_PCI_MAINCS_PME) |
| 330 | break; |
| 331 | } |
| 332 | if (!(val & MVSATA_PCI_MAINCS_PME)) { |
| 333 | aprint_error_dev(MVSATA_PCI_DEV(psc), |
| 334 | "PCI master won't flush\n" ); |
| 335 | return -1; |
| 336 | } |
| 337 | |
| 338 | /* reset */ |
| 339 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, |
| 340 | val | MVSATA_PCI_MAINCS_GSR); |
| 341 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); |
| 342 | delay(5); |
| 343 | if (!(val & MVSATA_PCI_MAINCS_GSR)) { |
| 344 | aprint_error_dev(MVSATA_PCI_DEV(psc), |
| 345 | "can't set global reset\n" ); |
| 346 | return -1; |
| 347 | } |
| 348 | |
| 349 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
| 350 | val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM); |
| 351 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); |
| 352 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); |
| 353 | delay(5); |
| 354 | if (val & MVSATA_PCI_MAINCS_GSR) { |
| 355 | aprint_error_dev(MVSATA_PCI_DEV(psc), |
| 356 | "can't set global reset\n" ); |
| 357 | return -1; |
| 358 | } |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static int |
| 364 | mvsata_pci_misc_reset(struct mvsata_softc *sc) |
| 365 | { |
| 366 | struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; |
| 367 | #define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371 |
| 368 | #define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0 |
| 369 | uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT; |
| 370 | |
| 371 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL, |
| 372 | 0x0fcfffff); |
| 373 | |
| 374 | if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { |
| 375 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 376 | MVSATA_PCI_GPIOPORTCTL); |
| 377 | val &= 0x3; |
| 378 | #if 0 |
| 379 | val |= 0x00000060; |
| 380 | #else /* XXXX */ |
| 381 | val |= 0x00000070; |
| 382 | #endif |
| 383 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 384 | MVSATA_PCI_GPIOPORTCTL, val); |
| 385 | } |
| 386 | |
| 387 | if (sc->sc_gen == gen1) { |
| 388 | /* Expansion ROM BAR Enable */ |
| 389 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 390 | MVSATA_PCI_EROMBAR); |
| 391 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 392 | MVSATA_PCI_EROMBAR, val | 0x00000001); |
| 393 | } |
| 394 | |
| 395 | if (sc->sc_flags & MVSATA_FLAGS_PCIE) { |
| 396 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 397 | MVSATA_PCI_MAINIRQMASK, 0); |
| 398 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 399 | MVSATA_PCI_E_IRQCAUSE, 0); |
| 400 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 401 | MVSATA_PCI_E_IRQMASK, 0); |
| 402 | } else { |
| 403 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 404 | MVSATA_PCI_MODE); |
| 405 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 406 | MVSATA_PCI_MODE, val & 0xff00ffff); |
| 407 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 408 | MVSATA_PCI_DISCTIMER, 0); |
| 409 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 410 | MVSATA_PCI_MSITRIGGER, 0); |
| 411 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 412 | MVSATA_PCI_XBARTIMEOUT, 0x000100ff); |
| 413 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 414 | MVSATA_PCI_MAINIRQMASK, 0); |
| 415 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 416 | MVSATA_PCI_SERRMASK, 0); |
| 417 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 418 | MVSATA_PCI_IRQCAUSE, 0); |
| 419 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 420 | MVSATA_PCI_IRQMASK, 0); |
| 421 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 422 | MVSATA_PCI_ERRLOWADDR, 0); |
| 423 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 424 | MVSATA_PCI_ERRHIGHADDR, 0); |
| 425 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 426 | MVSATA_PCI_ERRATTRIBUTE, 0); |
| 427 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 428 | MVSATA_PCI_ERRCOMMAND, 0); |
| 429 | } |
| 430 | |
| 431 | /* Enable LED */ |
| 432 | if (sc->sc_gen == gen1) { |
| 433 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 434 | MVSATA_PCI_GPIOPORTCTL, 0); |
| 435 | |
| 436 | /* XXXX: 50xxB2 errata ? */ |
| 437 | #if 0 |
| 438 | if (sc->sc_rev == 3) { |
| 439 | int port; |
| 440 | |
| 441 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 442 | MVSATA_PCI_GPIOPORTCTL); |
| 443 | |
| 444 | /* XXXX: check HDD connected */ |
| 445 | |
| 446 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 447 | MVSATA_PCI_GPIOPORTCTL, val); |
| 448 | } |
| 449 | #endif |
| 450 | |
| 451 | /* Disable Flash controller clock */ |
| 452 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 453 | MVSATA_PCI_EROMBAR); |
| 454 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 455 | MVSATA_PCI_EROMBAR, val & ~0x00000001); |
| 456 | } else |
| 457 | #if 0 |
| 458 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 459 | MVSATA_PCI_GPIOPORTCTL, 0x00000060); |
| 460 | #else /* XXXX */ |
| 461 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 462 | MVSATA_PCI_GPIOPORTCTL, 0x00000070); |
| 463 | #endif |
| 464 | |
| 465 | if (sc->sc_flags & MVSATA_FLAGS_PCIE) |
| 466 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 467 | MVSATA_PCI_E_IRQMASK, 0x0000070a); |
| 468 | else { |
| 469 | val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 470 | MVSATA_PCI_MODE); |
| 471 | if ((val & 0x30) >> 4) { /* PCI-X */ |
| 472 | int mv60x1b2 = |
| 473 | ((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 || |
| 474 | sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) && |
| 475 | sc->sc_rev == 7); |
| 476 | |
| 477 | pci_command &= |
| 478 | ~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; |
| 479 | if (sc->sc_gen == gen1 || mv60x1b2) |
| 480 | pci_command &= |
| 481 | ~MVSATA_PCI_COMMAND_MWRITECOMBINE; |
| 482 | } else |
| 483 | if (sc->sc_gen == gen1) |
| 484 | pci_command &= |
| 485 | ~(MVSATA_PCI_COMMAND_MWRITECOMBINE | |
| 486 | MVSATA_PCI_COMMAND_MREADCOMBINE); |
| 487 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 488 | MVSATA_PCI_COMMAND, pci_command); |
| 489 | |
| 490 | #define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6 |
| 491 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 492 | MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK); |
| 493 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, |
| 494 | MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK); |
| 495 | } |
| 496 | |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | static void |
| 501 | mvsata_pci_enable_intr(struct mvsata_port *mvport, int on) |
| 502 | { |
| 503 | struct mvsata_pci_softc *psc = |
| 504 | device_private(mvport->port_ata_channel.ch_atac->atac_dev); |
| 505 | uint32_t mask; |
| 506 | int hc = mvport->port_hc->hc, port = mvport->port; |
| 507 | |
| 508 | mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh, |
| 509 | MVSATA_PCI_MAINIRQMASK); |
| 510 | if (on) |
| 511 | mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port); |
| 512 | else |
| 513 | mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port); |
| 514 | bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, |
| 515 | mask); |
| 516 | } |
| 517 | |