opam-version: "2.0"
maintainer: "Andy Ray <andy.ray@ujamjar.com>"
authors: [ "Andy Ray" ]
license: "ISC"
homepage: "https://github.com/ujamjar/hardcaml-yosys"
bug-reports: "https://github.com/ujamjar/hardcaml-yosys/issues"
dev-repo: "git+https://github.com/ujamjar/hardcaml-yosys.git"
build: [ ["ocaml" "pkg/pkg.ml" "build"] ]
depends: [
  "ocaml" {>= "4.02.0"}
  "ocamlfind" {build}
  "ocamlbuild" {build}
  "topkg" {build}
  "atdgen" {< "1.13.0"}
  "camlp4"
  "hardcaml" {>= "1.2.0" & < "2.0.0"}
]
synopsis: "Import Verilog designs into HardCaml"
url {
  src: "https://github.com/ujamjar/hardcaml-yosys/archive/v0.1.0.tar.gz"
  checksum: "md5=609fd6fa6a27104a97b59f9019f03a84"
}
